Sense amplifier, method of operating the same, memory, and memory system

Abstract

The embodiment of the present disclosure provides a sense amplifier, comprising: a pre-charge unit, a readout unit, a first switch unit and a second switch unit; the pre-charge unit is coupled to a first bit line of a storage unit and a second bit line of the storage unit; the readout unit comprises a first node, a second node, a third node and a fourth node; wherein a power supply voltage terminal is coupled to the first node, and the power supply voltage terminal is coupled to the third node; the first switch unit is coupled to the power supply voltage terminal and the second node; the second switch unit is coupled to the power supply voltage terminal and the fourth node; wherein the second node and the fourth node in the sense amplifier are coupled to the same potential in a discharge stage.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a sense amplifier and an operating method thereof, a memory and a memory system. BACKGROUND

[0002] With the progress of integrated circuit technology, the requirements for chip power consumption, area, and performance are becoming higher and higher, for example: feature size and area are continuously reduced, power supply voltage and power consumption are continuously reduced, and performance requirements such as speed and accuracy are continuously improved.

[0003] The sense circuit is one of the key unit modules in the design of the memory, and the response speed and accuracy thereof directly determine the time size of reading data of the memory, so it is crucial to design a sense circuit that meets the application requirements of the circuit. The existing memory sense circuit design is difficult to meet the high-precision performance requirements. SUMMARY

[0004] According to a first aspect of an embodiment of the present disclosure, a sense amplifier is provided, comprising: a pre-charge unit, a sense unit, a first switch unit, and a second switch unit; wherein,

[0005] The pre-charge unit is coupled to a first bit line of a storage unit and a second bit line of the storage unit.

[0006] The sense unit comprises a first node, a second node, a third node, and a fourth node; wherein a power supply voltage terminal is coupled to the first node, and the power supply voltage terminal is coupled to the third node.

[0007] The first switch unit is coupled to the power supply voltage terminal and the second node.

[0008] The second switch unit is coupled to the power supply voltage terminal and the fourth node.

[0009] In the sense amplifier, the second node and the fourth node are coupled to the same potential in the discharging phase.

[0010] In some embodiments, the sense amplifier further comprises an enable signal line.

[0011] The enable signal line is configured to transmit an enable signal.

[0012] The first switch unit and the second switch unit are further coupled to the enable signal line, respectively, and are configured to be conductive when the enable signal is at a low level and non-conductive when the enable signal is at a high level.

[0013] In some embodiments, the first switch unit comprises a first transistor; wherein,

[0014] The gate of the first transistor is coupled with an enable signal line, the second end of the first transistor is coupled with the second node, and the first end of the first transistor is coupled with the power voltage end.

[0015] The first transistor is configured to be conductive when the enable signal transmitted by the received enable signal line is a logic low level, so as to enable the power voltage end to communicate with the second node.

[0016] In some embodiments, the second switch unit comprises: a second transistor; wherein

[0017] The gate of the second transistor is coupled with an enable signal line, the second end of the second transistor is coupled with the fourth node, and the first end of the second transistor is coupled with the power voltage end.

[0018] The second transistor is configured to be conductive when the enable signal transmitted by the received enable signal line is a logic low level, so as to enable the power voltage end to communicate with the fourth node.

[0019] In some embodiments, the first switch unit and the second switch unit both comprise P-type transistors.

[0020] In some embodiments, the sense amplifier further comprises a third switch unit, the first end of the third switch unit is coupled with the second node, the second end of the third switch unit is coupled with the fourth node, and the third end of the third switch unit is coupled with an enable signal line; wherein

[0021] The third switch unit is configured to be conductive, so as to enable the voltage of the second node to be equal to the voltage of the fourth node.

[0022] In some embodiments, the third switch unit comprises: a third transistor; wherein the gate of the third transistor is coupled with the enable signal line, the first end of the third transistor is coupled with the second node, and the second end of the third transistor is coupled with the fourth node; wherein

[0023] The third transistor is configured to be conductive when the enable signal transmitted by the received enable signal line is a logic low level, so as to enable the second node and the fourth node to communicate.

[0024] In some embodiments, the sense unit comprises: a fourth transistor and a fifth transistor; wherein

[0025] The gate of the fourth transistor and the gate of the fifth transistor are both coupled with an enable signal line, the first end of the fourth transistor is coupled with the power voltage end, the second end of the fourth transistor is coupled with the first node, the first end of the fifth transistor is coupled with the power voltage end, and the second end of the fifth transistor is coupled with the third node.

[0026] The fourth transistor is configured to be conductive when the enable signal transmitted by the received enable signal line is a logic low level, so as to couple the power voltage end to the first node.

[0027] The fifth transistor is configured to be conductive when the enable signal transmitted by the received enable signal line is a logic low level, so as to couple the power voltage end to the third node.

[0028] In some embodiments, the first switch unit comprises a sixth transistor; wherein,

[0029] The gate of the sixth transistor is coupled with an enable signal line, the second end of the sixth transistor is coupled with the second node, and the first end of the sixth transistor is coupled with the first node.

[0030] The sixth transistor is configured to be conductive when the received enable signal is a logic low level, so as to communicate the power voltage end with the second node.

[0031] In some embodiments, the second switch unit comprises a seventh transistor; wherein,

[0032] The gate of the seventh transistor is coupled with an enable signal line, the second end of the seventh transistor is coupled with the fourth node, and the first end of the seventh transistor is coupled with the third node.

[0033] The seventh transistor is configured to be conductive when the enable signal transmitted by the received enable signal line is a logic low level, so as to communicate the power voltage end with the fourth node.

[0034] In some embodiments, the readout unit comprises a first inverter, a second inverter, and a bypass transistor unit; wherein,

[0035] The input end of the first inverter is coupled with the output end of the second inverter, and the output end of the first inverter is coupled with the input end of the second inverter.

[0036] The output end of the first inverter and the output end of the second inverter are respectively coupled with the input end of the bypass transistor unit, and the output end of the bypass transistor unit is grounded.

[0037] In some embodiments, the first inverter includes an eighth transistor and a ninth transistor, and the second inverter includes a tenth transistor and an eleventh transistor; wherein,

[0038] a gate of the eighth transistor and a gate of the ninth transistor are coupled with an output terminal of the second inverter, a first terminal of the eighth transistor is coupled with the power voltage terminal, a second terminal of the eighth transistor and a second terminal of the ninth transistor are coupled with the first node, and a first terminal of the ninth transistor is coupled with the second node;

[0039] a gate of the tenth transistor and a gate of the eleventh transistor are coupled with an output terminal of the first inverter, a first terminal of the tenth transistor is coupled with the power voltage terminal, a second terminal of the tenth transistor and a second terminal of the eleventh transistor are coupled with the third node, and a first terminal of the eleventh transistor is coupled with the fourth node.

[0040] In some embodiments, the eighth transistor and the tenth transistor include P-type transistors, and the ninth transistor and the eleventh transistor include N-type transistors.

[0041] In some embodiments, the bypass transistor unit includes a first bypass transistor, a second bypass transistor, a third bypass transistor, and a fourth bypass transistor; wherein,

[0042] a gate of the first bypass transistor is coupled with the first bit line, and a second terminal of the first bypass transistor is coupled with an output terminal of the first inverter;

[0043] a gate of the second bypass transistor is coupled with the second bit line, and a second terminal of the second bypass transistor is coupled with an output terminal of the second inverter;

[0044] a first terminal of the first bypass transistor and a first terminal of the second bypass transistor are coupled with a second terminal of the third bypass transistor, a first terminal of the third bypass transistor is grounded, and a gate of the third bypass transistor is coupled with the enable signal line;

[0045] a first terminal of the fourth bypass transistor is coupled with the output terminal of the second inverter, a second terminal of the fourth bypass transistor is coupled with the output terminal of the first inverter, and a gate of the fourth bypass transistor is coupled with the enable signal line.

[0046] In some embodiments, the first bypass transistor, the second bypass transistor, and the third bypass transistor all include N-type transistors, and the fourth bypass transistor includes a P-type transistor.

[0047] According to a second aspect of the embodiments of the present disclosure, a memory is provided, comprising: a plurality of memory cells and a sense amplifier according to the above-mentioned embodiments; wherein

[0048] The memory cells are coupled to the sense amplifier and are configured to store data.

[0049] The sense amplifier is configured to read the data stored in the memory cells and amplify the data.

[0050] In some embodiments, the memory comprises a static random access memory, and the memory cells comprise static random access memory cells.

[0051] In some embodiments, the static random access memory cell comprises a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; wherein

[0052] The gate of the first PMOS transistor is coupled to the gate of the first NMOS transistor, the first end of the first PMOS transistor is coupled to a power supply voltage terminal, the second end of the first PMOS transistor is coupled to the second end of the first NMOS transistor, and the first end of the first NMOS transistor is grounded.

[0053] The gate of the second PMOS transistor is coupled to the gate of the second NMOS transistor, the first end of the second PMOS transistor is coupled to the power supply voltage terminal, the second end of the second PMOS transistor is coupled to the second end of the second NMOS transistor, and the first end of the second NMOS transistor is grounded.

[0054] The gate of the third NMOS transistor is coupled to a selection word line, the first end of the third NMOS transistor is coupled to a first bit line, the second end of the third NMOS transistor is coupled to the second end of the first PMOS transistor, the gate of the fourth NMOS transistor is coupled to the selection word line, the first end of the fourth NMOS transistor is coupled to a second bit line, and the second end of the fourth NMOS transistor is coupled to the second end of the second PMOS transistor.

[0055] According to a third aspect of the embodiments of the present disclosure, a memory system is provided, comprising a memory according to the above-mentioned embodiments and a memory controller; wherein

[0056] The memory;

[0057] The memory controller is coupled to the memory and is configured to control the memory.

[0058] According to a fourth aspect of the embodiments of the present disclosure, a method for operating a sense amplifier is provided, the method comprising:

[0059] In the precharge phase, the first bit line and the second bit line are precharged to the power supply voltage;

[0060] In the discharge phase, when the first switch unit and the second switch unit are turned on, the power supply voltage terminal is coupled to the second node and the power supply voltage terminal is coupled to the fourth node, so that the second node and the fourth node are coupled to the same potential;

[0061] In the reading phase, when the first switch unit and the second switch unit are turned off, the first node and the third node are discharged.

[0062] Generally speaking, the second node in the readout amplifier discharges faster than the fourth node, and the second node drops to 0 before the fourth node. However, when the memory exits the write operation and enters the read operation, the second node will be coupled to a voltage higher than the voltage of the fourth node. At this time, the second node is discharged from the higher voltage and the fourth node is discharged from the lower voltage, which may cause the fourth node to drop to 0 before the second node, and the final read result is erroneous.

[0063] In the disclosed embodiment, the first, second, third, and fourth nodes are controlled to discharge from the power supply voltage via the first and second switching units, thereby reducing the voltage difference between the second and fourth nodes. During the read phase, the second and fourth nodes are coupled to the same potential, which affects the discharge rate of the first and third nodes during the read phase, reduces the probability of read errors, and improves the read accuracy of the sense amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Figure 1 FIG1 is a schematic diagram showing a circuit structure of a sense amplifier according to an exemplary embodiment;

[0065] Figure 2 for Figure 1 The timing diagram of the sense amplifier during the read operation is shown;

[0066] Figure 3 is a schematic diagram of a storage unit according to an exemplary embodiment;

[0067] Figure 4 for Figure 1 Another timing diagram of the sense amplifier during a read operation is shown;

[0068] Figure 5a FIG1 is a schematic diagram of a first circuit structure of another sense amplifier according to an exemplary embodiment;

[0069] Figure 5b FIG1 is a schematic diagram of a second circuit structure of another sense amplifier according to an exemplary embodiment;

[0070] Figure 6 Another readout amplifier as shown in FIG. 1C; Figure 5a Figure 5b Timing diagram of another readout amplifier as shown in FIG. 1C during a read operation;

[0071] Figure 7 Schematic diagram of a memory as shown in FIG. 2A;

[0072] Figure 8 Schematic diagram of a memory system as shown in FIG. 3A;

[0073] Figure 9a Schematic diagram of a memory card as shown in FIG. 4A;

[0074] Figure 9b Schematic diagram of a solid state drive (SSD) as shown in FIG. 5A;

[0075] Figure 10 Flowchart of a method of operating a readout amplifier as shown in FIG. 6A. DETAILED DESCRIPTION

[0076] The technical solutions of the present disclosure are further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0077] In the embodiments of the present disclosure, the terms "first", "second", and the like are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0078] In the embodiments of the present disclosure, the term "contacting" between A and B includes the case where A and B are directly in contact, or the case where A and B are indirectly in contact with each other with other components interposed therebetween.

[0079] In the embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. The layer can extend over the entirety of an underlying or overlying structure, or can have a scope less than the scope of an underlying or overlying structure. Further, a layer can be a region of a homogenous or inhomogenous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer can be located between a top surface and a bottom surface of a continuous structure, or the layer can be between any horizontal pair of planes at the top surface and the bottom surface of the continuous structure. A layer can extend horizontally, vertically, and / or along an inclined surface. Also, a layer can include multiple sub-layers.

[0080] It can be understood that the meanings of "on", "over", and "above" in the present disclosure should be interpreted in the broadest way, such that "on" not only means "on" something with no intervening features or layers therebetween (i.e., directly on something), but also includes "on" something with intervening features or layers therebetween.​

[0081] Static Random Access Memory (SRAM) is often used in computer equipment to temporarily store data, as long as there is a continuous power supply, and the stored data can be continuously stored without any update operation. In order to avoid the disappearance of internal storage data, compared with Dynamic Random Access Memory (DRAM) circuit, static random access memory does not need to be refreshed once every period of time, therefore, SRAM circuit has higher performance and lower power consumption.

[0082] The sense amplifier is an important part of the static random access memory. Because the time consumed by the SRAM memory to read data is generally greater than the time consumed when writing data, the speed of the SRAM memory is mainly determined by the time of reading data. In the process of reading data in the SRAM memory, because many storage units are connected on the bit line, there is a large capacitance on the bit line, so the speed of the bit line will be slow in the process of charging and discharging, which affects the speed of reading data of the memory. The sense amplifier can amplify the small swing on the bit line of the SRAM memory to the level of digital signal, which not only speeds up the reading speed of the SRAM memory, but also reduces the voltage swing on the bit line and reduces most of the power consumption related to charging and discharging of the bit line.

[0083] The sense amplifier mainly has two types: voltage type amplifier and current type amplifier. The main feature of the voltage type amplifier is to detect and amplify the voltage difference on the bit line. The main feature of the current type amplifier is to detect and amplify the current difference on the bit line. The current type amplifier is not affected by the capacitance and load existing on the bit line, but its circuit structure is complex, the reliability is poor, and the power consumption is large. Although the voltage type amplifier is affected by the capacitance and load existing on the bit line, it has simple structure, high stability and low power consumption. Here, the voltage type amplifier is taken as an example for description.

[0084] The voltage type amplifier mainly includes operational amplifier type amplifier, cross-coupled type amplifier, latch type amplifier, etc. Here, the latch type amplifier with fast reading speed is taken as an example for description.

[0085] When reading data in the SRAM, an amplifier such as Figure 1 is needed, and the specific operation of reading data in the SRAM is described with reference to Figure 1 , Figure 2 and Figure 3 as follows:

[0086] According to Figure 2As shown, in the first time period T1, the selection word line SEL is set to a logic low level (e.g., "0"), the pre-charge signal end pre_n is first set to a logic low level, at this time the first bit line BT and the second bit line BB are pre-charged to the voltage VDD, and then the pre-charge signal end pre_n is set to a logic high level (e.g., "1"), and the first bit line BT and the second bit line BB remain at the voltage VDD. In the second time period T2, the pre-charge signal end pre_n remains at a logic high level, at this time the selection word line SEL is set to a logic high level, and the first bit line BT and the second bit line BB are discharged to the voltage VP (e.g., the control discharge is 200 mV, and the voltage VP is VDD-200 mV). Figure 3 If the data stored in the storage unit is represented by the voltage d of 1 and the voltage d_n of 0, at this time the first bit line BT remains at the voltage VDD, and the second bit line BB is gradually discharged to the voltage VP (e.g., the control discharge is 200 mV, and the voltage VP is VDD-200 mV).

[0087] According to Figure 1 As shown, the node dp is coupled to the voltage VDD end through the transistor MN2 and the transistor MP0, and the node dp_n is coupled to the voltage VDD end through the transistor MN3 and the transistor MP1, in combination with Figure 2 As shown, the node dp and the node dp_n remain at the voltage VDD-V THN , before the third time period T3, where V THN is the threshold voltage of the transistor MN3 or the transistor MN2.

[0088] In Figure 1 , when the enable signal line EN is set to a low level, the transistor MP2 and the transistor MP3 are turned on, the voltage of the node sout follows the voltage of the voltage VDD end, and the voltage of the node sout_n follows the voltage of the voltage VDD end. After the second time period T2 ends, the second bit line BB is discharged to the voltage VP (about VDD-200 mV), the first bit line BT remains at the voltage VDD, the voltage of the node dp is VDD-V THN , the voltage of the node sout is VDD, the voltage of the node dp_n is VDD-V THN , and the voltage of the node sout_n is VDD. In the third time period T3, the enable signal line EN is set to a logic high level, the transistor MP2 and the transistor MP3 are turned off, and the transistor MN0, the transistor MN1, and the transistor M_EN form a discharge path, at this time the node dp, the node sout, the node dp_n, and the node sout_n are discharged.

[0089] In the third time period T3, the discharge phase, as shown in Figure 1 , because the voltage VDD of the first bit line BT is greater than the voltage VP of the second bit line BB, the discharge speed of the node dp and the node sout is greater than the discharge speed of the node dp_n and the node sout_n, as shown in Figure 2Finally, the voltage of the sout node is 0, and the voltage of the sout_n node is 1. The differential signal output by the read amplifier (the voltage of the sout node is 0, and the voltage of the sout_n node is 1) is converted into a single-ended voltage signal output through the output circuit (not shown), completing the read operation.

[0090] but, Figure 1 The SRAM read circuit shown has a read error problem, which affects the read reliability of the SRAM.

[0091] Specifically, in the read / write circuitry of an SRAM, both read and write operations are performed via the second bit line BB and the first bit line BT. During a write operation, the second bit line BB and the first bit line BT are set to "0" or "1" for a long period of time. Here, the second bit line BB is set to "1" and the first bit line BT is set to "0."

[0092] Since the enable signal line EN is set to a low level (“0”) during a write operation, the voltages of the nodes dp and dp_n are both pulled to VDD-V THN , where V THN is the threshold voltage of the NMOS tube. When exiting the write operation and entering the read operation, refer to Figure 3 , set the pre-charge signal terminal pre_n to a logic low level, at this time the first bit line BT and the second bit line BB will be pre-charged to the voltage VDD, since the first bit line BT changes from a low level "0" to a high voltage VDD, therefore, the reference Figure 1 , the node dp will be coupled to a higher level due to the gate-drain parasitic capacitance of the transistor MN0. Usually, the voltage of the node dp may be coupled to VDD+V THN , and the node dp_n is coupled to the second bit line BB through the transistor MN1. Since the second bit line BB is always at the voltage VDD, the voltage of the node dp_n does not change and remains at VDD-V THN .

[0093] During read operation, refer to Figure 3 , the data stored in the memory cell is represented by the voltage of d as 1 and the voltage of d_n as 0. After the second bit line BB and the first bit line BT are discharged, the second bit line BB is discharged to the voltage VP (about VDD-200mV), and the first bit line BT maintains the voltage VDD. At this time, the enable signal line EN is set to a high level ("1"). Under normal circumstances, the discharge speed of the node dp is faster than the discharge speed of the node dp_n. Finally, the voltage of the sout node is 0 and the voltage of sout_n is 1, completing the read operation. However, since the node dp is now from a higher level VDD+V THN Discharge, node dp_n from the lower level VDD-V THNDischarge, which can cause the node dp_n and the node sout_n to drop to a lower level first, and finally the voltage of the sout node is 1 and the voltage of the sout_n node is 0, resulting in a readout error (refer to Figure 4 ).

[0094] Therefore, the present disclosure provides another readout amplifier.

[0095] Figure 5a FIG. 1 shows a first circuit structure diagram of another readout amplifier according to an exemplary embodiment. Referring to FIG. 1, the readout amplifier 100 includes a pre-charge unit 101, a readout unit 102, a first switch unit 103, and a second switch unit 104; wherein, Figure 5a The pre-charge unit 101 is coupled to the first bit line BT of the storage unit and the second bit line BB of the storage unit.

[0096] The readout unit 102 includes a first node sout, a second node dp, a third node sout_n, and a fourth node dp_n; wherein the power voltage end VDD is coupled to the first node sout, and the power voltage end VDD is coupled to the third node sout_n.

[0097] The first switch unit 103 is coupled to the power voltage end VDD and the second node dp.

[0098] The second switch unit 104 is coupled to the power voltage end VDD and the fourth node dp_n.

[0099] Wherein, the second node dp and the fourth node dp_n in the readout amplifier are coupled to the same potential in the discharge phase. Since the voltage difference between the node dp and the node sout and the voltage difference between the node dp_n and the node sout_n will affect the discharge rate of the first node sout and the third node sout_n in the read phase, the present embodiment makes the voltage difference between the node dp and the node sout and the voltage difference between the node dp_n and the node sout_n the same by coupling the second node dp and the fourth node dp_n to the same potential in the discharge phase, so that the discharge rate of the first node sout and the third node sout_n in the read phase meets the demand, thereby reducing the probability of readout error and improving the readout accuracy of the readout amplifier.

[0100] Here, the operation process of the readout amplifier 100 is described by taking the read operation of the storage unit as shown in FIG. 2.

[0101] The basic structure of the storage unit as shown in FIG. 2 includes six transistors (as shown in FIG. 3). Figure 3 Figure 3 Figure 3 ​​The storage unit is composed of transistors P1 to P6. Data information is stored in the storage unit by selecting word line SEL, first bit line BT and second bit line BB, for example, in two cross-coupled inverters (as shown in Figure 3 The storage unit is composed of transistors P1 to P4. Figure 3 The storage unit shown has two stable states (for example, logic states "1" or "0") to indicate the stored data information, and specifically, the logic state is represented by the voltage of node d and the voltage of node d_n. Figure 3 The storage unit shown also includes transistors P5 and P6 to control read and write operations on the storage unit.

[0102] When the data stored in the storage unit is read by the read amplifier, it can include a pre-charge phase, a discharge phase and a read phase. In the pre-charge phase (as shown in Figure 6 In the first time period T1, the first bit line BT and the second bit line BB are pre-charged to the power supply voltage. For example, the first bit line BT can be pre-charged to the power supply voltage VDD by the pre-charge unit 101, and the second bit line BB is maintained at the power supply voltage VDD. In the discharge phase (as shown in Figure 6 In the second time period T2, the first bit line BT or the second bit line BB is discharged. Specifically, the pre-charge signal end pre_n is maintained at a logic high level, the selection word line SEL is set to a logic high level, and the first bit line BT or the second bit line BB is discharged according to the data stored in the storage unit. In the discharge phase (as shown in Figure 6 In the second time period T2, when the first switch unit 103 and the second switch unit 104 are turned on, the power supply voltage end VDD is coupled to the second node dp_n and the fourth node dp respectively, so that the second node dp_n and the fourth node dp are coupled to the same potential. In the read phase (as shown in Figure 6 In the third time period T3, when the first switch unit 103 and the second switch unit 104 are turned off, the first node sout, the second node dp, the third node sout_n and the fourth node dp_n are all discharged from the power supply voltage VDD by the first switch unit 103 and the second switch unit 104, reducing the voltage difference between the second node dp and the fourth node dp_n. In the read phase, the second node dp and the fourth node dp_n are coupled to the same potential, affecting the discharge rate of the first node sout and the third node sout_n in the read phase.

[0103] Exemplarily, the voltage of node d is high ("1") and the voltage of node d_n is low ("0") are taken as examples. Referring to Figure 5a and Figure 6The process of reading the memory cell can include a first time period T1, a second time period T2 and a third time period T3, wherein the first time period T1 is a pre-charge phase of the first bit line BT and the second bit line BB, the second time period T2 is a conducting phase of the first switch unit 103 and the second switch unit 104, and a discharging phase of the first bit line BT or the second bit line BB, and the third time period T3 is a discharging phase of each node (the first node sout_n, the second node dp_n, the third node sout and the fourth node dp) in the readout unit 102.

[0104] Specifically, in the first time period T1, the pre-charge is performed, and the first bit line BT and the second bit line BB can be pre-charged to a stable voltage by the pre-charge unit 101, respectively. Specifically, referring to Figure 3 and Figure 6 In the first time period T1, the power voltage terminal VDD and the first bit line BT, and the power voltage terminal VDD and the second bit line BB are turned on by the pre-charge signal terminal pre_n, respectively, so that the first bit line BT and the second bit line BB are pre-charged to the power voltage VDD.

[0105] After the pre-charge is completed, referring to Figure 3 and Figure 6 In the second time period T2, the first bit line BT or the second bit line BB is discharged. Specifically, the pre-charge signal terminal pre_n keeps a logic high level, and at this time, the selection word line SEL is set to a logic high level, referring to Figure 3 Since the voltage of the node d is a high level (“1”) and the voltage of the node d_n is a low level (“0”), at this time, the first bit line BT will keep the power voltage VDD, and the second bit line BB will gradually discharge to the voltage VP (for example, the control discharge is 200 mV, and the voltage VP is VDD-200 mV).

[0106] Exemplarily, the power voltage VDD includes 3.3 V, and in other embodiments, a person skilled in the art can adjust the parameters of the power voltage VDD according to the actual application environment and circuit parameters.

[0107] Referring to Figure 5aDuring the first time period T1 of the read operation, the first switch unit 103 is gradually turned on and remains on during the second time period T2, coupling the second node dp to the power supply voltage terminal VDD. The voltage at the second node dp is the power supply voltage VDD. During the first time period T1 of the read operation, the second switch unit 104 is gradually turned on and remains on during the second time period T2, coupling the fourth node dp_n to the power supply voltage terminal VDD. The voltage at the fourth node dp_n is the power supply voltage VDD. Then, during the third time period T3, the first switch unit 103 and the second switch unit 104 are turned off, and the first node sout, the second node dp, the third node sout_n, and the fourth node dp_n in the read unit 102 are discharged.

[0108] Specifically, the first node sout, the second node dp, the third node sout_n, and the fourth node dp_n are discharged from the power supply voltage VDD. The readout unit 102 is coupled to the first bit line BT and the second bit line BB, respectively. According to the above analysis, the first bit line BT maintains the power supply voltage VDD, and the second bit line BB is discharged to the voltage VP. The power supply voltage VDD is greater than the voltage VP. Therefore, the discharge speed of the second node dp is faster than the discharge speed of the fourth node dp_n.

[0109] like Figure 6 As shown, an interval period may be included between the second time period T2 and the third time period T3, during which the first node sout, the second node dp, the third node sout_n, and the fourth node dp_n maintain the power supply voltage VDD. At the beginning of the third time period T3, the first node sout, the second node dp, the third node sout_n, and the fourth node dp_n discharge from the power supply voltage VDD.

[0110] refer to Figure 6 Even when exiting the write operation and entering the read operation, the second node dp is coupled to the higher level VDD+V due to the gate-drain parasitic capacitance of the transistor. THN , the voltage of the second node dp can be regulated to the power supply voltage VDD via the first switch unit 103, and the voltage of the fourth node dp_n can be regulated to the power supply voltage VDD via the second switch unit 104. Therefore, the first node sout, the second node dp, the third node sout_n, and the fourth node dp_n discharge from the power supply voltage VDD. Because the discharge rate of the second node dp is faster than the discharge rate of the fourth node dp_n, and the second node dp and the fourth node dp_n discharge from the same voltage, the voltage of the second node dp drops to 0 before the voltage of the fourth node dp_n. Ultimately, the voltage of the sout node is 0, and the voltage of the sout_n node is 1, indicating a correct reading.

[0111] It can be understood that, similar to the reading process that the voltage of node d is high ("1") and the voltage of node d_n is low ("0"), if the voltage of node d in the storage unit is low ("0") and the voltage of node d_n is high ("1"), the specific process of reading operation of the readout amplifier proposed in the embodiments of the present disclosure can be analyzed and deduced in combination with the reading process that the voltage of node d is high ("1") and the voltage of node d_n is low ("0"), and details are not repeated here.

[0112] In the discharge process, the readout amplifier proposed in the embodiments of the present disclosure controls the first node sout, the second node dp, the third node sout_n and the fourth node dp_n to discharge from the power supply voltage through the first switch unit 103 and the second switch unit 104, so as to reduce the voltage difference that may exist between the second node dp and the fourth node dp_n. Since the second node dp discharges faster than the fourth node dp_n, the second node dp can be discharged to 0 first compared with the fourth node dp_n, and the correct reading can be realized. The embodiments of the present disclosure can reduce the probability that the fourth node dp_n is discharged to 0 first compared with the second node dp, can realize correct reading of data, and improve the reading accuracy of the readout amplifier.

[0113] In some embodiments, with reference to Figure 5a or Figure 5b , the readout amplifier further comprises an enable signal line EN;

[0114] The enable signal line EN is configured to transmit an enable signal.

[0115] The first switch unit 103 and the second switch unit 104 are further coupled to the enable signal line EN, and are configured to be conductive when the enable signal is low and non-conductive when the enable signal is high.

[0116] Here, the first switch unit 103 and the second switch unit 104 can be controlled to be conductive or non-conductive through the enable signal line EN. When the enable signal is low, the first switch unit 103 is controlled to be conductive, so that the second node dp is coupled to the power supply voltage end VDD, and the second switch unit 104 is controlled to be conductive, so that the fourth node dp_n is coupled to the power supply voltage end VDD, so as to reduce the voltage difference between the fourth node dp_n and the second node dp.

[0117] The readout amplifier provided in the embodiment is synchronized to control the conduction or turn-off of the first switch unit 103 and the second switch unit 104 by the enable signal transmitted by the enable signal line EN. When the first switch unit 103 and the second switch unit 104 are synchronously conducted, the voltage of the fourth node dp_n and the voltage of the second node dp are synchronously adjusted. Compared with adding multiple enable signal lines to control the first switch unit 103 and the second switch unit 104 respectively, the first switch unit 103 and the second switch unit 104 in the embodiment are coupled to the same enable signal line, which reduces the influence of time delay on the voltage change of the fourth node dp_n and the voltage of the second node dp, thereby improving the reading operation accuracy. In addition, the way that different switch units are coupled to the same enable signal line is beneficial to reducing the area occupied by the readout amplifier and reducing the power consumption of the readout amplifier.

[0118] In some embodiments, referring to Figure 5a The first switch unit 103 comprises a first transistor Q1.

[0119] The gate of the first transistor Q1 is coupled to the enable signal line EN, the second end of the first transistor Q1 is coupled to the second node dp, and the first end of the first transistor Q1 is coupled to the power voltage end VDD.

[0120] The first transistor Q1 is configured to be conductive when the enable signal transmitted by the received enable signal line EN is a logic low level, so as to make the power voltage end VDD in communication with the second node dp.

[0121] It should be noted that the first end and the second end are the source and the drain of the transistor respectively. In an example, the first end is the source of the transistor, and the second end is the drain of the transistor. In another example, the first end is the drain of the transistor, and the second end is the source of the transistor. The gate of the first transistor Q1 can be coupled to the enable signal line EN, which is the read enable signal line in the readout amplifier, or the gate of the first transistor Q1 can be coupled to other signal lines to control the turn-off or conduction of the first switch unit 103 according to the high or low level output by the other signal lines. Here, the gate of the first transistor Q1 is coupled to the enable signal line EN as an example.

[0122] Referring to Figure 3 When the write operation is exited and the read operation is entered, the pre-charge signal end pre_n is set to a logic low level, and at this time the first bit line BT and the second bit line BB are pre-charged to the voltage VDD. Since the first bit line BT changes from the low level “0” to the high voltage VDD, referring to Figure 1 , the node dp will be coupled to a higher level due to the existence of the gate-drain parasitic capacitance of the transistor MN0. Usually, the voltage of the node dp can be coupled to VDD+V THN, and since the second bit line BB is always at voltage VDD, the voltage of node dp_n does not change and remains VDD-V THN . Node dp is discharged from a higher level VDD+V THN , and node dp_n is discharged from a lower level VDD-V THN , which can cause node dp_n and node sout_n to drop to a lower level first, and finally the voltage of the sout node is 1 and the voltage of the sout_n node is 0, resulting in a readout error.

[0123] In this embodiment, the first transistor Q1 is turned on when the enable signal is low, so that the power voltage end VDD is connected to the second node dp, and the voltage of the second node dp becomes the power voltage VDD. And control the second switch unit 104 to be turned on, so that the fourth node dp_n is coupled to the power voltage end VDD, and the voltage of the fourth node dp_n becomes the power voltage VDD, reducing the voltage difference that may exist between the second node dp and the fourth node dp_n. Since the second node dp discharges faster than the fourth node dp_n, the second node dp can be discharged to 0 first compared with the fourth node dp_n, and the readout is correct.

[0124] It should be noted that, with reference to Figure 5a , the size of the first transistor Q1 is related to the size of the ninth transistor Q9 and the size of the first bypass transistor M1.

[0125] Specifically, in an embodiment, the gate length of the first transistor Q1, the gate length of the ninth transistor Q9, and the gate length of the first bypass transistor M1 are the same, and the gate width of the first transistor Q1 is one third or one fourth of the sum of the gate width of the ninth transistor Q9 and the gate width of the first bypass transistor M1. In another embodiment, the gate length of the first transistor Q1 is one third or one fourth of the sum of the gate length of the ninth transistor Q9 and the gate length of the first bypass transistor M1, and the gate width of the first transistor Q1 is one third or one fourth of the sum of the gate width of the ninth transistor Q9 and the gate width of the first bypass transistor M1.

[0126] It can be understood that the size of the first transistor Q1 is exemplarily described here, and the size of the first transistor Q1 can be adjusted according to actual design requirements to meet the required discharge or charging requirements within a specified time.

[0127] The readout amplifier provided in the embodiment is configured to control the voltage of the second node dp when the enable signal is at a low level, so that the power supply voltage terminal VDD is connected to the second node dp, the voltage of the second node dp becomes the power supply voltage VDD, and the second switch unit 104 is controlled to be turned on, so that the fourth node dp_n is coupled to the power supply voltage terminal VDD, and the voltage of the fourth node dp_n becomes the power supply voltage VDD, thereby reducing the voltage difference between the second node dp and the fourth node dp_n. Since the second node dp is discharged faster than the fourth node dp_n, the second node dp can be discharged to 0 before the fourth node dp_n, so that the data can be correctly read out, and the readout accuracy of the readout amplifier is improved. In addition, compared with adding multiple transistors to realize the function, the method of adding only one first transistor Q1 can reduce the occupied area of the readout amplifier and reduce the power consumption of the readout amplifier.

[0128] In some embodiments, with reference to Figure 5a The second switch unit includes a second transistor Q2, wherein

[0129] The gate of the second transistor Q2 is coupled to an enable signal line EN, the second end of the second transistor Q2 is coupled to the fourth node dp_n, and the first end of the second transistor Q2 is coupled to the power supply voltage terminal VDD.

[0130] The second transistor Q2 is configured to be turned on when the enable signal transmitted by the received enable signal line EN is at a logic low level, so that the power supply voltage terminal VDD is connected to the fourth node dp_n.

[0131] It should be noted that the gate of the second transistor Q2 is coupled to the enable signal line EN, which is a read enable signal line in the readout amplifier, or the gate of the second transistor Q2 can be coupled to other signal lines to control the turn-off or turn-on of the second switch unit 104 according to the high or low level output by the other signal lines. Here, the gate of the second transistor Q2 is coupled to the enable signal line EN as an example.

[0132] Here, the second transistor Q2 is turned on when the enable signal is at a low level, so that the power supply voltage terminal VDD is connected to the fourth node dp_n, and the voltage of the fourth node dp_n becomes the power supply voltage VDD. In an embodiment, the first switch unit 103 is also controlled to be turned on, so that the voltage of the second node dp becomes the power supply voltage VDD.

[0133] Therefore, the second transistor Q2 is turned on when the enable signal is at a low level, so as to regulate the voltage of the fourth node dp_n, so that the voltage of the fourth node dp_n is the same as the voltage of the second node dp, and the voltage difference between the second node dp and the fourth node dp_n is reduced. Since the second node dp is discharged faster than the fourth node dp_n, the second node dp can be discharged to 0 before the fourth node dp_n, so as to realize correct reading.

[0134] It should be noted that, with reference to Figure 5a The size of the second transistor Q2 is related to the size of the eleventh transistor Q11 and the size of the second bypass transistor M2.

[0135] Specifically, in an embodiment, the gate length of the second transistor Q2, the gate length of the eleventh transistor Q11, and the gate length of the second bypass transistor M2 are the same, and the gate width of the second transistor Q2 is one third or one fourth of the sum of the gate width of the eleventh transistor Q11 and the gate width of the second bypass transistor M2. In another embodiment, the gate length of the second transistor Q2 is one third or one fourth of the sum of the gate length of the eleventh transistor Q11 and the gate length of the second bypass transistor M2, and the gate width of the second transistor Q2 is one third or one fourth of the sum of the gate width of the eleventh transistor Q11 and the gate width of the second bypass transistor M2.

[0136] It can be understood that the size of the second transistor Q2 is exemplarily described here, and the size of the second transistor Q2 can be adjusted according to actual design requirements to meet the required discharge or charging requirements within a specified time.

[0137] The readout amplifier provided in the embodiment has the second transistor Q2 turned on when the enable signal is at a low level, so as to regulate the voltage of the fourth node dp_n, so that the voltage of the fourth node dp_n is the same as the voltage of the second node dp, and the voltage difference between the second node dp and the fourth node dp_n is reduced. Since the second node dp is discharged faster than the fourth node dp_n, the second node dp can be discharged to 0 before the fourth node dp_n, so as to realize correct reading of data and improve the reading accuracy of the readout amplifier. Moreover, compared with adding multiple transistors to realize this function, the method of adding only one second transistor Q2 can reduce the occupied area of the readout amplifier and reduce the power consumption of the readout amplifier.

[0138] In some embodiments, with reference to Figure 5a The first switch unit 103 and the second switch unit 104 each include a P-type transistor.

[0139] It should be noted that before discharging the first node sout, the second node dp, the third node sout_n and the fourth node dp_n, the enable signal transmitted by the enable signal line EN is set to low level ("0"). In order to realize the conduction of the first switch unit 103 when the enable signal is at a logic low level ("0"), the first switch unit 103 preferably includes a P-type transistor.

[0140] It can be understood that the first switch unit 103 can also include multiple transistors to realize conduction when the enable signal is at a logic low level ("0").

[0141] The specific arrangement of the second switch unit 104 is described above with reference to the first switch unit 103, which will not be described here.

[0142] In this embodiment, the first switch unit 103 preferably includes a P-type transistor. This preferred mode not only realizes the conduction when the enable signal is at a low level, so that the power supply voltage terminal VDD is in communication with the second node dp, but also reduces the occupied area of the readout amplifier and reduces the power consumption of the readout amplifier compared to adding multiple transistors to realize this function.

[0143] In some embodiments, with reference to Figure 5a , the readout amplifier further includes a third switch unit 105, the first end of the third switch unit 105 is coupled to the second node dp, the second end of the third switch unit 105 is coupled to the fourth node dp_n, and the third end of the third switch unit 105 is coupled to the enable signal line EN; wherein

[0144] The third switch unit 105 is configured to be conductive to equalize the voltage of the second node dp and the voltage of the fourth node dp_n.

[0145] With reference to Figure 5a , the first switch unit 103 can be conductive to couple the second node dp to the power supply voltage terminal VDD, so that the voltage of the second node dp is the power supply voltage VDD. The second switch unit 104 can be conductive to couple the fourth node dp_n to the power supply voltage terminal VDD, so that the voltage of the fourth node dp_n is the power supply voltage VDD. It can be understood that since the first switch unit 103 or the second switch unit 104 can introduce noise error (for example, 10 mV), the voltage difference between the voltage of the second node dp and the voltage of the fourth node dp_n can be 20 mV due to noise error. At this time, there is a voltage difference between the voltage of the second node dp and the voltage of the fourth node dp_n.

[0146] In this embodiment, the third switch unit 105 can be turned on to make the voltage of the second node dp and the voltage of the fourth node dp_n more accurate, and further reduce the noise error of the first switch unit 103 and the second switch unit 104. Since the second node dp discharges faster than the fourth node dp_n, the second node dp can be discharged to 0 first compared with the fourth node dp_n, and the correct reading is realized.

[0147] In some embodiments, the third switch unit 105 comprises: a third transistor Q3; wherein the gate of the third transistor Q3 is coupled with the enable signal line EN, the first end of the third transistor Q3 is coupled with the second node dp, and the second end of the third transistor Q3 is coupled with the fourth node dp_n; wherein,

[0148] The third transistor Q3 is configured to be turned on when the enable signal transmitted by the received enable signal line EN is a logic low level, so as to make the second node dp and the fourth node dp_n communicate.

[0149] Here, the third transistor Q3 is turned on when the enable signal is a low level to make the second node dp and the fourth node dp_n communicate, so that the voltage of the second node dp and the voltage of the fourth node dp_n are more accurate.

[0150] Therefore, the third transistor Q3 is turned on when the enable signal is a low level, which realizes more accurate regulation of the voltage of the second node dp and the voltage of the fourth node dp_n, so that the voltage of the fourth node dp_n and the voltage of the second node dp are the same, and the voltage difference between the second node dp and the fourth node dp_n is reduced. Since the second node dp discharges faster than the fourth node dp_n, the second node dp can be discharged to 0 first compared with the fourth node dp_n, and the correct reading is realized.

[0151] It should be noted that, with reference to Figure 5a The size of the third transistor Q3 is related to the size of the first transistor Q1 and the size of the second transistor Q2.

[0152] Specifically, in an embodiment, the gate length of the third transistor Q3, the gate length of the first transistor Q1 and the gate length of the second transistor Q2 are the same, and the gate width of the third transistor Q3 is one third or one fourth of the sum of the gate width of the first transistor Q1 and the gate width of the second transistor Q2. In another embodiment, the gate length of the third transistor Q3 is one third or one fourth of the sum of the gate length of the first transistor Q1 and the gate length of the second transistor Q2, and the gate width of the third transistor Q3 is one third or one fourth of the sum of the gate width of the first transistor Q1 and the gate width of the second transistor Q2.

[0153] It can be understood that the size of the third transistor Q3 is exemplarily illustrated herein, and the size of the third transistor Q3 can be adjusted according to actual design requirements to meet the required discharge or charging requirements within a specified time.

[0154] The readout amplifier provided in the embodiment enables the third transistor Q3 to be turned on when the enable signal is at a low level, so as to control the voltage of the fourth node dp_n and the voltage of the second node dp, so that the voltage of the fourth node dp_n and the voltage of the second node dp are the same, and the voltage difference between the second node dp and the fourth node dp_n is further reduced. Since the second node dp discharges faster than the fourth node dp_n, the second node dp can be discharged to 0 before the fourth node dp_n, so that the data can be correctly read out, and the readout accuracy of the readout amplifier is improved. Moreover, compared with adding multiple transistors to realize the function, the method of adding only one third transistor Q3 can reduce the occupied area of the readout amplifier and reduce the power consumption of the readout amplifier.

[0155] In some embodiments, with reference to Figure 5a or Figure 5b The readout unit 102 includes a fourth transistor Q4 and a fifth transistor Q5, wherein

[0156] The gate of the fourth transistor Q4 and the gate of the fifth transistor Q5 are coupled with the enable signal line EN, the first end of the fourth transistor Q4 is coupled with the power voltage end VDD, the second end of the fourth transistor Q4 is coupled with the first node sout, the first end of the fifth transistor Q5 is coupled with the power voltage end VDD, and the second end of the fifth transistor Q5 is coupled with the third node sout_n.

[0157] The fourth transistor Q4 is configured to be conductive when the enable signal transmitted by the received enable signal line EN is at a logic low level, so as to couple the power voltage end VDD to the first node sout.

[0158] The fifth transistor Q5 is configured to be conductive when the enable signal transmitted by the received enable signal line EN is at a logic low level, so as to couple the power voltage end VDD to the third node sout_n.

[0159] Here, the voltage type readout amplifier 100 is taken as an example for description.

[0160] Specifically, before discharging the first node sout, the second node dp, the third node sout_n and the fourth node dp_n, the enable signal transmitted by the enable signal line EN is set to low level ("0"), the fourth transistor Q4 is controlled to be turned on by the enable signal line EN, so that the first node sout is coupled to the power supply voltage terminal VDD, and the voltage of the first node sout is the power supply voltage VDD. The fifth transistor Q5 is controlled to be turned on by the enable signal line EN, so that the third node sout_n is coupled to the power supply voltage terminal VDD, and the voltage of the third node sout_n is the power supply voltage VDD.

[0161] The enable signal transmitted by the enable signal line EN is set to high level ("1"), and the first node sout, the second node dp, the third node sout_n and the fourth node dp_n in the readout unit 102 are discharged.

[0162] Specifically, the first node sout, the second node dp, the third node sout_n and the fourth node dp_n are discharged from the power supply voltage VDD.

[0163] In this embodiment, the voltage type readout amplifier 100 is preferred to perform storage data information readout, and the power supply voltage VDD is collected by the fourth transistor Q4 and the fifth transistor Q5 in the readout unit 102, so that the first node sout, the second node dp, the third node sout_n and the fourth node dp_n are discharged from the power supply voltage VDD. The voltage type readout amplifier 100 can collect and amplify the voltage difference, and has the advantages of simple structure, high stability and low power consumption.

[0164] In some embodiments, with reference to Figure 5b The first switch unit 103 includes a sixth transistor Q6, wherein

[0165] The gate of the sixth transistor Q6 is coupled to the enable signal line EN, the second end of the sixth transistor Q6 is coupled to the second node dp, and the first end of the sixth transistor Q6 is coupled to the first node sout.

[0166] The sixth transistor Q6 is configured to be turned on when the enable signal transmitted by the received enable signal line EN is a logic low level, so that the power supply voltage terminal VDD is in communication with the second node dp.

[0167] Here, with reference to Figure 5b The power supply voltage terminal VDD is coupled to the first node sout through the fourth transistor Q4, and the power supply voltage terminal VDD is coupled to the second node dp through the fourth transistor Q4 and the sixth transistor Q6.

[0168] In this embodiment, the sixth transistor Q6 is turned on when the enable signal is low, so that the power supply voltage terminal VDD is communicated with the second node dp through the fourth transistor Q4, and the voltage of the second node dp becomes the power supply voltage VDD. In addition, the second switch unit 104 is controlled to be turned on, so that the fourth node dp_n is coupled to the power supply voltage terminal VDD through the fifth transistor Q5, and the voltage of the fourth node dp_n becomes the power supply voltage VDD, thereby reducing the voltage difference between the second node dp and the fourth node dp_n. Since the second node dp discharges faster than the fourth node dp_n, the second node dp can be discharged to 0 before the fourth node dp_n, and correct reading can be realized.

[0169] It should be noted that the size of the sixth transistor Q6 can refer to the related description of the first transistor Q1 in the above Figure 5a embodiment, which will not be described here.

[0170] The readout amplifier provided in this embodiment includes the sixth transistor Q6, which is turned on when the enable signal is low, so that the power supply voltage terminal VDD is communicated with the second node dp through the fourth transistor Q4, and the voltage of the second node dp becomes the power supply voltage VDD. In addition, the second switch unit 104 is controlled to be turned on, so that the fourth node dp_n is coupled to the power supply voltage terminal VDD through the fifth transistor Q5, and the voltage of the fourth node dp_n becomes the power supply voltage VDD, thereby reducing the voltage difference between the second node dp and the fourth node dp_n. Since the second node dp discharges faster than the fourth node dp_n, the second node dp can be discharged to 0 before the fourth node dp_n, and correct reading can be realized, thereby improving the reading accuracy of the readout amplifier. In addition, compared with adding multiple transistors to realize this function, the method of adding only one sixth transistor Q6 can reduce the occupied area of the readout amplifier and reduce the power consumption of the readout amplifier. In addition, compared with the readout amplifier shown in Figure 5a Figure 5b the readout amplifier provided in this embodiment reduces the number of power supply voltage terminals, thereby reducing the manufacturing cost of the readout amplifier.

[0171] In some embodiments, referring to Figure 5b the second switch unit 104 includes: a seventh transistor Q7; wherein

[0172] The gate of the seventh transistor Q7 is coupled to the enable signal line EN, the second end of the seventh transistor Q7 is coupled to the fourth node dp_n, and the first end of the seventh transistor Q7 is coupled to the third node sout_n;

[0173] The seventh transistor Q7 is configured to be turned on when the enable signal transmitted by the received enable signal line EN is a logic low level, so that the power supply voltage terminal VDD is communicated with the fourth node dp_n.​

[0174] Here, referring to Figure 5b , the power voltage terminal VDD is coupled with the third node sout_n through the fifth transistor Q5, and the power voltage terminal VDD is coupled with the fourth node dp_n through the fifth transistor Q5 and the seventh transistor Q7.

[0175] In this embodiment, the seventh transistor Q7 is turned on when the enable signal is at a low level, so that the power voltage terminal VDD is connected with the fourth node dp_n through the fifth transistor Q5, and the voltage of the fourth node dp_n becomes the power voltage VDD. In an embodiment, the first switch unit 103 is also controlled to be turned on, so that the voltage of the second node dp becomes the power voltage VDD.

[0176] Therefore, the seventh transistor Q7 is turned on when the enable signal is at a low level, so as to regulate the voltage of the fourth node dp_n, so that the voltage of the fourth node dp_n and the voltage of the second node dp are the same, and the voltage difference between the second node dp and the fourth node dp_n is reduced. Since the second node dp discharges faster than the fourth node dp_n, the second node dp can be discharged to 0 first compared with the fourth node dp_n, and correct reading is realized.

[0177] It should be noted that the size of the seventh transistor Q7 can refer to the related description of the second transistor Q2 in the above Figure 5a , which will not be described here.

[0178] The readout amplifier provided in this embodiment, the seventh transistor Q7 is turned on when the enable signal is at a low level, so as to regulate the voltage of the fourth node dp_n, so that the voltage of the fourth node dp_n and the voltage of the second node dp are the same, and the voltage difference between the second node dp and the fourth node dp_n is reduced. Since the second node dp discharges faster than the fourth node dp_n, the second node dp can be discharged to 0 first compared with the fourth node dp_n, and correct reading is realized, which improves the reading accuracy of the readout amplifier. Moreover, compared with adding multiple transistors to realize this function, adding only one seventh transistor Q7 can reduce the occupied area of the readout amplifier and reduce the power consumption of the readout amplifier.

[0179] In some embodiments, referring to Figure 5a or Figure 5b , the readout unit 102 includes: a first inverter 1021, a second inverter 1022, and a bypass transistor unit 1023; wherein,

[0180] The input end of the first inverter 1021 is coupled with the output end of the second inverter 1022, and the output end of the first inverter 1021 is coupled with the input end of the second inverter 1022;

[0181] The output end of the first inverter 1021 and the output end of the second inverter 1022 are coupled with the input end of the bypass transistor unit 1023, and the output end of the bypass transistor unit 1023 is grounded.

[0182] Here, the readout amplifier 100 of the voltage latch type is taken as an example for description.

[0183] The readout amplifier 100 of the voltage latch type can be formed in the form of a latch formed by two CMOS inverters (for example, the first inverter 1021 and the second inverter 1022) facing each other, as shown in FIG. 1. Figure 5a Or Figure 5b The output voltage signals of the first inverter 1021 and the second inverter 1022 can reach full swing. Since the larger the voltage signal swing is, the more obvious the fluctuation of the voltage signal is, and the effective output voltage signal is easy to be generated, therefore, the voltage latch type readout amplifier 100 whose output voltage signal can reach full swing is preferred.

[0184] In the embodiment, the voltage latch type readout amplifier 100 is preferred to read the stored data information, amplify the voltage difference on the first bit line BT and the second bit line BB through the first inverter 1021, the second inverter 1022 and the bypass transistor unit 1023, and has the advantages of fast readout speed and more effective output voltage signal.

[0185] In some embodiments, referring to Figure 5a Or Figure 5b The first inverter 1021 includes an eighth transistor Q8 and a ninth transistor Q9, and the second inverter 1022 includes a tenth transistor Q10 and an eleventh transistor Q11; wherein,

[0186] The gate of the eighth transistor Q8 and the gate of the ninth transistor Q9 are coupled with the output end of the second inverter 1022, the first end of the eighth transistor Q8 is coupled with the power voltage end VDD, the second end of the eighth transistor Q8 and the second end of the ninth transistor Q9 are coupled with the first node sout, and the first end of the ninth transistor Q9 is coupled with the second node dp;

[0187] The gate of the tenth transistor Q10 and the gate of the eleventh transistor Q11 are coupled with the output end of the first inverter 1021, the first end of the tenth transistor Q10 is coupled with the power voltage end VDD, the second end of the tenth transistor Q10 and the second end of the eleventh transistor Q11 are coupled with the third node sout_n, and the first end of the eleventh transistor Q11 is coupled with the fourth node dp_n.

[0188] Here, the eighth transistor Q8 and the ninth transistor Q9 in the first inverter 1021 are cross-coupled with the ninth transistor Q9 and the tenth transistor Q10 in the second inverter 1022, so as to latch the voltages provided by the first node sout and the third node sout_n, respectively, during a latch mode; wherein the latch mode includes a period when the enable signal transmitted by the enable signal line EN is at a low level ("0").

[0189] After entering the read mode from the latch mode, the enable signal transmitted by the enable signal line EN is set to a high level ("1"), and the first node sout, the second node dp, the third node sout_n and the fourth node dp_n in the read unit 102 are discharged.

[0190] In the present embodiment, in order to improve the read accuracy and the performance of the sense amplifier 100, the transistor parameters in the first inverter 1021 and the second inverter 1022 can be adjusted, specifically, the eighth transistor Q8 in the first inverter 1021 and the tenth transistor Q10 in the second inverter 1022 are set to have equal or substantially equal driving strengths. Similarly, the ninth transistor Q9 in the first inverter 1021 and the eleventh transistor Q11 in the second inverter 1022 are set to have equal or substantially equal driving strengths.

[0191] In the present embodiment, the voltage-latch type sense amplifier 100 is preferred for reading the stored data information, amplifies the voltage difference on the first bit line BT and the second bit line BB through the first inverter 1021, the second inverter 1022 and the bypass transistor unit 1023, and has the advantages of fast read speed and more effective output voltage signal.

[0192] In some embodiments, referring to Figure 5a or Figure 5b The eighth transistor Q8 and the tenth transistor Q10 include P-type transistors, and the ninth transistor Q9 and the eleventh transistor Q11 include N-type transistors.

[0193] For example, the eighth transistor Q8 and the tenth transistor Q10 are P-type transistors. When the gate voltages of these P-type transistors are below the threshold voltage, these P-type transistors will be turned on and supply a positive voltage of the voltage terminal marked as "VDD" to the corresponding nodes (the first node sout and the third node sout_n), thereby "pulling up strongly" at the node. Since the eighth transistor Q8 and the tenth transistor Q10 are PMOS pull-up strong driving, the discharge change of the first node sout and the third node sout_n will be very fast, thereby achieving the effect of accelerating the read speed.

[0194] Exemplarily, the ninth transistor Q9 and the eleventh transistor Q11 are N-type transistors, which will be turned on and discharge the corresponding nodes (the first node sout and the third node sout_n) to the ground terminal or the voltage terminal providing negative voltage when the gate voltage of the N-type transistors exceeds the threshold voltage.

[0195] In the embodiment, the eighth transistor Q8 and the tenth transistor Q10 include P-type transistors, and the ninth transistor Q9 and the eleventh transistor Q11 include N-type transistors, which are discharged quickly through the eighth transistor Q8 and the tenth transistor Q10, the ninth transistor Q9 and the eleventh transistor Q11, thereby achieving the effect of accelerating the reading speed.

[0196] In some embodiments, referring to Figure 5a or Figure 5b , the bypass transistor unit 1023 includes a first bypass transistor M1, a second bypass transistor M2, a third bypass transistor M3 and a fourth bypass transistor M4; wherein,

[0197] The gate of the first bypass transistor M1 is coupled with the first bit line BT, and the second end of the first bypass transistor M1 is coupled with the output end of the first inverter 1021;

[0198] The gate of the second bypass transistor M2 is coupled with the second bit line BB, and the second end of the second bypass transistor M2 is coupled with the output end of the second inverter 1022;

[0199] The first end of the first bypass transistor M1 and the first end of the second bypass transistor M2 are coupled with the second end of the third bypass transistor M3, the first end of the third bypass transistor M3 is grounded, and the gate of the third bypass transistor M3 is coupled with the enable signal line EN;

[0200] The first end of the fourth bypass transistor M4 is coupled with the output end of the second inverter 1022, the second end of the fourth bypass transistor M4 is coupled with the output end of the first inverter 1021, and the gate of the fourth bypass transistor M4 is coupled with the enable signal line EN.

[0201] Exemplarily, the first bypass transistor M1, the second bypass transistor M2 and the third bypass transistor M3 are turned on when the enable signal transmitted by the enable signal line EN is set to high level, and discharge the corresponding nodes (such as the second node dp and the fourth node dp_n in Figure 7 or Figure 7 ) to the ground terminal or the voltage terminal providing negative voltage.

[0202] In another embodiment, the first end of the third bypass transistor M3 is grounded, which reduces the power consumption of the third bypass transistor M3 caused by the enable signal in the logic "low" state received by the gate when the readout amplifier 100 is not working.

[0203] Here, the gate of the first bypass transistor M1 is coupled with the first bit line BT, the gate of the second bypass transistor M2 is coupled with the second bit line BB, and the readout amplifier 100 collects the voltage value transmitted by the first bit line BT through the first bypass transistor M1 and collects the voltage value of the second bit line BB through the second bypass transistor M2, so that the voltage difference on the first bit line BT and the second bit line BB can be collected and amplified by the readout unit 102 of the readout amplifier 100, and the readout amplifier 100 has the advantages of simple structure, high stability and low power consumption.

[0204] In this embodiment, the voltage difference on the first bit line BT and the second bit line BB is amplified by the first inverter 1021, the second inverter 1022 and the bypass transistor unit 1023, and the readout speed is fast and the output voltage signal is more effective. And the structure of the bypass transistor unit 1023 is simple, and the required control signal is less, that is, the discharge can be realized, which is convenient for preparation and can greatly reduce the production cost.

[0205] In some embodiments, with reference to Figure 7 or Figure 7 The first bypass transistor M1, the second bypass transistor M2 and the third bypass transistor M3 all include N-type transistors, and the fourth bypass transistor M4 includes a P-type transistor.

[0206] Exemplarily, the first bypass transistor M1, the second bypass transistor M2 and the third bypass transistor M3 are N-type transistors, and when the gate voltage of the N-type transistors exceeds the threshold voltage, the N-type transistors will be turned on.

[0207] Exemplarily, the fourth bypass transistor M4 includes a P-type transistor, and the gate of the fourth bypass transistor M4 is coupled with the enable signal line EN and is configured to be turned on when the enable signal is at a low level (“0”) and turned off when the enable signal is at a high level (“1”). The fourth bypass transistor M4 is turned on during the latch mode to regulate the voltage of the first node sout and the voltage of the third node sout_n, so that the voltage of the first node sout and the voltage of the third node sout_n are the same, further reducing the voltage difference that may exist between the first node sout and the third node sout_n; wherein the latch mode includes the period when the enable signal transmitted by the enable signal line EN is at a low level.

[0208] After entering the readout mode after the latch mode, the enable signal transmitted by the enable signal line EN is set to a high level, and the fourth bypass transistor M4 is turned off. At this time, the first node sout, the second node dp, the third node sout_n and the fourth node dp_n in the readout unit 102 are discharged.

[0209] In this embodiment, the first bypass transistor M1, the second bypass transistor M2 and the third bypass transistor M3 preferably comprise N-type transistors to be turned on when the enable signal transmitted by the enable signal line EN is at a high level, so that the required control signal can be reduced to realize discharging, thereby facilitating the reduction of production cost. The fourth bypass transistor M4 preferably comprises a P-type transistor, and the gate of the fourth bypass transistor M4 is coupled to the enable signal line EN to be turned on when the enable signal is at a low level, thereby realizing the regulation of the voltage of the first node sout and the voltage of the third node sout n, further reducing the voltage difference that may exist between the first node sout and the third node sout n, and achieving correct reading of data, thereby improving the reading accuracy of the sense amplifier.

[0210] Figure 3 A schematic diagram of a memory according to an exemplary embodiment is shown. Based on the above-mentioned sense amplifier structure, the embodiment of the present disclosure provides a memory, such as Figure 3 As shown, the memory 700 comprises a plurality of storage units and a sense amplifier according to the above-mentioned embodiment; wherein,

[0211] The storage unit is coupled to the sense amplifier and is configured to store first data or second data; wherein, the first data comprises a logic high level, and the second data comprises a logic low level.

[0212] The sense amplifier is configured to read the data stored in the storage unit and amplify the data.

[0213] It should be noted that, with reference to Figure 3 , the storage unit is coupled to the sense amplifier through the first bit line BT and the second bit line BB, and the data stored in the storage unit is read out through the sense amplifier. Specifically, the sense amplifier collects and amplifies the voltage difference on the first bit line BT and the second bit line BB, and finally outputs the amplified signal, which represents the data stored in the storage unit.

[0214] In some embodiments, the memory comprises a static random access memory, and the storage unit comprises a static random access memory cell.

[0215] Exemplarily, the memory comprises a static random access memory SRAM, and the storage unit can comprise a static random access memory cell (SRAM cell) as shown in Figure 3

[0216] In some embodiments, with reference to Figure 3 , the static random access memory cell comprises a first PMOS transistor P1, a first NMOS transistor P2, a second PMOS transistor P3, a second NMOS transistor P4, a third NMOS transistor P5 and a fourth NMOS transistor P6; wherein,

[0217] ​The gate of the first PMOS transistor P1 is coupled with the gate of the first NMOS transistor P2, the first end of the first PMOS transistor P1 is coupled with the power voltage terminal VDD, the second end of the first PMOS transistor P1 is coupled with the second end of the first NMOS transistor P2, and the first end of the first NMOS transistor P2 is grounded;

[0218] The gate of the second PMOS transistor P3 is coupled with the gate of the second NMOS transistor P4, the first end of the second PMOS transistor P3 is coupled with the power voltage terminal VDD, the second end of the second PMOS transistor P3 is coupled with the second end of the second NMOS transistor P4, and the first end of the second NMOS transistor P4 is grounded;

[0219] The gate of the third NMOS transistor P5 is coupled with the selection word line SEL, the first end of the third NMOS transistor P5 is coupled with the first bit line BT, the second end of the third NMOS transistor P5 is coupled with the second end of the first PMOS transistor P1, the gate of the fourth NMOS transistor P6 is coupled with the selection word line SEL, the first end of the fourth NMOS transistor P6 is coupled with the second bit line BB, and the second end of the fourth NMOS transistor P6 is coupled with the second end of the second PMOS transistor P3.

[0220] Exemplarily, referring to Figure 3 , Figure 3 a specific structure of a static random access memory cell is shown. Figure 3 The basic structure of the memory cell shown includes six transistors (e.g. Figure 8 transistors P1 to P6). Data information is stored in two cross-coupled inverters (e.g. Figure 8 consisting of transistors P1 to P4) in the memory cell through the selection word line SEL. Figure 8 The memory cell shown has two stable states (e.g. logic states "1" or "0") to indicate the stored data information, in particular, the logic state is represented by the voltage of node d and the voltage of node d_n. Figure 9a The memory cell shown also includes transistors P5 and P6 to control the read and write operations of the memory cell.

[0221] In another embodiment, the static random access memory cell can also include other memory cells that perform read operation in a differential-signal manner.

[0222] Figure 8 a schematic diagram of a memory system according to an exemplary embodiment is shown. Based on the memory structure described above, the embodiments of the present disclosure provide a memory system, as Figure 9b shown, including the memory as described in the above embodiments, and a memory controller; wherein,

[0223] Memory 700;

[0224] Memory controller 706 coupled to memory 700 is configured to control memory 700.

[0225] Memory system 800 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage.

[0226] As shown in FIG. 8A, memory system 800 can include a host 708 and a storage subsystem 702 having one or more memories 700. Storage subsystem 702 also includes a memory controller 706. Host 708 can be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. Host 708 can be configured to send data to memory 700. Alternatively, host 708 can be configured to receive data from memory 700. Figure 8

[0227] Memory 700 can be any memory disclosed in the present disclosure.

[0228] According to some embodiments, memory controller 706 is also coupled to host 708. Memory controller 706 can manage data stored in memory 700 and communicate with host 708.

[0229] In some embodiments, memory controller 706 is designed for operation in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0230] In some embodiments, memory controller 706 is designed for operation in a high duty cycle environment, such as a solid state drive (SSD) or an embedded multimedia card (eMMC) used as data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0231] ​The memory controller 706 may be configured to control operations of the memory 700, such as read and write operations. The memory controller 706 may also be configured to manage various functions related to data stored or to be stored in the memory 700, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 706 is further configured to process error correction code (ECC) on data read from or written to the memory 700.

[0232] The memory controller 706 may also perform any other suitable functions, such as formatting the memory 700. The memory controller 706 may communicate with an external device (e.g., the host 708) according to a specific communication protocol. For example, the memory controller 706 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini-interface (SCSI) protocol, an enhanced minidisk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0233] The memory controller 706 and one or more memories 700 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 800 can be implemented and packaged into different types of terminal electronic products.

[0234] In such Figure 10 In one example shown in FIG, the memory controller 706 and the single memory 700 may be integrated into a memory card 802. The memory card 802 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 802 may also include a memory card that connects the memory card 802 to a host (e.g., ​ A memory card connector 804 coupled to the host 708).

[0235] In such ​ In another example shown in FIG, the memory controller 706 and the plurality of memories 700 may be integrated into a solid state drive (SSD) 806. The solid state drive 806 may also include a processor that interfaces the solid state drive 806 with a host (e.g., ​The solid state drive connector 808 is coupled to the host 708 in the computer 700. In some embodiments, the storage capacity and / or operating speed of the solid state drive 806 is greater than the storage capacity and / or operating speed of the memory card 802.

[0236] It can be understood that the memory controller 706 can perform the reading method as provided in any of the embodiments of the present disclosure.

[0237] ​ A flowchart of an operation method of the sense amplifier according to an exemplary embodiment is shown. Based on the structure of the sense amplifier described above, the embodiments of the present disclosure provide an operation method of the sense amplifier, which includes the following steps.

[0238] S10: pre-charging the first bit line and the second bit line to the power supply voltage in a pre-charging stage;

[0239] S20: coupling the power supply voltage terminal to the second node and the fourth node to make the second node and the fourth node coupled to the same potential when the first switch unit and the second switch unit are turned on in a discharging stage.

[0240] S30: discharging the first node and the third node when the first switch unit and the second switch unit are turned off in a reading stage.

[0241] It should be noted that the specific implementation process of the operation method of the sense amplifier provided in the embodiments of the present disclosure can refer to the above-mentioned embodiments of the sense amplifier, which will not be described here.

[0242] It can be understood that the pre-charging unit 101, the sense unit 102, the first bit line BT, the second bit line BB, the first switch unit 103 and the second switch unit 104 in the embodiments of the present disclosure can be manufactured by using a conventional integrated circuit processing technology, and the process conditions have no special requirements and can be compatible with the conventional MOS processing technology.

[0243] Here, it is preferred that the pre-charging unit 101, the sense unit 102, the first bit line BT, the second bit line BB, the first switch unit 103 and the second switch unit 104 are prepared and formed in the same MOS processing technology process, which is convenient for simplifying the process flow and saving manufacturing cost.

[0244] It should be understood that the "some embodiments" mentioned throughout the specification are meant to refer to particular features, structures, or characteristics related to embodiments that include the recited elements in at least one of the embodiments. Thus, they are not necessarily meant to refer to the same embodiments in each instance when they are used in this specification. Furthermore, these features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the sequence of the above-mentioned processes does not mean the order of execution, and the execution order of the processes should be determined according to their functions and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The above-mentioned sequence of the embodiments of the present disclosure is only for description, and does not represent the advantages or disadvantages of the embodiments.

[0245] The above description is merely a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure.

Claims

1. A sense amplifier, characterized in that: The readout amplifier comprises a pre-charge unit, a readout unit, a first switch unit and a second switch unit; wherein The pre-charge unit is coupled to a first bit line of a storage unit and a second bit line of the storage unit; The readout unit comprises a first node, a second node, a third node and a fourth node; wherein a power supply voltage terminal is coupled to the first node, and the power supply voltage terminal is coupled to the third node; The first switch unit is coupled to the power supply voltage terminal and the second node; The second switch unit is coupled to the power supply voltage terminal and the fourth node; In the readout amplifier, the second node and the fourth node are coupled to the same potential in a discharging stage. The readout amplifier further comprises an enable signal line; 2. The sense amplifier of claim 1, wherein, The enable signal line is configured to transmit an enable signal; The first switch unit and the second switch unit are further coupled to the enable signal line respectively, and are configured to be conductive when the enable signal is at a low level and non-conductive when the enable signal is at a high level. The first switch unit comprises a first transistor; wherein 3. The sense amplifier of claim 1, wherein, The gate of the first transistor is coupled to the enable signal line, the second end of the first transistor is coupled to the second node, and the first end of the first transistor is coupled to the power supply voltage terminal; The first transistor is configured to be conductive when the enable signal transmitted by the received enable signal line is at a logic low level, so as to make the power supply voltage terminal communicate with the second node. The second switch unit comprises a second transistor; wherein 4. The sense amplifier of claim 1, wherein, The gate of the second transistor is coupled to the enable signal line, the second end of the second transistor is coupled to the fourth node, and the first end of the second transistor is coupled to the power supply voltage terminal; The second transistor is configured to be conductive when the enable signal transmitted by the received enable signal line is at a logic low level, so as to make the power supply voltage terminal communicate with the fourth node. The first switch unit and the second switch unit both comprise P-type transistors.

5. The sense amplifier of claim 1, wherein, The readout amplifier further comprises a third switch unit, the first end of the third switch unit is coupled to the second node, the second end of the third switch unit is coupled to the fourth node, and the third end of the third switch unit is coupled to the enable signal line; wherein 6. The sense amplifier of claim 1, wherein, The third switch unit is configured to be conductive, so as to make the voltage of the second node equal to the voltage of the fourth node. The third switch unit comprises a third transistor; wherein the gate of the third transistor is coupled to the enable signal line, the first end of the third transistor is coupled to the second node, and the second end of the third transistor is coupled to the fourth node; wherein 7. The sense amplifier of claim 6, wherein, The third transistor is configured to be conductive when the enable signal transmitted by the received enable signal line is at a logic low level, so as to make the second node and the fourth node communicate. The readout unit comprises a fourth transistor and a fifth transistor; wherein 8. The sense amplifier of claim 1, wherein, ​ The gate of the fourth transistor and the gate of the fifth transistor are both coupled with an enable signal line, the first end of the fourth transistor is coupled with the power voltage end, the second end of the fourth transistor is coupled with the first node, the first end of the fifth transistor is coupled with the power voltage end, and the second end of the fifth transistor is coupled with the third node. The fourth transistor is configured to be conductive when the enable signal transmitted by the received enable signal line is a logic low level, so as to couple the power voltage end to the first node. The fifth transistor is configured to be conductive when the enable signal transmitted by the received enable signal line is a logic low level, so as to couple the power voltage end to the third node.

9. The sense amplifier of claim 1, wherein, The first switch unit comprises a sixth transistor; wherein The gate of the sixth transistor is coupled with an enable signal line, the second end of the sixth transistor is coupled with the second node, and the first end of the sixth transistor is coupled with the first node. The sixth transistor is configured to be conductive when the enable signal transmitted by the received enable signal line is a logic low level, so as to communicate the power voltage end with the second node.

10. The sense amplifier of claim 1, wherein, The second switch unit comprises a seventh transistor; wherein The gate of the seventh transistor is coupled with an enable signal line, the second end of the seventh transistor is coupled with the fourth node, and the first end of the seventh transistor is coupled with the third node. The seventh transistor is configured to be conductive when the enable signal transmitted by the received enable signal line is a logic low level, so as to communicate the power voltage end with the fourth node.

11. The sense amplifier of claim 2, wherein, The readout unit comprises a first inverter, a second inverter and a bypass transistor unit; wherein The input end of the first inverter is coupled with the output end of the second inverter, and the output end of the first inverter is coupled with the input end of the second inverter. The output end of the first inverter and the output end of the second inverter are respectively coupled with the input end of the bypass transistor unit, and the output end of the bypass transistor unit is grounded.

12. The sense amplifier of claim 11, wherein, The first inverter comprises an eighth transistor and a ninth transistor, and the second inverter comprises a tenth transistor and an eleventh transistor; wherein The gate of the eighth transistor and the gate of the ninth transistor are coupled with the output end of the second inverter, the first end of the eighth transistor is coupled with the power voltage end, the second end of the eighth transistor and the second end of the ninth transistor are coupled with the first node, and the first end of the ninth transistor is coupled with the second node. The gate of the tenth transistor and the gate of the eleventh transistor are coupled with the output end of the first inverter, the first end of the tenth transistor is coupled with the power voltage end, the second end of the tenth transistor and the second end of the eleventh transistor are coupled with the third node, and the first end of the eleventh transistor is coupled with the fourth node.

13. The sense amplifier of claim 12, wherein, The eighth transistor and the tenth transistor comprise P-type transistors, and the ninth transistor and the eleventh transistor comprise N-type transistors.

14. The sense amplifier of claim 11, wherein, The bypass transistor unit comprises a first bypass transistor, a second bypass transistor, a third bypass transistor and a fourth bypass transistor; wherein, the gate of the first bypass transistor is coupled with the first bit line, and the second end of the first bypass transistor is coupled with the output end of the first inverter; the gate of the second bypass transistor is coupled with the second bit line, and the second end of the second bypass transistor is coupled with the output end of the second inverter; the first end of the first bypass transistor and the first end of the second bypass transistor are coupled with the second end of the third bypass transistor, the first end of the third bypass transistor is grounded, and the gate of the third bypass transistor is coupled with the enable signal line; the first end of the fourth bypass transistor is coupled with the output end of the second inverter, the second end of the fourth bypass transistor is coupled with the output end of the first inverter, and the gate of the fourth bypass transistor is coupled with the enable signal line.

15. The sense amplifier of claim 14, wherein, The first bypass transistor, the second bypass transistor and the third bypass transistor all comprise N-type transistors, and the fourth bypass transistor comprises a P-type transistor.

16. A memory, comprising: It comprises: a plurality of storage units and the read-out amplifier according to any one of claims 1 to 15; wherein, the storage unit, coupled with the read-out amplifier, is configured to store data; the read-out amplifier is configured to read the data stored in the storage unit and amplify the data.

17. The memory of claim 16, wherein, The storage unit comprises a static random access memory, and the storage unit comprises a static random access memory unit.

18. The memory of claim 17, wherein, The static random access memory unit comprises a first PMOS tube, a first NMOS tube, a second PMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube; wherein, the gate of the first PMOS tube is coupled with the gate of the first NMOS tube, the first end of the first PMOS tube is coupled with the power voltage end, the second end of the first PMOS tube is coupled with the second end of the first NMOS tube, and the first end of the first NMOS tube is grounded; the gate of the second PMOS tube is coupled with the gate of the second NMOS tube, the first end of the second PMOS tube is coupled with the power voltage end, the second end of the second PMOS tube is coupled with the second end of the second NMOS tube, and the first end of the second NMOS tube is grounded; the gate of the third NMOS tube is coupled with a selection word line, the first end of the third NMOS tube is coupled with a first bit line, the second end of the third NMOS tube is coupled with the second end of the first PMOS tube, the gate of the fourth NMOS tube is coupled with the selection word line, the first end of the fourth NMOS tube is coupled with a second bit line, and the second end of the fourth NMOS tube is coupled with the second end of the second PMOS tube.

19. A memory system, comprising: It comprises the memory according to any one of claims 16 to 18 and a memory controller; wherein, the memory; the memory controller is coupled to the memory and is configured to control the memory.

20. A method of operating a sense amplifier, comprising: The method comprises: In a pre-charge phase, the first bit line and the second bit line are pre-charged to a power supply voltage; In a discharge phase, when the first switch unit and the second switch unit are turned on, a power supply voltage terminal is coupled to the second node and the power supply voltage terminal is coupled to the fourth node, so that the second node and the fourth node are coupled to the same potential; In a read phase, when the first switch unit and the second switch unit are turned off, the first node and the third node are discharged.

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