Symmetrical Fusion Vision Sensor Pixel Structure and Its Preparation and Signal Control Method

Abstract

The present invention relates to a symmetric fusion vision sensor pixel structure, its preparation and signal control method. The dynamic vision sensor pixel includes: a hybrid substrate, a buried oxide layer, four pixel active regions, four readout transistor active regions, an ohmic contact region, five top silicon channel regions, and a gate oxide layer, a gate, two deep trench isolation sidewalls, a shallow trench isolation sidewall, a gate sidewall, a gate metal contact, a source metal contact, a drain metal contact, and a substrate metal contact on the channel regions. Compared with the prior art, based on a single-transistor optoelectronic in-situ detector structure, the present invention can simultaneously read out the absolute light intensity signal and the differential signal inside a compact pixel architecture, realizing the fusion of the light intensity data of a traditional image sensor and the event data of a dynamic vision sensor, and laying a foundation for the application of PISD in the next-generation new dynamic vision sensor.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor image sensing, and relates to a symmetric fusion vision sensor pixel structure and its preparation and signal control method. Background Art

[0002] Mainstream technologies represented by CMOS image sensors (CIS) have been developed and matured. However, its basic principle is that the PN junction performs photoelectric integration within one frame exposure time, so it is not conducive to imaging high-speed dynamic images with a large dynamic range (High Dynamic Range). In the past ten years or so, dynamic vision sensors (Dynamic Vision Sensor) have attracted extensive interest in the academic and industrial fields. Dynamic vision technologies based on event cameras and frame difference methods have been proposed, which are expected to solve the bottleneck of traditional CIS technology in dynamic imaging applications (see G. Kim, M. Barangi, Z. Foo, N. Pinckney, S. Bang, D. Blaauw, and D. Sylvester, "A 467nW CMOS visual motion sensor with temporal averaging and pixel aggregation." pp. 480-481. and C. Li, L. Longinotti, F. Corradi, and T. Delbruck, "A 132 by 104 10μm-Pixel 250μW 1kefps Dynamic Vision Sensor with Pixel-Parallel Noise and Spatial Redundancy Suppression." pp. C216-C217.).

[0003] Dynamic vision sensors have many advantages, such as a larger dynamic range, less data redundancy, and lower power consumption. Therefore, they can be widely applied in fields such as autonomous driving, behavior detection, and feature recognition (see K.D. Choo, L. Xu, Y. Kim, J.H. Seol, X. Wu, D. Sylvester, and D. Blaauw, "5.2 Energy-Efficient Low-Noise CMOS Image Sensor with Capacitor Array-Assisted Charge-Injection SAR ADC for Motion-Triggered Low-Power IoT Applications." pp. 96-98. and B. Son, Y. Suh, S. Kim, H. Jung, J.S. Kim, C. Shin, K. Park, K. Lee, J. Park, J. Woo, Y. Roh, H. Lee, Y. Wang, I. Ovsiannikov, and H. Ryu, "4.1 A 640×480 dynamic vision sensor with a 9µm pixel and 300Meps address-event representation." pp. 66-67.). However, event-based technologies generally only output motion signals and cannot provide the gray value of the pixel itself. In addition, both event cameras and frame difference methods currently require a large number of in-pixel circuits, resulting in complex pixel structures and reduced fill factors.

[0004] To solve the above problems, the present invention provides a symmetric fusion vision sensor pixel structure. Summary of the Invention

[0005] The object of the present invention is to provide a symmetric fusion vision sensor pixel structure and its preparation and signal control method to output absolute light intensity signals and differential light intensity signals while achieving a compact structure.

[0006] Based on the principle of a single-transistor optoelectronic in-situ detection device (PISD) (see J. Liu, Y. F. Cao, X. J. Wang, Y. L. Jiang, and J. Wan, “A Novel One-Transistor Active Pixel Sensor With Tunable Sensitivity,” IEEE Electron Device Letters, vol. 42, no. 6, pp. 927-930, Apr, 2021.), the present invention designs a brand-new compact pixel structure based on the frame difference method and its signal control method. The innovation of the present invention lies in introducing two reset gates on both sides of the pixel transistor to control the differential capacitance operation on both sides, and the result is amplified and read out through two differential signal readout transistors. Therefore, the absolute light intensity signals and differential signals of consecutive frames can be fused and output simultaneously in a compact pixel structure.

[0007] The object of the present invention can be achieved by the following technical solutions:

[0008] One of the technical solutions of the present invention provides a symmetric fusion vision sensor pixel structure, including a hybrid substrate, and a left substrate and a right substrate respectively located on the left and right sides of the hybrid substrate. Among them,

[0009] A shallow trench isolation sidewall and a substrate ohmic contact region are formed on the hybrid substrate, and support the first buried oxide layer above and the first top layer region of the uppermost layer. The first top layer region includes four pixel active regions, a first top layer channel region located between two adjacent pixel active regions. Above the three first top layer channel regions, a body gate and two reset gates are respectively provided. The two reset gates are respectively located on both sides of the body gate. The body gate and the reset gate respectively control the on / off of the corresponding first top layer channel region through the gate oxide layer below them. Protective sidewalls are formed on both sides of the body gate and the reset gate, and deep trench isolation sidewalls are formed on the left and right sides of the hybrid substrate.

[0010] The left substrate supports the second buried oxide layer above and the second top layer region of the uppermost layer. The second top layer region includes two first read transistor active regions and a second top layer channel region located between the two first read transistor active regions. A first read transistor gate is provided above the second top layer channel region, and the first read transistor gate also controls the on / off of the second top layer channel region through the gate oxide layer below it. Protective sidewalls are also formed on both sides of the first read transistor gate.

[0011] The right substrate supports the upper third buried oxide layer and the uppermost third top region. The third top region includes two second read transistor active regions and a third top channel region located between the two second read transistor active regions. A second read transistor gate is provided above the third top channel region, and the second read transistor gate also controls the on / off state of the third top channel region through the gate oxide layer below it. Protective sidewalls are also formed on both sides of the second read transistor gate.

[0012] Source metal contact electrodes are also respectively provided on the pixel active region to the left of the main gate, the first read transistor active region to the right of the first read transistor gate, and the second read transistor active region to the left of the second read transistor gate. Drain metal contact electrodes are also respectively provided on the pixel active region to the right of the main gate, the pixel active regions respectively close to the shallow trench isolation sidewall and the deep trench isolation sidewall, the outermost first read transistor active region and the second read transistor active region. A substrate metal contact electrode is provided on the substrate ohmic contact region, and gate metal contact electrodes are respectively provided on the main gate, the reset gate, the first read transistor gate, and the second read transistor gate.

[0013] Further, the hybrid substrate, the left substrate, and the right substrate are all semiconductors, and are respectively and independently selected from silicon, germanium, germanium-silicon, gallium nitride, or indium gallium arsenide.

[0014] Further, the pixel active region, the first read transistor active region, the second read transistor active region, the first top channel region, the second top channel region, and the third top channel region are also all made of semiconductors, and are respectively and independently selected from silicon, germanium, germanium-silicon, gallium nitride, or indium gallium arsenide.

[0015] Further, the first buried oxide layer, the second buried oxide layer, and the third buried oxide layer are respectively and independently silicon dioxide, aluminum oxide, or hafnium oxide insulating materials.

[0016] Further, the hybrid substrate, the left substrate, and the right substrate are lightly doped P-type, with a doping concentration of 10 15 -10 17 cm -3 。

[0017] Further, the pixel active region, the first read transistor active region, and the second read transistor active region are heavily doped N-type, with a doping concentration of 10 19 -10 21 cm -3 。

[0018] Further, the substrate ohmic contact region is heavily doped P-type, with a doping concentration of 10 19 -10 21 cm -3 。

[0019] Further, an anti-reflection layer is deposited and grown on the bottoms of the hybrid substrate, the left substrate, and the right substrate. Even further, the anti-reflection layer is composed of an anti-reflection SiO2 layer, an anti-reflection Si3N4 layer, and an anti-reflection SiO2 layer.

[0020] The second technical solution of the present invention provides a method for manufacturing a symmetrically integrated vision sensor pixel structure, including the following steps:

[0021] (1) On the starting insulating layer silicon wafer, through etching and epitaxy, a hybrid substrate, a left substrate, a right substrate, a first buried oxide layer, a second buried oxide layer, a third buried oxide layer, a first top channel region, a second top channel region, and a third top channel region are formed;

[0022] (2) After photolithography and etching, a shallow trench isolation sidewall and two deep trench isolation sidewalls are formed by oxidation growth in the hybrid substrate;

[0023] (3) Photolithography and ion implantation are performed to form a substrate ohmic contact region;

[0024] (4) A gate oxide layer is deposited and grown on the structure, and a gate material is epitaxially grown. After photolithography and etching, a main gate, a reset gate, a first readout transistor gate, and a second readout transistor gate are obtained;

[0025] (5) A protective sidewall is formed by atomic layer deposition;

[0026] (6) The top silicon portion covered by the main gate, the reset gate, the first readout transistor gate, and the second readout transistor gate is removed by photolithography and etching, and then epitaxially grown and in-situ doped to obtain a pixel active region, a first readout transistor active region, and a second readout transistor active region;

[0027] (7) Windows of each gate, source-drain contact region, and substrate ohmic contact region are opened by photolithography, metal is deposited and annealed to form metal contact electrodes on the tops of the pixel active region, the first readout transistor active region, the second readout transistor active region, and each gate;

[0028] (8) An anti-reflection layer is deposited and grown.

[0029] The pixel structure formed by the above manufacturing process has the characteristics of multiple transistors and multiple gates. Except for the main transistor gate, the reset gate plays a role in connecting the two-sided differential capacitors, and the outermost two transistors are differential signal readout transistors. Therefore, the pixel implemented by the present invention can simultaneously achieve the fusion readout of the absolute light intensity signal and the differential signal.

[0030] Further, in step (1), the thicknesses of the first buried oxide layer, the second buried oxide layer, and the third buried oxide layer are 10 nm to 1000 nm.

[0031] Further, in step (1), the thicknesses of the first top channel region, the second top channel region, and the third top channel region are 5 nm to 500 nm.

[0032] Further, in step (3), boron or boron fluoride is used for ion implantation, and the dose is 10 13 cm -2 ~10 16 cm -2 , the energy is 1 keV to 100 keV, the ion activation annealing temperature is 900 to 1200 °C, and the time is 1 microsecond to 10 seconds.

[0033] Further, in step (4), the thickness of the gate oxide layer is 1 to 30 nm;

[0034] The thickness of the grown gate material is 10 nm to 500 nm.

[0035] Further, in step (7), the deposited metal is aluminum, nickel, titanium or metal silicide, and the annealing temperature is 300 to 900 °C.

[0036] The third technical solution of the present invention provides a signal control method for a symmetric fusion vision sensor pixel structure. The pixel structure includes a pixel transistor part on a hybrid substrate and a differential signal readout transistor part on the left substrate and the right substrate. The signal control method is as follows:

[0037] Step 1: The gate (i.e., the main gate) and the drain (i.e., the drain on the right side of the main gate) of the pixel intermediate transistor are appropriately biased so that it is always in the on state; before integration, turn on the reset gate on the right side and turn off the reset gate on the left side; subsequently, apply a negative pulse voltage of an appropriate magnitude to the substrate metal contact (forming a virtual photodiode in the substrate), and start the first frame of integration;

[0038] Step 2: Turn off the reset gate on the right side and turn on the reset gate on the left side; read out the differential capacitance signal I E through the drain of the left differential signal readout transistor, and read out the pixel light intensity signal I out through the drain of the intermediate transistor; subsequently, zero the negative pulse voltage of the substrate (reset the substrate virtual photodiode, and at the same time the differential capacitance records the first frame of light intensity signal); prepare for the second frame of integration;

[0039] Step 3: Apply a negative pulse voltage of an appropriate magnitude to the substrate, and start the second frame of integration; turn off the reset gate on the left side and turn on the reset gate on the right side; read out the differential capacitance signal I O through the drain of the right differential signal readout transistor, and read out the pixel light intensity signal I out through the drain of the intermediate transistor;

[0040] Repeat the above steps 1 to 3, and the differential signals of consecutive frames and the optical intensity signals of each frame can be output at full rate.

[0041] The more specific operation steps are as follows:

[0042] (a) Connect the drain metal contact electrodes of the pixel active regions close to the shallow trench isolation sidewall and the deep trench isolation sidewall respectively to the gate metal contact electrodes on the gates of the adjacent first and second readout transistors. At the same time, bias the source, drain, and gate voltages of the pixel transistor part and the differential signal readout transistor part. Among them, all sources are grounded to GND, the right side of the main gate, and the two outermost drains are connected to a high-potential power supply V DS , and the main gate is connected to another high-potential power supply V GS , so that the pixel transistor is in a normally open state;

[0043] (b) Before the integration starts, pull the left reset gate to a low level, pull the right reset gate to a high level, and at the same time the substrate metal contact electrode is in a high level state;

[0044] (c) Apply a low-level transient pulse to the substrate metal contact electrode to form a deep depletion region in the hybrid substrate to prepare for collecting photo-generated electrons;

[0045] (d) When the light is turned on, the photo-generated carriers start to integrate in the above-mentioned depletion region;

[0046] (e) When the light is turned off, pull the left reset gate to a high level, pull the right reset gate to a low level, and read the first frame of differential signal I from the drain of the left differential signal readout transistor part before the substrate metal contact electrode is reset E ; at the same time, read the first frame of absolute signal I from the drain on the right side of the pixel transistor part out ;

[0047] (f) Pull the substrate metal contact electrode to a high level for reset. At the end of the first frame, at the same time, the right differential capacitor (that is, the transistor capacitor controlled by the right reset gate, correspondingly called the right differential capacitor) stores the first frame of optical intensity signal; then apply a low-level transient pulse to the substrate metal contact electrode to form a deep depletion region in the hybrid substrate to prepare for collecting photo-generated electrons;

[0048] (g) When the light is turned on, the photo-generated carriers start to integrate in the above-mentioned depletion region;

[0049] (h) When the light is turned off, pull the left reset gate to a low level and the right reset gate to a high level; read the second frame of differential signal I from the drain of the right differential signal readout transistor part before the substrate metal contact electrode is reset O, while reading the second-frame absolute signal I from the drain on the right side of the pixel transistor section out ;

[0050] (i) Pull the substrate metal contact electrode to a high level for reset, the second frame ends, and at the same time, the left differential capacitor stores the second-frame light intensity signal.

[0051] (j) Repeat the above steps, and the middle pixel transistor section can obtain the absolute light intensity signal of each frame, and the differential capacitors on both sides can calculate the light intensity differential signal between each frame and the previous frame, which is alternately read out through the readout transistors on both sides.

[0052] In the present invention, a virtual photodiode is formed under the buried oxide layer / substrate interface by applying a substrate pulse, and an auxiliary reset gate is introduced on the pixel active region as a reset switch to realize the differential operation inside the pixel. Two differential signal readout transistors are added outside the deep trench isolation surrounding area. Among them, the middle transistor senses the light intensity signal of the substrate virtual diode and amplifies and reads it out. The capacitors connected by the two reset gates perform a differential operation on the light intensity signals between frames, and the result is amplified and read out through the corresponding differential signal readout transistors. The present invention is based on the structure of a single-transistor optoelectronic in-situ detector (Photoelectron in-situ Sensing Device: PISD). Inside the compact pixel architecture, the absolute light intensity signal and the differential signal can be read out simultaneously, realizing the fusion of the light intensity data of a traditional image sensor (Active Pixel Sensor: APS) and the event data of a dynamic vision sensor (Dynamic Vision Sensor: DVS), laying a foundation for the application of PISD in the next-generation new dynamic vision sensor. Description of the Drawings

[0053] Figure 1 It is a structural diagram of the fusion vision sensor pixel of the present invention.

[0054] Figure 2 It is a preparation process diagram of the fusion vision sensor pixel of the present invention.

[0055] Figure 3 It is a signal control method diagram of the fusion vision sensor pixel of the present invention.

[0056] Figure 4 It is the structure of Example 2 of the fusion vision sensor pixel of the present invention.

[0057] Figure 5 It is a signal control method diagram of Example 2 of the fusion vision sensor pixel of the present invention. Detailed Embodiments

[0058] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. This embodiment is implemented on the premise of the technical solution of the present invention, and gives the detailed implementation manners and specific operation processes, but the protection scope of the present invention is not limited to the following embodiments.

[0059] Based on the same working principle, the structures of the pixels and the corresponding preparation and signal control methods can be different, and the specific implementation manners are embodied in different embodiments.

[0060] In addition, in the following embodiments, if there is no special description of the functional component structure or processing technology, it means that they are all conventional component structures or conventional processing technologies in the art to achieve the corresponding functions.

[0061] Embodiment 1 (corresponding to the pixel structure of Figure 1 , the process flow of Figure 2 and the control signal of Figure 3 ):

[0062] This embodiment provides a symmetric fusion vision sensor pixel structure, the structure of which is shown in Figure 1 . It includes a hybrid substrate 2, and a left substrate 1 and a right substrate 3 respectively located on the left and right sides of the hybrid substrate 2. Among them,

[0063] A shallow trench isolation sidewall 31 and a substrate ohmic contact region 15 are formed on the hybrid substrate 2, and support the first buried oxide layer 5 above and the topmost first top region. The first top region includes four pixel active regions 7, 8, 9, 10, and the first top channel regions 16, 17, 18 corresponding to between two adjacent pixel active regions respectively. Above the three first top channel regions, a main gate 27 and two reset gates 26, 28 are respectively provided. The two reset gates 26, 28 are respectively located on both sides of the main gate 27. The main gate 27 and the reset gates 26, 28 respectively control the on and off of the corresponding first top channel regions 17, 16, 18 through the gate oxide layers 22, 21, 23 below them. Protective sidewalls 36, 37, 34, 35, 38, 39 are formed on both sides of the main gate 27 and the reset gates 26, 28. Deep trench isolation sidewalls 32, 33 are formed on the left and right sides of the hybrid substrate 2.

[0064] The left substrate 1 supports the upper second buried oxide layer 4 and the uppermost second top region. The second top region includes two segments of the first read transistor active regions 11, 12, and a second top channel region 19 located between the two first read transistor active regions 11, 12. Above the second top channel region 19, there is a first read transistor gate 29. The first read transistor gate 29 also controls the on / off of the second top channel region 19 through the gate oxide layer 24 below it. Protective sidewalls 40, 41 are also formed on both sides of the first read transistor gate 29.

[0065] The right substrate 3 supports the upper third buried oxide layer 6 and the uppermost third top region. The third top region includes two segments of the second read transistor active regions 13, 14, and a third top channel region 20 located between the two second read transistor active regions 13, 14. Above the third top channel region 20, there is a second read transistor gate 30. The second read transistor gate 30 also controls the on / off of the third top channel region 20 through the gate oxide layer 25 below it. Protective sidewalls 42, 43 are also formed on both sides of the second read transistor gate 30.

[0066] Source metal contact electrodes 49, 50, 51 are also respectively provided on the pixel active region 8 on the left side of the main gate 27, the first read transistor active region 12 on the right side of the first read transistor gate 29, and the second read transistor active region 13 on the left side of the second read transistor gate 30. Drain metal contact electrodes 53, 54, 55, 56 are also respectively provided on the pixel active region 9 on the right side of the main gate 27, the pixel active regions 7, 10 respectively close to the shallow trench isolation sidewall 31 and the deep trench isolation sidewall 33, the outermost first read transistor active region 11 and the second read transistor active region 14. A substrate metal contact electrode 57 is provided on the substrate ohmic contact region 15. Gate metal contact electrodes 45, 44, 46, 47, 48 are respectively provided on the main gate 27, the reset gates 26, 28, the first read transistor gate 29, and the second read transistor gate 30.

[0067] In addition, an anti-reflection layer (which consists of a silicon oxide layer 58, a silicon nitride layer 59, and a silicon oxide layer 60) is provided at the bottom of all substrates.

[0068] As Figure 2 shown, the process flow of Embodiment 1 mainly has the following steps:

[0069] (1) As Figure 2 (a) shown, it is the starting silicon-on-insulator wafer. Its substrate doping is generally weakly p-type doped silicon, and the doping concentration is at 10 15 -10 17 cm -3Between. Depending on the detected optical wavelength, the substrate can also be made of materials such as silicon germanium, gallium nitride, or indium gallium arsenide. Its buried layer is generally silicon dioxide, with a thickness between 10 nm and 1000 nm. The upper channel is generally made of materials such as silicon, silicon germanium, gallium nitride, or indium gallium arsenide, with a thickness between 5 nm and 500 nm.

[0070] (2) Using photoresist as a mask, etch the oxidized buried layer to the substrate silicon, and then epitaxially grow silicon; photolithograph and open the windows for substrate sidewall isolation of STI and DTI, and then use photoresist as a mask to etch the substrate silicon, and then oxidize and grow silicon dioxide. The STI and DTI oxidation isolation layers can be formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD) methods, such as Figure 2 (b). The etching can be selected from dry or wet methods: dry etching generally uses fluorine-based or halogen element gases, such as SF6, Cl2, etc.; while wet etching generally uses strong acids or strong bases such as HF, NH4HF2, etc.

[0071] (3) Photolithograph and open the windows of the substrate contact area, and perform ion implantation or epitaxial doping on the surface of the hybrid substrate to form the substrate ohmic contact area. Ion implantation generally uses boron or boron fluoride, with a dose between 10 13 cm -2 to 10 16 cm -2 between, with an energy between 1 keV and 100 keV, and the ion activation annealing temperature is generally between 900 degrees and 1200 degrees, and the time is between 1 microsecond and 10 seconds, such as Figure 2 (c).

[0072] (4) Deposit and grow a gate oxide layer and epitaxially grow a gate material on the structure. The oxide layer can be a high-K dielectric material such as hafnium oxide or aluminum oxide, deposited by an atomic layer deposition system (ALD), with a thickness generally between 1 nm and 30 nm. The gate material can be a polysilicon layer or a composite layer of polysilicon and metal, with a thickness between 10 nm and 500 nm.

[0073] (5) Photolithograph and open the windows of the five gates, and then use photoresist as a mask to etch the materials grown in step (4) to form the pattern of the gates, as shown in Figure 2 (d); the etching can be selected from dry or wet methods. Dry etching generally uses fluorine-based or halogen element gases, such as SF6, CHF3, HBr, or Cl2, etc. While wet etching generally uses solutions such as TMAH, KOH, etc.

[0074] (6) Deposit a layer of gate sidewall material, such as commonly used silicon nitride, silicon dioxide, or low dielectric constant dielectrics such as SiOCN and SiBCN. The deposition can use processes such as chemical vapor deposition (CVD) and atomic layer deposition (ALD). Then perform etching to form the gate sidewall as shown in Figure 2 (e). Etching generally uses reactive ion etching with vertical directionality. Dry etching generally uses fluorine-based gases such as SF6, CHF3, or CH3F, etc.

[0075] (7) Lithograph and open the pixel and readout transistor active region windows, use photoresist as a mask to etch away the top silicon part covered by the gate, and then epitaxially grow silicon. In-situ doping is carried out during epitaxial growth, and the doping concentration is between 10 19 cm -3 to 10 21 cm -3 . Finally, form an N-type heavily doped active region (i.e., the pixel active region and the readout transistor active region), as shown in Figure 2 (f).

[0076] (8) Lithograph and open the windows for five gates, source-drain contact regions, and substrate ohmic contact regions, deposit metal and anneal to form the electrodes as shown in Figure 2 (g) on the top of the N-type heavily doped active region and the five gates; commonly used metals are aluminum, nickel, titanium, or metal silicides such as nickel silicide and titanium silicide, etc., and the annealing temperature is between 300 and 900 °C.

[0077] (9) Deposit and grow an SiO2 / Si3N4 / SiO2 antireflection layer, which can be formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD) methods, as shown in Figure 2 (h).

[0078] As shown in Figure 3 , the left-side digital labels in the figure are the numbers of each electrode. The signal control method for the pixel structure obtained in the above embodiments is as follows:

[0079] The drain metal contact electrode 53 and the gate metal contact electrode 47 are connected and shorted, and the drain metal contact electrode 54 and the gate metal contact electrode 48 are connected and shorted. First, bias the source, drain, and gate voltages of the pixel transistor and the differential signal readout transistor at appropriate fixed biases, where all sources (i.e., metal contact electrodes 49, 50, 51) are grounded to GND; all drains (i.e., drain metal contact electrodes 52, 55, 56) are connected to a high-potential power supply V DS (such as 0.8 V); at the same time, the gate of the pixel transistor (i.e., the gate metal contact electrode 45) is connected to another high-potential power supply V GS (such as 1.8 V) to keep the transistor in an always-on state.

[0080] Before the integration starts, pull the left reset gate (i.e., gate metal contact electrode 44) to a low level; at the same time, pull the right reset gate (i.e., gate metal contact electrode 46) to a high level; the pixel transistor substrate bias (i.e., substrate metal contact electrode 57) is in a high level state;

[0081] Then, apply a low-level transient pulse to the substrate bias to form a deep depletion region (virtual photodiode) in the substrate to prepare for collecting photo-generated carriers;

[0082] When the light illumination is turned on, photo-generated carriers start to integrate in the above-mentioned depletion region;

[0083] When the light illumination ends, pull the left reset gate (i.e., gate metal contact electrode 44) to a high level; at the same time, pull the right reset gate (i.e., gate metal contact electrode 46) to a low level; before resetting the substrate bias, read the first frame of differential signal I from the drain of the left differential signal read transistor (i.e., drain metal contact electrode 55) E ; at the same time, read the first frame of absolute signal I from the drain of the pixel transistor (i.e., drain metal contact electrode 52) out ;

[0084] Pull the substrate bias to a high level for reset, the first frame ends, and at the same time the right differential capacitor stores the first frame of light intensity signal; then apply a low-level transient pulse to the substrate bias to form a deep depletion region (virtual photodiode) in the substrate to prepare for collecting photo-generated carriers;

[0085] When the light illumination is turned on, photo-generated carriers start to integrate in the above-mentioned depletion region;

[0086] When the light illumination ends, pull the left reset gate to a low level; at the same time, pull the right reset gate to a high level; before resetting the substrate bias, read the second frame of differential signal I from the drain of the right differential signal read transistor (i.e., drain metal contact electrode 56) O ; at the same time, read the second frame of absolute signal I from the drain of the pixel transistor (i.e., drain metal contact electrode 52) out ;

[0087] Pull the substrate bias to a high level for reset, the second frame ends, and at the same time the left differential capacitor stores the second frame of light intensity signal.

[0088] Repeat the above steps, and the middle pixel transistor can obtain the absolute light intensity signal of each frame, and the differential capacitors on both sides can calculate the light intensity differential signal between each frame and the previous frame, which are alternately read out through the read transistors on both sides.

[0089] Embodiment 2 (corresponding to the pixel structure of Figure 4 and the control signal of Figure 5 ):

[0090] AsFigure 4 As shown, Example 2 is similar to Example 1, except that the substrate is lightly doped N-type, and the transistors in the upper silicon layer are P-type instead of N-type. Therefore, the process flow of this example is similar to that of Example 1, only need to replace the SOI substrate in step (1), and reverse the type of in-situ doping impurities during the epitaxial growth in steps (3) and (7).

[0091] As Figure 5 shown, for the signal control of Example 2, only need to change the corresponding partial signal control according to the change of the device doping type to complete the corresponding functions of Example 1. The signal control is as follows:

[0092] The drain metal contact electrode 53 and the gate metal contact electrode 47 are connected and shorted, and the drain metal contact electrode 54 and the gate metal contact electrode 48 are connected and shorted. First, bias the source, drain, and gate voltages of the pixel transistor and the differential signal readout transistor at appropriate fixed biases, where all sources (i.e., source metal contact electrodes 49, 50, 51) are grounded to GND; all drains (i.e., drain metal contact electrodes 52, 55, 56) are connected to a low-potential power supply V DS (such as -0.8V); at the same time, the gate of the pixel transistor (i.e., the gate metal contact electrode 45) is connected to another low-potential power supply V GS (such as -1.8V) to keep the transistor in the normally open state.

[0093] Before the integration starts, pull the left reset gate (i.e., the gate metal contact electrode 44) to a high level; at the same time, pull the right reset gate (i.e., the gate metal contact electrode 46) to a low level; the substrate bias of the pixel transistor (i.e., the substrate metal contact electrode 57) is in the low-level state;

[0094] Then, apply a high-level transient pulse to the substrate bias to form a deep depletion region (virtual photodiode) in the substrate to prepare for collecting photo-generated carriers;

[0095] When the light illumination is turned on, the photo-generated carriers start to integrate in the above-mentioned depletion region;

[0096] When the light illumination ends, pull the left reset gate (i.e., the gate metal contact electrode 44) to a low level; at the same time, pull the right reset gate (i.e., the gate metal contact electrode 46) to a high level; before the substrate bias is reset, read the first frame of differential signal I from the drain of the left differential signal readout transistor (i.e., the drain metal contact electrode 55) E ; at the same time, read the first frame of absolute signal I from the drain of the pixel transistor (i.e., the drain metal contact electrode 52) out ;

[0097] The substrate bias is pulled to a low level for reset. The first frame ends, and at the same time, the right differential capacitor stores the first-frame light intensity signal. Then, a high-level transient pulse is applied to the substrate bias to form a deep depletion region (virtual photodiode) in the substrate to prepare for collecting photo-generated carriers.

[0098] The light illumination is turned on, and photo-generated carriers start to integrate in the above-mentioned depletion region.

[0099] The light illumination ends. The left reset gate is pulled to a high level; at the same time, the right reset gate is pulled to a low level. Before the substrate bias is reset, the second-frame differential signal I is read from the drain of the right-side differential signal read transistor (i.e., the drain metal contact electrode 56). O At the same time, the second-frame absolute signal I is read from the drain of the pixel transistor (i.e., the drain metal contact electrode 52). out ;

[0100] The substrate bias is pulled to a low level for reset. The second frame ends, and at the same time, the left differential capacitor stores the second-frame light intensity signal.

[0101] Repeat the above steps, and the middle pixel transistor can obtain the absolute light intensity signal of each frame. The differential capacitors on both sides can calculate the light intensity differential signal between each frame and the previous frame, and are alternately read out through the read transistors on both sides.

[0102] The above description of the embodiments is for the convenience of those of ordinary skill in the art to understand and use the invention. Obviously, those skilled in the art can easily make various modifications to these embodiments and apply the general principles described herein to other embodiments without creative efforts. Therefore, the present invention is not limited to the above embodiments, and the improvements and modifications made by those skilled in the art without departing from the scope of the present invention according to the disclosure of the present invention should be within the protection scope of the present invention.

Claims

1. A symmetric fusion vision sensor pixel structure, characterized in that, It includes a hybrid substrate, a left substrate and a right substrate respectively located on the left and right sides of the hybrid substrate. Among them, a shallow trench isolation sidewall and a substrate ohmic contact region are formed on the hybrid substrate, and the first buried oxide layer above and the topmost first top region are supported. The first top region includes four pixel active regions, a first top channel region located between two adjacent pixel active regions. Above the three first top channel regions, a body gate and two reset gates are respectively provided. The two reset gates are respectively located on both sides of the body gate. The body gate and the reset gate respectively control the on / off of the corresponding first top channel region through the gate oxide layer below them. Protective sidewalls are formed on both sides of the body gate and the reset gate. Deep trench isolation sidewalls are formed on the left and right sides of the hybrid substrate. the left substrate supports the second buried oxide layer above and the topmost second top region. The second top region includes two first read transistor active regions and a second top channel region located between the two first read transistor active regions. A first read transistor gate is provided above the second top channel region. The first read transistor gate also controls the on / off of the second top channel region through the gate oxide layer below it. Protective sidewalls are also formed on both sides of the first read transistor gate. the right substrate supports the third buried oxide layer above and the topmost third top region. The third top region includes two second read transistor active regions and a third top channel region located between the two second read transistor active regions. A second read transistor gate is provided above the third top channel region. The second read transistor gate also controls the on / off of the third top channel region through the gate oxide layer below it. Protective sidewalls are also formed on both sides of the second read transistor gate. Source metal contact electrodes are respectively provided on the pixel active region on the left side of the body gate, the first read transistor active region on the right side of the first read transistor gate, and the second read transistor active region on the left side of the second read transistor gate. Drain metal contact electrodes are respectively provided on the pixel active region on the right side of the body gate, the pixel active regions respectively close to the shallow trench isolation sidewall and the deep trench isolation sidewall, the outermost first read transistor active region and the second read transistor active region. A substrate metal contact electrode is provided on the substrate ohmic contact region. Gate metal contact electrodes are respectively provided on the body gate, the reset gate, the first read transistor gate and the second read transistor gate.

2. The symmetric fusion vision sensor pixel structure according to claim 1, wherein the hybrid substrate, the left substrate and the right substrate are all semiconductors, and are respectively independently selected from silicon, germanium, germanium-silicon, gallium nitride or indium gallium arsenide; the pixel active region, the first read transistor active region, the second read transistor active region, the first top channel region, the second top channel region and the third top channel region also all adopt semiconductors, and are respectively independently selected from silicon, germanium, germanium-silicon, gallium nitride or indium gallium arsenide; the first buried oxide layer, the second buried oxide layer and the third buried oxide layer are respectively independently silicon dioxide, aluminum oxide or hafnium oxide insulating materials.

3. A symmetric fusion vision sensor pixel structure according to claim 1, characterized in that The described hybrid substrate, left substrate, and right substrate are P-type lightly doped with a doping concentration of 10 15 -10 17 cm -3 ; The pixel active region, the first readout transistor active region, and the second readout transistor active region are N-type heavily doped, with a doping concentration of 10 19 -10 21 cm -3 ; The substrate ohmic contact region is P-type heavily doped with a doping concentration of 10 19 -10 21 cm -3 .

4. A symmetric fusion vision sensor pixel structure according to claim 1, characterized in that, An antireflection layer is also deposited and grown on the bottoms of the described hybrid substrate, left substrate, and right substrate.

5. The preparation method of a symmetric fusion vision sensor pixel structure according to any one of claims 1-4, characterized in that It includes the following steps: (1) On the starting insulating silicon wafer, a hybrid substrate, a left substrate, a right substrate, a first buried oxide layer, a second buried oxide layer, a third buried oxide layer, a first top channel region, a second top channel region, and a third top channel region are formed by etching and epitaxy. (2) After photolithography and etching, a shallow trench isolation sidewall and two deep trench isolation sidewalls are formed by oxidation growth in the hybrid substrate. (3) Photolithography and ion implantation are performed to form a substrate ohmic contact region. (4) A gate oxide layer is deposited and grown on the structure, and a gate material is epitaxially grown. After photolithography and etching, a main gate, a reset gate, a first readout transistor gate, and a second readout transistor gate are obtained. (5) A protective sidewall is formed by atomic layer deposition. (6) The top silicon part covered by the main gate, reset gate, first readout transistor gate, and second readout transistor gate is removed by photolithography and etching, and then epitaxially grown and in-situ doped to obtain a pixel active region, a first readout transistor active region, and a second readout transistor active region. (7) Windows of each gate, source-drain contact region, and substrate ohmic contact region are opened by photolithography, and metal is deposited and annealed to form metal contact electrodes on the top of the pixel active region, the first readout transistor active region, the second readout transistor active region, and each gate. (8) An antireflection layer is deposited and grown.

6. The manufacturing method of a symmetric fusion vision sensor pixel structure according to claim 5, characterized in that In step (1), the thicknesses of the first buried oxide layer, the second buried oxide layer, and the third buried oxide layer are 10 nm to 1000 nm. In step (1), the thicknesses of the first top channel region, the second top channel region, and the third top channel region are 5 nm to 500 nm.

7. The preparation method of a symmetric fusion vision sensor pixel structure according to claim 5, characterized in that In step (3), boron or boron fluoride is used for ion implantation, and the dose is 10 13 cm -2 ~10 16 cm -2 , the energy is 1 keV to 100 keV, the ion activation annealing temperature is 900 to 1200 °C, and the time is 1 microsecond to 10 seconds.

8. The manufacturing method of a symmetric fusion vision sensor pixel structure according to claim 5, characterized in that, In step (4), the thickness of the gate oxide layer is 1 to 30 nm. The thickness of the grown gate material is 10 nm to 500 nm.

9. The manufacturing method of a symmetric fusion vision sensor pixel structure according to claim 5, characterized in that, In step (7), the deposited metal is aluminum, nickel, titanium, or a metal silicide, and the annealing temperature is 300 to 900 °C.

10. The signal control method of the symmetric fusion vision sensor pixel structure according to any one of claims 1-4, characterized in that, This pixel structure includes a pixel transistor part on a hybrid substrate and a differential signal readout transistor part on the left and right substrates. This signal control method includes the following steps: (a) Connect the drain metal contact electrodes of the pixel active regions adjacent to the shallow trench isolation sidewalls and the deep trench isolation sidewalls to the gate metal contact electrodes on the adjacent first and second readout transistor gates. At the same time, bias the source, drain, and gate voltages of the pixel transistor part and the differential signal readout transistor part, where all sources are grounded to GND, the right side of the main gate, and the two outermost drains are connected to a high-potential power supply V DS , and the main gate is connected to another high-potential power supply V GS , so that the pixel transistor is in an always-on state; (b) Before the start of integration, the left reset gate is pulled to a low level, the right reset gate is pulled to a high level, and at the same time, the substrate metal contact electrode is in a high level state. (c) A low-level transient pulse is applied to the substrate metal contact electrode to form a deep depletion region in the hybrid substrate to prepare for collecting photo-generated electrons. (d) When the light is turned on, photo-generated carriers start to integrate in the above depletion region. (e) When the illumination ends, the reset gate on the left is pulled to a high level, and the reset gate on the right is pulled to a low level. Before the substrate metal contact electrode is reset, the first frame of differential signal I is read from the drain of the differential signal read transistor section on the left E ; at the same time, the first frame of absolute signal I is read from the drain on the right side of the pixel transistor section out ; (f) The substrate metal contact electrode is pulled to a high level for reset, the first frame ends, and at the same time, the right differential capacitance stores the first frame light intensity signal; then a low-level transient pulse is applied to the substrate metal contact electrode to form a deep depletion region in the hybrid substrate to prepare for collecting photo-generated electrons. (g) When the light is turned on, photo-generated carriers start to integrate in the above depletion region. (h) When the light illumination ends, pull the left reset gate to low level and the right reset gate to high level; before resetting the substrate metal contact electrode, read the second-frame differential signal I from the drain of the right differential signal read transistor part O , and at the same time read the second-frame absolute signal I from the drain on the right side of the pixel transistor part out ; (i) The substrate metal contact electrode is pulled to a high level for reset, the second frame ends, and at the same time, the left differential capacitance stores the second frame light intensity signal. (j) Repeat the above steps, and the absolute light intensity signal of each frame can be obtained for the middle pixel transistor part. The differential capacitance on both sides can calculate the light intensity differential signal between each frame and the previous frame, and is alternately read out through the readout transistors on both sides.

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