A reconfigurable sensor interface circuit based on switched capacitors

Abstract

The present invention discloses a reconfigurable sensor interface circuit based on switched capacitors, comprising a sampling circuit, a conversion circuit and a digital control circuit. The output end of the digital control circuit is connected to the input end of the digital processor, and the sampling circuit is connected to the sensor connection interface, and is used to sample the output signal of a capacitance / resistance / current / voltage sensor and convert it into charge and store it in a reference capacitor array C. R The conversion circuit employs a combined time-domain and voltage-domain control method to generate a multi-bit quantized output of the charge acquired by the sampling circuit through multiple cycles of charge-discharge, voltage comparison, and charge amplification until the desired measurement resolution is achieved. The digital control circuit, under the control of a digital processor, reconfigures the sampling and conversion circuits by controlling switch switching, thereby sampling and quantizing the output signals of capacitance, resistance, current, or voltage sensors. Based on the sensor's output type, the circuit converts the charge into a uniform, ultimately digital output. The circuit comprises a sampling circuit, a conversion circuit, and a digital control circuit. The input of the reconfigurable measurement circuit is connected to the sensor connection interface, and the output is connected to a port of the digital processor.

Description

Technical Field

[0001] The present invention relates to the field of sensor interface circuits, and in particular to a reconfigurable sensor interface circuit based on switched capacitors. Background Art

[0002] In recent years, sensor application systems have flourished as one of the core parts of the Internet of Things (IoT) field and have been widely used in various electronic devices, covering environmental monitoring, health care, smart city creation, smart factories, smart farms and other fields.

[0003] Sensors are widely used to detect various physical, chemical, and biological information. Their output is often expressed as electrical signals or electrically convertible forms. The output types of most sensors can be divided into four types: capacitance / resistance / current / voltage (C / R / I / V). The sensor interface circuit digitizes the output signals of various types of sensors and displays the results, while performing operations such as data transmission. It is a key part of the sensor application system.

[0004] Previous research on sensor interface circuits mainly focused on specific target sensors. Different sensor output signal types have dedicated interface circuits and architectures, so they have specific functions and performance for specific sensor output types. However, in the context of the rapid development of the Internet of Things market, huge sensor application systems hope to be realized in a short time and at low cost, and the design and development of sensor-specific interface circuits requires considerable cost and time. In contrast, the reconfigurable sensor interface circuit design realizes a reconfigurable interface circuit that can detect four types of signals: capacitance / resistance / current / voltage (C / R / I / V). It has the versatility to be applied to various sensor application systems. When different types of signals need to be collected, mode switching can be performed directly, which is convenient and flexible, and effectively meets the rapidly growing needs of sensor application systems.

[0005] While the designs of reconfigurable interface circuits have varied in recent years, they can generally be summarized as a combination of an analog front end and an analog-to-digital converter. Specifically, the analog front end detects the output signals of different sensor types and converts them into voltage outputs that match the input range of the analog-to-digital converter. The analog-to-digital converter then quantizes (measures) this output voltage, converts it into a digital output, and transmits it to the subsequent digital processor module. Furthermore, these architectures achieve adaptability to diverse sensor outputs by designing analog front ends that combine multiple amplifier types or consist of reconfigurable amplifiers, without involving an analog-to-digital converter. By optimizing the reconfigurable analog front end, these architectural designs have, to a certain extent, met the rapidly growing demand for versatile sensor interface circuits in sensor application systems. However, it should be noted that these designs still consume a large amount of area and power, with the analog-to-digital converter occupying the majority of the interface circuit area and power.

[0006] In particular, for the detection of capacitive sensors, the integration requirements of capacitive sensors in application systems such as the Internet of Things and wearable devices have driven the sensor process size to continue to shrink to microns (10 -6 m), which makes the capacitance change of the sensor as the process size is reduced to femtofarad (10 -15 F) level, the parasitic capacitance caused by the bonding wires, pads, printed circuit boards (PCBs) and electrostatic protection devices in the sensor application environment usually reaches pF (10 -12 In this case, the parasitic charge generated on the large parasitic capacitor can easily interfere with or even swallow up the signal charge on the sensor capacitor, thereby severely limiting the signal processing range and accuracy of the capacitive sensor readout circuit. Therefore, it is also necessary to suppress the influence of parasitic capacitance. Summary of the Invention

[0007] The present invention provides a reconfigurable sensor interface circuit based on switched capacitors. By designing a reconfigurable analog front end with an integrated analog-to-digital converter quantization function, the use of additional analog-to-digital converters is avoided, the circuit integration is improved, higher area efficiency and lower power consumption are achieved, and the design requirements of sensor application systems are more effectively met.

[0008] The present invention can be achieved through the following technical solutions:

[0009] A reconfigurable sensor interface circuit based on switched capacitors includes a sampling circuit, a conversion circuit, and a digital control circuit. The output end of the digital control circuit is connected to the input end of the digital processor. The sampling circuit is connected to the sensor connection interface and is used to sample the output signal of the output type of capacitance / resistance / current / voltage sensor and convert it into charge and store it in the reference capacitor array C. R superior,

[0010] The conversion circuit is used to output a multi-bit quantized result of the charge acquired by the sampling circuit by adopting a control method combining time domain and voltage domain, through multiple cycles of charge and discharge, voltage comparison and charge amplification, until the required measurement resolution is achieved;

[0011] The digital control circuit is used to reconstruct the sampling circuit and the conversion circuit by controlling the switching of the switch under the control of the digital processor, thereby realizing the sampling and quantization processing of the output signal of the output type of the capacitance / resistance / current / voltage sensor.

[0012] Furthermore, the conversion circuit is configured into three circuit structures. The first circuit structure is configured as a voltage comparator to generate an enable signal of the counter or a one-bit quantization result; the second circuit structure is configured as a unity gain buffer to convert the reference capacitor array C in the sampling circuit into a single-bit quantization result. R The voltage on capacitor C1 is stored on capacitor C1; the third circuit structure is configured as a charge amplifier, with capacitor C1 as the input capacitor and capacitor C2 as the feedback capacitor to amplify the voltage on capacitor C1;

[0013] For sensors with capacitive output type:

[0014] Through the cooperation of the three circuit structures, the connection with the sensor is first disconnected to obtain the reference capacitance array C R The corresponding discharge time is T1, and then the connection with the sensor is restored to discharge the charge collected by the sampling circuit, and the voltage on the capacitor Cx to be measured after the discharge time T1 is stored on the capacitor C1, and the voltage V at this time is recorded. S(0) , then continue to discharge Time, record the voltage V at this time S(1) , and then the voltage V s(1) and reference voltage V R Make a comparison and output the most significant bit (MSB) of the digital conversion result. At the same time, based on the comparison result, update the voltage of the capacitor Cx to be measured through charge amplification and record the voltage at this time as V′ S(1) , repeat the above duration Discharge, voltage comparison, and charge amplification processes until the conversion result reaches the required resolution;

[0015] For sensors with output type current / resistance / voltage:

[0016] Through the cooperation of the three circuit structures, the connection with the sensor is first disconnected to obtain the reference capacitance array C R The corresponding discharge time is T1, and then the connection with the sensor is restored, and the charge collected by the sampling circuit is stored in C R The voltage generated on the capacitor C1 is stored, and the voltage V at this time is recorded.S(0) , and then proceed Time of discharge, record the voltage V at this time S(1) , then the voltage V s(1) and reference voltage V R Make a comparison and output the most significant bit MSB of the digital conversion result. At the same time, based on the comparison result, the reference capacitor array C is updated through charge amplification. R The voltage at this time is recorded as V' S(1) , repeat the above duration Discharge, voltage comparison, and charge amplification processes are repeated until the conversion result reaches the required resolution.

[0017] Furthermore, the first circuit structure includes an A-shaped structure and a B-shaped structure.

[0018] The A-type structure includes disconnecting the connection with the sensor through the switch S4, firstly increasing the charging voltage V through the switch S15 C and reference capacitor array C R connected, and then disconnect the charging voltage V through switch S15 C The current source I R1 and reference capacitor array C R The positive electrode of the operational amplifier U1 is connected to the positive electrode of the operational amplifier U1 through the switch S2, the switch S1, and the error capacitor Cos. The negative electrode of the operational amplifier U1 is connected to the positive electrode of the operational amplifier U1 through the switch S6, the switch S12 and the reference voltage V R The output end of the operational amplifier U1 is connected to the digital control circuit;

[0019] The B-shaped structure includes an operational amplifier U1, the positive electrode of which is sequentially connected to the error capacitor Cos, the switch S1, the switch S2 and the parallel reference capacitor array C R , current source I R1 Connected to the sensor, where the current source I R1 The parallel branch where the sensor is located is connected to a switch S3, the parallel branch where the sensor is located is connected to a switch S4, the cathode of the operational amplifier U1 is connected to its output terminal through a switch S5, and the output terminal of the operational amplifier U1 is connected to the digital control circuit;

[0020] The second circuit structure includes an operational amplifier U1, the positive electrode of which is sequentially connected to the error capacitor Cos, the switch S1, the switch S2 and the parallel reference capacitor array C R The parallel branch where the sensor is located is connected to a switch S4. The negative electrode of the operational amplifier U1 is connected to its output terminal through a switch S5, and is also connected to the reference voltage V through a switch S6, a capacitor C1, a switch S7 and a reference voltage V RThe output end of the operational amplifier U1 is connected to the digital control circuit;

[0021] The third circuit structure is first configured into the first structure and then configured into the second structure.

[0022] The first structure includes an operational amplifier U1, the positive electrode of which is connected to the reference voltage V R The negative electrode of the operational amplifier U1 is connected to the capacitor C1 via the switch S11, and is also connected to the output end via the switch S9, the feedback capacitor C2, and the switch S10 in sequence. The output end of the operational amplifier U1 is connected to the digital control circuit;

[0023] The second structure operational amplifier U1, the positive electrode of the operational amplifier U1 is sequentially connected through the error capacitor Cos, the switch S8 and the reference voltage V R The negative electrode of the operational amplifier U1 is connected to the reference voltage V through the switch S11, the capacitor C1, the switch S2 and the reference voltage V R The output of the operational amplifier U1 is connected to the reference capacitor array C1 in parallel through the switch S13, the switch S2 and the reference capacitor array C2 in parallel. R It is connected to the sensor, wherein the parallel branch where the sensor is located is connected to a switch S4, and the output end of the operational amplifier U1 is also connected to the digital control circuit.

[0024] Furthermore, for sensors whose output type is capacitance,

[0025]

[0026] Among them, C XMAX The capacitance value to be measured corresponds to the full scale of the sensor whose output type is capacitance;

[0027] For sensors with resistance / voltage / current output, ΔT MAX =T1;

[0028] According to the comparison result, the capacitor to be measured Cx or the reference capacitor array C is updated by charge amplification according to the rule shown in the following formula. R voltage;

[0029] V S(1) >V R →V′ S(1) =2V S(1) -V R

[0030] V S(1) ≤V R →V′ S(1)=2V S(0) -V R

[0031] Under the control of the digital processor, disconnect the sensor and first pass the charging voltage V C For the parallel reference capacitor array C R and parasitic capacitance to ground C P The upper plate is charged, and the charging voltage is V C , and then through the current source I R1 For the parallel reference capacitor array C R and parasitic capacitance to ground C P Discharge until the upper plate voltage is equal to the reference voltage V R , and the corresponding discharge duration is recorded as T1.

[0032] Furthermore, the sampling circuit includes a current source I R2 , reference capacitor array C R , charging voltage V C , they are all connected to the sensor through the sensor connection interface, where the current source I R2 , charging voltage V C The parallel branches are respectively connected to a switch S14 and a switch S15.

[0033] Furthermore, the conversion circuit also includes an automatic calibration circuit. The automatic calibration circuit adopts the principle of correlated double sampling and realizes the charging and discharging of the error capacitor Cos through switch control. The connection between the conversion circuit and the sampling circuit is first cut off, the circuit noise and amplifier input offset voltage at this time are sampled and stored, and then the connection with the sampling circuit is quickly restored, thereby achieving the effect of noise reduction and compensation of the operational amplifier input offset voltage.

[0034] The beneficial technical effects of the present invention are:

[0035] By reconfiguring the sampling circuit, a single measurement circuit can measure the signals of four sensor output types. Compared to measurement circuits that require multiple types of amplifiers, this reduces circuit complexity, and optimizes circuit area and power consumption.

[0036] The strategy of quantizing charge in the time domain essentially eliminates the influence of parasitic capacitance at the interface on measurement accuracy. Meanwhile, traditional methods for quantizing time mostly rely on direct timing with a counter, which relies on a high-precision clock and has difficulty achieving high measurement accuracy. This invention proposes a new quantization method that combines counter timing with cyclic charge-discharge and charge amplification techniques to achieve high-precision measurement. Furthermore, performance such as measurement accuracy and measurement range can be reconfigured as needed.

[0037] The reconfigurable sensor interface circuit provided by the present invention can simplify circuit design and give full play to the advantages of reconfigurable technology to a greater extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 The interface circuit structure of the present invention and its position diagram in the sensor application system are shown;

[0039] Figure 2 Taking capacitance measurement as an example, the main reconstruction forms of various circuits in the present invention are demonstrated, among which:

[0040] Figure 2 (a) Capacitor C R 、C R The upper plate is precharged to V C , operational amplifier U1 samples the noise and input offset voltage for easy compensation later;

[0041] Figure 2 In (b), operational amplifier U1 is used as a voltage comparator, and capacitor C R 、C P The upper plate passes through the current source I R1 From V C Discharge to V R , the voltage at the output of the operational amplifier U1 is V O From high to low, the internal counter of the digital control circuit records the corresponding number of discharge cycles;

[0042] Figure 2 (c) Capacitor C X 、C R 、C P The upper plate is precharged to V C , operational amplifier U1 samples the noise and input offset voltage for easy compensation later;

[0043] Figure 2 (d) Capacitor C X 、C R 、C P The upper plate passes through the current source I R1 Discharge;

[0044] Figure 2 In (e), the operational amplifier U1 is reconfigured into a unity-gain buffer by switching the capacitor C X 、C R 、C P The voltage of the upper plate is stored in the upper plate of capacitor C1 to facilitate subsequent charge amplification operations;

[0045] Figure 2 (f) and Figure 2(g) shows the present invention amplifies the charge stored on the upper plate of capacitor C1 and stores it in capacitor C X 、C R 、C P The above process, first in Figure 2 In (f), the operational amplifier U1 is connected to the feedback capacitor C2, and the non-inverting input terminal is connected to the capacitor C OS Connect to V R , the negative input terminal is connected to the lower plate of capacitor C1; Figure 2 In (g), the upper plate of C1 is connected to V R , under the action of operational amplifier U1, the charge on C1 is transferred to C2, realizing charge amplification;

[0046] Figure 3 The working principle of the present invention in capacitance measurement mode is demonstrated, wherein Figure 3 (a) is a schematic overview of the two discharge processes. Figure 3 (b) is a schematic diagram of the quantification of the discharge time difference;

[0047] Figure 4 The present invention shows a sampling circuit reconfigured into different measurement modes, wherein Figure 4 (a) is a schematic diagram of the structure of the sampling circuit of the present invention reconstructed to measure the output type of the sensor as capacitance, Figure 4 (b) is a schematic diagram of the structure of the sampling circuit of the present invention reconstructed to measure the output type of the sensor as resistance, Figure 4 (c) is a schematic diagram of the structure of the sampling circuit of the present invention reconstructed into a sensor whose output type of measurement is current, Figure 4 (d) is a schematic diagram of the structure of the sampling circuit of the present invention reconstructed to measure the output type of the sensor as voltage;

[0048] Figure 5 The conversion process of the present invention in resistance / current / voltage measurement mode is demonstrated, wherein Figure 5 (a) is an overview of the sampling and second discharge process. Figure 5 (b) is a schematic diagram of the voltage comparison and charge amplification process;

[0049] Figure 6 The application of the correlated double sampling technique in the present invention is demonstrated, wherein Figure 6 (a) is a schematic diagram of the circuit structure of sampling noise and input offset voltage of operational amplifier U1. Figure 6 (b) is the input signal passing through the error capacitor C OS Schematic diagram of the circuit structure connected to the input of operational amplifier U1 for voltage comparison;

[0050] Figure 7 A schematic diagram showing the principle of the charge amplification process performed in the conversion stage of the present invention is shown. DETAILED DESCRIPTION

[0051] The specific implementation of the present invention is described in detail below with reference to the accompanying drawings and preferred embodiments.

[0052] like Figure 1 As shown, the present invention provides a reconfigurable sensor interface circuit based on switched capacitors. Under the control of a digital processor, a digital control circuit controls the switching of switches to reconfigure the sampling circuit and conversion circuit, performing signal measurements for four sensor output types. During the sampling phase, the circuit pre-records the discharge time corresponding to the parasitic capacitance at the sensor connection interface, thereby eliminating the effect of parasitic capacitance on conversion accuracy during the conversion phase. During the conversion phase, a control method combining time and voltage domains is employed. Through multiple cycles of charge and discharge, voltage comparison, and charge amplification, the charge acquired by the sampling circuit is quantized into a multi-bit output until the required measurement resolution is achieved. This improves conversion accuracy while reducing measurement time. The present invention has a simple structure and can effectively complete the conversion of various sensor types. It is highly practical and low-cost, making it suitable for widespread use.

[0053] The details are as follows:

[0054] The digital control circuit receives measurement mode selection, range selection, conversion resolution selection, sampling rate selection, repeated measurement and other signals input by the digital processor. By controlling the switching of the switch, the current value of the programmable current source, the capacitance value of the programmable capacitor array, the time and number of cyclic discharges, etc., it outputs accurate results that meet the measurement requirements, which better reflects the reconfigurable characteristics of the sensor interface circuit.

[0055] The sampling circuit includes a parallel current source I R2 , reference capacitor array C R , charging voltage V C , they are all connected to the sensor through the sensor connection interface, where the current source I R2 , charging voltage V C The parallel branches are connected to switches S14 and S15 respectively. Figure 4 As shown, according to the different measurement modes, under the control of the digital processor, the sampling circuit is reconstructed by switching to convert different types of measured signals into charge quantities and store them in the reference capacitor array C. R And the parasitic capacitance to ground C P At the same time, the operational amplifier U1 also samples the noise and input offset voltage to facilitate compensation later, such as Figure 2 (c) shown.

[0056] The conversion circuit is configured into three circuit structures. The first circuit structure is configured as a voltage comparator to generate an enable signal of the counter or a one-bit quantization result; the second circuit structure is configured as a unity gain buffer to convert the reference capacitor array C in the sampling circuit into a single-bit quantization result. R The voltage on capacitor C1 is stored on capacitor C1; the third circuit structure is configured as a charge amplifier, with capacitor C1 as the input capacitor and capacitor C2 as the feedback capacitor to amplify the voltage on capacitor C1.

[0057] The first circuit structure includes an A-shaped structure and a B-shaped structure.

[0058] The A-type structure includes disconnecting the connection with the sensor through the switch S4, firstly making the charging voltage V C and reference capacitor array C R connected, and then disconnect the charging voltage V through switch S15 C The current source I R1 and reference capacitor array C R The positive electrode of the operational amplifier U1 is connected to the positive electrode of the operational amplifier U1 through the switch S2, the switch S1, and the error capacitor Cos. The negative electrode of the operational amplifier U1 is connected to the positive electrode of the operational amplifier U1 through the switch S6, the switch S12 and the reference voltage V R The output end of the operational amplifier U1 is connected to the digital control circuit;

[0059] The B-shaped structure includes an operational amplifier U1, the positive electrode of which is sequentially connected to the error capacitor Cos, the switch S1, the switch S2 and the parallel reference capacitor array C R , current source I R1 Connected to the sensor, where the current source I R1 The parallel branch where the sensor is located is connected to a switch S3, the parallel branch where the sensor is located is connected to a switch S4, the cathode of the operational amplifier U1 is connected to its output terminal through a switch S5, and the output terminal of the operational amplifier U1 is connected to the digital control circuit;

[0060] The second circuit structure includes an operational amplifier U1, the positive electrode of which is sequentially connected to the error capacitor Cos, the switch S1, the switch S2 and the parallel reference capacitor array C R The parallel branch where the sensor is located is connected to a switch S4. The negative electrode of the operational amplifier U1 is connected to its output terminal through a switch S5, and is also connected to the reference voltage V through a switch S6, a capacitor C1, a switch S7 and a reference voltage V R The output end of the operational amplifier U1 is connected to the digital control circuit;

[0061] The third circuit structure is first configured into the first structure and then configured into the second structure.

[0062] The first structure includes an operational amplifier U1, the positive electrode of which is connected to the error capacitor Cos, the switch S8 and the reference voltage V R The negative electrode of the operational amplifier U1 is connected to the capacitor C1 via the switch S11, and is also connected to the output end via the switch S9, the feedback capacitor C2, and the switch S10 in sequence. The output end of the operational amplifier U1 is connected to the digital control circuit;

[0063] The second structure of the operational amplifier U1, the positive electrode of the operational amplifier U1 is sequentially connected through the error capacitor Cos, the switch S8 and the reference voltage V R The negative electrode of the operational amplifier U1 is connected to the reference voltage V through the switch S11, the capacitor C1, the switch S2 and the reference voltage V R The output of the operational amplifier U1 is connected to the reference capacitor array C1 in parallel through the switch S13, the switch S2 and the reference capacitor array C2 in parallel. R It is connected to the sensor, wherein the parallel branch where the sensor is located is connected to a switch S4, and the output end of the operational amplifier U1 is also connected to the digital control circuit.

[0064] Through the coordinated operation of these three circuit structures, the conversion circuit corresponds to two measurement modes. The first measurement mode corresponds to sensors whose output type is capacitance, and the second measurement mode corresponds to sensors whose output type is current / resistance / voltage.

[0065] For sensors with capacitive output type:

[0066] Through the cooperation of the above three circuit structures, first disconnect the connection with the sensor and obtain the reference capacitor array C R The corresponding discharge time is T1, and then the connection with the sensor is restored to discharge the charge collected by the sampling circuit, and the voltage on the capacitor Cx to be measured after the discharge time T1 is stored on the capacitor C1, and the voltage V at this time is recorded. S(0) , then continue to discharge Time, record the voltage V at this time S(1) , and then the voltage V s(1) and reference voltage V R Make a comparison and output the most significant bit (MSB) of the digital conversion result. At the same time, based on the comparison result, update the voltage of the capacitor Cx to be measured through charge amplification and record the voltage at this time as V′ S(1) , repeat the above duration The process of discharge, voltage comparison, and charge amplification continues until the conversion result reaches the required resolution. The details are as follows:

[0067] like Figure 2As shown, in the first measurement mode, namely the capacitance measurement mode, its principle is to convert the measurement of the capacitance value to be measured into the quantification of the time difference of the discharge process, which is analyzed as follows:

[0068] The internal circuit of the reconfigurable sensor interface and the capacitor C to be measured X To disconnect, first Figure 2 (a) For the reference capacitor array C R And the parasitic capacitance C in parallel with it P The upper plate is charged, and the charging voltage is V C , the amount of charge stored on the capacitor is Q = V C (C R +C P ),like Figure 2 (b) Then through the current source I R1 Discharge the capacitor until the upper plate voltage is equal to the reference voltage V R , corresponding to the first discharge duration like Figure 3 As shown in (a).

[0069] Then the second charge and discharge process is carried out. Figure 2 As shown in (c), the sensor interface circuit can be reconfigured to connect the capacitor C to be measured. X , connect the capacitor C to be tested in parallel X , reference capacitor array C R and parasitic capacitance to ground C P The upper plate is charged again to V C , Figure 2 (d) Then, the current source I R1 When the discharge time reaches T1, the remaining charge on the capacitor is ΔQ = (C R +C P +C X )V C -T1I R1 >0, due to the increase in capacitance, the capacitor to be measured C is connected X , at this time the voltage V S(0) Still higher than the reference voltage V R , assuming that the current source I R1 Discharge until the voltage on the capacitor plate is equal to the reference voltage V R , the duration of the second discharge process will be:

[0070]

[0071] The time difference between the two discharge processes is:

[0072]

[0073] As can be seen from the above formula, the time difference between the two discharge processes is theoretically proportional to the capacitance value to be measured. Therefore, the capacitance value to be measured can be obtained by measuring the time difference. At the same time, because the expression of the final time difference does not include the reference capacitor array C R and parasitic capacitance to ground C P , that is, it has nothing to do with it. This method theoretically eliminates the contribution of parasitic capacitance in the measurement results, and effectively solves the problem that the parasitic charge generated on the large parasitic capacitance can easily interfere with or even swallow up the signal charge on the sensor capacitance, thereby seriously limiting the signal processing range and accuracy of the capacitive sensor readout circuit.

[0074] The actual measurement process is based on the theoretical analysis of the two discharge processes mentioned above and can be divided into two stages:

[0075] In the first stage, the reference capacitor array C is obtained, which is consistent with the first charge and discharge process mentioned above. R And the parasitic capacitance C in parallel with it P From V C Discharge to V R The time required is T1; then the signal to be measured is sampled, such as Figure 4 As shown in (a) of FIG, the sampling circuit is reconstructed by switching the switch to convert different types of measured signals into charge quantities and store them in C R and C P At this time, the amount of charge stored is Q = V C (C R +C P +C X ). At the same time, during the charging process at this stage, the operational amplifier U1 samples the noise and input offset voltage, and then compensates for them during the subsequent discharge process, such as Figure 2 As shown in (a) and (c).

[0076] The second stage is to store the X 、C R and C P The charge on the capacitor C is quantified to realize the X The traditional method of quantifying time is mostly to directly count time through a counter, which relies on a high-precision clock and is difficult to achieve high measurement accuracy. This invention proposes a new quantification method that combines counter timing with cyclic charging and discharging and charge amplification technologies to achieve high-precision measurement, and the accuracy can be adjusted as needed. The following is a detailed description:

[0077] Select the capacitance value to be measured as full scale, that is, C X =CMAX When , the corresponding time difference is:

[0078]

[0079] like Figure 3 As shown in (b), during the second charge and discharge process, the capacitor C X 、C R 、C P The voltage on the top plate is V S(0) ,like Figure 2 (e) The voltage is stored on capacitor C1 and then continues to discharge time, at which point the capacitor C X 、C R 、C P The upper plate voltage becomes V S(1) , by comparing this voltage value with the reference voltage V R By comparison, we can get the most significant bit (MSB) of the digital conversion result, and the corresponding relationship is as follows:

[0080] V S(1) >V R →MSB=1

[0081] V S(1) ≤V R →MSB=0

[0082] once The discharge time and the corresponding voltage comparison process can produce a digital output, and in order to re-match the full-scale corresponding V in the remaining digital bit evaluation process S(0) value, we need to amplify the remaining digits by a factor of two, specifically through a charge amplification process, such as Figure 2 As shown in (f) and (g), the capacitor C X The upper plate voltage is updated to V′ S(1) , and the corresponding relationships are as follows:

[0083] V S(1) >V R →V′ S(1) =2V S(1) -V R

[0084] V S(1) ≤V R →V′ S(1) =2V S(0) -V R

[0085] Then from the voltage V' S(1) Start duration The discharge process, the voltage after discharge is recorded as V S(2) , the second digital output is obtained through the same voltage comparison and charge amplification process as before and the voltage is updated to V′ S(2) , repeating the above discharge, voltage comparison and charge amplification process to obtain more bits of digital output until the required conversion resolution is achieved.

[0086] For sensors with output type current / resistance / voltage:

[0087] Through the cooperation of the above three circuit structures, first disconnect the connection with the sensor and obtain the reference capacitor array C R The corresponding discharge time is T1, and then the connection with the sensor is restored, and the charge collected by the sampling circuit is stored in C R The voltage generated on the capacitor C1 is stored, and the voltage V at this time is recorded. S(0) , and then proceed Time of discharge, record the voltage V at this time S(1) , then the voltage V s(1) and reference voltage V R Make a comparison and output the most significant bit MSB of the digital conversion result. At the same time, based on the comparison result, the reference capacitor array C is updated through charge amplification. R The voltage at this time is recorded as V' S(1) , repeat the above duration The process of discharge, voltage comparison, and charge amplification continues until the conversion result reaches the required resolution. The details are as follows:

[0088] In the second measurement mode, resistance / current / voltage measurement mode, the entire measurement phase can also be divided into two phases. The first phase is the same as the capacitance measurement mode. First, the reference capacitance array C is recorded. R And the parasitic capacitance C in parallel with it P From V C Discharge to V R Specifically, the time required for the reconfigurable interface circuit to be connected to the resistance to be measured R X / Measured current I X / Measured voltage V X Disconnect the reference capacitor array C R And the parasitic capacitance C in parallel with it P The upper plate voltage is charged to V C , then through the current source I R1 Discharge the capacitor upper plate voltage to the reference voltage V R , corresponding to the first discharge duration T1; then the signal to be measured is sampled. According to the different measurement modes, the sampling circuit is reconstructed by switching to convert different types of measured signals into charge and store them in CR and C P Above, such as Figure 4 As shown in (b)-(d) in the figure, the sampling results are shown in the following formula. Unlike the capacitance measurement mode, for the resistance / current / voltage measurement mode, after the sampling phase, the reconfigurable interface circuit will disconnect the sensor signal to be measured to avoid additional power consumption and the impact on the conversion process.

[0089] The second stage requires the storage in C R and C P The charge on the sensor is digitized, and the conversion process in resistance / current / voltage mode is different from that in capacitance measurement mode, such as Figure 5 As shown, where V S(0) After the sampling phase, C R and C P The upper plate voltage is related to the resistance to be measured R X / Measured current I X / Measured voltage V X The corresponding relationships are:

[0090] (1) When sampling the resistor, V S(0) =R X I R2

[0091] (2) When sampling current, T S Sampling duration

[0092] (3) When sampling voltage, V S(0) =V X (Sampling time)

[0093] With the help of the linear relationship (1)-(3) above, we can calculate the resistance to be measured R X / Measured current I X / Measured voltage V X The measurement is converted to V S(0) digitalization.

[0094] In the first stage of different measurement modes, we get Figure 5 The reference capacitor array C shown in (a) R and parasitic capacitance to ground C P From V C To V R Based on the discharge curve and the corresponding discharge time T1, we will C To V R Sampling value within the range V S(0) Go digital.

[0095] The specific implementation is: After the sampling is completed,S(0) Start to continue discharging Time, at this time ΔT MAX =T1, the voltage on the capacitor plate becomes V S(1) , by comparing V S(1) and reference voltage V R , we can get the most significant bit MSB of the digital conversion result, the corresponding relationship is as follows:

[0096] V S(1) >V R →MSB=1

[0097] V S(1) ≤V R →MSB=0

[0098] like Figure 5 (b) shows that in order to re-match V C to V R To increase the conversion range, we need to amplify the remaining digital bits by two times and repeat the above bit evaluation process. The specific method is to use the charge amplification process to increase the capacitance C R and C P The upper plate voltage is updated to V′ S(1) , and the corresponding relationships are as follows:

[0099] V S(1) >V R →V′ S(1) =2V S(1) -V R

[0100] V S(1) ≤V R →V′ S(1) =2V S(0) -V R

[0101] Then from the voltage V' S(1) Start duration The discharge process, at this time ΔT MAX =T1, the voltage after discharge is recorded as V S(2) , the second digital output is obtained through the same voltage comparison and charge amplification process as before and the voltage is updated to V′ S(2) , repeat the above The discharge, voltage comparison and charge amplification process are used to obtain more digital output bits until the required conversion resolution is achieved.

[0102] See also Figure 6 As shown, the conversion circuit realizes automatic calibration of the operational amplifier U1 based on the principle of correlated double sampling technology, and controls the circuit error capacitor C through the switch. OSDuring charging and discharging, the connection between the conversion circuit and the sampling circuit is first cut off, the circuit noise and the amplifier input offset voltage are sampled and stored, and then the connection with the sampling circuit is quickly restored, thereby achieving the effect of noise reduction and compensation of the amplifier input offset voltage.

[0103] Figure 7 The schematic diagram shows the charge amplification process in the conversion phase. In phase 1, the circuit stores C1V on the input capacitor C1. in In phase 2, the left end of the input capacitor C1 is grounded. At the same time, since the right end of the input capacitor C1 is connected to the amplifier's "virtual ground" terminal, the charge is transferred from the input capacitor C1 to the feedback capacitor C2, and the output node voltage increases. The required amplification gain can be obtained by adjusting the ratio of C1 and C2. It is worth noting that the charge amplifier circuit adopts a stray-insensitive structure. By reasonably arranging the switching sequence of the switches, the influence of the stray capacitance of capacitors C1 and C2 to the ground on the amplification gain is avoided.

[0104] Although specific embodiments of the present invention are described above, those skilled in the art should understand that these are merely examples and that various changes or modifications may be made to these embodiments without departing from the principles and essence of the present invention. Therefore, the scope of protection of the present invention is limited by the appended claims.

Claims

1. A reconfigurable sensor interface circuit based on switched capacitors, characterized in that: The system includes a sampling circuit, a conversion circuit and a digital control circuit. The output end of the digital control circuit is connected to the input end of the digital processor. The sampling circuit is connected to the sensor connection interface and is used to sample the output signal of the output type of capacitance / resistance / current / voltage sensor and convert it into charge and store it in the reference capacitor array C. R superior, The conversion circuit is used to output a multi-bit quantized result of the charge acquired by the sampling circuit by adopting a control method combining time domain and voltage domain, through multiple cycles of charge and discharge, voltage comparison and charge amplification, until the required measurement resolution is achieved; The digital control circuit is used to reconfigure the sampling circuit and the conversion circuit by controlling the switching of the switch under the control of the digital processor, thereby sampling and quantizing the output signal of the output type of the capacitance / resistance / current / voltage sensor; The conversion circuit is configured into three circuit structures. The first circuit structure is configured as a voltage comparator to generate an enable signal of a counter or a one-bit quantization result; the second circuit structure is configured as a unity gain buffer to convert the reference capacitor array C in the sampling circuit into a single-bit quantization result. R The charge on the capacitor is stored on the capacitor C1; the third circuit structure is configured as a charge amplifier, with capacitor C1 as the input capacitor and capacitor C2 as the feedback capacitor to amplify the voltage on the capacitor C1; For sensors with capacitive output type: Through the cooperation of the three circuit structures, the connection with the sensor is first disconnected to obtain the reference capacitance array C R The corresponding discharge time is T1, and then the connection with the sensor is restored to discharge the charge collected by the sampling circuit, and the voltage on the capacitor Cx to be measured after the discharge time T1 is stored on the capacitor C1, and the voltage V at this time is recorded. S(0) , then continue to discharge Time, record the voltage V at this time S(1) , and then the voltage V s(1) and reference voltage V R Make a comparison and output the most significant bit (MSB) of the digital conversion result. At the same time, based on the comparison result, update the voltage of the capacitor Cx to be measured through charge amplification and record the voltage at this time as V′ S(1) , repeat the above duration Discharge, voltage comparison, and charge amplification processes until the conversion result reaches the required resolution; For sensors with output type current / resistance / voltage: Through the cooperation of the three circuit structures, the connection with the sensor is first disconnected to obtain the reference capacitance array C R The corresponding discharge time is T1, and then the connection with the sensor is restored, and the charge collected by the sampling circuit is stored in C R The voltage generated on the capacitor C1 is stored, and the voltage V at this time is recorded. S(0) , and then proceed Time of discharge, record the voltage V at this time S (1), then the voltage V s (1) and reference voltage V R Make a comparison and output the most significant bit MSB of the digital conversion result. At the same time, based on the comparison result, the reference capacitor array C is updated through charge amplification. R The voltage at this time is recorded as V' S(1) , repeat the above duration Discharge, voltage comparison, and charge amplification processes are repeated until the conversion result reaches the required resolution.

2. The switch capacitor-based reconfigurable sensor interface circuit according to claim 1, wherein: The first circuit structure includes an A-shaped structure and a B-shaped structure, The A-type structure includes disconnecting the connection with the sensor through the switch S4, firstly increasing the charging voltage V through the switch S15 C and reference capacitor array C R connected, and then disconnect the charging voltage V through switch S15 C The current source I R1 and reference capacitor array C R The positive electrode of the operational amplifier U1 is connected to the positive electrode of the operational amplifier U1 through the switch S2, the switch S1, and the error capacitor Cos. The negative electrode of the operational amplifier U1 is connected to the positive electrode of the operational amplifier U1 through the switch S6, the switch S12 and the reference voltage V R The output end of the operational amplifier U1 is connected to the digital control circuit; The B-shaped structure includes an operational amplifier U1, the positive electrode of which is sequentially connected to the error capacitor Cos, the switch S1, the switch S2 and the parallel reference capacitor array C R , current source I R1 Connected to the sensor, where the current source I R1 The parallel branch where the sensor is located is connected to a switch S3, the parallel branch where the sensor is located is connected to a switch S4, the cathode of the operational amplifier U1 is connected to its output terminal through a switch S5, and the output terminal of the operational amplifier U1 is connected to the digital control circuit; The second circuit structure includes an operational amplifier U1, the positive electrode of which is sequentially connected to the error capacitor Cos, the switch S1, the switch S2 and the parallel reference capacitor array C R The parallel branch where the sensor is located is connected to a switch S4. The negative electrode of the operational amplifier U1 is connected to its output terminal through a switch S5, and is also connected to the reference voltage V R The output end of the operational amplifier U1 is connected to the digital control circuit; The third circuit structure is first configured into the first structure and then configured into the second structure. The first structure includes an operational amplifier U1, the positive electrode of which is connected to the reference voltage V R The negative electrode of the operational amplifier U1 is connected to the capacitor C1 via the switch S11, and is also connected to the output end via the switch S9, the feedback capacitor C2, and the switch S10 in sequence. The output end of the operational amplifier U1 is connected to the digital control circuit; The second structure includes an operational amplifier U1, the positive electrode of which is connected to the reference voltage V R The negative electrode of the operational amplifier U1 is connected to the reference voltage V through the switch S11, the capacitor C1, the switch S12 and the reference voltage V R The output of the operational amplifier U1 is connected to the reference capacitor array C1 in parallel through the switch S13, the switch S2 and the reference capacitor array C2 in parallel. R It is connected to the sensor, wherein the parallel branch where the sensor is located is connected to a switch S4, and the output end of the operational amplifier U1 is also connected to the digital control circuit.

3. The switch capacitor-based reconfigurable sensor interface circuit according to claim 1, wherein: For sensors with capacitive output type, Among them, C XMAX The capacitance value to be measured corresponds to the full scale of the sensor whose output type is capacitance; For sensors with resistance / voltage / current output, ΔT MAX =T1; According to the comparison result, the capacitor to be measured Cx or the reference capacitor array C is updated by charge amplification according to the rule shown in the following formula. R voltage; V S(1) >V R →V′ S(1) =2V S(1) -V R V S(1) ≤V R →V′ S(1) =2V S(0) -V R Under the control of the digital control circuit, disconnect the sensor and first pass the charging voltage V C For the parallel reference capacitor array C R and parasitic capacitance to ground C P The upper plate is charged, and the charging voltage is V C , and then through the current source I R1 For the parallel reference capacitor array C R and parasitic capacitance to ground C P Discharge until the upper plate voltage is equal to the reference voltage V R , and the corresponding discharge duration is recorded as T1.

4. The switch capacitor-based reconfigurable sensor interface circuit according to claim 1, wherein: The sampling circuit includes a current source I R2 , reference capacitor array C R , charging voltage V C , they are all connected to the sensor through the sensor connection interface, where the current source I R2 , charging voltage V C The parallel branches are respectively connected to a switch S14 and a switch S15.

5. The switch capacitor-based reconfigurable sensor interface circuit according to claim 1, wherein: The conversion circuit also includes an automatic calibration circuit. The automatic calibration circuit adopts the principle of correlated double sampling and realizes the charging and discharging of the error capacitor Cos through switch control. The connection between the conversion circuit and the sampling circuit is first cut off, the circuit noise and the amplifier input offset voltage at this time are sampled and stored, and then the connection with the sampling circuit is quickly restored, thereby achieving the effect of noise reduction and compensating the operational amplifier input offset voltage.

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