Pipeline analog-to-digital converter and signal conversion method

Abstract

A pipeline analog-to-digital converter includes a plurality of converter circuitries and a correction circuitry. The plurality of converter circuitries converts an input signal into a plurality of first digital codes in sequence. A first converter circuitry of the plurality of converter circuitries performs a quantization operation to generate a first corresponding digital code of the first digital codes according to a first signal, wherein the first signal is a signal of the input signal and a previous stage residual signal processed by the first converter circuitry. The correction circuitry combines the first digital codes to output a second digital code, and detects whether the quantization operation is completed to generate a first and a second enable signals, and determines whether to set the second digital code as one of a first or a second default digital code according to the first and the second enable signals. The second enable signal is a delayed signal of the first enable signal.

Description

TECHNICAL FIELD

[0001] The present application relates to pipelined analog-to-digital converters, and more particularly, to pipelined analog-to-digital converters with default digital codes and signal conversion methods thereof. BACKGROUND

[0002] A pipelined analog-to-digital converter can sequentially convert an input signal into corresponding digital codes through multiple stages of conversion. In the prior art, the operation period of each stage of conversion is fixed. As frequency speed increases, the period of time for one cycle becomes shorter. As a result, the comparator circuit in the pipelined analog-to-digital converter can not be able to produce a correct quantization result within a predetermined period of time, resulting in an inaccurate final output digital code. SUMMARY

[0003] In some embodiments, a pipelined analog-to-digital converter includes a plurality of converter circuit systems and a correction circuit system. The plurality of converter circuit systems are configured to sequentially convert an input signal into a plurality of first digital codes, wherein a first converter circuit system of the plurality of converter circuit systems is configured to perform a quantization operation according to a first signal to generate a first corresponding digital code of the plurality of first digital codes, wherein the first signal is the input signal and a signal of a previous stage residual signal processed by the first converter circuit system. The correction circuit system is configured to combine the plurality of first digital codes to output a second digital code, and to detect whether the quantization operation is completed to generate a first enable signal and a second enable signal, and to determine whether to set the second digital code as one of a first default digital code or a second default digital code according to the first enable signal and the second enable signal, wherein the second enable signal is a delayed signal of the first enable signal.

[0004] In some embodiments, a signal conversion method includes sequentially converting an input signal into a plurality of first digital codes through a plurality of converter circuit systems, wherein a first converter circuit system of the plurality of converter circuit systems is configured to perform a quantization operation according to a first signal to generate a first corresponding digital code of the plurality of first digital codes, wherein the first signal is the input signal and a signal of a previous stage residual signal processed by the first converter circuit system; combining the plurality of first digital codes to output a second digital code; detecting whether the quantization operation is completed to generate a first enable signal and a second enable signal, wherein the second enable signal is a delayed signal of the first enable signal; and determining whether to set the second digital code as one of a first default digital code or a second default digital code according to the first enable signal and the second enable signal.

[0005] The features, operation, and effects of the present application will be described in detail below with reference to the accompanying drawings and preferred embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 a schematic diagram of a pipeline analog-to-digital converter according to some embodiments of the present application;

[0007] Figure 2A a schematic diagram of a converter circuit system in Figure 1 according to some embodiments of the present application;

[0008] Figure 2B a schematic diagram of a sub-analog-to-digital converter circuit in Figure 2A according to some embodiments of the present application;

[0009] Figure 2C a schematic diagram of a detection circuit in Figure 1 according to some embodiments of the present application;

[0010] Figure 2D a graph of a conversion characteristic of a signal and a residual signal in Figure 1 according to some embodiments of the present application;

[0011] Figure 3 a flowchart of an operation of a correction circuit system in Figure 1 according to some embodiments of the present application;

[0012] Figure 4 a flowchart of a signal conversion method according to some embodiments of the present application; and

[0013] Figure 5 a partial enlarged view of an interval in Figure 2D according to some embodiments of the present application.

[0014] Symbol Explanation

[0015] 00, 01, 10: digital code

[0016] 100: pipeline analog-to-digital converter

[0017] 110: sample-and-hold circuit

[0018] 120[1], 120[2], 120[3]: converter circuit system

[0019] 121: sub-analog-to-digital converter circuit

[0020] 122: multiplication digital-to-analog converter circuit

[0021] 122-1: sub-digital-to-analog converter circuit

[0022] 122-2: subtracter circuit

[0023] 122-3: residual value amplifier circuit

[0024] 130: correction circuitry

[0025] 132: detection circuitry

[0026] 134: control logic circuitry

[0027] 201, 202: comparator circuitry

[0028] 203: encoder circuitry

[0029] 211, 212: logic gate circuitry

[0030] 213, 214: delay circuitry

[0031] 215-218: flip-flop circuitry

[0032] 221, 222: interval

[0033] 400: signal conversion method

[0034] 501, 502, 503: sub-interval

[0035] A, A', B, B', C, C', D, D': point

[0036] CLK1, CLK1', CLK2, CLK2', CLK3, CLK3': frequency signal

[0037] D1[1]-D1[3], DOUT: digital code

[0038] D2[1]-D2[X]: default digital code

[0039] S1, S2, S3: signal

[0040] S2[1], S2[2]: residual signal

[0041] S310, S320, S330, S410, S420, S430, S440: operation

[0042] SV[1]-SV[4]: effective signal

[0043] VC[1]-VC[8]: control signal

[0044] VIN: input signal

[0045] Tsample: sampling period

[0046] Tamplify: amplification period

[0047] VREF, VREF1, VREF2: reference voltage

[0048] VO1~VO4: Output signals Detailed Implementation

[0049] All terms used herein have their common meanings. The definitions of the above terms in commonly used dictionaries, and examples of the use of any term discussed herein, are merely illustrative and should not be construed as limiting the scope or meaning of the invention. Similarly, the invention is not limited to the various embodiments shown in this specification.

[0050] As used herein, "coupled" or "connected" can refer to two or more components making direct physical or electrical contact with each other, or indirectly making direct physical or electrical contact with each other, or to two or more components operating or moving together. As used herein, the term "circuit" can refer to a single system formed by at least one circuit, and the term "circuit" can refer to a device consisting of at least one transistor and / or at least one active / passive component connected in a certain manner to process signals.

[0051] As used herein, the term "and / or" includes any combination of one or more of the listed related items. The terms first, second, and third, etc., are used herein to describe and identify individual components. Therefore, a first component may also be referred to as a second component without departing from the spirit of the invention. For ease of understanding, similar components in the accompanying drawings will be designated with the same reference numerals.

[0052] Figure 1 A schematic diagram of a pipeline analog-to-digital converter 100 is shown for some embodiments of the present invention. The pipeline analog-to-digital converter 100 includes a sample-and-hold circuit 110, multiple converter circuit systems 120[1] to 120[3] and a correction circuit system 130.

[0053] The sample-and-hold circuit 110 samples the input signal VIN according to the frequency signal CLK1 and outputs the sampled input signal VIN as signal S1. In some embodiments, the sample-and-hold circuit 110 may be implemented by a switched capacitor circuit. Multiple converter circuit systems 120[1] to 120[3] sequentially convert the input signal VIN (i.e. signal S1) sampled by the sample-and-hold circuit 110 into multiple digital codes D1[1] to D1[3]. In some embodiments, the multiple converter circuit systems 120[1] to 120[2] have the same structure. In some embodiments, the converter circuit system 120[3] may be (but is not limited to) a flash analog-to-digital converter circuit, which is used to generate digital code D1[3] according to the residual signal S2[2] generated by the converter circuit system 120[2].

[0054] The correction circuit system 130 detects whether the quantization operation of the converter circuit system 120[1] is complete to generate multiple control signals VC[1] to VC[4]. Similarly, the correction circuit system 130 can detect whether the quantization operation of the converter circuit system 120[2] is complete to generate multiple control signals VC[5] to VC[8]. The correction circuit system 130 also combines multiple digital codes D1[1] to D1[3] to output digital code DOUT, and determines whether to set the digital code DOUT to the corresponding one of multiple default digital codes D2[1] to D2[X] according to the multiple control signals VC[1] to VC[8], where X is a positive integer greater than 1. In some embodiments, the correction circuit system 130 can detect whether the quantization operation of the converter circuit system 120[1] is complete to generate multiple active signals (e.g., for Figure 2A Multiple active signals SV[1]~SV[4] are generated, and multiple control signals VC[1]~VC[4] are generated based on these multiple active signals.

[0055] Similarly, the calibration circuit system 130 can detect whether the quantization operation of the converter circuit system 120[2] is completed to generate multiple active signals (not shown), and generate multiple control signals VC[5] to VC[8] based on the multiple active signals. In other words, the calibration circuit system 130 can determine whether to set the digital code DOUT to the corresponding one of the multiple default digital codes D2[1] to D2[X] based on the multiple active signals. In some embodiments, the calibration circuit system 130 is also used to test the multiple converter circuit systems 120[1] to 120[3] during the test period to generate a portion of the digital codes of the multiple default digital codes D2[1] to D2[X]. The operation here will be referred to below. Figure 3 illustrate.

[0056] In some embodiments, the correction circuit system 130 includes a detection circuit 132 and a control logic circuit 134. The detection circuit 132 can detect whether the quantization operation of the converter circuit system 120[1] and the conversion circuit system 120[2] is completed to generate multiple control signals VC[1] to VC[8]. The control logic circuit 134 can combine multiple digital codes D1[1] to D1[3] into a digital code DOUT. In some embodiments, the detection circuit 132 is also used to store the aforementioned multiple active signals according to at least one frequency signal (e.g., frequency signal CLK3 or CLK3') to generate multiple control signals VC[1] to VC[8]. The control logic circuit 134 determines whether to set the digital code DOUT to the corresponding one of the default digital codes D2[1] to D2[X] according to the multiple control signals VC[1] to VC[8].

[0057] For example, if the detection circuit 132 detects the comparator circuit in the converter circuit system 120 [1] (e.g., for... Figure 2B Before the quantization operation of the comparator circuit 201 is completed, the detection circuit 132 can output multiple control signals VC[1] to VC[2] with a first logic value (e.g., logic value 1). In response to these multiple control signals VC[1] to VC[2], the control logic circuit 134 can set the digital code DOUT to the default digital code D2[y] among multiple default digital codes D2[1] to D2[X], where y is a positive integer greater than 1 and less than X. If the control signal VC[1] has a first logic value and the control signal VC[2] has a second logic value (e.g., logic value 0), the control logic circuit 134 can set the digital code DOUT to the default digit code D2[y-1] or the default digit code D2[y+1] among multiple default digital codes D2[1] to D2[X]. If multiple control signals VC[1]~VC[2] all have a second logic value, the control logic circuit 134 does not set the digital code DOUT to the default digital code D2[y-1], the default digit code D2[y], or the default digit code D2[y+1].

[0058] Similarly, if the detection circuit 132 detects another comparator circuit in the converter circuit system 120 [1] (e.g., a... Figure 2B Before the quantization operation of the comparator circuit 202 is completed, the detection circuit 132 can output control signals VC[3] to VC[4] with a first logic value. In response to these multiple control signals VC[3] to VC[4], the control logic circuit 134 can set the digital code DOUT to the default bit code D2[y+2] among multiple default digital codes D2[1] to D2[X]. If the control signal VC[3] has a first logic value and the control signal VC[4] has a second logic value, the control logic circuit 134 sets the digital code DOUT to the default bit code D2[y+1] or the default bit code D2[y+3] among multiple default digital codes D2[1] to D2[X]. If all multiple control signals VC[3] to VC[4] have a second logic value, the control logic circuit 134 does not set the digital code DOUT to the default digital code D2[y+1], the default bit code D2[y+2], or the default bit code D2[y+3].

[0059] Similarly, the correspondence between the multiple control signals VC[5] to VC[8] and the other digital codes in the multiple default digital codes D2[1] to D2[X] should be understandable. In some embodiments, the control logic circuit 134 may include multiple digital circuits and at least one buffer circuit, wherein the at least one buffer circuit can be used to store multiple default digital codes D2[1] to D2[X], and the multiple digital circuits can be operated as a controller circuit or a processor circuit to execute Figure 3 andFigure 4 Multiple operations within.

[0060] Figure 2A Drawing according to some embodiments of the present invention Figure 1 A schematic diagram of the converter circuit system 120[1]. The converter circuit system 120[1] includes a sub-analog-to-digital converter circuit 121 and a multiplying digital to analog converter (MDAC) circuit 122 (hereinafter referred to as MDAC circuit 122). During the sampling period Tsample of the frequency signal CLK1, the sub-analog-to-digital converter circuit 121 performs a quantization operation based on the signal S1 to generate a digital code D1[1]. The MDAC circuit 122 processes the digital code D1[1] and the signal S1 based on the frequency signal CLK2 to generate a current residual signal S2[1]. For example, in response to the rising edge of the frequency signal CLK2, the MDAC circuit 122 may begin processing the digital code D1[1] and the signal S1, and generate the current residual signal S2[1] during the amplification period Tapmplify of the frequency signal CLK2.

[0061] In some embodiments, the MDAC circuit 122 includes a sub-digital-to-analog converter circuit 122-1, a subtractor circuit 122-2, and a residual amplifier circuit 122-3. In response to the frequency signal CLK2, the sub-digital-to-analog converter circuit 122-1 converts digital code D1[1] into signal S2. The subtractor circuit 122-2 subtracts signal S2 from signal S1 to generate signal S3. The residual amplifier circuit 122-3 amplifies signal S3 to output the current residual signal S2[1]. In some embodiments, the sub-digital-to-analog converter circuit 122-1, the subtractor circuit 122-2, and the residual amplifier circuit 122-3 may be implemented by a switched-capacitor circuit (not shown). Some switches of this switched-capacitor circuit are turned on during the sampling period of the frequency signal CLK1 (Tsample) to store signal S1. Other switches of this switched-capacitor circuit are turned on during the amplification period of the frequency signal CLK2 (Tamplify) to perform the relevant operations of the MDAC circuit 122.

[0062] Figure 2B Drawing according to some embodiments of the present invention Figure 2AA schematic diagram of the sub-analog-to-digital converter circuit 121 is shown. In some embodiments, the sub-analog-to-digital converter circuit 121 includes a comparator circuit 201, a comparator circuit 202, and an encoder circuit 203. The comparator circuit 201 and the comparator circuit 202 compare the signal S1 with the reference voltage VREF1 and the reference voltage VREF2 respectively (equivalent to the aforementioned quantization operation) to generate a plurality of output signals VO1 to VO4. The encoder circuit 203 is used to encode the plurality of output signals VO1 to VO4 according to the frequency signal CLK2 to output the corresponding digital code D1[1]. In some embodiments, the encoder circuit 203 may include a plurality of logic gate circuits (e.g., but not limited to, a plurality of AND gate circuits), which output the digital code D1 on time when the frequency signal CLK2 is a high bit[1].

[0063] In detail, comparator circuit 201 compares signal S1 with reference voltage VREF1 to generate output signals VO1 and VO2. In some embodiments, comparator circuit 201 is a differential comparator circuit. In an initial state, the two outputs of this differential comparator circuit are reset to preset levels so that output signals VO1 and VO2 have default levels. For example, the preset level is a high level (i.e., output signals VO1 and VO2 both have a logic value of 1 in the initial state). In some embodiments, the aforementioned initial state may be (but is not limited to) the state of comparator circuit 201 before entering the amplification period (Tamplify). Alternatively, in other examples, the preset level is a low level (i.e., output signals VO1 and VO2 both have a logic value of 0 in the initial state). After the comparison of signal S1 with reference voltage VREF1 is completed, one output of comparator circuit 201 will have a high level, and the other output of comparator circuit 201 will have a low level. In other words, after the quantization operation is completed, one of the output signals VO1 and VO2 has a logic value of 1 and the other has a logic value of 0. Therefore, the detection circuit 132 can determine whether the quantization operation of the comparator circuit 201 is complete based on the multiple output signals VO1 to VO2. Similarly, the detection circuit 132 can determine whether the quantization operation of the comparator circuit 202 is complete based on the multiple output signals VO3 to VO4. The relevant operations of the comparator circuit 202 can be referred to the relevant operations of the comparator circuit 201, so they will not be repeated. In some embodiments, the reference voltage VREF1 may be (but is not limited to) -0.25 times the reference voltage VREF, and the reference voltage VREF2 may be (but is not limited to) 0.25 times the reference voltage VREF.

[0064] Figure 2C Drawing according to some embodiments of the present invention Figure 1 A schematic diagram of the detection circuit 132 is shown. For ease of drawing, Figure 2COnly the circuit portion of the detection circuit 132 used to detect the quantization operation of the converter circuit system 120 [1] is shown. The detection circuit 132 includes a plurality of logic gate circuits 211-212, a plurality of delay circuits 213-214, and a plurality of flip-flop circuits 215-218. In some embodiments, the logic gate circuit 211 may be (but is not limited to) an anti-mutex OR gate (XNOR) circuit that can generate an activation signal SV [1] based on a plurality of output signals VO1-VO2 from the converter circuit system 120 [1]. In different embodiments, the logic gate circuit 211 may also be implemented by other types of logic gate circuits (e.g., including, but not limited to, NOT AND gate circuits, NOT OR gate circuits, etc.). As previously stated, in the initial state, Figure 2B Multiple output signals VO1 to VO2 have the same logic value. Under this condition, the logic gate circuit 211 outputs an active signal SV with a first logic value [1]. After the quantization operation is completed, one of the output signals VO1 and VO2 has a logic value of 1 and the other has a logic value of 0. Under this condition, the logic gate circuit 211 outputs an active signal SV with a second logic value [1].

[0065] Delay circuit 213 is used to delay the active signal SV[1] to generate active signal SV[2]. In other words, active signal SV[2] is a delayed signal of active signal SV[1]. In some embodiments, the delay time introduced by delay circuit 213 can be adjusted according to system specifications. In some embodiments, delay circuit 213 can be implemented by (but is not limited to) a plurality of serially connected logic gate circuits, which are used to perform an even number of inversions on active signal SV[1]. A plurality of flip-flop circuits 215-216 receive a plurality of active signals SV[1] and SV[2] respectively according to frequency signal CLK3 to generate a plurality of control signals VC[1]-VC[2]. In some embodiments, each of the plurality of flip-flop circuits 215-216 can be a D-type flip-flop circuit. In some embodiments, frequency signal CLK3 can be a delayed signal of frequency signal CLK2. For example, detection circuit 132 may further include a delay circuit (not shown) used to delay frequency signal CLK2 to generate frequency signal CLK3. In some other embodiments, the frequency signal CLK3 may be the same as the frequency signal CLK2.

[0066] If multiple control signals VC[1] to VC[2] all have a second logic value, it means that the quantization operation of comparator circuit 201 can be completed quickly within a predetermined period (e.g., the amplification period Tapmplify). Under this condition, it means that the level of the currently sampled input signal VIN (i.e., signal S1) is significantly different from the reference voltage VREF1. For example, signal S1 is located at... Figure 5The interval corresponding to the digital code 00 or the interval corresponding to the digit code 01. If the control signal VC[1] is the first logic value and the control signal VC[2] is the second logic value, it means that the processing time of the quantization operation of the comparator circuit 201 slightly exceeds the predetermined period. Under this condition, it means that the level of the signal S1 may be near the level of the reference voltage VREF1. For example, the signal S1 is located at Figure 5 Sub-interval 502 or sub-interval 503. Alternatively, if both control signal VC[1] and control signal VC[2] have a first logic value, it means that the quantization operation of comparator circuit 201 requires a long processing time and cannot be completed within the predetermined period. Under this condition, the level of signal S1 may be quite close to the reference voltage VREF1. For example, signal S1 is located at Figure 5 Sub-interval 501. Therefore, based on the same control signal VC[1] and control signal VC[2], the control logic circuit 134 can determine whether to set the digital code DOUT to the default digital code D2[y-1], the default digit code D2[y], or the default digit code D2[y+1]. In other words, in some embodiments, the detection circuit 132 can operate as a time-to-digital converter circuit, which can detect the quantization operation of the comparator circuit 201 to generate digital information that reflects different processing times (i.e., control signals VC[1] and VC[2]). Detailed operation here will be referred to later. Figure 5 illustrate.

[0067] Similar to logic gate circuit 211 and delay circuit 213, logic gate circuit 212 and delay circuit 214 can be used to detect whether the quantization operation of comparator circuit 202 is completed, so as to generate activation signal SV[3] and activation signal SV[4]. Similar to multiple flip-flop circuits 215-216, multiple flip-flop circuits 217-218 can receive activation signal SV[3] and activation signal SV[4] according to frequency signal CLK3, so as to generate control signal VC[3] and VC[4]. According to different control signals VC[3] and VC[4], control logic circuit 134 can decide whether to set digital code DOUT to default digital code D2[y+1], default digital code D2[y+2], or default digital code D2[y+3].

[0068] The circuit structure of converter circuit system 120[2] is the same as that of converter circuit system 120[1]. For example Figure 1 As shown, the operation of the converter circuit system 120[2] is performed based on the frequency signals CLK1' and CLK2'. Similar to... Figure 2AThe frequency signals CLK1' and CLK2' are intermediate frequency signals. CLK1' has a sampling period Tsample, and CLK2' has an amplification period Tapmplify, with the amplification period Tapmplify following the sampling period Tsample of CLK1'. In some embodiments, the sampling period Tsample of CLK1' and the amplification period Tapmplify of CLK2 may partially overlap or not overlap. Similarly, the detection circuit 132 may include additional multiple logic gate circuits, delay circuits, and two flip-flop circuits to detect the quantization operation of the converter circuit system 120 [2]. The multiple logic gate circuits described above may receive multiple output signals from the converter circuit system 120 [2] to generate multiple active signals, and the multiple flip-flop circuits are based on another frequency signal (e.g., Tsample). Figure 1 The frequency signal CLK3' receives the multiple active signals to output control signals VC[5] to VC[8]. The setting method between the frequency signal CLK3' and the frequency signal CLK2' is similar to that of the frequency signal CLK2'. Figure 2C The setting method between frequency signal CLK3 and frequency signal CLK2. The operation and setting method of the above converter circuit system 120[2] and detection circuit 132 can be referred to Figure 2B as well as Figure 2C I understand, so I won't repeat myself.

[0069] Figure 2D Drawing according to some embodiments of the present invention Figure 1 The conversion characteristics of the input signal VIN and the residual signal S2[1] are shown in the figure. Figure 2D In the diagram, the horizontal axis represents the input signal VIN (i.e., signal S1) to the converter circuit system 120[1], and the vertical axis represents the current residual signal S2[1] to the converter circuit system 120[2]. Figure 2B In the example, the sub-analog-to-digital converter circuit 121 is equivalent to a 1.5-bit analog-to-digital converter, which can provide a digital code D1[1] (or D1[2]) corresponding to the region in which the analog signal (e.g., signal S1 or residual signal S2[1]) falls. For example, if the input signal VIN is less than -0.25 times the reference voltage VREF (i.e., reference voltage VREF1), the digital code D1[1] is 00 (its corresponding value is -1). If the input signal VIN is between -0.25 times the reference voltage VREF and 0.25 times the reference voltage VREF (i.e., reference voltage VREF2), the digital code D1[1] is 01 (its corresponding value is 0). If the input signal VIN is greater than 0.25 times the reference voltage VREF, the digital code D1[1] is 10 (its corresponding value is 1).

[0070] In order for the residual signal S2[1] to conform to the input signal range of the secondary converter circuit system (e.g., converter circuit system 120[2]), the MDAC circuit 122 can process the input signal VIN according to the current digital code D1[1] (as shown below). In this way, it can be ensured that the converter circuit system 120[2] can correctly process the input signal VIN in sequence.

[0071] S2[1]=2×V IN -VREF, if V IN >0.25×VREF

[0072] S2[1]=2×V IN If -0.25×VREF < V IN <0.25×VREF

[0073] S2[1]=2×V IN +VREF, if V IN <-0.25×VREF

[0074] According to the above formula, if the sub-analog-to-digital converter circuit 121 determines that the input signal VIN (i.e., signal S1) is less than -0.25 times the reference voltage VREF, the MDAC circuit 122 will shift the input signal VIN upward to output the current stage residual signal S2[1]. In this way, the subsequent converter circuit system (e.g., converter circuit system 120[2] and converter circuit system 120[3]) will output digital codes D1[2] and D1[3] with larger values ​​according to the current stage residual signal S2[1]. Alternatively, if the sub-analog-to-digital converter circuit 121 determines that the input signal VIN is between -0.25 times the reference voltage VREF and 0.25 times the reference voltage VREF, the MDAC circuit 122 will not shift the input signal VIN to output the current stage residual signal S2[1]. In this way, compared to the digital codes D1[2] and D1[3] in the above cases, the subsequent converter circuit system will output digital codes D1[2] and D1[3] with smaller values ​​based on the current residual signal S2[1]. If the sub-analog-to-digital converter circuit 121 determines that the input signal VIN is greater than 0.25 times the reference voltage VREF, the MDAC circuit 122 shifts the input signal VIN downward to output the current residual signal S2[1]. In this way, compared to the digital codes D1[2] and D1[3] in the previous two cases, the subsequent converter circuit system will output digital codes D1[2] and D1[3] with the smallest values ​​based on the current residual signal S2[1].

[0075] Taking two consecutive intervals corresponding to the digital codes 00 and 01 as an example, if the input signal VIN (e.g., falling at point A) is less than but very close to -0.25 times the reference voltage VREF, ideally, the comparator circuit 201 can determine that the input signal VIN is less than -0.25 times the reference voltage VREF. However, due to noise and / or due to a small voltage difference (e.g., the difference between the input signal VIN and the reference voltage VREF1) (denoted as interval 221), the comparator circuit 201 may need a longer time to complete the quantization operation. If the quantization operation cannot be completed within the predetermined amplification period Tapmplify, the comparator circuit 201 may misjudge the input signal VIN (e.g., misjudge it as falling at point A') as being between -0.25 times the reference voltage VREF and 0.25 times the reference voltage VREF. In this case, the MDAC circuit 122 will not shift the input signal VIN (corresponding to the position of point A') upwards, and the subsequent converter circuit system 120[2] and converter circuit system 120[3] will output relatively small digital codes D1[2] and D1[3]. As a result, the subsequent output digital code DOUT will be inaccurate.

[0076] Alternatively, if the input signal VIN (e.g., at point B) is greater than but very close to -0.25 times the reference voltage VREF, ideally, comparator circuit 201 can determine that the input signal VIN is between -0.25 times the reference voltage VREF and 0.25 times the reference voltage VREF. However, due to noise and / or due to a small voltage difference, comparator circuit 201 may misjudge the input signal VIN (e.g., misjudge it as falling at point B') as being less than -0.25 times the reference voltage VREF. In this case, MDAC circuit 122 will shift the input signal VIN (corresponding to point B') upwards, and subsequent converter circuit system 120[2] and converter circuit system 120[3] will output larger digital codes D1[2] and D1[3]. This will make the digital code DOUT inaccurate.

[0077] Similarly, for the two intervals corresponding to two consecutive digital codes 01 and 10, if the input signal VIN (e.g., at point C) is very close to but less than 0.25 times the reference voltage VREF, ideally, the comparator circuit 202 can determine that the input signal VIN is less than 0.25 times the reference voltage VREF. However, due to noise and / or due to the small voltage difference (e.g., the difference between the input signal VIN and the reference voltage VREF) (denoted as interval 222), the comparator circuit 202 may need a long time to complete the quantization operation. If the quantization operation cannot be completed within the predetermined amplification period Tapmplify, the comparator circuit 202 may misjudge the input signal VIN (e.g., misjudge it as falling at point C') as greater than 0.25 times the reference voltage VREF. In this case, the MDAC circuit 122 will shift the input signal VIN (corresponding to the position of point C') downwards, and the subsequent converter circuit system 120[3] will output a smaller digital code D1[3]. This will cause the subsequent output numeric code DOUT to be inaccurate.

[0078] Alternatively, if the input signal VIN (e.g., at point D) is greater than but very close to 0.25 times the reference voltage VREF, ideally, the comparator circuit 202 can determine that the input signal VIN is greater than 0.25 times the reference voltage VREF. However, due to noise and / or due to the small voltage difference, the comparator circuit 202 may misjudge the input signal VIN (e.g., misjudge it as falling at point D') to be between -0.25 times the reference voltage VREF and 0.25 times the reference voltage VREF. In this case, the MDAC circuit 122 will not shift the input signal VIN (corresponding to the position of point D'), and the subsequent converter circuit system 120[3] will output a larger digital code D1[2] to D1[3]. This will make the digital code DOUT inaccurate. In some embodiments, the correction circuit system 130 can be used to correct the input signal VIN (corresponding to the position of point D') by... Figure 3 and Figure 4 The relevant operations will be used to improve the above problems.

[0079] Figure 3 Drawing according to some embodiments of the present invention Figure 1 The operation flowchart of the correction circuit system 130 is shown. In some embodiments, Figure 3 Multiple operations can be performed by the control logic circuit 134 of the correction circuit system 130.

[0080] During operation S310, during a test, the maximum value generated by subsequent converter circuit systems (e.g., converter circuit systems 120[2] to 120[3] after converter circuit system 120[1]) based on the current residual signal output by the converter circuit system is recorded when the converter circuit system (e.g., converter circuit system 120[1]) outputs a corresponding digital code with a first value. For example, when converter circuit system 120[1] outputs a digital code D1[1] with a value of -1 (e.g., digital code 00), control logic circuit 134 may record the maximum value generated by converter system 120[2] and converter circuit system 120[3] based on the residual signal S2[1]. As previously stated, the aforementioned maximum value may be the value generated when a signal S1 with a value of 0 is misjudged as a digital code D1[1] with a value of -1 (e.g., misjudging point B as point B'). Alternatively, when the converter circuit system 120[2] outputs a digital code D1[2] with a value of -1, the control logic circuit 134 can record the maximum value generated by the converter circuit system 120[3] based on the residual signal S2[1].

[0081] During operation S320, during the test, the minimum value generated by the subsequent converter circuit system based on the residual signal of the current stage output by the converter circuit system is recorded when the converter circuit system outputs a corresponding digital code with a second value, wherein the first value and the second value are consecutive values ​​and the second value is greater than the first value. For example, when the converter circuit system 120[1] outputs a digital code D1[1] with a value of 0 (e.g., digital code 01), the control logic circuit 134 can record the minimum value generated by the converter system 120[2] and the converter circuit system 120[3] based on the residual signal S2[1]. As previously mentioned, the minimum value may be the value generated when the signal S1 with a value of -1 is misjudged as a digital code D1[1] with a value of 0 (e.g., misjudging point A as point A'). Alternatively, when the converter circuit system 120[2] outputs a digital code D1[2] with a value of 0, the control logic circuit 134 can record the minimum value generated by the converter circuit system 120[3] based on the residual signal S2[1].

[0082] In operation S330, the corresponding value among the plurality of default numeric codes is determined based on the minimum value, maximum value, first value, and second value. In some embodiments, after recording the maximum value and the minimum value corresponding to all comparator circuits in converter circuit system 120[1] and converter circuit system 120[2], the corresponding value of the plurality of default numeric codes D2[1] to D2[X] can be determined. Figure 2B For the comparator circuit 201 in the middle, the default digital code D2[y] can be expressed as the following formula:

[0083]

[0084] Wherein, N1 is the aforementioned first value (e.g., -1), N2 is the aforementioned second value (e.g., 0), X1 is the aforementioned maximum value, X2 is the aforementioned minimum value, and ω is the weight value. In some embodiments, the weight value ω is the value of normalization of the digital code of the current converter circuit system (e.g., digital code D1[1]) to all digital codes (e.g., digital codes D1[2] and D1[3]) output by the subsequent converter system.

[0085] according to Figure 2D Understandably, after obtaining the minimum and maximum values, the control logic circuit 134 can make the default digital code D2[y] as close as possible to the middle value of interval 221. In this way, a default digital code D2[y] that is closer to the ideal conversion characteristic can be obtained. In this example, the default digital code D2[y-1] can be the digital code corresponding to the aforementioned first value (e.g., -1) (e.g., ...). Figure 2D The digit code 00), while the default digit code D2[y+1] can be the digit code corresponding to the aforementioned second value (e.g., 0). Figure 2D The default digital code D2[y-1] and the default digital code D2[y+1] are known digital codes in advance. Using the above calculation, the control logic circuit 134 can insert an additional default digital code D2[y] between the default digital code D2[y-1] and the default digital code D2[y+1].

[0086] Similarly, by operating S310, S320, and S330, the calibration circuit system 130 can record, during the test, a portion of the digital code (i.e., a portion of the multiple default digital codes D2[1] to D2[X]) corresponding to multiple comparator circuits (e.g., multiple comparator circuits 201 and 202) in the converter circuit system 120[1] and the converter circuit system 120[2]. In this way, in subsequent operations, the calibration circuit system 130 can decide whether to set the digital code DOUT to one of the multiple default digital codes D2[1] to D2[X] based on the detection result of the quantization operation.

[0087] Figure 4A flowchart of a signal conversion method 400 is provided according to some embodiments of the present invention. In operation S410, the input signal is sequentially converted into a plurality of first digital codes (e.g., digital codes D1[1] to D1[3]) by a plurality of converter circuit systems (e.g., converter circuit systems 120[1] to 120[3]), wherein the first converter circuit system in the plurality of converter circuit systems is used to perform a quantization operation according to a first signal to generate a first corresponding digital code among the plurality of first digital codes, wherein the first signal is the signal processed by the first converter circuit system in the input signal and the residual signal from the previous stage. For example, if the first converter circuit system is converter circuit system 120[1], the first signal is the sampled input signal VIN (e.g., signal S1). Or, if the first converter circuit system is converter circuit system 120[2], the first signal is the residual signal S2[1] from converter circuit system 120[1].

[0088] In operation S420, the multiple first digital codes are combined to output a second digital code. In operation S430, it is detected whether the quantization operation is completed to generate a first effective signal and a second effective signal, wherein the second effective signal is a delayed signal of the first effective signal. For example, the logic gate circuit 211 can detect whether the quantization operation performed by the comparator circuit 201 in the converter circuit system 120[1] is completed to generate an effective signal SV[1] and an effective signal SV[2]. Multiple flip-flop circuits 215-216 can receive the effective signal SV[1] and the effective signal SV[2] according to the frequency signal CLK3 to generate multiple control signals VC[1] and VC[2]. Similarly, the detection circuit 212 and the multiple flip-flop circuits 217-218 can detect whether the quantization operation performed by the comparator circuit 202 in the converter circuit system 120[1] is completed to generate multiple control signals VC[3] and VC[4].

[0089] In operation S440, a decision is made based on the first activation signal and the second activation signal whether to set the second digital code to one of the first default digital code (e.g., D1[y]) or the second default digital code (e.g., D1[y-1] or D1[y+1]).

[0090] To illustrate operation S440, refer to Figure 5 ,and Figure 5 Drawing according to some embodiments of the present invention Figure 2D A magnified view of interval 221 in the image. (See image below.) Figure 5As shown, interval 221 can be divided into sub-intervals 501, 502, and 503. Sub-interval 501 is a voltage interval covering -0.25 times the reference voltage VREF. Sub-interval 502 is located between the left boundary of interval 221 and sub-interval 501. Sub-interval 503 is located between the right boundary of interval 221 and sub-interval 501. The voltage (or digital code) corresponding to sub-interval 503 is higher than the voltage (or digital code) corresponding to sub-interval 502. For example, sub-interval 503 corresponds to the default digital code D2[y+1], sub-interval 501 corresponds to the default digital code D2[y], and sub-interval 502 corresponds to the default digital code D2[y-1].

[0091] As mentioned earlier, if multiple control signals VC[1] to VC[2] all have a second logic value (e.g., logic value 0), it means that the quantization operation of comparator circuit 201 can be completed quickly within a predetermined period. Under this condition, signal S1 (or the residual signal from the previous stage) may differ greatly from the reference voltage VREF1 and not be located in sub-interval 501, sub-interval 502, or sub-interval 503 (it may be located outside the aforementioned sub-intervals). Therefore, control logic circuit 134 may not set the digital code DOUT to one of the multiple default digital codes D2[1] to D2[X].

[0092] If multiple control signals VC[1] to VC[2] all have a first logic value (e.g., logic value 1), it means that the quantization operation of comparator circuit 201 cannot be completed within a predetermined period. Under this condition, signal S1 (or the residual signal from the previous stage) may be very close to the reference voltage VREF1 and located in sub-interval 501. Therefore, control logic circuit 134 can set digital code DOUT to the first default digital code (e.g., default digital code D2[y]).

[0093] If control signal VC[1] has a first logic value and control signal VC[2] has a second logic value, it means that the processing time of the quantization operation of comparator circuit 201 may exceed the predetermined period. Under this condition, signal S1 (or the residual signal from the previous stage) may be close to the reference voltage VREF1 and located in sub-interval 502 or sub-interval 503. Therefore, control logic circuit 134 can set digital code DOUT to a second default digital code (e.g., default digital code D2[y-1] or default digital code D2[y+1]).

[0094] In some embodiments, in response to a control signal VC[1] having a first logic value and a control signal VC[2] having a second logic value, the control logic circuit 134 may randomly set the aforementioned second default digit code to one of a default digit code D2[y-1] or a default digit code D2[y+1]. For example, in some embodiments, the correction circuit system 130 further includes a pseudo-random value generator circuit (not shown) for generating pseudo-random values. The control logic circuit 134 may set the second default digit code to the default digit code D2[y-1] in response to a pseudo-random value having the first logic value. Alternatively, the control logic circuit 134 may set the second default digit code to the default digit code D2[y+1] in response to a pseudo-random value having the second logic value.

[0095] In some embodiments, in response to a control signal VC[1] having a first logic value and a control signal VC[2] having a second logic value, the control logic circuit 134 may set a second default digital code to one of a default digital code D2[y-1] or a default digital code D2[y+1] based on a plurality of output signals generated by the quantization operation of the converter circuit system 120[1]. Taking the detection of the quantization operation of the comparator circuit 201 as an example, in response to a control signal VC[1] having a first logic value and a control signal VC[2] having a second logic value, the control logic circuit 134 may set a second default digital code based on a plurality of output signals (e.g., output signal VO3 and / or output signal VO4) of a neighboring comparator circuit (e.g., comparator circuit 202) in the converter circuit system 120[1].

[0096] For example, if comparator circuit 202 determines that signal S1 is greater than reference voltage VREF2, output signal VO3 has a first logic value and output signal VO4 has a second logic value. Under this condition, control logic circuit 134 can set the aforementioned second default digital code to default digital code D2[y+1]. Alternatively, if comparator circuit 202 determines that signal S1 is not greater than reference voltage VREF2, output signal VO3 has a second logic value and output signal VO4 has a first logic value. Under this condition, control logic circuit 134 can set the aforementioned second default digital code to default digital code D2[y-1].

[0097] The above example only uses a sub-analog-to-digital converter circuit 121 containing two comparator circuits, but the present invention is not limited thereto. In a sub-analog-to-digital converter circuit 121 containing three or more comparator circuits, the control logic circuit 134 can set the second default digital code to the default digital code D2[y+1] or the default digital code D2[y-1] based on the output signals generated by the multiple comparator circuits used to identify adjacent voltage ranges.

[0098] The various operations of the signal conversion method 400 described above are merely examples and are not limited to being performed in the order shown in these examples. Without departing from the operation mode and scope of the various embodiments of the present invention, the various operations in the signal conversion method 400 may be appropriately added, replaced, omitted, or performed in a different order.

[0099] The number of circuit components in the above embodiments is for illustrative purposes only and is not intended to limit the invention. For example, the pipelined analog-to-digital converter 100 may include more converter circuitry. Alternatively, the sub-analog-to-digital converter circuit 121 may include more comparator circuitry. Correspondingly, the detection circuit 132 may include more logic gate circuitry, delay circuitry, and flip-flop circuitry.

[0100] In summary, the pipelined analog-to-digital converter and signal conversion method in some embodiments of the present invention can detect whether the quantization operation of each stage of the converter circuit system is completed, so as to generate digital information that reflects different processing times, and decide whether to replace the final output digital code with a specific one of multiple default digital codes based on this digital information. In this way, inaccurate digital codes generated by each stage of the converter circuit system can be avoided.

[0101] Although the above embodiments of the present invention have been disclosed, they are not intended to limit the invention. Any person skilled in the art can make changes to the technical features of the present invention based on the explicit or implicit content of the invention. All such changes fall within the protection scope of the present invention; in other words, the protection scope of the present invention shall be determined by the claims of this application.

Claims

1. A pipelined analog-to-digital converter, characterized in that, The pipeline analog-to-digital converter includes: Multiple converter circuit systems are configured to sequentially convert an input signal into multiple first digital codes, wherein the first converter circuit system in the multiple converter circuit systems is configured to perform a quantization operation based on a first signal to generate a first corresponding digital code among the multiple first digital codes, wherein the first signal is the input signal and the signal processed by the first converter circuit system in the previous stage residual signal; as well as A correction circuit system is used to combine the plurality of first digital codes to output a second digital code, and to detect whether the quantization operation is completed to generate a first effective signal and a second effective signal, and to determine whether to set the second digital code as one of a first default digital code or a second default digital code based on the first effective signal and the second effective signal, wherein the second effective signal is a delayed signal of the first effective signal.

2. The pipeline analog-to-digital converter as described in claim 1, characterized in that, The correction circuit system includes: A detection circuit is used to detect whether the quantization operation is completed to generate the first effective signal, delay the first effective signal to generate the second effective signal, and store the first effective signal and the second effective signal according to the frequency signal to generate a plurality of control signals. as well as A control logic circuit is used to combine the plurality of first digital codes to generate the second digital code, and to determine whether to set the second digital code as the first default digital code or the second default digital code according to the plurality of control signals.

3. The pipeline analog-to-digital converter as described in claim 2, characterized in that, The detection circuit includes: A logic gate circuit is used to generate the first activation signal based on a plurality of output signals from the first converter circuit system; A delay circuit is used to delay the first effective signal to generate the second effective signal; as well as Multiple flip-flop circuits are used to receive the first active signal and the second active signal according to the frequency signal to generate the multiple control signals.

4. The pipeline analog-to-digital converter as described in claim 3, characterized in that, The first converter circuit system performs the quantization operation based on the frequency signal to generate the plurality of output signals.

5. The pipeline analog-to-digital converter as described in claim 1, characterized in that, The first converter circuit system is further configured to process the first signal according to the first corresponding digital code to generate a current level residual signal, and the correction circuit system is further configured to record, during the test, the maximum value generated by at least one of the plurality of converter circuit systems according to the current level residual signal when the first converter circuit system outputs the first corresponding digital code with a first value, and to record the minimum value generated by at least one of the plurality of converter circuit systems according to the current level residual signal when the first converter circuit system outputs the first corresponding digital code with a second value, to generate the first default digital code.

6. The pipeline analog-to-digital converter as described in claim 5, characterized in that, The first value and the second value are consecutive values, and the second value is greater than the first value.

7. The pipeline analog-to-digital converter as described in claim 5, characterized in that, The first default numeric code is determined based on the minimum value, the maximum value, the third value, and the fourth value. The third value is the product of the first value and the weight value, and the fourth value is the product of the second value and the weight value.

8. The pipeline analog-to-digital converter as described in claim 5, characterized in that, The second default numeric code is either the first digit code corresponding to the first value or the second digit code corresponding to the second value.

9. The pipeline analog-to-digital converter as described in claim 8, characterized in that, The correction circuit system is also used to randomly set the second default digital code to the first digital code or the second digital code, or to set the second default digital code to the first digital code or the second digital code according to the multiple output signals generated by the first converter circuit system based on the quantization operation.

10. A signal conversion method, characterized in that, The signal conversion method includes: The input signal is sequentially converted into a plurality of first digital codes by a plurality of converter circuit systems. The first converter circuit system in the plurality of converter circuit systems is used to perform a quantization operation according to a first signal to generate a first corresponding digital code among the plurality of first digital codes. The first signal is the input signal and the signal processed by the first converter circuit system in the previous stage residual signal. as well as Combine the plurality of first digital codes to output a second digital code; The quantization operation is checked to determine whether it is complete in order to generate a first effective signal and a second effective signal, wherein the second effective signal is a delayed signal of the first effective signal; as well as Based on the first activation signal and the second activation signal, it is determined whether to set the second numeric code as one of the first default numeric code or the second default numeric code.

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