An apparatus for implementing a fast two-dimensional DCT transform and a method thereof

Abstract

The application discloses a device for realizing fast two-dimensional DCT transformation and a method thereof. The device comprises a bit line driving unit, a word line driving unit, a source line driving unit, a photoelectric storage and calculation integrated device array unit, an integration unit, a current-voltage conversion and analog-digital conversion unit and a shift accumulation unit. The driving units are used for inputting a transformation matrix and a data vector. The photoelectric storage and calculation integrated device array unit is used for completing multiplication operation of the transformation matrix and the data vector. The integration unit is used for integrating positive value components and negative value components into one data. The current-voltage conversion and analog-digital conversion unit is used for converting a photoelectric current signal into a voltage signal and converting a voltage analog signal into a digital signal. The shift accumulation unit is used for shifting and accumulating intermediate results. The device can realize fast two-dimensional DCT transformation, and when the hardware is used to realize calculation acceleration, the area, power consumption and calculation delay of the hardware architecture are greatly reduced.

Description

Technical Field

[0001] This invention relates to an apparatus and method for implementing fast two-dimensional DCT transformation, belonging to the field of integrated circuit design. Background Technology

[0002] In recent years, with the continuous improvement of image sensor resolution, the amount of information contained in a single image has increased significantly, leading to a corresponding increase in the resources consumed in image transmission and storage. In the JPEG image compression process, the most important algorithm is the Discrete Cosine Transform (DCT). Current research mainly focuses on one-dimensional DCT transformations, while the mainstream method for implementing two-dimensional DCT transformations involves dividing the data into blocks for row and column decomposition, performing a one-dimensional DCT transformation in one direction, and then performing another one-dimensional DCT transformation on the result in another direction, ultimately obtaining the two-dimensional DCT transformation result. During the two-dimensional DCT transformation calculation, most of the computational resources and time are consumed in matrix multiplication. Crossbar arrays based on optoelectronic in-memory computing devices (such as CN110288078A) can handle this task effectively, significantly reducing the power consumption and time required for computation.

[0003] Existing research directly maps the two-dimensional DCT coefficient matrix to the memristor array. First, the N×N data matrix is ​​split into N column vectors, each multiplied by the transformation matrix D to obtain an intermediate result DX. Then, the transpose of the DX matrix is ​​also split into N column vectors, each multiplied by the transformation matrix D to obtain the final result DXD. T Completing a single 2D DCT transformation requires a large number of multiplication and addition operations. When implemented in hardware, the power consumption and area required for multiplication are far greater than those for addition. Therefore, using fewer multiplications to implement the 2D DCT transformation is the key to optimization. Summary of the Invention

[0004] The present invention aims to provide an apparatus for realizing fast two-dimensional DCT transform calculation, which achieves high-precision calculation while reducing latency, power consumption, and area. Another objective of the present invention is to provide a method for performing two-dimensional DCT transform using the above-described apparatus.

[0005] The technical solution adopted by the device of the present invention is as follows:

[0006] A device for implementing fast two-dimensional DCT transformation includes a word line driving unit, a bit line driving unit, a source line driving unit, an opto-in-memory computing (OIM) array unit, an integration unit, a current-to-voltage conversion and analog-to-digital conversion unit, and a shift-accumulator unit. The word line driving unit, bit line driving unit, and source line driving unit are used to convert the voltage value of the input signal into the operating voltage required by the OIM and to input the transformation matrix and data vector. The OIM array unit is used to perform the multiplication operation of the transformation matrix and data vector. The integration unit is used to integrate the positive and negative numerical components of each element obtained after the matrix-vector multiplication operation by the OIM unit into a single data value. The current-to-voltage conversion and analog-to-digital conversion unit is used to convert the photocurrent signal into a voltage signal and then convert the analog voltage signal into a digital signal. The shift-accumulator unit is used to perform shift and accumulation operations on the intermediate results.

[0007] Furthermore, the opto-in-memory computing device array unit is composed of multiple opto-in-memory computing devices on P-type substrates arranged in a crisscross pattern. 2 ×2N 2 A cross-switch array, where N is any positive integer; the gates of opto-memory computing devices in the same row are connected together as a common electrical signal input terminal, and the sources of opto-memory computing devices in the same column are also connected together.

[0008] Furthermore, the integration unit includes N 2 The subtractor, the integration unit subtracts the negative value component from the positive value component of each element in the intermediate result vector to complete the integration of positive and negative data, and then transmits the integrated photocurrent data to the current-voltage conversion and analog-to-digital conversion unit.

[0009] Furthermore, the current-to-voltage conversion and analog-to-digital conversion unit includes N 2 A current-to-voltage converter and N 2 Each analog-to-digital converter (ADC) converts the photocurrent signal of each element in the integrated intermediate result vector into a voltage signal, and then converts the analog voltage signal into a digital signal through the ADC to obtain the intermediate result vector in digital form.

[0010] This invention also provides a method for implementing fast two-dimensional DCT transformation using the above-described apparatus, the specific steps of which are as follows:

[0011] Before performing the DCT transformation calculation, the word line driving unit, bit line driving unit and source line driving unit control the word line, bit line and source line terminal signals of the array, and use the chip select signal to select the opto-memory computing device to be operated.

[0012] Apply the voltage required for operation to the source, drain, and gate of the opto-in-memory computing device to put it into the light input state, expose the opto-in-memory computing device array unit to uniform illumination, and by controlling the exposure time, divide each column vector of the transformation matrix T into positive value column vectors and negative value column vectors, and input and store them into two adjacent columns of opto-in-memory computing devices in the opto-in-memory computing device array unit respectively.

[0013] During the DCT transformation calculation in the opto-in-memory computing device array unit, the word line driving unit inputs each element of the data vector V sequentially from low to high bit position into the opto-in-memory computing device array unit. The data vector V is a vector containing N... 2 A one-dimensional vector with n elements is expressed as: N is any positive integer, which is formed by concatenating the vectors of each row of the original N×N pixel value matrix X in top-down order. Each element has k bits, denoted as v. i =[v i，k-1 v i，k-2 , ..., v i，0 ] binary , 1≤i≤N 2 Each input single-bit vector is

[0014] Each input single-bit vector V j The corresponding element-wise multiplication operation is performed with the transformation matrix T stored in the opto-in-memory computing array unit; the sources of the opto-in-memory computing devices in the same column are connected together, and the photocurrents converge at the source line ends to complete the addition operation in the matrix-vector operation, obtaining the intermediate result vector R. j ;

[0015] The shift-accumulation unit sequentially receives each intermediate result vector R. j After shifting it right by j bits and accumulating it, a total of k-1 shift and accumulation operations are performed to finally obtain the complete matrix-vector multiplication result R. Then, the elements in it are split into N groups of N row vectors and arranged from top to bottom to obtain the DCT transformation result matrix.

[0016] Furthermore, the transformation matrix T is an N 2 ×N 2 A dimensional matrix, which is reconstructed from the original N×N dimensional DCT transformation matrix, is reconstructed in the following way:

[0017] T(a,b)=D(ceil(b / N),ceil(a / N))×D(mod(b,N),mod(a,N)), a,b∈{1,2,…,N 2}

[0018] Where D is the original N×N dimensional DCT transformation matrix, (a, b) represents the element in the a-th row and b-th column, ceil is the rounding function, and mod is the modulo function.

[0019] This invention provides an innovative device and method for calculating two-dimensional DCT transforms. It utilizes the advantages of matrix multiplication using the crossbar array of an opto-in-memory computing device and optimizes the DCT algorithm. This device can be adapted to large-scale arrays and is not limited by the error accumulation caused by multiple matrix operations, thus achieving low-latency and high-energy-efficiency DCT transform calculations. Attached Figure Description

[0020] Figure 1 To realize the overall hardware architecture of the fast two-dimensional DCT transformation device;

[0021] Figure 2 This is the hardware architecture for an optoelectronic in-memory computing device array unit. Detailed Implementation

[0022] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] This embodiment provides a device for implementing fast two-dimensional DCT transformation, including a word-line (WL) driving unit, a bit-line (BL) driving unit, a source-line (SL) driving unit, an opto-memory computing (OMC) array unit, an integration unit, a current-to-voltage conversion and analog-to-digital conversion unit, and a shift-accumulator unit. The gates of devices in the same row are connected together and connected to the word-line driving unit; the sources and drains of devices in the same column are connected together and connected to the source-line driving unit and the bit-line driving unit, respectively. The BL, WL, and SL driving units are used to convert the voltage value of the input signal into the operating voltage required by the opto-in-memory computing device in the opto-in-memory computing device array unit, and to complete the input of the transformation matrix and data vector; the opto-in-memory computing device array unit is used to complete the multiplication operation of the transformation matrix and data vector; the integration unit is used to integrate the positive and negative value components of each element obtained after the matrix-vector multiplication operation of the opto-in-memory computing device unit into a single data; the current-to-voltage conversion and analog-to-digital conversion unit is used to convert the photocurrent signal into a voltage signal and the voltage analog signal into a digital signal; and the shift-accumulation unit is used to perform shift and accumulation operations on the intermediate results.

[0024] Before performing the DCT transformation calculation, the opto-in-memory computing (OMC) array is exposed to uniform illumination. By controlling the WL, BL, and SL terminal signals, the chip select signal is used to select the OMC to be operated. The required operating voltage is applied to their source, drain, and gate to bring them into the light input state. Each column vector of the transformation matrix T is divided into positive and negative value column vectors, which are then input and stored in adjacent columns of OMCs within the OMC array. The transformation matrix T is an N... 2 ×N 2 A dimensional matrix, which is reconstructed from the original N×N dimensional DCT transformation matrix, is reconstructed in the following way:

[0025] T(a,b)=D(ceil(b / N),ceil(a / N))×D(mod(b,N),mod(a,N)), a,b∈{1,2,…,N 2}, where D is the original N×N dimensional DCT transformation matrix, (a, b) represents the element in the a-th row and b-th column, ceil is the rounding function, and mod is the modulo function.

[0026] After the transformation matrix T is input, during the DCT transformation calculation in the opto-in-memory computing device array unit, the WL driver in the BL, WL, and SL driver units inputs each element of the data vector V sequentially from low to high bit position into the opto-in-memory computing device array unit. The data vector V is a vector containing N... 2 A one-dimensional vector with n elements is expressed as: It is formed by concatenating the vectors of each row of the original N×N pixel value matrix X in a top-to-bottom order, where each element has k bits, represented as...

[0027] v i =[v i，k-1 v i，k-2 , ..., v i，0 ] binary , 1≤i≤N 2 ,

[0028] The single-bit vector input each time is

[0029]

[0030] The aforementioned optoelectronic in-memory computing device array unit is an N-type array composed of multiple optoelectronic in-memory computing devices arranged in a crisscross pattern on P-type substrates. 2 ×2N 2 A crossbar array of N dimensions 2 ×2N 2 N opto-in-memory computing devices are arranged in a row2 Line 2N 2 The columns connect the gates of the opto-memory computing devices in the same row as a common electrical signal input terminal, and each time a single-bit vector V is input from the WL controller. j The photocurrents of the photocurrents are multiplied element-wise by the transformation matrix T stored in the opto-in-memory computing array unit. Connecting the sources of the same column of opto-in-memory computing devices causes their photocurrents to converge at the SL terminal, where the addition operation in the matrix-vector operation is performed, yielding the intermediate result vector R. j The operation expression is in, Among them, V j Let T be the single-bit vector input for each iteration, T be the transformation matrix stored in the array cell of the opto-in-memory computing device, and R be the vector. j Each element is divided into positive and negative numerical components.

[0031] The integration unit contains N 2 One subtractor, using the intermediate result vector R j The positive value component of each element is subtracted from the negative value component to complete the integration of positive and negative data. The integrated photocurrent data is then transmitted to the IV conversion and analog-to-digital conversion units.

[0032] The current-to-voltage conversion and analog-to-digital conversion unit contains N 2 A current-to-voltage (IV) converter and N 2 Each analog-to-digital converter (ADC) will integrate the intermediate result vector R. j The photocurrent signal of each element is converted into a voltage signal by an IV converter, and then the analog voltage signal is converted into a digital signal by an ADC to obtain the intermediate result vector R in digital form. j .

[0033] The shift-accumulator unit receives each intermediate result vector R sequentially during the DCT transformation calculation process. j After shifting it right by j bits and accumulating the results, a total of k-1 shift and accumulation operations are performed to obtain the complete DCT transform result vector R. The expression for its shift and accumulation is as follows: The result matrix of the DCT transformation is obtained by splitting the elements into N groups of N row vectors and arranging them from top to bottom.

[0034] In this embodiment, the dimensions of both the data matrix and the DCT transformation matrix are 4×4. The opto-in-memory computing device array uses 512 opto-in-memory computing devices with P-type substrates arranged in a 16×32-dimensional crossbar array. For a specific structural example, please refer to Figure 8 of patent application CN110288078A.

[0035] The 4×4 dimensional DCT transformation matrix D is shown in Table 1.

[0036] Table 1 DCT Transform Matrix D

[0037] 0.5000 0.5000 0.5000 0.5000 0.6533 0.2706 -0.2706 -0.6533 0.5000 -0.5000 -0.5000 0.5000 0.2706 -0.6533 0.6533 -0.2706

[0038] The DCT transformation matrix D is reconstructed according to T(a, b) = D(ceil(b / N), ceil(a / N)) × D(mod(b, N), mod(a, N)), i, j ∈ {1, 2, ..., 16} to obtain a 16×16 dimensional transformation matrix T, as shown in Table 2. Here, D is the original N×N dimensional DCT transformation matrix, (a, b) represents the element in the a-th row and b-th column, ceil is the rounding function, and mod is the modulo function.

[0039] Table 2. Reconstructed Transformation Matrix T

[0040] 0.25 0.3266 0.25 0.1353 0.3266 0.4268 0.3266 0.1768 0.25 0.3266 0.25 0.1353 0.1353 0.1768 0.1353 0.0732 0.25 0.1353 -0.25 -0.3266 0.3266 0.1768 -0.3266 -0.4268 0.25 0.1353 -0.25 -0.3266 0.1353 0.0732 -0.1353 -0.1768 0.25 -0.1353 -0.25 0.3266 0.3266 -0.1768 -0.3266 0.4268 0.25 -0.1353 -0.25 0.3266 0.1353 -0.0732 -0.1353 0.1768 0.25 -0.3266 0.25 -0.1353 0.3266 -0.4268 0.3266 -0.1768 0.25 -0.3266 0.25 -0.1353 0.1353 -0.1768 0.1353 -0.0732 0.25 0.3266 0.25 0.1353 0.1353 0.1768 0.1353 0.0732 -0.25 -0.3266 -0.25 -0.1353 -0.3266 -0.4268 -0.3266 -0.1768 0.25 0.1353 -0.25 -0.3266 0.1353 0.0732 -0.1353 -0.1768 -0.25 -0.1353 0.25 0.3266 -0.3266 -0.1768 0.3266 0.4268 0.25 -0.1353 -0.25 0.3266 0.1353 -0.0732 -0.1353 0.1768 -0.25 0.1353 0.25 -0.3266 -0.3266 0.1768 0.3266 -0.4268 0.25 -0.3266 0.25 -0.1353 0.1353 -0.1768 0.1353 -0.0732 -0.25 0.3266 -0.25 0.1353 -0.3266 0.4268 -0.3266 0.1768 0.25 0.3266 0.25 0.1353 -0.1353 -0.1768 -0.1353 -0.0732 -0.25 -0.3266 -0.25 -0.1353 0.3266 0.4268 0.3266 0.1768 0.25 0.1353 -0.25 -0.3266 -0.1353 -0.0732 0.1353 0.1768 -0.25 -0.1353 0.25 0.3266 0.3266 0.1768 -0.3266 -0.4268 0.25 -0.1353 -0.25 0.3266 -0.1353 0.0732 0.1353 -0.1768 -0.25 0.1353 0.25 -0.3266 0.3266 -0.1768 -0.3266 0.4268 0.25 -0.3266 0.25 -0.1353 -0.1353 0.1768 -0.1353 0.0732 -0.25 0.3266 -0.25 0.1353 0.3266 -0.4268 0.3266 -0.1768 0.25 0.3266 0.25 0.1353 -0.3266 -0.4268 -0.3266 -0.1768 0.25 0.3266 0.25 0.1353 -0.1353 -0.1768 -0.1353 -0.0732 0.25 0.1353 -0.25 -0.3266 -0.3266 -0.1768 0.3266 0.4268 0.25 0.1353 -0.25 -0.3266 -0.1353 -0.0732 0.1353 0.1768 0.25 -0.1353 -0.25 0.3266 -0.3266 0.1768 0.3266 -0.4268 0.25 -0.1353 -0.25 0.3266 -0.1353 0.0732 0.1353 -0.1768 0.25 -0.3266 0.25 -0.1353 -0.3266 0.4268 -0.3266 0.1768 0.25 -0.3266 0.25 -0.1353 -0.1353 0.1768 -0.1353 0.0732

[0041] Before performing the DCT transformation calculation, the opto-in-memory computing device array unit is exposed to uniform illumination. By controlling the BL, WL, and SL terminal signals, the chip select signal is used to select the opto-in-memory computing device to be operated. The voltage required for operation is applied to their source, drain, and gate to put them into the light input state. Then, each column vector of the transformation matrix T is divided into positive value vectors and negative value vectors, which are input and stored in two adjacent columns of opto-in-memory computing devices in the opto-in-memory computing device array unit.

[0042] The 4×4 pixel value matrix X is shown in Table 3.

[0043] Table 3 Pixel Value Matrix X

[0044] 135 199 238 33 145 120 3 86 41 203 79 135 42 154 67 167

[0045] The data vector V is formed by concatenating the vectors of each row of the pixel value matrix X in top-down order, where V = [135, 199, 238, 33, 145, 120, 3, 86, 41, 203, 79, 135, 42, 154, 67, 167]. Converting this from decimal to binary, each element has 8 bits, represented as v. i =[v i，7 v i，6 , ..., v i，0 ] binary , 1≤i≤16, as shown in Table 4.

[0046] Table 4. Binary form of data vector V

[0047] <![CDATA[v1]]> 10000111 <![CDATA[v9]]> 00101001 <![CDATA[v2]]> 11000111 <![CDATA[v 10 ]]> 11001011 <![CDATA[v3]]> 11101110 <![CDATA[v 11 ]]> 01001111 <![CDATA[v4]]> 00100001 <![CDATA[v 12 ]]> 10000111 <![CDATA[v5]]> 10010001 <![CDATA[v 13 ]]> 00101010 <![CDATA[v6]]> 01111000 <![CDATA[v 14 ]]> 10011010 <![CDATA[v7]]> 00000011 <![CDATA[v 15 ]]> 01000011 <![CDATA[v8]]> 01010110 <![CDATA[v 16 ]]> 10100111

[0048] Each input single-bit vector is V j =[v 1，j-1 v 2，j-1 , ..., v 16，j-1 ], 1≤j≤8, as shown in Table 5,

[0049] Table 5 Single-bit data vector V j

[0050]

[0051]

[0052] The gates of opto-memory computing devices in the same row are connected together as their common signal input port, and a single-bit data vector V is transmitted from the WL driver. j The data are sequentially input into the opto-in-memory computing (OMC) array unit, where they are multiplied element-wise with the transformation matrix T stored in the OMC array unit. The sources of the OMC devices in the same column are connected, and their photocurrents converge at the SL terminal to perform addition operations in matrix-vector operations, yielding an intermediate result vector R. j The operation expression is R j =V j ×T=[r 1，j-1 r 2，j-1 , ..., r 16，j-1 ], R j Each element is divided into positive and negative numerical components. The integration unit contains 16 subtractors, using an intermediate result vector R. j Subtracting the negative value component from the positive value component of each element completes the integration of positive and negative data. At this point, the intermediate result vector R is... j As shown in Table 6

[0053] Table 6 Intermediate Result Vector R j

[0054] <![CDATA[R1]]> 2.75 -0.1353 0.25 0.3266 0.056 0.884 0.3266 -0.4268 -0.25 -0.5179 0.25 -0.5972 0.7885 0.0732 0.1353 -0.884 <![CDATA[R2]]> 3 -0.4619 -0.5 0.1913 -0.4619 0.3536 -0.1913 0.3536 0.5 1.1151 0 0.0793 0.1913 0.3536 -0.4619 -0.3536 <![CDATA[R3]]> 1.75 -0.7885 0.25 0.056 0.5179 0.9268 -0.5179 0.1768 0.25 0.7885 -0.25 -0.056 0.5972 0.1768 -0.5972 0.5732 <![CDATA[R4]]> 1.75 0.7885 -0.75 -0.056 -0.5972 -0.884 -0.3266 0.4268 -0.25 -0.1353 0.25 0.3266 0.5179 -0.0732 -0.1353 0.884 <![CDATA[R5]]> 1 0.2706 0 -0.6532 0.0793 -0.1036 0.4619 0.25 -0.5 0 -0.5 0 -1.1151 -0.25 -0.1913 0.6036 <![CDATA[R6]]> 1.5 0 0.5 0 0 -0.7072 -0.9238 0 0.5 -0.9238 0.5 0.3826 0 0 0.3826 0.7072 <![CDATA[R7]]> 1.75 -0.3266 -1.25 -0.1353 0.3266 0.0732 -0.056 -0.6768 -0.25 0.056 -0.25 0.7885 0.1353 0.3232 -0.7885 0.4268 <![CDATA[R8]]> 2 0.2706 0 -0.6532 0.1913 0.9572 -0.1913 1.1036 0.5 0 -0.5 0 0.4619 -0.3964 -0.4619 -0.4572

[0055] At this point, the intermediate result vector R j The photocurrent flows into the current-to-voltage (V / V) converter and analog-to-digital (ADC) conversion unit, containing 16 V / V converters and 16 ADCs, and integrates the intermediate result vector R. j The photocurrent signal of each element is converted into a voltage signal by an IV converter, and then the analog voltage signal is converted into a digital signal by an ADC to obtain the intermediate result vector R in digital form. j .

[0056] During the matrix-vector multiplication calculation process in the opto-in-memory computing device array unit, the shift-accumulator unit sequentially receives each intermediate result vector R. j After shifting it right by j bits and then accumulating the results, a total of 7 shift and accumulation operations are performed to finally obtain the complete matrix-vector multiplication result R. The expression for its shift and accumulation is as follows: R = [461.75 20.1589 -69.75 -102.235 43.0838 101.1448 -54.982 106.3476 55.75 -22.1937 -70.75 64.6574 57.6439 -33.1524 -104.665 8.8552]. The elements in this matrix are split into four groups of four, forming four row vectors arranged from top to bottom. This results in the DCT transformation matrix.

[0057] Compared to traditional DXD T The method of implementing two-dimensional DCT transformation is such that the reconstruction of two-dimensional DCT transformation using the device of this invention is not limited by the error accumulation caused by multiple matrix operations. While improving the accuracy of the operation, it greatly reduces the area, power consumption and computational latency of the hardware architecture.

Claims

1. A method for implementing a fast two-dimensional DCT transform, the device comprising a word line driving unit, a bit line driving unit, a source line driving unit, an array unit of optoelectronic memory and arithmetic integrated devices, an integrating unit, a current-voltage conversion and analog-digital conversion unit, and a shift and accumulation unit, wherein the word line driving unit, the bit line driving unit, and the source line driving unit are used to convert the voltage value of an input signal into the operating voltage required by the optoelectronic memory and arithmetic integrated devices, and to complete the input of the transform matrix and the data vector. The photoelectric storage and calculation integrated device array unit is used to complete multiplication operation of a transformation matrix and a data vector; the integration unit is used to integrate positive value components and negative value components of each element obtained after the photoelectric storage and calculation integrated device unit completes matrix vector multiplication operation into one data; the current-voltage conversion and analog-digital conversion unit is used to convert a photoelectric current signal into a voltage signal, and then convert the voltage analog signal into a digital signal; and the shift and accumulation unit is used to perform shift and accumulation operation on an intermediate result. Before performing calculation of DCT transformation, the word line driving unit, the bit line driving unit and the source line driving unit control word line, bit line and source line end signals of the array, and a chip selection signal is used to select the photoelectric storage and calculation integrated device which needs to be operated; A voltage required for operation is applied to a source electrode, a drain electrode and a gate electrode of the photoelectric storage and calculation integrated device which needs to be operated, so that the photoelectric storage and calculation integrated device enters a light input state, the photoelectric storage and calculation integrated device array unit is exposed to uniform light, and each column vector of the transformation matrix T is divided into a positive value column vector and a negative value column vector, and is input and stored into two adjacent column photoelectric storage and calculation integrated devices in the photoelectric storage and calculation integrated device array unit by controlling exposure time. In the calculation process of DCT transformation in the optoelectronic memory-computing integrated device array unit, the word line driving unit inputs each element in the data vector V from low to high in bit to the optoelectronic memory-computing integrated device array unit, the data vector V is a one-dimensional vector containing N 2 elements, and the expression is N is any positive integer, which is spliced by connecting the head and tail of each row vector of the original N*N pixel value matrix X from top to bottom, and each element has k bits, expressed as v i =[v i,k-1 ,v i,k-2 ,……,v i,0 ] binary , 1≤i≤N 2 , and the single-bit vector input each time is The single-bit vector T input each time j The corresponding elements are multiplied with the transformation matrix T stored in the optoelectronic memory and calculation integrated array unit; the source electrodes of the same column of optoelectronic memory and calculation integrated devices are connected, the photocurrents converge at the source line end to complete the addition operation in the matrix vector operation, and the intermediate result vector R is obtained j ; The shift and accumulation unit receives each intermediate result vector R in turn j After k-1 times of shift and accumulation operation, the complete matrix-vector multiplication result R is obtained, and the elements in R are split into N row vectors arranged from top to bottom as the DCT transformation result matrix.

2. The method for implementing a fast two-dimensional DCT transform according to claim 1, wherein, The photoelectric storage and calculation integrated device array unit is N 2 ×2N 2 crossbar array, wherein N is any positive integer; the gates of photoelectric storage and calculation integrated devices in the same row are connected as a common electrical signal input terminal, and the sources of photoelectric storage and calculation integrated devices in the same column are also connected.

3. The method for implementing a fast two-dimensional DCT transform according to claim 2, wherein, The integration unit includes N 2 subtraction units, which subtract the positive value component from the negative value component of each element in the intermediate result vector to complete the positive-negative data integration, and then pass the integrated photocurrent data to the current-voltage conversion and analog-digital conversion unit.

4. The method for implementing a fast two-dimensional DCT transform according to claim 2, wherein, The current-voltage conversion and analog-digital conversion unit comprises N 2 current-voltage converters and N 2 analog-digital converters, the current-voltage conversion and analog-digital conversion unit converts the photocurrent signal of each element in the integrated intermediate result vector into a voltage signal through the current-voltage converters respectively, and then converts the voltage analog signal into a digital signal through the analog-digital converters to obtain the intermediate result vector in digital form.

5. The method for implementing a fast two-dimensional DCT transform according to claim 1, wherein, The transformation matrix T is an N 2 x N 2 dimensional matrix which is reconstructed from the original N x N dimensional DCT transformation matrix in such a way that T(a,b) = D(ceil(b / N), ceil(a / N)) x D(mod(b,N), mod(a,N)), a,b e {1,2,...,N 2} Wherein, D is an original N×N-dimensional DCT transformation matrix, (a, b) represents an a-th row and b-th column element, ceil is a rounding function, and mod is a remainder function.

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