Method for adjusting row hammer refresh rate and related memory device and system

Abstract

Methods for adjusting row hammer refresh rates and related memory devices and systems are disclosed. A method can include determining a number of valid commands associated with at least one bank of a memory device during a first time interval. The method can further include adjusting a row hammer refresh rate for the at least one bank for a second time interval based on the number of valid commands associated with the at least one bank during the first time interval.

Description

[0001] Related information of divisional application

[0002] This application is a divisional application. The parent of this divisional application is International Patent Application PCT / US2020 / 018750, filed February 19, 2020, entering the National Stage for Application Number “202080021480.3” and entitled “Methods for Adjusting Row Hammer Refresh Rates and Related Memory Devices and Systems” invention patent application. The above-identified application claims the benefit under Article 8 of the Patent Cooperation Treaty of U.S. Patent Application Serial No. 16 / 391,560, filed April 23, 2019. TECHNICAL FIELD

[0003] Embodiments of the present disclosure relate to adjusting row hammer refresh rates for memory devices, and more specifically, to independently adjusting row hammer refresh rates for one or more banks of a memory device based on bank activity. Still more specifically, some embodiments relate to methods for such adjustment and related memory devices and systems. BACKGROUND

[0004] Memory devices are typically provided as internal semiconductor circuits in computers or other electronic systems. There are many different types of memory, including volatile and non-volatile memory. Volatile memory requires power to maintain its data (e.g., host data, error data, etc.) and includes, among others, random access memory (RAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), content addressable memory (CAM), thyristor random access memory (TRAM), low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), and graphics DDR SDRAM.

[0005] As memory density increases, intermittent failures have emerged in some memory devices that can experience failure due to repeated access to a particular row of memory cells (e.g., cells coupled to an access line). For example, a row that is physically proximate to a row that is frequently accessed experiences an increased probability of data corruption. Repeated access to a particular row can be referred to as a “hammering” event, and hammering of a row can cause problems such as, for example, migration across pass gates. Leakage and parasitic current caused by hammering of a row can cause data corruption in unaccessed physically proximate rows, which can be referred to as adjacent rows or victim rows. For example, the resulting corruption problem can be referred to as hammering interference and / or row hammer interference.

[0006] Row hammer effects are due to the nature of memory cells, which can include a transistor and a capacitor. The charge state of the capacitor can determine whether the memory cell stores a "1" or a "0" as a binary value. In addition, a large number of memory cells are packed closely together. The densely packed cells can cause an activated capacitor to have an effect on the charge of neighboring capacitors, especially when one of the cells is activated quickly (e.g., row hammer effects). In addition, capacitors can have a natural discharge rate and can be rewritten to compensate for this discharge, referred to as "refreshing."

[0007] Some methods to reduce the adverse effects of row hammering on neighboring rows include refreshing a neighboring row in response to determining that a hammering event has occurred. For example, in response to determining that a particular row has been targeted for repeated accesses (e.g., the row has been subjected to more than a threshold number of accesses within a refresh period), a physically adjacent row thereof can be selected for a targeted refresh operation, which can be referred to as a row hammer refresh operation. SUMMARY

[0008] One or more embodiments of the disclosure include a method of operating a memory device. The method can include determining a number of active commands associated with at least one memory bank of the memory device during a first time interval. The method can also include adjusting a row hammer refresh rate of the at least one memory bank for a second time interval based on the number of active commands associated with the at least one memory bank during the first time interval.

[0009] Some embodiments of the disclosure include a memory device. The memory device can include a memory array including a number of memory banks. The memory can also include at least one controller configured to adjust a row hammer refresh rate of at least one of the number of memory banks based on an amount of activity associated with the at least one memory bank.

[0010] Additional embodiments of the disclosure include an electronic system. The electronic system can include at least one input device, at least one output device, and at least one processor device operably coupled to the input device and the output device. The electronic system can also include at least one memory device operably coupled to the at least one processor device and including a memory cell array including a number of memory banks and at least one controller. The at least one controller can be configured to detect row accesses associated with at least one of the number of memory banks. The at least one controller can also be configured to set a row hammer refresh rate of the at least one memory bank based on a number of detected row accesses associated with the at least one memory bank. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 is a block diagram of a memory device in accordance with at least one embodiment of the disclosure.

[0012] Figure 2 An example integrated circuit including a number of memory banks is illustrated in accordance with at least one embodiment of the present disclosure.

[0013] Figure 3A and 3B An example timing diagram including a number of refresh commands associated with a memory device is depicted.

[0014] Figure 4A and 4B Another example timing diagram including a number of refresh commands associated with independent auto-refresh and row hammer refresh pumping of a memory device is depicted.

[0015] Figure 5 Timing diagrams including a number of example time intervals associated with a number of memory banks of a memory device are illustrated in accordance with various embodiments of the present disclosure.

[0016] Figure 6 Another timing diagram including a number of example time intervals associated with a number of memory banks of a memory device is depicted in accordance with various embodiments of the present disclosure.

[0017] Figure 7 A number of example refresh sequences associated with a memory device are depicted.

[0018] Figure 8 Timing diagrams including a number of example time intervals associated with memory banks of a memory device are depicted in accordance with various embodiments of the present disclosure.

[0019] Figure 9 Additional example refresh sequences associated with a number of memory banks of a memory device are depicted in accordance with various embodiments of the present disclosure.

[0020] Figure 10A is a block diagram of a portion of a memory device including example refresh address control circuitry in accordance with one or more embodiments of the present disclosure.

[0021] Figure 10B is a table illustrating various row hammer refresh rates and associated multi-bit words used to program a row hammer refresh rate.

[0022] Figure 11 is a block diagram of an example controller in accordance with various embodiments of the present disclosure.

[0023] Figure 12 is a flow diagram of an example method of operating a memory device in accordance with various embodiments of the present disclosure.

[0024] Figure 13 is a simplified block diagram of an example memory device implemented in accordance with one or more embodiments described herein.

[0025] Figure 14 is a simplified block diagram of an example electronic system implemented in accordance with one or more embodiments described herein. DETAILED DESCRIPTION

[0026] Generally, a "row hammer event" occurs when a refresh command is executed to refresh a word line adjacent to a hammered word line. A particular word line is "hammered" when it is accessed via a memory access operation (e.g., an active command) in a manner that can cause data errors in adjacent word lines. Typically, a word line is hammered when it is accessed more than a predetermined number of times.

[0027] Row hammer refresh operations can generally be performed via a refresh steal operation, in which a refresh operation (or a portion of a refresh operation) sent from a memory device controller and received at a memory device is "stolen" and a row hammer refresh is performed in place of the automatic refresh.

[0028] Various embodiments of the present disclosure relate to adjusting a row hammer refresh rate of a memory device. More specifically, in some embodiments, a row hammer refresh rate of one or more banks of a memory device can be independently adjusted based on an amount of activity (e.g., a number of row accesses) associated with the one or more banks. Still more specifically, according to some embodiments, a number of active signals associated with a bank (e.g., a number of active signals received at the bank) (e.g., during a time interval) can be counted, and a row hammer refresh rate of the bank (e.g., over a subsequent time interval) can be adjusted based on the number of active signals.

[0029] As disclosed more fully herein, various embodiments can reduce power consumption and processing overhead of a memory device without substantially reducing performance and / or reliability of the memory device. More specifically, at least some embodiments can eliminate unnecessary row hammer refresh operations, thereby reducing power consumption while still mitigating adverse row hammer effects.

[0030] Figure 1 is a block diagram of a memory device 100 in accordance with one or more embodiments of the present disclosure. The memory device 100 can include, for example, DRAM (dynamic random access memory), SDRAM (synchronous dynamic random access memory), DDR SDRAM (double data rate DRAM), SGRAM (synchronous graphics random access memory), LPDDR SDRAM, graphics DDR SDRAM, content addressable memory (CAM), or any combination thereof. The memory device 100, which can be integrated on a semiconductor chip, can include an array of memory cells 102.

[0031] In Figure 1In this embodiment, the memory cell array 102 is shown to include eight memory banks BANK0 to 7. In other embodiments, the memory cell array 102 may include more or fewer memory banks. Each memory bank includes several word lines WL, several bit lines BL, and... and arranged on several word lines WL and several bit lines BL and Several memory cells MC at the intersection point. The selection of word line WL can be performed by row decoder 104 and bit line BL and The selection can be performed by the column decoder 106. Figure 1 In one embodiment, row decoder 104 may include a corresponding row decoder for each memory bank BANK0 to 7, and column decoder 106 may include a corresponding column decoder for each memory bank BANK0 to 7.

[0032] Bitline BL and Coupled to the corresponding sense amplifier SAMP. From bit line BL or The read data can be amplified by the sense amplifier SAMP and transmitted to the read / write amplifier 107 via the complementary local data line (LIOT / B), the transmission gate (TG), and the complementary main data line (MIOT / B). Conversely, the write data output from the read / write amplifier 107 can be transmitted to the sense amplifier SAMP via the complementary main data line MIOT / B, the transmission gate TG, and the complementary local data line LIO / B, and written to the coupled bit line BL or In the memory cell MC.

[0033] The memory device 100 is typically configured to receive various inputs (e.g., from an external controller) via various terminals such as address terminal 110, command terminal 112, clock terminal 114, data terminal 116, and data mask terminal 118. The memory device 100 may include additional terminals such as power supply terminals 120 and 122.

[0034] During expected operation, one or more command signals COM received via command terminal 112 can be transmitted to command decoder 150 via command input circuitry 152. Command decoder 150 may include circuitry configured to generate various internal commands by decoding one or more command signals COM. Examples of internal commands include valid signal ACT, read / write signal R / W, and refresh signal AREF.

[0035] Further, one or more address signals ADD received via address terminals 110 can be communicated to address decoders 130 via address input circuitry 132. Address decoders 130 can be configured to supply a row address XADD to row decoders 104 and a column address YADD to column decoders 106. The row address XADD, which can be supplied to refresh address control circuitry 140, can be a signal including a plurality of bits (which can be transmitted serially or in parallel) and can correspond to a particular row of a memory bank (e.g., activated by an active signal ACT).

[0036] An active signal ACT can include a pulsed signal activated in response to a command signal COM indicating a row access (e.g., an active command). A row decoder 104 specifying a memory bank address can be activated in response to the active signal ACT. Thus, a word line WL specified by the row address XADD can be selected and activated.

[0037] A read / write signal R / W can include a pulsed signal activated in response to a command signal COM indicating a column access (e.g., a read command or a write command). A column decoder 106 can be activated in response to the read / write signal R / W, and a bit line BL specified by the column address YADD can be selected.

[0038] In response to the active signal ACT, the read signal, the row address XADD, and the column address YADD, data can be read from a memory cell MC specified by the row address XADD and the column address YADD. The read data can be output via a sense amplifier SAMP, a pass gate TG, a read / write amplifier 107, input / output circuitry 162, and data terminals 116. Further, in response to the active signal ACT, the write signal, the row address XADD, and the column address YADD, write data can be supplied to the memory cell array 102 via data terminals 116, input / output circuitry 162, read / write amplifier 107, pass gate TG, and sense amplifier SAMP. The write data can be written to a memory cell MC specified by the row address XADD and the column address YADD.

[0039] A refresh signal AREF can include a pulsed signal activated when the command signal COM includes an auto-refresh command. The refresh signal AREF can be supplied to refresh address control circuitry 140, which is also configured to receive the active signal ACT and the row address XADD. The refresh address control circuitry 140 is configured to provide a row address RXADD specifying a particular word line to be refreshed. In some examples, the refresh address control circuitry 140 can be responsive to a refresh signal AREF from an external controller (e.g., a microprocessor) to provide the row address RXADD to the row decoders 104. Figure 1The refresh address control circuit 140 can be configured to provide a row address RXADD in response to a sequential refresh command received (not shown). In addition, the refresh address control circuit 140 can be configured to "steal" or otherwise preempt a refresh operation received from an external controller and replace the refresh operation with a row hammer refresh operation. In this example, the refresh address control circuit 140 can provide a row address RXADD in response to a row hammer refresh event.

[0040] The clock signal CK and may be received via the clock terminal 114. The clock input circuit 170 can generate an internal clock signal ICLK based on the clock signal CK and The internal clock signal ICLK can be communicated to various components of the memory device 100, such as the command decoder 150 and the internal clock generator 172. The internal clock generator 172 can generate an internal clock signal LCLK, which can be communicated to the input / output circuit 162 (e.g., for controlling the timing of operation of the input / output circuit 162). In addition, the data mask terminal 118 can receive one or more data mask signals DM. When the data mask signal DM is activated, overwriting of corresponding data can be inhibited.

[0041] Figure 2 An example integrated circuit (IC) (also referred to herein as a "die") 200 is illustrated that includes a number of memory banks 202. The IC 200 also includes logic 204 for performing one or more refresh operations including a row hammer refresh (RHR) operation. In addition, in at least some embodiments, each memory bank 202 can include dedicated logic (such as one or more address registers (e.g., flip-flops or latches) for storing one or more row hammer addresses (RHAs) for the associated memory bank; Figure 2 (not shown). It will be appreciated by persons skilled in the art that, for memory systems (e.g., including single-die or multi-die packages), it can be desirable to mitigate row hammer effects while also minimizing power consumption.

[0042] Figure 3A A timing diagram 300 is depicted that includes a number of refresh commands REF for a refresh sequence for a memory device, where each refresh command REF includes a number of refreshes (also referred to herein as "pumps") 302. In the timing diagram 300, each refresh 302 of each refresh command REF is used for an auto-refresh. In other words, in this example, Figure 3A None of the refreshes shown in the timing diagram 350 are stolen for RHR operations. Figure 3B A timing diagram 350 is depicted that includes a number of refresh commands REF. In the timing diagram 350, for every eight refresh commands REF, four refreshes (depicted as refreshes 304) are stolen for RHR. For example, for the first eight refresh commands REF, the refreshes 304 are stolen for RHR. In this example, the refreshes 304 are stolen for RHR in response to a row hammer refresh event. Figure 3BEach of the two initial refresh commands REF of the refresh sequence shown in FIG. 3A can be stolen for refreshing adjacent word lines. In other words, for every eight refresh commands REF, two refreshes (depicted by reference element 304) can be stolen for refreshing two word lines of the neighboring (+1 / -1) hammered rows.

[0043] Figure 4A A timing diagram 400 including a number of refresh commands REF is depicted, where each refresh command REF includes one refresh (e.g., one pump). In timing diagram 400, all refreshes are auto-refreshes 402. In other words, Figure 4A None of the refreshes shown in FIG. 3B are stolen for RHR operations. Figure 4B A timing diagram 450 including a number of refresh commands REF is depicted. In timing diagram 450, for every three refresh commands REF, two refreshes (depicted by reference element 404) are used to refresh two word lines of the neighboring (+1 / -1) hammered rows.

[0044] In contrast to the operations described in FIG. 3A, Figure 3B In contrast to the operations described in FIG. 3A, Figure 4B The RHR operations described in FIG. 3B can not use auto-refresh pumps. Rather, according to some embodiments, dedicated RHR pumps can be used for RHR operations. In other words, auto-refresh pumps and RHR pumps can be independent, and thus it is not necessary to steal auto-refresh pumps for RHR operations.

[0045] In some systems, if at least one row access does not occur at the memory device (i.e., no bank of the memory device receives a valid command) during a time interval (e.g., a "steal phase" or "steal series"), a row hammer operation is skipped for a subsequent time interval (e.g., a subsequent steal phase or steal series). However, in these systems, if a row access occurs at only one bank or only a number of banks of the memory device during a time interval, an RHR operation can still occur at each bank of the memory device during a subsequent time interval (e.g., regardless of whether a row access occurs at each bank). Thus, power is not necessarily used to perform an RHR operation on a bank that does not receive at least one row access. In other words, regardless of whether a row access is associated with a bank during a time interval, an RHR operation is still performed on the bank during a subsequent time interval.

[0046] According to various embodiments of the present disclosure, the row hammer refresh rate of each memory bank of a memory device is adjustable. More specifically, in some embodiments, based on activity (or lack thereof) associated with a memory bank, a row hammer refresh operation of the memory bank can be activated or deactivated, or in some cases unmodified. Further, in some embodiments, based on activity (or lack thereof) associated with a memory bank, the row hammer refresh rate of the memory bank can be increased or decreased, or in some cases unmodified.

[0047] More specifically, according to some embodiments, a row hammer refresh of a memory bank can be activated or deactivated based on whether activity is occurring at the memory bank. For example, if a memory bank does not receive at least one valid signal (e.g., during a time interval), no row hammer refresh can be performed on the memory bank (e.g., the row hammer refresh rate is zero) (e.g., during a subsequent time interval). Further, if a memory bank receives at least one valid signal (e.g., during a time interval), a row hammer refresh can be performed on the memory bank (e.g., during a subsequent time interval).

[0048] Alternatively or additionally, the row hammer refresh rate of a memory bank can be independently adjusted (e.g., via one or more bits) based on the amount of activity of the memory bank. In a more particular example, based on a relatively high amount of activity (e.g., 25, 50, or 100 valid commands or more) associated with a memory bank, the row hammer refresh rate of the memory bank can be set (e.g., via one or more bits) to a relatively high rate (e.g., such that two refreshes are stolen for every refresh command). As another example, based on an average amount of activity associated with a memory bank, the row hammer refresh rate of the memory bank can be set (e.g., via one or more bits) to an average rate (e.g., such that two refreshes are stolen for every three refresh commands). In yet another example, based on a relatively low amount of activity (e.g., 15, 10, or 5 valid commands or less) associated with a memory bank, the row hammer refresh rate of the memory bank can be set (e.g., via one or more bits) to a relatively low rate (e.g., such that two refreshes are stolen for every six refresh commands). According to some embodiments, the amount of activity of a memory bank during a first time interval can be detected, and the row hammer refresh rate of the memory bank for a second subsequent time interval can be set based on the amount of activity detected during the first time interval.

[0049] Figure 5is a timing diagram 500 depicting a number of time intervals (e.g., a steal series) 502A to 502L for a number of memory banks (e.g., all memory banks) of a memory device. According to various embodiments of the present disclosure, for each time interval for a number of memory banks that does not include at least one row access (e.g., does not include a valid signal), a subsequent time interval for the memory banks can not include an RHR operation (e.g., the row hammer refresh rate is zero). In some embodiments, for example, activity (e.g., one or more valid signals) associated with a memory bank of a memory device can be monitored during a sampling period (e.g., during a time interval 502). Further, based on the activity (or lack thereof), a periodic RHR operation can or can not be performed (e.g., after the sampling period is complete). More specifically, for example, if a time interval 502D does not include a valid signal, the row hammer refresh rate for a number of memory banks can be set such that an RHR operation can not occur at the number of memory banks during a subsequent time interval 502E.

[0050] Figure 6 is a timing diagram 600 depicting a number of time intervals 602 for a number of particular memory banks of a memory device. More specifically, the timing diagram 600 depicts a number of time intervals 602 for four example memory banks of a memory device (i.e., bank 2, bank 12, bank 19, and bank 23). According to various embodiments of the present disclosure, for each time interval (e.g., a steal series) for a memory bank that does not include a valid signal, a subsequent time interval for the memory bank can not include an RHR operation. More specifically, for example, if a time interval 602D for a first memory bank 610 (e.g., "bank 2") of a memory device does not include a valid signal, a subsequent time interval 602E for the first memory bank 610 can not include an RHR operation. Further, for example, if a time interval 602G for a second memory bank 612 (e.g., "bank 12") of a memory device does not include a valid signal, a subsequent time interval 602H for the second memory bank 612 can not include an RHR operation. Further, for example, if a time interval 602B for a third memory bank 614 (e.g., "bank 19") of a memory device does not include a valid signal, a subsequent time interval 602C for the third memory bank 614 can not include an RHR operation. Additionally, for example, if a time interval 602F for a fourth memory bank 616 (e.g., "bank 23") of a memory device does not include a valid signal, a subsequent time interval 602G for the fourth memory bank 616 can not include an RHR operation.

[0051] Figure 7 depicts a number of refresh sequences associated with a memory device. More specifically, Figure 7A refresh sequence 702 is depicted that includes a number of refresh commands REF, where each refresh command REF includes a number of auto-refreshes 703 and RHR 705. For example, in some embodiments, refresh sequence 702 can represent a default refresh sequence for a memory device (e.g., memory device 100) where the default refresh sequence can indicate a default row hammer refresh rate. In this example, the default row hammer refresh rate for refresh sequence 702 is that for every three refresh commands REF, two refreshes are stolen for RHR operations. Other default row hammer refresh rates can occur, such as a maximum row hammer refresh rate (e.g., for every refresh command, two refreshes are stolen for RHR operations), a minimum row hammer refresh rate (e.g., for every 10 refresh commands, two refreshes are stolen for RHR operations), or any other row hammer refresh rate. Figure 1

[0052] Figure 7 Further depicted are a refresh sequence 704 for one bank of a memory device (i.e., bank X) and a refresh sequence 706 for another bank of the memory device (e.g., bank Y). As illustrated, each refresh sequence 704 / 706 includes a number of refresh commands REF, where each refresh command REF includes a number of refreshes (e.g., auto-refreshes 703 and RHR 705).

[0053] In this example, as depicted by refresh sequence 704, the row hammer refresh rate for bank X is the same as the row hammer refresh rate depicted by refresh sequence 702. For example, in this embodiment, bank X can have received (e.g., during a certain time interval) at least one valid command, thus, the row hammer refresh rate for bank X is unchanged relative to the default row hammer refresh rate.

[0054] Continuing with this example, as depicted by refresh sequence 706, the row hammer refresh rate for bank Y is different than the row hammer refresh rate depicted by refresh sequence 702. For example, in this embodiment, bank Y can not have received (e.g., during a certain time interval) at least one valid command, thus, the row hammer refresh rate for bank Y is decreased relative to the default row hammer refresh rate. As a more particular example, during a first time interval (e.g., a time interval that includes refresh commands REF 750, 751, and / or 752), bank Y can not have received at least one valid command, thus, unlike bank X, bank Y does not include an RHR operation during refresh command 753. In other words, because bank Y did not receive at least one valid command during a time interval, the row hammer refresh rate for bank Y can be adjusted such that no RHR operation is performed at bank Y during a subsequent time interval (e.g., during refresh command 753).

[0055] ​Further, for example, during a subsequent time interval (e.g., a time interval including refresh command REF 753, 754, and / or 755), bank Y can have received at least one valid command, thus, like bank X, bank Y includes an RHR operation during refresh command 756. In other words, because at least some activity occurred at bank Y during a time interval (e.g., a time interval including refresh command 753, 754, and / or 755), the row hammer refresh rate of bank Y can be adjusted such that an RHR operation is performed at bank Y during a subsequent time interval (e.g., during refresh command 756).

[0056] Thus, as shown in, for example Figures 5 to 7 According to various embodiments, the row hammer refresh operations of different banks of a memory device are independently controlled, thus, during a certain time interval, some banks of a memory device can perform row hammer refresh operations and some banks of a memory device can not perform row hammer refresh operations, as shown in, for example

[0057] As noted above, in some embodiments, the row hammer refresh rate of a bank can be adjusted based on the amount of activity of the bank. In some embodiments, for example, activity (e.g., one or more valid signals) associated with a bank of a memory device can be monitored during a sampling period (e.g., a time interval). Further, based on the activity (or lack of activity), the row hammer refresh rate of the bank can be adjusted (e.g., between sampling periods). More specifically, in some embodiments, for example, in response to a bank not receiving at least a minimum threshold number (e.g., 1, 5, 10, 20, 50, etc.) of valid commands (e.g., during a time interval), the row hammer refresh rate of the bank can be adjusted from one row hammer refresh rate (e.g., a default row hammer refresh rate) to another, lower row hammer refresh rate (e.g., a minimum row hammer refresh rate). Further, for example, in response to a bank operating at a reduced row hammer refresh rate (e.g., relative to a default row hammer refresh rate) receiving at least a minimum threshold number of valid commands (e.g., during a time interval), the row hammer refresh rate of the bank can be adjusted from the lower row hammer refresh rate to a higher row hammer refresh rate (e.g., a default row hammer refresh rate).

[0058] For example, Figure 8 A memory device (e.g., Figure 1the number of valid signals associated with the bank (e.g., received at the bank) for each time interval of the bank. Moreover, based on the number of valid signals associated with the bank, the row hammer refresh rate of the bank can be adjusted. More specifically, for example, if the bank receives 2Z valid signals during a time interval 802E, the row hammer refresh rate of the memory device for time interval 802F can be adjusted to a first row hammer refresh rate (e.g., such that for every three refresh commands, two refreshes are stolen for RHR operations). Moreover, for example, if the bank receives 3Z valid signals during time interval 802F, the row hammer refresh rate of the memory device for time interval 802G can be adjusted (e.g., increased) to a second row hammer refresh rate (e.g., such that for every refresh command, two refreshes are stolen for RHR operations). As another example, if the bank receives Z valid signals during time interval 802H, the row hammer refresh rate of the memory device for time interval 8021 can be adjusted (e.g., decreased) to a third row hammer refresh rate (e.g., such that for every six refresh commands, two refreshes are stolen for RHR operations). Although the time intervals depicted in FIG. 8 depict only one bank of the memory device 100, the same or similar operations can be performed for other banks (e.g., all banks) of the memory device. Figure 8 The time intervals depicted depict only one bank of the memory device, but the same or similar operations can be performed for other banks (e.g., all banks) of the memory device.

[0059] Figure 9 The time intervals depicted depict only one bank of the memory device, but the same or similar operations can be performed for other banks (e.g., all banks) of the memory device. Figure 9 Each refresh sequence illustrated in FIG. 9 can indicate a refresh rate (e.g., during one or more time intervals, such as time interval 802 shown in FIG. 8) for the memory device. More specifically, for example, the refresh sequence 902 depicted in FIG. 9 indicates a first row hammer refresh rate, such as a maximum row hammer refresh rate (i.e., two refreshes are stolen for RHR for every refresh command REF). Figure 8 The time intervals depicted depict only one bank of the memory device, but the same or similar operations can be performed for other banks (e.g., all banks) of the memory device. Figure 9 The time intervals depicted depict only one bank of the memory device, but the same or similar operations can be performed for other banks (e.g., all banks) of the memory device.

[0060] Figure 9The refresh sequence 904 of one bank of the memory device (i.e., bank A) and the refresh sequence 906 of another bank of the memory device (e.g., bank B) are further described. As illustrated, each refresh sequence 904 / 906 contains a plurality of refresh commands REF, wherein each refresh command REF contains a plurality of refreshes 903 and RHR 905. In this example, refresh sequence 904 describes a second row hammer refresh rate (i.e., for every three refresh commands REF, two refreshes are stolen), and refresh sequence 906 describes a third row hammer refresh rate (i.e., for every six refresh commands REF, two refreshes are stolen for RHR).

[0061] Therefore, for example Figure 8 and 9 As shown in the examples, according to various embodiments, the row hammer refresh rate of different banks of the memory device is independently controlled, and therefore at various time intervals (e.g., Figure 8 During the time interval 802), the memory bank of the memory device can operate at different row refresh rates (e.g., as...). Figure 9 (For example, based on the need for row hammer refresh).

[0062] Figure 10A This is a block diagram of a portion of a memory device 1000 including a refresh address control circuitry 1040, according to various embodiments of the present disclosure. For example, Figure 1 The refresh address control circuit 140 may include a refresh address control circuit 1040. The memory device 1000 further includes a row decoder 104 coupled to the refresh address control circuit 1040.

[0063] In at least some embodiments, at least some components of the refresh address control circuitry 1040 and / or the line decoder 104 may correspond to a specific memory bank of the memory device, and in at least some embodiments, these components may be reused for each memory bank of the memory device. Therefore, in some embodiments, the memory device (e.g. Figure 1 The memory device 100 may include multiple refresh address control circuits 1040 and row decoders 104. For the sake of brevity, only the components of a single memory bank will be described.

[0064] The refresh address control circuit 1040 includes a controller 1050, an RHR status control 1052, an address sampler 1054, an ArmSample generator 1056, and a refresh address generator 1058. The refresh address control circuit 1040 can be configured to receive various signals, such as the automatic refresh signal AREF, the row address XADD, and the valid signal ACT. In some embodiments, the refresh address control circuit 1040 can receive signals from the memory controller (…). Figure 10A (Not shown in China) Figure 1The address decoders 130 and / or command decoders 150 shown in FIG. 1 receive one or more of these signals.

[0065] The ArmSample generator 1056 can be configured to generate a sampling signal, ArmSample, which can alternate between a low logic level and a high logic level. An ArmSample activation can be a "pulse" in which ArmSample is raised to a high logic level and then returned to a low logic level.

[0066] The address sampler 1054 can be configured to receive a row address, XADD, and ArmSample. In some embodiments, the row address, XADD, can change as access operations (e.g., valid operations) are directed to different rows of a memory cell array (e.g., the memory cell array 102) of a memory device. Whenever the address sampler 1054 receives an activation (e.g., a pulse) of ArmSample, the address sampler 1054 can sample and capture a current value of the row address, XADD. In some embodiments, the address sampler 1054 can provide the current sampled and captured value of the row address, XADD, as a match address, HitXADD, to the refresh address generator 1058. The refresh address generator 1058 can provide one or more victim addresses (e.g., to the row decoder 104) associated with the match address, HitXADD, as a refresh address, RXADD. Figure 1

[0067] The controller 1050 can be configured to receive a valid signal, ACT. According to various embodiments of the disclosure, the controller 1050, which can include logic such as one or more flip-flops and / or one or more counters 1051, can be configured to count a number of times the valid signal, ACT, is received at an associated bank. More specifically, the controller 1050 can be configured to count a number of times the valid signal, ACT, is received at an associated bank during a time interval (e.g., a steal sequence). In these embodiments, the counter 1051 can be reset (e.g., via control logic) (e.g., at the end of the time interval). Further, based on the number of times the valid signal, ACT, is received at an associated bank (e.g., during the time interval), the controller 1050 can generate a signal communicated to the RHR state control 1052.

[0068] ​In some embodiments, controller 1050 can be configured to determine whether a row hammer refresh operation should occur at the memory bank and / or at what rate the row hammer refresh should occur (i.e., the row hammer refresh rate) based on the number of valid signals received (e.g., during a time interval). Thus, in these embodiments, the signal sent from controller 1050 to RHR state control 1052 can include an indication of whether a row hammer refresh operation should occur at the memory bank and / or the row hammer refresh rate of the memory bank. In other embodiments, controller 1050 can be configured to count the number of valid signals and communicate this information to RHR state control 1052. In these embodiments, RHR state control 1052 can be configured to determine whether a row hammer refresh operation should occur at the memory bank and / or at what rate the row hammer refresh should occur.

[0069] RHR state control 1052 can include, for example, logic components and can be configured to control the rate and timing of refresh operations (e.g., auto-refresh and / or RHR operations). For example, based on the signals received from controller 1050, RHR state control 1052 can provide a signal RHR to activate row hammer refresh (e.g., refresh of victim rows corresponding to identified aggressor rows). As noted above, in some embodiments, RHR state control 1052 can receive a signal from controller 1050 indicating whether a row hammer refresh operation should occur at the memory bank and / or at what rate the row hammer refresh should occur. In other embodiments, based on the signals received from controller 1050, RHR state control 1052 can be configured to determine whether a row hammer refresh operation should occur at the memory bank and / or at what rate the row hammer refresh should occur. In some embodiments, RHR state control 1052 can assert an internal refresh signal IREF and / or a row hammer refresh signal RHR in response to the signals received from controller 1050.

[0070] In some embodiments, the row hammer refresh rate of a memory bank can be set via one or more bits (e.g., of a multi-bit word). Figure 10B Table 1080 illustrates various RHR rates for programming the row hammer refresh rate and associated multi-bit words. For example, with reference to Figure 10A and 10BThe controller 1050 and / or the RHR state control 1052 can set the row hammer refresh rate via a multi-bit word "000" such that for every refresh command, all refreshes are stolen as row hammer refreshes. As another example, the controller 1050 and / or the RHR state control 1052 can set the row hammer refresh rate via a multi-bit word "011" such that for every four refresh commands, one refresh is stolen as a row hammer refresh. As yet another example, the controller 1050 and / or the RHR state control 1052 can set the row hammer refresh rate via a multi-bit word "111" such that for every eight refresh commands, one refresh is stolen as a row hammer refresh. Other row hammer refresh rates and multi-bit words for programming the associated row hammer refresh rate can be used (e.g., as described in Figure 10B

[0071] The RHR state control 1052 can also provide an internal refresh signal IREF to indicate that an auto-refresh should occur. In response to the RHR activation, a refresh address generator 1058 can provide a refresh address RXADD, which can be an auto-refresh address or can be one or more victim addresses corresponding to victim lines of an aggressor line corresponding to the matching address HitXADD. A row decoder 104 can perform a targeted refresh operation in response to the refresh address RXADD and the row hammer refresh signal RHR.

[0072] Methods, apparatuses, and systems for determining aggressor and / or victim lines related to row hammer refresh operations are known in the art and thus details related to determining aggressor and / or victim lines will not be described in detail.

[0073] With continued reference to Figure 10A The refresh address generator 1058 can receive the row hammer refresh signal RHR and the matching address HitXADD. The matching address HitXADD can represent an aggressor line. The refresh address generator 1058 can determine the location of one or more victim lines based on the matching address HitXADD and provide them as the refresh address RXADD. In some embodiments, the victim lines can include lines that are physically adjacent to the aggressor line (e.g., HitXADD+1 and HitXADD-1). Further, in some embodiments, the victim lines can also include lines that are physically adjacent to the physically adjacent lines of the aggressor line (e.g., HitXADD+2 and HitXADD-2). Other relationships between victim lines and identified aggressor lines can be used in other examples.

[0074] The refresh address generator 1058 can determine the value of the refresh address RXADD based on the row hammer refresh signal RHR. In some embodiments, when the signal RHR is not active, the refresh address generator 1058 can provide one of the auto-refresh address sequences. When the signal RHR is active, the refresh address generator 1058 can provide a targeted refresh address, such as a victim address, as the refresh address RXADD. ​

[0075] Row decoder 104 can perform one or more operations on a memory array (not shown) based on the received signals and address. For example, in response to active signal ACT and row address XADD (and IREF and RHR at low logic levels), row decoder 104 can perform one or more access operations (e.g., active operations) on the specified row address XADD. In response to RHR signal being active, row decoder 104 can refresh refresh address RXADD.

[0076] Although controller 1050 is illustrated as a separate component, in some embodiments, RHR state control 1052 can include controller 1050, or vice versa. Further, in some embodiments, rather than a memory device (e.g., memory device 100) including a controller dedicated to each memory bank, the memory device can include a number of controllers less than or equal to the number of memory banks. For example, in some embodiments, at least one controller external to the one or more memory banks can be used to control, set, and / or adjust the row hammer refresh rate of the one or more memory banks. For example, in at least some embodiments, a memory device can include one or more controllers configured to monitor activity associated with one or more memory banks of the memory device. The one or more controllers can also be configured to communicate one or more signals to the one or more memory banks to control, set, and / or adjust the row hammer refresh rate of the one or more memory banks. More specifically, the one or more controllers can be configured to independently monitor (e.g., activity) and control (e.g., set and / or adjust the row hammer refresh rate) each memory bank of the memory device.

[0077] Further, in at least some other embodiments, at least one controller external to the memory device can be configured to determine an amount of activity associated with each memory bank. For example, the at least one external controller can be configured to receive and / or sense one or more signals sent to and / or received from the memory device indicative of an amount of activity associated with one or more memory banks of the memory device. More specifically, for example, the at least one controller can be configured to receive and / or sense active signals sent to the memory banks. Further, in these embodiments, the at least one controller can be configured to control, set, and / or adjust row hammer refresh operations and / or row hammer refresh rates of one or more memory banks of the memory device. For example, in these embodiments, the at least one controller can send one or more signals to the memory device (e.g., memory device 100) (e.g., via command terminals 112) to control, set, and / or adjust row hammer refresh operations and / or row hammer refresh rates of the one or more memory banks. Figure 1

[0078] ​In each of these embodiments, the controller can be configured to control (e.g., activate and deactivate) the row hammer refresh operation of the memory bank based on whether any activity has occurred (e.g., whether a valid signal has been received). Alternatively or additionally, the controller can be configured to set and / or adjust the row hammer refresh rate of the memory bank based on an amount of activity that has occurred (e.g., based on a number of valid signals that have been received at the memory bank).

[0079] Figure 11 A controller 1100 according to various embodiments of the disclosure is depicted. According to various embodiments, the controller 1100 can be implemented within a memory device or can be external to the memory device. The controller 1100 can be configured to receive one or more signals 1102. For example, the signals 1102, which can include one or more signals, can be received from components within or external to the memory device. The signals 1102 can be indicative of activity associated with one or more memory banks of the memory device. The controller 1100 can also be configured to communicate one or more signals 1104 to one or more memory banks (memory bank 0 through memory bank J-l). More specifically, for example, the controller 1100 can be configured to send at least one signal to each memory bank of the memory device.

[0080] As a non-limiting example, the controller 1100 can include one or more counters (e.g., one counter for each memory bank) for counting a number of valid signals sent to and / or received at each memory bank (e.g., during a time interval). For example, the controller 1100 can determine that a first memory bank has received M valid signals during a first time interval based on one or more received signals and a value stored in a counter associated with the first memory bank. In response thereto, the controller 1100 can communicate a signal (e.g., to the first memory bank) to increase a row hammer refresh rate of the first memory bank (e.g., for a second time interval). Further, for example, the controller 1100 can determine that a second memory bank has received N valid signals during the first time interval (where N < M) based on one or more received signals and a value stored in a counter associated with the second memory bank. In response thereto, the controller 1100 can communicate a signal (e.g., to the second memory bank) to decrease a row hammer refresh rate of the second memory bank (e.g., for the second time interval).

[0081] Various embodiments of the disclosure can apply to each memory bank of the memory bank. For example, the above with reference to Figures 5 to 11The described embodiments can apply to each memory bank of a memory device or to some subset of the memory banks of a memory device. More specifically, for example, in some embodiments, a memory device can be configured to count active signals associated with each memory bank and adjust the row hammer refresh rate of each memory bank of the memory device based on the number of associated active signals. In other embodiments, a memory device can be configured to activate or deactivate row hammer refresh operations for each memory bank of the memory device based on whether the memory bank has received one or more active signals. In yet other embodiments, the row hammer refresh rate of some memory banks of a memory device can be adjusted based on the number of active signals and the row hammer refresh rate of other memory banks of the memory device can be activated or deactivated based on whether any activity is detected (e.g., whether at least one active signal is received).

[0082] Figure 12 FIG. 12 is a flow diagram of an example method 1200 of operating a memory device in accordance with various embodiments of the present disclosure. The method 1200 can be arranged in accordance with at least one embodiment described in the present disclosure. In some embodiments, the method 1200 can be performed by a device or system such as Figure 1 the memory device 100 of FIG. 1, Figure 2 the integrated circuit 200 of FIG. 2, Figure 10A the refresh address control circuit 1040 of FIG. 10, Figure 11 the controller 1100 of FIG. 11, Figure 13 the memory device 1300 of FIG. 13, and / or Figure 14 the electronic system 1400 of FIG. 14, or another device or system. Although illustrated as discrete blocks, various blocks can be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation.

[0083] The method 1200 can begin at block 1202, where an amount of activity associated with one or more memory banks of a memory device can be determined, and the method 1200 can continue to block 1204. For example, in some embodiments, for each memory bank of a memory device, it can be determined whether the memory bank received an active signal during a time interval. Further, in some embodiments, for each memory bank, it can be determined how many active signals the memory bank received during the time interval. For example, one or more counters within and / or external to the memory bank can count the number of active signals received at the memory bank during the time interval. Further, in this example, the one or more counters can be reset after the time interval ends.

[0084] At block 1204, a row hammer refresh rate of at least one of the one or more memory banks can be set and / or adjusted based on the determined amount of activity of the at least one memory bank. For example, based on the determined amount of activity of the at least one memory bank, the row hammer refresh rate of the at least one memory bank can be increased or decreased and / or the row hammer refresh operation of the at least one memory bank can be activated or deactivated. More specifically, for example, if the memory bank did not receive valid signals during the first time interval, the memory bank can not perform a row hammer refresh operation during a subsequent time interval (e.g., the row hammer refresh operation can be deactivated, assuming it was in an activated state). Also, for example, if the memory bank received valid signals during the first time interval, the memory bank can perform a row hammer refresh operation during a subsequent time interval (e.g., the row hammer refresh operation can be activated, assuming it was in a deactivated state). As another example, if the memory bank did not receive more than a first threshold number (e.g., 1, 5, 10, 20, 30, or more) of valid signals during the first time interval, the row hammer refresh rate of the memory bank can be decreased or not modified (e.g., for a subsequent time interval). Similarly, if the memory bank received more than a second threshold number (e.g., 10, 20, 50, 100, or more) of valid signals during the first time interval, the row hammer refresh rate of the memory bank can be increased or not modified (e.g., for a subsequent time interval).

[0085] Modifications, additions, or omissions can be made to the method 1200 without departing from the scope of the present disclosure. For example, the operations of the method 1200 can be implemented in differing order. Additionally, the outlined operations and actions are provided for exemplification and as an overview of some embodiments of the present disclosure, and some operations and actions can be optional, combined into fewer operations and actions, or expanded into additional operations and actions without detracting from the essence of the disclosed embodiments. For example, in various embodiments, the determined amount of activity of each memory bank can be compared to a threshold amount of activity. Also, in addition to adjusting the row hammer refresh rate of the at least one memory bank during the second time interval, the method can include determining an amount of activity of one or more memory banks of the memory device during the second time interval. Further, based on the amount of activity during the second time interval, the row hammer refresh rate of the at least one memory bank can or can not be adjusted for a third time interval.

[0086] Also disclosed are memory devices. According to various embodiments, a memory device can include one or more memory cell arrays, such as memory cell array 102 (see Figure 1 ), for example. The one or more memory cell arrays can include a number of memory banks.

[0087] Figure 13is a simplified block diagram of a memory device 1300 implemented in accordance with one or more embodiments described herein. The memory device 1300, which can include, for example, a semiconductor device, includes a memory array 1302 and a controller 1304. The memory array 1302, which can include a number of memory banks, can include a number of memory cells.

[0088] The controller 1304 can be operatively coupled with the memory array 1302 to read, write, or refresh any or all of the memory cells within the memory array 1302. The controller 1304 can be configured to implement one or more embodiments disclosed herein. For example, in some embodiments, the controller 1304, which can include, for example, Figure 10A the controller 1050 of Figure 11 the controller 1100, can be configured to determine an amount of activity associated with a memory bank and set and / or adjust a row hammer refresh rate for the memory bank.

[0089] Systems are also disclosed. According to various embodiments, a system can include a memory device including a number of memory banks, each memory bank having an array of memory cells. Each memory cell can include an access transistor and a storage element operatively coupled with the access transistor.

[0090] Figure 14 is a simplified block diagram of an electronic system 1400 implemented in accordance with one or more embodiments described herein. The electronic system 1400 includes at least one input device 1402, which can include, for example, a keyboard, a mouse, or a touchscreen. The electronic system 1400 further includes at least a first output device 1404, such as a monitor, a touchscreen, or a speaker. The input device 1402 and the output device 1404 are not necessarily separate from one another. The electronic system 1400 further includes a storage device 1406. The input device 1402, the output device 1404, and the storage device 1406 can be coupled to a processor 1408. The electronic system 1400 further includes a memory device 1410 coupled to the processor 1408. The memory device 1410, which can include, for example, Figure 13 the memory device 1300 of The electronic system 1400 can include, for example, a computing, processing, industrial, or consumer product. For example, but not limited to, the electronic system 1400 can include a personal computer or computer hardware component, a server or other networking hardware component, a database engine, an intrusion prevention system, a handheld device, a tablet computer, an electronic notebook, a camera, a telephone, a music player, a wireless device, a display, a chipset, a game, a vehicle, or other known system.

[0091] According to various embodiments disclosed herein and in contrast to some conventional devices, systems, and methods, the row hammer refresh rate of one or more banks of a memory device can be independently adjusted. More specifically, the row hammer refresh rate of a bank can be adjusted based on an amount of activity of the bank. Thus, in contrast to conventional devices, systems, and methods, various embodiments can provide for reduced power consumption and / or processing overhead of a memory device with little to no reduction in performance and / or reliability of the memory device.

[0092] One or more embodiments of the disclosure include a method of operating a memory device. The method can include determining a number of active commands associated with at least one bank of a memory device during a first time interval. The method can also include adjusting a row hammer refresh rate of the at least one bank for a second time interval based on the number of active commands associated with the at least one bank during the first time interval.

[0093] Some embodiments of the disclosure include a memory device. The memory device can include a memory array including a number of banks. The memory can also include at least one controller configured to adjust a row hammer refresh rate of at least one bank of the number of banks based on an amount of activity associated with the at least one bank.

[0094] Additional embodiments of the disclosure include an electronic system. The electronic system can include at least one input device, at least one output device, and at least one processor device operably coupled to the input device and the output device. The electronic system can also include at least one memory device operably coupled to the at least one processor device and including a memory cell array including a number of banks and at least one controller. The at least one controller can be configured to detect a row access associated with at least one bank of the number of banks. The at least one controller can also be configured to set a row hammer refresh rate of the at least one bank based on a number of detected row accesses associated with the at least one bank.

[0095] According to convention, individual features illustrated in the figures can not be drawn to scale. The illustrations presented in the present disclosure are meant to be idealized representations that do not necessarily portray actual views of any specific apparatus (e.g., device, system, etc.) or method. Thus, the dimensions of the various features can be arbitrarily expanded or reduced for the sake of clarity. In addition, some of the figures can be simplified for the sake of clarity. Thus, the figures can not depict all of the components of a given apparatus (e.g., device) or every operation of a particular method.

[0096] As used herein, the term "device" or "memory device" can include a device with memory, but is not limited to only devices with memory. For example, a device or memory device can include memory, a processor, and / or other components or functionality. For example, a device or memory device can include a system on a chip (SOC).

[0097] The terms used herein and especially in the appended claims (for example, the body of the appended claims) are generally intended as "open" terms (for example, the term "including" should be interpreted as "including, but not limited to," the term "having" should be interpreted as "having at least," the term "includes" should be interpreted as "includes, but is not limited to,").

[0098] Additionally, if a particular number of introduced claim recitations is intended, such intention should be clearly recited in the claims, and if not so explicitly recited, there is no intention to so limit the number of claim recitations. For example, to aid in the understanding of the claims, the appended claims can contain usage of introductory phrases such as "at least one of" and "one or more of," to introduce a claim recitation. However, such introductory phrases are not to be construed in either the alternative or the disjunctive sense, but rather should only be understood in the sense that such phrases serve to introduce the started term or terms list of alternatives that individually follow such phrase. For example, when used in a claim, the phrases "at least one of A and B" and "one or more of A and B" each should be construed to mean A alone, B alone, or A and B together. It will be understood by those within the art that whenever a word or phrase is denoted as asserting a preference or preference, such assertion also allows for an optional substitution of the mutually exclusive alternative or alternatives that have been characterized as preferred. Further, it is intended that the scope of the exclusion be interpreted as that stated, regardless of the inclusion of additional modification relationships in the claims. As used herein, "and / or" includes any and all combinations of one or more of the associated listed items.

[0099] Additionally, even if a specific number of introduced claim recitations is explicitly recited, it should be understood that such recitation should be interpreted to mean at least the recited number (for example, the naked recitation of "two recitations" means at least two recitations or two or more recitations). Moreover, when a claim recitation is presented in the form of a list, such as a list of items prefaced by the term "at least one of" or "one or more of," it should be interpreted to mean that the list is an "open-ended" list, which can be expanded to include additional recitations beyond those which appear in the list. For example, a recitation of "at least one of A, B, and C" should be interpreted to mean A alone; B alone; C alone; two of the items A, B, and C; three of the items A, B, and C; or all of the items A, B, and C. Such an open-ended list should be interpreted to include any and all combinations of the items so listed.

[0100] Furthermore, any disjunctive word or phrase presenting two or more alternative items, for example, the phrase "at least one of A, B, and C," or "one or more of A, B, and C" should be interpreted to mean that the items in the list are to be taken individually, that the items in the list are to be taken collectively, or that the items in the list are to be taken individually or collectively in any combination. For example, the phrase "at least one of A, B, and C" should be interpreted to mean A alone; B alone; C alone; A and B together; A and C together; B and C together; or A, B, and C together.

[0101] In addition, use of the terms“first,”“second,”“third,” etc. herein does not necessarily imply a specific order or number of elements. Generally, the terms“first,”“second,”“third,” etc. are used as generic identifiers to distinguish different elements. If the terms“first,”“second,”“third,” etc. are shown to imply a specific order, then the terms are not to be interpreted to imply a specific order. Furthermore, if the terms“first,”“second,”“third,” etc. are shown to imply a specific number of elements, then the terms are not to be interpreted to imply a specific number of elements.

[0102] The embodiments of the disclosure described above and illustrated in the drawings are not intended to limit the scope of the disclosure, which is encompassed by the claims below and their legal equivalents. Any equivalent embodiments are within the scope of the disclosure. Indeed, various modifications of the disclosure, in addition to those described herein, will become apparent to those skilled in the art from the description. Such modifications are also intended to fall within the scope of the appended claims and equivalents thereof.

Claims

1. A method of operating a memory device, comprising: Determine the amount of activity associated with at least one storage bank of the memory device; and The row hammer refresh rate of the at least one memory bank is adjusted based on the amount of activity associated with the at least one memory bank.

2. The method of claim 1, wherein determining the amount of activity associated with the at least one storage unit includes determining the number of valid commands received at the at least one storage unit.

3. The method of claim 1, wherein adjusting the row hammer refresh rate includes increasing the row hammer refresh rate in response to the activity amount being greater than a threshold activity amount.

4. The method of claim 1, wherein adjusting the row hammer refresh rate includes reducing the row hammer refresh rate in response to the activity amount being less than a threshold activity amount.

5. The method of claim 1, wherein adjusting the row hammer refresh rate comprises at least one of the following: In response to the activity associated with a first memory bank in the at least one memory bank being less than a threshold activity amount, the row hammer refresh rate of the first memory bank is reduced; and The row hammer refresh rate of the second different memory is increased in response to the activity associated with the second different memory in the at least one memory being greater than the threshold activity.

6. The method of claim 1, wherein determining the activity level includes determining that the number of valid commands associated with the at least one memory bank during the first time interval is equivalent to 0.

7. The method of claim 6, wherein adjusting the row hammer refresh rate includes deactivating the row hammer refresh operation of the at least one memory bank during a second subsequent time interval.

8. A memory device comprising: Several storage units; and At least one controller configured to: During the first time interval, determine the number of valid commands associated with at least one of the plurality of memory banks; and In response to the number of valid commands associated with the at least one memory bank being equal to 0, at least one row hammer refresh operation of the at least one memory bank is skipped during the second time interval.

9. The memory device of claim 8, wherein the at least one controller is coupled to each of the plurality of memory banks and configured to transmit a signal to each memory bank to independently control the row hammer refresh rate associated with each memory bank.

10. The memory device of claim 8, wherein the at least one controller comprises a plurality of controllers, wherein each of the plurality of memory banks is associated with a controller among the plurality of controllers, the controller being configured to adjust a row hammer refresh rate associated therewith.

11. The memory device of claim 8, wherein the at least one controller is configured to: Determine the number of valid commands associated with each of the plurality of memory banks; and The row hammer refresh rate of each of the plurality of memory banks is adjusted based on the number of valid commands associated with each memory bank.

12. The memory device of claim 8, wherein the at least one controller is configured to: During the first time interval, determine the number of valid commands associated with the second memory bank of the plurality of memory banks; and In response to the number of valid commands associated with the second memory bank exceeding a threshold number, the row hammer refresh rate of the second memory bank is increased during the second time interval.

13. The memory device of claim 12, wherein the at least one controller is configured to: During the first time interval, determine the number of valid commands associated with a third memory bank of the plurality of memory banks; and In response to the number of valid commands associated with the third memory being less than the threshold number, the row hammer refresh rate of the third memory is reduced during the second time interval.

14. A system comprising: At least one input device; At least one output device; At least one processor device operatively coupled to the input device and the output device; and At least one memory device operatively coupled to the at least one processor device and comprising: A memory cell array, which contains several memory banks; and At least one controller, configured to The row hammer refresh rate of the at least one memory bank is set based on the amount of activity associated with at least one memory bank among the plurality of memory banks.

15. The system of claim 14, wherein the at least one controller comprises a plurality of controllers, wherein each memory bank is associated with a controller among the plurality of controllers.

16. The system of claim 14, wherein the at least one controller is coupled to the at least one memory and configured to transmit one or more control signals to the at least one memory to set the row hammer refresh rate of the at least one memory.

17. The system of claim 14, wherein the at least one controller is configured to: Detecting the amount of activity associated with the at least one storage unit within one of several time intervals; and The row hammer refresh rate of the at least one memory bank is set in another subsequent time interval among the plurality of time intervals based on the detected amount of activity associated with the time interval.

18. The system of claim 14, wherein the at least one controller is configured to: Compare the activity level of the at least one storage cell with a threshold activity level; and The row hammer refresh rate of the at least one memory bank is set based on the comparison.

19. The system of claim 18, wherein the at least one controller is configured to: The row hammer refresh rate of the at least one memory bank is reduced in response to the activity level of the at least one memory bank being less than the threshold activity level; and The row hammer refresh rate of the at least one memory cell is increased in response to the activity level of the at least one memory cell being greater than or equal to the threshold activity level.

20. The system of claim 14, wherein the at least one controller includes at least one counter for counting detected row accesses associated with the at least one memory bank to detect the amount of activity associated with the at least one memory bank.

21. A method comprising: Within a time interval, the first memory bank of a plurality of memory banks of the memory device is set to a first row hammer refresh rate; and During the time interval, the second different memory banks of the plurality of memory banks of the memory device are set with a second different row refresh rate.

22. The method of claim 21, further comprising determining an activity level associated with the first memory bank, wherein setting the first row hammer refresh rate includes setting the first row hammer refresh rate based on the activity level associated with the first memory bank.

23. The method of claim 22, wherein determining the amount of activity associated with the first storage bank includes determining the number of valid commands received at the first storage bank.

24. The method of claim 22, further comprising determining an activity level associated with the second different memory bank, wherein setting the second different row hammer refresh rate includes setting the second different row hammer refresh rate based on the activity level associated with the second different memory bank.

25. The method of claim 21, wherein setting the first row hammer refresh rate includes increasing the first row hammer refresh rate in response to an activity level associated with the first memory bank being greater than a threshold activity level.

26. The method of claim 25, wherein setting the second different row hammer refresh rate of the second different memory bank includes reducing the second different row hammer refresh rate in response to an activity level associated with the second different memory bank being less than the threshold activity level.

27. The method of claim 21, wherein setting the first row refresh rate includes one of the following: The first row hammer refresh rate is reduced in response to the activity associated with the first memory bank being less than a threshold activity level; and The first row hammer refresh rate is increased in response to the activity associated with the first memory bank being greater than the threshold activity.

28. A memory device comprising: First storage and second storage; and A circuit coupled to each of the first memory bank and the second memory bank and configured to independently control the row hammer refresh rate of each of the first memory bank and the second memory bank.

29. The memory device of claim 28, wherein the circuitry includes at least one controller coupled to each of the first memory bank and the second memory bank and configured to transmit a signal to each of the first memory bank and the second memory bank to independently control the row hammer refresh rate associated with the first memory bank and the second memory bank.

30. The memory device of claim 29, wherein the at least one controller comprises a plurality of controllers, wherein each of the first memory bank and the second memory bank comprises a dedicated controller among the plurality of controllers, the dedicated controller being configured to adjust the row hammer refresh rate associated therewith.

31. The memory device of claim 28, wherein the circuitry is further configured to: Determine the number of valid commands associated with at least one of the first memory bank or the second memory bank; and The row hammer refresh rate of at least one of the first or second memory banks is adjusted based on the number of valid commands associated with at least one of the first or second memory banks.

32. The memory device of claim 28, wherein the circuitry is further configured to: During the first time interval, the amount of activity associated with the first storage cell is determined; and The row hammer refresh rate of the first memory is increased or decreased in a second time interval based on the amount of activity associated with the first memory during the first time interval.

33. The memory device of claim 32, wherein the circuitry is further configured to: During the first time interval, determine the amount of activity associated with the second storage unit; and The row hammer refresh rate of the second memory is increased or decreased during the second time interval based on the amount of activity associated with the second memory during the first time interval.

34. A system comprising: At least one input device; At least one output device; At least one processor device operatively coupled to the input device and the output device; and At least one memory device operatively coupled to the at least one processor device and comprising: A memory cell array, which contains several memory banks; and At least one controller configured to independently control the row hammer refresh rate of each of the first and second memory banks of the plurality of memory banks.

35. The system of claim 34, wherein the at least one controller comprises a plurality of controllers, and each of the plurality of storage units contains a controller among the plurality of controllers.

36. The system of claim 34, wherein the at least one controller is coupled to each of the first memory and the second memory and configured to transmit one or more control signals to each of the first memory and the second memory to set the row hammer refresh rate of the first memory and the second memory.

37. The system of claim 34, wherein the at least one controller is configured to: Detecting an activity level associated with at least one of the first memory or the second memory within one of a plurality of time intervals; and Based on the activity level, the row hammer refresh rate of at least one of the first or second memory is set in another subsequent time interval among the plurality of time intervals.

38. The system of claim 34, wherein the at least one controller is further configured to: Compare the activity level of at least one of the first or second memory with a threshold activity level; and The row hammer refresh rate of at least one of the first memory bank or the second memory bank is set based on the comparison.

39. The system of claim 38, wherein the at least one controller is further configured to: In response to the activity level of at least one of the first memory bank or the second memory bank being less than the threshold activity level, the row hammer refresh rate of at least one of the first memory bank or the second memory bank is reduced; and The row hammer refresh rate of at least one of the first or second memory is increased in response to the activity level of at least one of the first or second memory being greater than or equal to the threshold activity level.

40. The system of claim 34, wherein the at least one controller includes at least one counter for counting detected row accesses associated with each of the first and second storage units to detect the amount of activity associated with each of the first and second storage units.

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