Measurement Method and Measurement System for Semiconductor Structure

Abstract

The present application provides a method and a measurement system for measuring a semiconductor structure, relating to the field of semiconductor technology. The method for measuring the semiconductor structure includes the following steps: providing a first semiconductor structure and a second semiconductor structure. By separately obtaining the capacitance values of the first semiconductor structure and the second semiconductor structure, and at the same time, on the premise that the second semiconductor structure and the first semiconductor structure are fabricated on the same wafer, the ratio of the capacitance value of the first central region to the capacitance value of the second central region, and the ratio of the capacitance value of the first edge region to the capacitance value of the second edge region are obtained. Based on the above values, the ratio of the capacitance value of the first central region to the capacitance value of the first edge region is obtained, and the thickness uniformity of the active layer is judged by the magnitude of this ratio, so as to provide a theoretical support for the fabrication of the semiconductor structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and particularly to a method and a system for measuring a semiconductor structure. Background Art

[0002] A dynamic random access memory (DRAM) is a semiconductor memory that writes and reads data at high speed and randomly, and is widely used in data storage modules or devices.

[0003] A dynamic random access memory generally includes an array region and a peripheral circuit region disposed around the array region. Among them, a transistor is disposed in the peripheral circuit region, and the transistor generally includes an active layer, a gate oxide layer, and a gate disposed on the active layer. In related technologies, a capacitance-voltage measurement method is usually used to measure the capacitance value between the active layer and the gate, and the capacitance value is used to ensure the performance of the dynamic random access memory.

[0004] However, the above measurement method can only obtain the capacitance value between the active layer and the gate, and cannot characterize the uniformity of the active layer. Summary of the Invention

[0005] In view of the above problems, embodiments of the present application provide a method and a system for measuring a semiconductor structure, which are used to characterize the uniformity of an active layer.

[0006] To achieve the above object, embodiments of the present application provide the following technical solutions:

[0007] A first aspect of embodiments of the present application provides a method for measuring a semiconductor structure, which includes the following steps:

[0008] Provide a first semiconductor structure, where the first semiconductor structure includes a first active layer, a first gate oxide layer, and a first gate stacked on the first active layer, and a projection of the first gate on the first active layer includes a first central region and a first edge region surrounding the first central region;

[0009] Provide a second semiconductor structure, where the second semiconductor structure is fabricated on the same wafer as the first semiconductor structure, and the second semiconductor structure includes a second active layer, a second gate oxide layer, and a second gate stacked on the second active layer, and a projection of the second gate on the second active layer includes a second central region and a second edge region surrounding the second central region; the lengths of the first central region and the second central region are different, and the lengths of the first edge region and the second edge region are the same;

[0010] Obtain the capacitance value C of the first semiconductor structure 总1and the capacitance value C of the second semiconductor structure 总2 ;

[0011] Obtain the ratio of the capacitance value of the first central region to the capacitance value of the second central region, and obtain the ratio of the capacitance value of the first edge region to the capacitance value of the second edge region;

[0012] According to the C 总1 、the C 总2 、the ratio of the capacitance value of the first central region to the capacitance value of the second central region, and the ratio of the capacitance value of the first edge region to the capacitance value of the second edge region, obtain the ratio of the capacitance value of the first central region to the capacitance value of the first edge region.

[0013] The measurement method of the semiconductor structure as described above, wherein, in the step of obtaining the capacitance value C 总1 of the first semiconductor structure and the capacitance value C 总2 of the second semiconductor structure, it includes:

[0014] Obtain the capacitance value between the first gate and the first active layer in the first semiconductor structure, and this capacitance value is denoted as C 总1 ;

[0015] Obtain the capacitance value between the second gate and the second active layer in the second semiconductor structure, and this capacitance value is denoted as C 总2 .

[0016] The measurement method of the semiconductor structure as described above, wherein, in the step of obtaining the capacitance value C 总1 between the first gate and the first active layer in the first semiconductor structure, it includes:

[0017] Provide a first power module, which is connected to the first gate and used to provide voltage to the first gate;

[0018] Provide a first detection module, which is connected to the first active layer and used to measure the amplitude and phase shift of the current flowing through the first gate and the first gate oxide layer;

[0019] According to the voltage value, the amplitude of the current, and the phase shift, obtain C 总1 .

[0020] The measurement method of the semiconductor structure as described above, wherein the first power module is connected to the first gate through a first connecting wire;

[0021] The first detection module is connected to the first active layer through a second connecting wire.

[0022] A method for measuring a semiconductor structure as described above, wherein there is a first pad between the first connection wire and the first gate, and a second pad between the second connection wire and the first active layer.

[0023] A method for measuring a semiconductor structure as described above, wherein there are multiple first semiconductor structures, and the multiple first semiconductor structures are arranged in an array;

[0024] The number of the first connection wires is multiple, and each first connection wire connects the first pads of each of the first semiconductor structures located in the same row;

[0025] The number of the second connection wires is multiple, and each second connection wire connects the second pads of each of the first semiconductor structures located in the same row.

[0026] A method for measuring a semiconductor structure as described above, wherein when the number of the first semiconductor structures is multiple and the multiple first semiconductor structures are arranged in an array, the step of obtaining the capacitance value C of the first semiconductor structure 总1 includes:

[0027] Obtaining the total capacitance value between the first active layer and the first gate of the multiple first semiconductor structures;

[0028] According to the total capacitance value between the first active layer and the first gate of the multiple first semiconductor structures, obtaining the average value of the capacitance values between the first active layer and the first gate of the first semiconductor structure, and using this average value as C 总1 .

[0029] A method for measuring a semiconductor structure as described above, wherein the step of obtaining the capacitance value between the second gate and the second active layer in the second semiconductor structure includes:

[0030] Providing a second power supply module, which is connected to the second gate and is used to supply voltage to the second gate;

[0031] Providing a second detection module, which is connected to the second active layer and is used to measure the amplitude and phase shift of the current flowing through the second gate and the second gate oxide layer;

[0032] Obtaining C according to the voltage value, the amplitude of the current, and the phase shift 总2 .

[0033] A method for measuring a semiconductor structure as described above, wherein the second power supply module is connected to the second gate through a third connection wire;

[0034] The second detection module is connected to the second active layer through a fourth connecting wire.

[0035] The measuring method of the semiconductor structure as described above, wherein there is a third pad between the third connecting wire and the second gate, and there is a fourth pad between the fourth connecting wire and the second active layer.

[0036] The measuring method of the semiconductor structure as described above, wherein there are multiple second semiconductor structures, and the multiple second semiconductor structures are arranged in an array;

[0037] The number of the third connecting wires is multiple, and each third connecting wire connects the third pads of each second semiconductor structure located in the same row;

[0038] The number of the fourth connecting wires is multiple, and each fourth connecting wire connects the fourth pads of each second semiconductor structure located in the same row.

[0039] The measuring method of the semiconductor structure as described above, wherein when the number of the second semiconductor structures is multiple and the multiple second semiconductor structures are arranged in an array, the steps of obtaining the capacitance value between the second gate and the second active layer in the second semiconductor structure include:

[0040] Obtaining the total capacitance value between the second active layer and the second gate of multiple second semiconductor structures;

[0041] According to the total capacitance value between the second active layer and the second gate of multiple second semiconductor structures, obtaining the average value of the capacitance value between the second active layer and the second gate of the second semiconductor structure, and this average value is used as C 总2 .

[0042] The measuring method of the semiconductor structure as described above, wherein in the steps of obtaining the ratio of the capacitance value of the first central region to the capacitance value of the second central region, and obtaining the ratio of the capacitance value of the second edge region to the capacitance value of the second edge region, it includes:

[0043] Along the first direction, the widths of the first central region and the first edge region are both A;

[0044] Along the second direction, the length of the first central region is a, the length of the first edge region is A - a, the area of the first central region is A×a, and the area of the first edge region is A×(A - a);

[0045] Along the first direction, the widths of the second central region and the second edge region are both nA;

[0046] Along the second direction, the length of the second central region is (n - 1)A + a, the length of the second edge region is A - a, the area of the second central region is [(n - 1)A + a] × nA, and the area of the second edge region is nA(A - a);

[0047] The ratio of the capacitance value of the first central region to the capacitance value of the second central region is

[0048] The ratio of the capacitance value of the first edge region to the capacitance value of the second edge region is

[0049] A measurement method for the semiconductor structure as described above, wherein the ratio of the capacitance value of the first central region to the capacitance value of the first edge region is obtained by the following formula:

[0050]

[0051] where C c1 represents the capacitance value of the first central region, C2 represents the capacitance value of the first edge region, and m represents the ratio of C 总1 to C 总2 .

[0052] A measurement method for the semiconductor structure as described above, wherein the first central region includes a first edge and a second edge arranged oppositely;

[0053] The first edge region includes a first region and a second region. The first region is attached to the first edge, and the second region is attached to the second edge;

[0054] The capacitance value of the first edge region is equal to the sum of the capacitance values of the first region and the second region.

[0055] The second aspect of the embodiments of the present application provides a measurement system for a semiconductor structure, including:

[0056] A first semiconductor structure, which includes a first active layer, a first gate oxide layer and a first gate stacked on the first active layer. The projection of the first gate on the first active layer includes a first central region and a first edge region surrounding the first central region;

[0057] A second semiconductor structure, and the second semiconductor structure includes a second active layer, a second gate oxide layer and a second gate stacked on the second active layer. The projection of the second gate on the second active layer includes a second central region and a second edge region surrounding the second central region;

[0058] The widths of the first central region and the second central region are different, and the widths of the first edge region and the second edge region are the same;

[0059] A processor for obtaining the capacitance value C of the first semiconductor structure 总1 and the capacitance value C of the second semiconductor structure 总2 ; obtaining the ratio of the capacitance value of the first central region to the capacitance value of the second central region, and obtaining the ratio of the capacitance value of the first edge region to the capacitance value of the second edge region; and based on the C 总1 the C 总2 , the ratio of the capacitance value of the first central region to the capacitance value of the second central region, and the ratio of the capacitance value of the first edge region to the capacitance value of the second edge region, obtain the ratio of the capacitance value of the first central region to the capacitance value of the first edge region.

[0060] A measurement system for a semiconductor structure as described above, wherein the processor includes a first power module, a first detection module, a second power module, and a second detection module;

[0061] The first power module is connected to the first gate for providing a voltage to the first gate;

[0062] The first detection module is connected to the first active layer for measuring the amplitude and phase shift of the current after flowing through the first gate and the first gate oxide layer;

[0063] The second power module is connected to the second gate for providing a voltage to the second gate;

[0064] The second detection module is connected to the second active layer for measuring the amplitude and phase shift of the current after flowing through the second gate and the second gate oxide layer.

[0065] A measurement system for a semiconductor structure as described above, wherein the first power module is connected to the first gate through a first connecting wire; the first detection module is connected to the first active layer through a second connecting wire;

[0066] The second power module is connected to the second gate through a third connecting wire; the second detection module is connected to the second active layer through a fourth connecting wire.

[0067] A measurement system for a semiconductor structure as described above, wherein the number of the first semiconductor structures is multiple, and the multiple first semiconductor structures are arranged in a rectangular array;

[0068] The number of the first connection wires is multiple, and each of the first connection wires is connected to the first gates of the first semiconductor structures located in the same row;

[0069] The number of the second connection wires is multiple, and each of the second connection wires is connected to the first active layers of the first semiconductor structures located in the same row.

[0070] A measurement system of the semiconductor structure as described above, wherein the number of the second semiconductor structures is multiple, and the multiple second semiconductor structures are arranged in a rectangular array;

[0071] The number of the third connection wires is multiple, and each of the third connection wires is connected to the second gates of the second semiconductor structures located in the same row;

[0072] The number of the fourth connection wires is multiple, and each of the fourth connection wires is connected to the second active layers of the first semiconductor structures located in the same row.

[0073] In the measurement method and measurement system of the semiconductor structure provided by the embodiments of the present application, by respectively obtaining the capacitance values of the first semiconductor structure and the second semiconductor structure, and at the same time, on the premise that the second semiconductor structure and the first semiconductor structure are fabricated on the same wafer, the ratio of the capacitance value of the first central region to the capacitance value of the second central region, and the ratio of the capacitance value of the first edge region to the capacitance value of the second edge region are obtained, and based on the above values, the ratio of the capacitance value of the first central region to the capacitance value of the first edge region is obtained, and the thickness uniformity of the active layer is judged by the magnitude of this ratio.

[0074] In addition to the technical problems solved by the embodiments of the present application described above, the technical features constituting the technical solutions, and the beneficial effects brought by the technical features of these technical solutions, other technical problems that can be solved by the measurement method and measurement system of the semiconductor structure provided by the embodiments of the present application, other technical features included in the technical solutions, and the beneficial effects brought by these technical features will be further described in detail in the specific implementation manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0076] Figure 1 It is a process flow diagram of the measurement method of the semiconductor structure provided by the embodiments of the present application;

[0077] Figure 2 Schematic diagram of the first semiconductor structure provided by the embodiment of the present application;

[0078] Figure 3 Top view of the first semiconductor structure provided by the embodiment of the present application;

[0079] Figure 4 Top view of the second semiconductor structure provided by the embodiment of the present application;

[0080] Figure 5 Arrangement diagram of the first semiconductor structure provided by the embodiment of the present application;

[0081] Figure 6 Arrangement diagram of the second semiconductor structure provided by the embodiment of the present application.

[0082] Reference numerals:

[0083] 100: First semiconductor structure; 110: Substrate;

[0084] 120: First active layer; 121: Second pad;

[0085] 130: First gate oxide layer; 131: Oxide layer;

[0086] 132: Dielectric layer; 140: First gate;

[0087] 141: First pad; 150: First central region;

[0088] 151: First edge; 152: Second edge;

[0089] 160: First edge region; 161: First region;

[0090] 162: Second region; 200: Second semiconductor structure;

[0091] 220: Second active layer; 221: Fourth pad;

[0092] 240: Second gate; 241: Third pad;

[0093] 300: First power module; 310: First connecting wire;

[0094] 400: First detection module; 410: Second connecting wire;

[0095] 500: Second power module; 510: Third connecting wire;

[0096] 600: Second detection module; 610: Fourth connecting wire. Detailed implementation manners

[0097] When preparing a transistor, an active layer, a gate oxide layer, and a gate are usually formed on a substrate in a stacked manner by an epitaxial growth process. Limited by the epitaxial growth process, it is difficult to ensure the thickness uniformity of the active layer, resulting in the thickness of the central region of the active layer being greater than that of the edge region of the active layer, thereby affecting the performance of the transistor. In the related art, the capacitance value between the active layer and the gate is usually measured, and this capacitance value is used to characterize the performance of the transistor. However, in the above method, the capacitance value between the central region of the active layer and the gate, and the capacitance value between the edge region of the active layer and the gate cannot be measured, and the thickness uniformity of the active layer cannot be characterized.

[0098] To solve the above technical problems, in this embodiment, by respectively obtaining the capacitance values of the first semiconductor structure and the second semiconductor structure, and at the same time, on the premise that the second semiconductor structure and the first semiconductor structure are fabricated on the same wafer, the ratio of the capacitance value of the first central region to the capacitance value of the second central region, and the ratio of the capacitance value of the first edge region to the capacitance value of the second edge region are obtained. And based on the above values, the ratio of the capacitance value of the first central region to the capacitance value of the first edge region is obtained, and the thickness uniformity of the active layer is judged by the magnitude of this ratio.

[0099] In order to make the above objects, features, and advantages of the embodiments of the present application more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0100] This embodiment does not limit the semiconductor structure. Hereinafter, a dynamic random access memory (DRAM) will be taken as an example for introduction, but this embodiment is not limited thereto. The semiconductor structure in this embodiment can also be other structures.

[0101] As Figure 1 shown, the method for preparing a semiconductor structure provided by the embodiment of the present application includes the following steps:

[0102] Step S100: Provide a first semiconductor structure, the first semiconductor structure includes a first active layer, and a first gate oxide layer and a first gate stacked on the first active layer, and the projection of the first gate on the first active layer includes a first central region and a first edge region surrounding the first central region.

[0103] As Figure 2As shown, the first semiconductor structure 100 may further include a substrate 110. The substrate 110 serves as a support component for the dynamic random access memory and is used to support other components disposed thereon. Among them, the substrate 110 may be made of a semiconductor material, and the semiconductor material may be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbon compounds.

[0104] As Figure 2 shown, the first active layer 120 is disposed on the substrate 110. The first active layer 120 is usually formed by an epitaxial growth process. Affected by the epitaxial growth process, the first active layer 120 usually has a structure that is thick in the middle and thin on both sides, so that the longitudinal cross-sectional shape of the first active layer 120 is a trapezoidal structure with a smaller upper part and a larger lower part. Among them, the material of the first active layer 120 may include silicon germanide.

[0105] The first gate oxide layer 130 is disposed on the first active layer 120. Among them, the first gate oxide layer 130 may be a single film layer or a stacked structure. When the first gate oxide layer 130 may include an oxide layer 131 and a dielectric layer 132, the oxide layer 131 is disposed on the surface of the first active layer 120 facing away from the substrate 110, and the dielectric layer 132 is disposed on the surface of the oxide layer 131 facing away from the first active layer 120. Moreover, the material of the oxide layer 131 may include insulating materials such as silicon oxide, and the dielectric layer 132 may include HfO2, HfSiO, HfSiON, HfAlO, HfZrO, Al2O3, TaO2, etc., and this material has a high dielectric constant.

[0106] The first gate 140 is disposed on the first gate oxide layer 130, and the first gate 140 and the first active layer 120 have an overlapping area. When there is a voltage difference between the first gate 140 and the first active layer 120, an electrostatic field distribution will exist between the first gate 140 and the first active layer 120. Thus, under the action of the electrostatic field, charges are stored, and the total stored charge Q is proportional to its voltage U, and the ratio is called capacitance, denoted by C.

[0107] The projection of the first gate 140 on the first active layer 120 includes a first central region 150 and a first edge region 160, where the first edge region 160 is disposed around the first central region 150.

[0108] At this time, the capacitance value C between the first gate 140 and the first active layer 120 总1 is equal to the sum of the capacitance value of the first central region and the capacitance value of the first edge region, and its formula is as follows:

[0109] C 总1 = C c1 + C e1 (Formula 1.1)

[0110] C c1represents the capacitance value of the first central region, C e1 represents the capacitance value of the first edge region.

[0111] It should be noted that, as Figure 2 shown, the capacitance value of the first central region refers to the capacitance value of the capacitor formed between the first gate and the first active layer located in the middle square, and the capacitance value of the first edge region refers to the capacitance value of the capacitor formed between the first gate and the first active layer located in the left and right squares.

[0112] In this embodiment, the first edge region 160 is disposed around the first central region 150, which can be understood as the first edge region 160 semi - enclosing the first central region 150. For example, as Figure 3 shown, along the second direction, that is, Figure 3 the X - direction in

[0113] shown, the first central region 150 has a first edge 151 and a second edge 152 which are oppositely arranged. The first edge region 160 includes a first region 161 and a second region 162. The first region 161 is attached to the first edge 151, and the second region 162 is attached to the second edge 152.

[0114] Step S200: Provide a second semiconductor structure. The second semiconductor structure is fabricated on the same wafer as the first semiconductor structure, and the second semiconductor structure includes a second active layer, and a second gate oxide layer and a second gate stacked on the second active layer. The projection of the second gate on the second active layer includes a second central region and a second edge region surrounding the second central region. The widths of the first central region and the second central region are different, and the lengths of the first edge region and the second edge region are the same.

[0115] It should be noted that, since the second semiconductor structure and the first semiconductor structure are fabricated on the same wafer, under the same fabrication conditions, it can be considered that the structure of the second semiconductor structure is similar to the structure of the first semiconductor structure in the embodiment, that is, the morphologies of the first edge region and the second edge region are the same, only the lengths of the first central region and the second central region are different.

[0116] As Figure 4 shown, the projection of the second gate 240 on the second active layer 220 includes a second central region 250 and a second edge region 260. The second edge region 260 is disposed around the second central region 250.

[0117] The capacitance value C of the second semiconductor structure 总2is equal to the sum of the capacitance value of the second central region and the capacitance value of the second edge region, and the formula is as follows:

[0118] C 总2 =C c2 +C e2 (Formula 1.2)

[0119] C c2 represents the capacitance value of the second central region, and C e2 represents the capacitance value of the second edge region.

[0120] Step S300: Obtain the capacitance value C 总1 of the first semiconductor structure and the capacitance value C 总2 of the second semiconductor structure.

[0121] Exemplarily, as Figure 5 shown, a first power supply module 300 is provided. The first power supply module 300 is connected to the first gate 140 and is used to supply a voltage to the first gate 140. For example, the first power supply module 300 can apply a voltage with a known amplitude and frequency to the first gate 140.

[0122] A first detection module 400 is provided. The first detection module 400 is connected to the first active layer 120 and is used to measure the amplitude and phase shift of the current after flowing through the first gate 140 and the first gate oxide layer 130;

[0123] According to the voltage value, the amplitude of the current, and the phase shift, C 总1 is obtained. That is to say, C 总1 is calculated based on the voltage, the amplitude of the current, and the phase shift, and its calculation formula is as follows:

[0124]

[0125] where V represents the voltage value of the first power supply module, I represents the amplitude of the current, represents the phase shift.

[0126] The first gate 140 and the first power supply module 300 can be directly connected or indirectly connected. For example: as Figure 5 shown, a first connection wire 310 is provided between the first gate 140 and the first power supply module 300.

[0127] To facilitate the connection between the first connection wire 310 and the first gate 140, a first pad 141 can be provided on the first gate 140. The first connection wire 310 is connected to the first pad 141, and the first pad 141 transmits the electrical signal on the first gate 140, which can improve the accuracy of detecting the voltage of the first gate 140.

[0128] A second connecting wire 410 is provided between the first active layer 120 and the first detection module 400. To facilitate the connection between the second connecting wire 410 and the first active layer 120, a second pad 121 can be provided on the first active layer 120, and the second connecting wire 410 is connected to the second pad 121.

[0129] In some embodiments, the number of the first semiconductor structures 100 can be multiple, and the multiple first semiconductor structures 100 are arranged in an array. For example, as Figure 5 shown, the number of the first semiconductor structures 100 is nine, and the nine first semiconductor structures 100 are arranged in three rows and three columns.

[0130] The number of the first connecting wires 310 is multiple, and each first connecting wire is connected to the first pads 141 of the respective first semiconductor structures 100 located in the same row.

[0131] The number of the second connecting wires 410 is multiple, and each second connecting wire 410 is connected to the second pads 121 of the respective first semiconductor structures 100 located in the same row.

[0132] At this time, the above measurement method needs to be adopted to measure the capacitance value of each first semiconductor structure 100, so as to obtain the total capacitance value between the first active layer 120 and the first gate 140 of the multiple first semiconductor structures 100.

[0133] According to the total capacitance value between the first active layer 120 and the first gate 140 of the multiple first semiconductor structures 100, the average value of the capacitance values between the first active layer 120 and the first gate 140 of the first semiconductor structure 100 is obtained, and this average value is used as C 总1 .

[0134] This embodiment provides multiple first semiconductor structures. By obtaining the average value of the capacitance values of the first semiconductor structure as C 总1 , the accuracy of the capacitance value C 总1 of the first semiconductor structure can be ensured, thereby providing a guarantee for obtaining the accurate ratio of the capacitance values of the first central region and the first edge region subsequently.

[0135] In this embodiment, the method for obtaining the capacitance value C 总2 of the second semiconductor structure can be carried out according to the following steps:

[0136] Exemplarily, as Figure 6 shown, a second power supply module 500 is provided. The second power supply module 500 is connected to the second gate 240 and is used to supply voltage to the second gate 240, and a voltage with a known amplitude and frequency is applied to the second gate 240 through the second voltage module.

[0137] A second detection module 600 is provided. The second detection module 600 is connected to the second active layer 220 and is used to measure the amplitude and phase shift of the current after flowing through the second gate 240 and the second gate oxide layer;

[0138] Based on the voltage value, the amplitude of the current, and the phase shift, C is obtained 总2 , that is, C is calculated based on the voltage, current, and phase shift 总2 .

[0139] It should be noted that the calculation formula for the capacitance value C of the second semiconductor structure 总2 is the same as the calculation formula for the above-mentioned C 总1 , and this embodiment will not be elaborated here.

[0140] The second gate 240 and the second power supply module 500 can be directly connected or indirectly connected. For example: as Figure 4 shown, a third connection wire 510 is provided between the second gate 240 and the second power supply module 500.

[0141] To facilitate the connection between the third connection wire 510 and the second gate 240, a third pad 241 can be provided on the second gate 240, and the third connection wire 510 is connected to the third pad 241.

[0142] A fourth connection wire 610 is provided between the second active layer 220 and the second detection module 600. To facilitate the connection between the fourth connection wire 610 and the second active layer 220, a fourth pad 221 can be provided on the second active layer 220, and the fourth connection wire 610 is connected to the fourth pad 221.

[0143] In some embodiments, the number of the second semiconductor structures 200 can be multiple, and the multiple second semiconductor structures 200 are arranged in an array. For example, as Figure 4 shown, the number of the second semiconductor structures 200 is nine, and the nine second semiconductor structures 200 are arranged in three rows and three columns.

[0144] The number of the third connection wires 510 is multiple, and each third connection wire 510 is connected to the first pads 141 of the second semiconductor structures 200 located in the same row.

[0145] The number of the fourth connection wires 610 is multiple, and each fourth connection wire 610 is connected to the second pads 121 of the second semiconductor structures 200 located in the same row.

[0146] At this time, the above measurement method needs to be used to measure the capacitance value of each second semiconductor structure 200 to obtain the total capacitance value between the second active layer 220 and the second gate 240 of the multiple second semiconductor structures 200.

[0147] Based on the total capacitance value between the second active layer 220 and the second gate 240 of multiple second semiconductor structures 200, an average value of the capacitance value between the second active layer 220 and the second gate 240 of the second semiconductor structure 200 is obtained, and this average value is used as C 总2 。

[0148] This embodiment provides multiple second semiconductor structures. By obtaining the average value of the capacitance values of the second semiconductor structures as C 总2 , the accuracy of the capacitance value C 总2 of the second semiconductor structure can be ensured, thereby providing a guarantee for subsequently obtaining an accurate ratio of the capacitance values of the first central region and the first edge region.

[0149] Step S400: Obtain the ratio of the capacitance value of the first central region to the capacitance value of the second central region, and obtain the ratio of the capacitance value of the second edge region to the capacitance value of the second edge region.

[0150] In this embodiment, it is assumed that the shape of the projection of the first gate 140 on the first active layer 120 is a square, and it is also assumed that the shape of the projection of the second gate 240 on the second active layer 220 is also a square.

[0151] As Figure 3 shown, along the first direction, that is Figure 3 the Y direction in , the widths of both the first central region 150 and the first edge region 160 are A.

[0152] Along the second direction, that is Figure 3 the X direction in , the length of the first central region 150 is a, and the length of the first edge region is A - a. Correspondingly, the area of the first central region 150 is A×a, and the area of the first edge region 160 is A×(A - a).

[0153] As Figure 4 shown, along the first direction, that is Figure 4 the Y direction in , the widths of both the second central region 250 and the second edge region 260 are nA.

[0154] Since the first semiconductor structure 100 and the second semiconductor structure 200 are fabricated on the same wafer, on the premise of the same epitaxial growth process, the lengths of the first edge region 160 and the second edge region 260 are the same. Therefore, the length of the second edge region 260 is A - a. Correspondingly, the length of the second central region 250 is equal to nA - (A - a), that is, the length of the second central region 250 is equal to (n - 1)A + a.

[0155] The area of the second central region 250 is the length of the second central region 250 multiplied by the width of the second central region 250, and its formula is [(n - 1)A + a] × nA. The area of the second edge region 260 is equal to the length of the second edge region 260 multiplied by the width of the second edge region 260, and its formula is nA(A - a).

[0156] Based on the formula of capacitance Among them, ε is a dielectric constant, S is the facing area of the capacitor plates, d is the distance between the capacitor plates, and k is also the dielectric constant. When the dielectric constants are the same, the capacitance is proportional to the area.

[0157] Therefore, the ratio of the capacitance value of the first central region 150 to the capacitance value of the second central region 250 is The formula is as follows:

[0158]

[0159] Among them, C c1 represents the capacitance value of the first central region, and C c2 represents the capacitance value of the second central region.

[0160] The ratio of the capacitance value of the first edge region 160 to the capacitance value of the second edge region 260 is The formula is as follows:

[0161]

[0162] Among them, C e1 represents the capacitance value of the first edge region, and C e2 represents the capacitance value of the second edge region.

[0163] Dividing formula 1.1 by formula 1.2, the following formula can be obtained:

[0164]

[0165] Substituting the above formula 1.3 and formula 1.4 into formula 1.5 to obtain the ratio of the capacitance values of the first central region to the first edge region, specifically as follows:

[0166]

[0167] Among them, C c1 represents the capacitance value of the first central region, C c2 represents the capacitance value of the first edge region, and m represents the ratio of C 总1 to C 总2 .

[0168] In this embodiment, the capacitance values of the first semiconductor structure and the second semiconductor structure are obtained respectively in the above manner. Meanwhile, on the premise that the second semiconductor structure and the first semiconductor structure are fabricated on the same wafer, the ratio of the capacitance value of the first central region to the capacitance value of the second central region, and the ratio of the capacitance value of the first edge region to the capacitance value of the second edge region are obtained. And based on the above values, the ratio of the capacitance value of the first central region to the capacitance value of the first edge region is obtained, and the thickness uniformity of the active layer is judged by the magnitude of this ratio.

[0169] Embodiment 2

[0170] This embodiment of the present application also provides a measurement system for a semiconductor structure, as Figures 2 to 6 shown. The measurement system includes a first semiconductor structure 100. The first semiconductor structure 100 includes a first active layer 120, and a first gate oxide layer 130 and a first gate 140 stacked on the first active layer 120. The projection of the first gate 140 on the first active layer 120 includes a first central region 150 and a first edge region 160 surrounding the first central region 150;

[0171] a second semiconductor structure 200, and the second semiconductor structure 200 includes a second active layer 220, and a second gate oxide layer and a second gate 240 stacked on the second active layer 220. The projection of the second gate 240 on the second active layer 220 includes a second central region 250 and a second edge region 260 surrounding the second central region 250.

[0172] The widths of the first central region 150 and the second central region 250 are different, and the widths of the first edge region 160 and the second edge region 260 are the same.

[0173] a processor, which is used to obtain the capacitance value C of the first semiconductor structure 总1 and the capacitance value C of the second semiconductor structure 总2 ; obtain the ratio of the capacitance value of the first central region to the capacitance value of the second central region, and obtain the ratio of the capacitance value of the first edge region to the capacitance value of the second edge region; and based on C 总1 、C 总2 、the ratio of the capacitance value of the first central region to the capacitance value of the second central region, and the ratio of the capacitance value of the first edge region to the capacitance value of the second edge region, obtain the ratio of the capacitance value of the first central region to the capacitance value of the first edge region.

[0174] In this embodiment, through the setting of the processor, the ratio of the capacitance value of the first central region to the capacitance value of the first edge region of the first semiconductor structure is obtained, and the thickness uniformity of the active layer is judged by the magnitude of this ratio, so as to provide a theoretical basis for the fabrication of the first semiconductor structure.

[0175] In some embodiments, the detection module may include a first power supply module 300, a first detection module 400, a second power supply module 500, and a second detection module 600.

[0176] The first power supply module 300 is connected to the first gate 140 and is configured to provide a voltage to the first gate 140.

[0177] The first detection module 400 is connected to the first active layer 120 and is configured to measure the amplitude and phase shift of the current after flowing through the first gate and the first gate oxide layer.

[0178] The first gate 140 and the first power supply module 300 may be directly connected or indirectly connected. For example, as Figure 4 shown, a first connecting wire 310 is provided between the first gate 140 and the first power supply module 300.

[0179] To facilitate the connection between the first connecting wire 310 and the first gate 140, a first pad 141 may be provided on the first gate 140, and the first connecting wire 310 is connected to the first pad 141.

[0180] A second connecting wire 410 is provided between the first active layer 120 and the first detection module 400. To facilitate the connection between the second connecting wire 410 and the first active layer 120, a second pad 121 may be provided on the first active layer 120, and the second connecting wire 410 is connected to the second pad 121.

[0181] It should be noted that when the number of the first semiconductor structures 100 is multiple, the multiple first semiconductor structures 100 are arranged in a matrix array. For example, as Figure 5 shown, the number of the first semiconductor structures 100 is nine, and the nine first semiconductor structures 100 are arranged in three rows and three columns.

[0182] The number of the first connecting wires 310 is multiple, and each first connecting wire is connected to the first pads 141 of the respective first semiconductor structures 100 located in the same row.

[0183] The number of the second connecting wires 410 is multiple, and each second connecting wire 410 is connected to the second pads 121 of the respective first semiconductor structures 100 located in the same row.

[0184] The second power supply module 500 is connected to the second gate 240 and is configured to provide a voltage to the second gate 240.

[0185] The second detection module 600 is connected to the second active layer 220 and is configured to measure the amplitude and phase shift of the current after flowing through the second gate 240 and the second gate oxide layer.

[0186] The second gate 240 and the second power supply module 500 can be directly connected or indirectly connected. For example, as Figure 4 shown, a third connecting wire 510 is provided between the second gate 240 and the second power supply module 500.

[0187] To facilitate the connection between the third connecting wire 510 and the second gate 240, a third pad 241 can be provided on the second gate 240, and the third connecting wire 510 is connected to the third pad 241.

[0188] A fourth connecting wire 610 is provided between the second active layer 220 and the second detection module 600. To facilitate the connection between the fourth connecting wire 610 and the second active layer 220, a fourth pad 221 can be provided on the second active layer 220, and the fourth connecting wire 610 is connected to the fourth pad 221.

[0189] When the number of the second semiconductor structures 200 can be multiple, the multiple second semiconductor structures 200 are arranged in an array. For example, as Figure 6 shown, the number of the second semiconductor structures 200 is nine, and the nine second semiconductor structures 200 are arranged in three rows and three columns.

[0190] The number of the third connecting wires 510 is multiple, and each third connecting wire 510 is connected to the first pads 141 of the respective second semiconductor structures 200 located in the same row.

[0191] The number of the fourth connecting wires 610 is multiple, and each fourth connecting wire 610 is connected to the second pads 121 of the respective second semiconductor structures 200 located in the same row.

[0192] When forming the active layer, the active layer is likely to form a structure that is thick in the middle and thin on both sides. Therefore, based on the above technical problems, in this embodiment, a measurement system for a semiconductor structure is designed to facilitate measuring the ratio of the capacitance value of the central region of the active layer to the capacitance value of the edge region, and using this ratio to measure the thickness uniformity of the active layer.

[0193] The embodiments or implementation manners in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts among the embodiments can be referred to each other.

[0194] In the description of this specification, the description with reference to terms such as "one implementation manner", "some implementation manners", "illustrative implementation manner", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the implementation manner or example are included in at least one implementation manner or example of the present application.

[0195] In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiments or examples. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0196] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for measuring a semiconductor structure, characterized in that, It includes the following steps: Provide a first semiconductor structure, which includes a first active layer, a first gate oxide layer and a first gate stacked on the first active layer. The projection of the first gate on the first active layer includes a first central region and a first edge region surrounding the first central region; Provide a second semiconductor structure, which is fabricated on the same wafer as the first semiconductor structure. The second semiconductor structure includes a second active layer, a second gate oxide layer and a second gate stacked on the second active layer. The projection of the second gate on the second active layer includes a second central region and a second edge region surrounding the second central region; the lengths of the first central region and the second central region are different, and the lengths of the first edge region and the second edge region are the same; Obtain the capacitance value C of the first semiconductor structure 总1 and the capacitance value C of the second semiconductor structure 总2 ; Obtain the ratio of the capacitance value of the first central region to the capacitance value of the second central region, and obtain the ratio of the capacitance value of the first edge region to the capacitance value of the second edge region; According to the said C 总1 and the said C 总2 , the ratio of the capacitance value of the first central region to the capacitance value of the second central region and the ratio of the capacitance value of the first edge region to the capacitance value of the second edge region are used to obtain the ratio of the capacitance value of the first central region to the capacitance value of the first edge region.

2. The method for measuring a semiconductor structure according to claim 1, characterized in that, Obtain the capacitance value C of the first semiconductor structure 总1 and the capacitance value C of the second semiconductor structure 总2 In the step of, include: Obtain the capacitance value between the first gate and the first active layer in the first semiconductor structure, and denote this capacitance value as C 总1 ; Obtain the capacitance value between the second gate and the second active layer in the second semiconductor structure, and denote this capacitance value as C 总2 .

3. The method for measuring a semiconductor structure according to claim 2, characterized in that, Obtain the capacitance value between the first gate and the first active layer in the first semiconductor structure, and denote this capacitance value as C 总1 In the step of Provide a first power supply module, which is connected to the first gate and used to supply voltage to the first gate; Provide a first detection module, which is connected to the first active layer and used to measure the amplitude and phase shift of the current after flowing through the first gate and the first gate oxide layer; Obtain C based on the voltage value, the amplitude of the current, and the phase shift 总1 .

4. The method for measuring a semiconductor structure according to claim 3, characterized in that, The first power supply module is connected to the first gate through a first connecting wire; The first detection module is connected to the first active layer through a second connecting wire.

5. The method for measuring a semiconductor structure according to claim 4, characterized in that, There is a first pad between the first connecting wire and the first gate, and there is a second pad between the second connecting wire and the first active layer.

6. The method for measuring a semiconductor structure according to claim 5, characterized in that, There are multiple first semiconductor structures, and the multiple first semiconductor structures are arranged in an array; The number of the first connecting wires is multiple, and each first connecting wire connects the first pads of the first semiconductor structures located in the same row; The number of the second connecting wires is multiple, and each second connecting wire connects the second pads of the first semiconductor structures located in the same row.

7. The method for measuring a semiconductor structure according to claim 6, characterized in that, When the number of the first semiconductor structures is multiple and the multiple first semiconductor structures are arranged in an array, the step of obtaining the capacitance value C of the first semiconductor structure includes: 总1 The steps of: Obtain the total capacitance value between the first active layer and the first gate of the multiple first semiconductor structures; Based on the total capacitance value between the first active layer and the first gate of the multiple first semiconductor structures, an average value of the capacitance value between the first active layer and the first gate of the first semiconductor structure is obtained, and this average value is used as C 总1 .

8. The method for measuring a semiconductor structure according to claim 2, characterized in that, The step of obtaining the capacitance value between the second gate and the second active layer in the second semiconductor structure includes: Provide a second power supply module, which is connected to the second gate and used to supply voltage to the second gate; Provide a second detection module, which is connected to the second active layer and used to measure the amplitude and phase shift of the current after flowing through the second gate and the second gate oxide layer; Obtain C based on the voltage value, the amplitude of the current, and the phase shift 总2 .

9. The method for measuring a semiconductor structure according to claim 8, characterized in that, The second power supply module is connected to the second gate through a third connecting wire; The second detection module is connected to the second active layer through a fourth connecting wire.

10. The measuring method of the semiconductor structure according to claim 9, wherein, There is a third pad between the third connecting wire and the second gate, and there is a fourth pad between the fourth connecting wire and the second active layer.

11. The measuring method of the semiconductor structure according to claim 10, wherein, There are multiple second semiconductor structures, and the multiple second semiconductor structures are arranged in an array; The number of the third connection wires is multiple, and each of the third connection wires connects the third pads of the second semiconductor structures located in the same row; The number of the fourth connection wires is multiple, and each of the fourth connection wires connects the fourth pads of the second semiconductor structures located in the same row.

12. The measuring method of the semiconductor structure according to claim 11, wherein, When the number of the second semiconductor structures is multiple and the multiple second semiconductor structures are arranged in an array, the steps of obtaining the capacitance value between the second gate and the second active layer in the second semiconductor structure include: Obtaining the total capacitance value between the second active layer and the second gate of the multiple second semiconductor structures; Based on the total capacitance value between the second active layer and the second gate of the plurality of second semiconductor structures, an average value of the capacitance value between the second active layer and the second gate of the second semiconductor structure is obtained, and this average value is used as C 总2 .

13. The measuring method of the semiconductor structure according to any one of claims 2 - 12, wherein, In the steps of obtaining the ratio of the capacitance value of the first central region to the capacitance value of the second central region, and obtaining the ratio of the capacitance value of the second edge region to the capacitance value of the second edge region, it includes: Along the first direction, the widths of the first central region and the first edge region are both A; Along the second direction, the length of the first central region is a, the length of the first edge region is A - a, the area of the first central region is A×a, and the area of the first edge region is A×(A - a); Along the first direction, the widths of the second central region and the second edge region are both nA; Along the second direction, the length of the second central region is (n - 1)A + a, the length of the second edge region is A - a, the area of the second central region is [(n - 1)A + a]×nA, and the area of the second edge region is nA(A - a); The ratio of the capacitance value of the first central region to the capacitance value of the second central region is The ratio of the capacitance value of the first edge region to the capacitance value of the second edge region is 14. The measuring method of the semiconductor structure according to claim 13, wherein, The ratio of the capacitance value of the first central region to the capacitance value of the first edge region is obtained through the following formula: Among them, C c1 represents the capacitance value of the first central region, C2 represents the capacitance value of the first edge region, and m represents the ratio of C 总1 to C 总2 .

15. The measuring method of the semiconductor structure according to any one of claims 1 - 12, wherein, The first central region includes a first edge and a second edge which are oppositely arranged; The first edge region includes a first region and a second region, the first region is attached to the first edge, and the second region is attached to the second edge; The capacitance value of the first edge region is equal to the sum of the capacitance value of the first region and the capacitance value of the second region.

16. A measuring system for a semiconductor structure, wherein, It includes: A first semiconductor structure, the first semiconductor structure includes a first active layer, a first gate oxide layer and a first gate which are stacked on the first active layer, and the projection of the first gate on the first active layer includes a first central region and a first edge region surrounding the first central region; A second semiconductor structure, and the second semiconductor structure includes a second active layer, a second gate oxide layer and a second gate which are stacked on the second active layer, and the projection of the second gate on the second active layer includes a second central region and a second edge region surrounding the second central region; The widths of the first central region and the second central region are different, and the widths of the first edge region and the second edge region are the same; a processor configured to obtain a capacitance value C of the first semiconductor structure 总1 and a capacitance value C of the second semiconductor structure 总2 ; obtain a ratio of the capacitance value of the first central region to the capacitance value of the second central region, and obtain a ratio of the capacitance value of the first edge region to the capacitance value of the second edge region; and based on the C 总1 and the C 总2 , the ratio of the capacitance value of the first central region to the capacitance value of the second central region, and the ratio of the capacitance value of the first edge region to the capacitance value of the second edge region, obtain a ratio of the capacitance value of the first central region to the capacitance value of the first edge region.

17. The measuring system for a semiconductor structure according to claim 16, wherein, The processor includes a first power module, a first detection module, a second power module and a second detection module; The first power module is connected to the first gate and is used to provide voltage to the first gate; The first detection module is connected to the first active layer and is configured to measure the amplitude and phase shift of the current after flowing through the first gate and the first gate oxide layer; The second power supply module is connected to the second gate and is configured to supply a voltage to the second gate; The second detection module is connected to the second active layer and is configured to measure the amplitude and phase shift of the current after flowing through the second gate and the second gate oxide layer.

18. The measuring system for a semiconductor structure according to claim 17, wherein, The first power supply module is connected to the first gate through a first connection wire; the first detection module is connected to the first active layer through a second connection wire; The second power supply module is connected to the second gate through a third connection wire; the second detection module is connected to the second active layer through a fourth connection wire.

19. The measuring system for a semiconductor structure according to claim 18, wherein, The number of the first semiconductor structures is multiple, and the multiple first semiconductor structures are arranged in a rectangular array; The number of the first connection wires is multiple, and each first connection wire connects the first gates of the first semiconductor structures located in the same row; The number of the second connection wires is multiple, and each second connection wire connects the first active layers of the first semiconductor structures located in the same row.

20. The measuring system for a semiconductor structure according to claim 18, wherein, The number of the second semiconductor structures is multiple, and the multiple second semiconductor structures are arranged in a rectangular array; The number of the third connection wires is multiple, and each third connection wire connects the second gates of the second semiconductor structures located in the same row; The number of the fourth connection wires is multiple, and each fourth connection wire connects the second active layers of the first semiconductor structures located in the same row.

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