Asymmetric Fusion Vision Sensor Pixel Structure, Its Fabrication, and Signal Control Method

Abstract

The present invention relates to an asymmetric fusion vision sensor pixel structure and its preparation and signal control method. The dynamic vision sensor pixel includes: a hybrid substrate, an oxide buried layer, three pixel active regions, two read transistor active regions, an ohmic contact region, three top silicon channel regions, and a gate oxide layer, a gate, two deep trench isolation sidewalls, a shallow trench isolation sidewall, a gate sidewall, a gate metal contact, a source metal contact, a drain metal contact, and a substrate metal contact. Based on a single-transistor optoelectronic in-situ detector structure, the present invention can simultaneously read out the absolute light intensity signal and the differential signal within a compact pixel architecture, realizing the fusion of the light intensity data of a traditional image sensor and the event data of a dynamic vision sensor, and laying a foundation for the application of PISD in the next-generation new dynamic vision sensors.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor image sensing, and relates to an asymmetric fusion vision sensor pixel structure and a preparation and signal control method thereof. Background Art

[0002] Mainstream technologies represented by CMOS image sensors (CIS) have been developed and matured. However, its basic principle is that a PN junction performs photoelectric integration within a frame exposure time, so it is not conducive to imaging high-speed dynamic images with a large dynamic range (High Dynamic Range). In the past decade or so, dynamic vision sensors (Dynamic Vision Sensor) have attracted extensive interest in the academic and industrial fields. Dynamic vision technologies based on event cameras (Event Camera) and frame difference methods (Frame difference) have been proposed, which are expected to solve the bottleneck in the application of traditional CIS technologies in dynamic imaging (see G. Kim, M. Barangi, Z. Foo, N. Pinckney, S. Bang, D. Blaauw, and D. Sylvester, "A 467nW CMOS visual motion sensor with temporal averaging and pixel aggregation." pp. 480-481. and C. Li, L. Longinotti, F. Corradi, and T. Delbruck, "A 132 by 104 10μm-Pixel 250μW 1kefps Dynamic Vision Sensor with Pixel-Parallel Noise and Spatial Redundancy Suppression." pp. C216-C217.).

[0003] Dynamic vision sensors have many advantages, such as a larger dynamic range, less data redundancy, and lower power consumption. Therefore, they can be widely used in fields such as autonomous driving, behavior detection, and feature recognition (see K.D. Choo, L. Xu, Y. Kim, J.H. Seol, X. Wu, D. Sylvester, and D. Blaauw, "5.2 Energy-Efficient Low-Noise CMOS Image Sensor with Capacitor Array-Assisted Charge-Injection SAR ADC for Motion-Triggered Low-Power IoT Applications." pp. 96-98. and B. Son, Y. Suh, S. Kim, H. Jung, J.S. Kim, C. Shin, K. Park, K. Lee, J. Park, J. Woo, Y. Roh, H. Lee, Y. Wang, I. Ovsiannikov, and H. Ryu, "4.1 A 640×480 dynamic vision sensor with a 9µm pixel and 300Meps address-event representation." pp. 66-67.). However, event-based technologies generally only output motion signals and cannot provide the gray value of the pixel itself. In addition, both event cameras and frame difference methods currently require a large amount of in-pixel circuitry, resulting in a complex pixel structure and a reduced fill factor.

[0004] To solve the above problems, the present invention provides an asymmetric fused vision sensor pixel structure. Summary of the Invention

[0005] The object of the present invention is to provide an asymmetric fused vision sensor pixel structure and its preparation and signal control method to output absolute light intensity signals, differential light intensity signals, etc. while achieving a compact structure.

[0006] Based on the principle of a single-transistor optoelectronic in-situ detection device (PISD) (see J. Liu, Y. F. Cao, X. J. Wang, Y. L. Jiang, and J. Wan, “A Novel One-Transistor Active Pixel Sensor With Tunable Sensitivity,” IEEE Electron Device Letters, vol. 42, no. 6, pp. 927-930, Apr, 2021.), the present invention designs a brand-new compact pixel structure based on the frame difference method and its signal control method. The innovation of the present invention lies in introducing a reset gate on one side of the pixel transistor to control the differential capacitance operation on that side, and the result is then amplified and read out through a differential signal readout transistor. Therefore, the absolute light intensity signal and the differential signal of consecutive frames can be fused and output simultaneously in a compact pixel structure.

[0007] The object of the present invention can be achieved through the following technical solutions:

[0008] One of the technical solutions of the present invention provides an asymmetric fusion vision sensor pixel structure, including an anti-reflection layer at the bottom, and a hybrid substrate and a left substrate located on the anti-reflection layer, wherein,

[0009] A shallow trench isolation sidewall and a substrate ohmic contact region are formed on the hybrid substrate, and support the first buried oxide layer above and the topmost first top region. The first top region includes three pixel active regions, a first top channel region located between two adjacent pixel active regions. A main gate and a reset gate are respectively provided above the two first top channel regions. The reset gate is located on the left side of the main gate. The main gate and the reset gate respectively control the on / off of the corresponding first top channel region through the gate oxide layer below them. Protective sidewalls are formed on both sides of the main gate and the reset gate. Deep trench isolation sidewalls are formed on the left and right sides of the hybrid substrate.

[0010] The left substrate supports the second buried oxide layer above and the topmost second top region. The second top region includes two read transistor active regions and a second top channel region located between the two read transistor active regions. A read transistor gate is provided above the second top channel region. The read transistor gate also controls the on / off of the second top channel region through the gate oxide layer below it. Protective sidewalls are also formed on both sides of the read transistor gate.

[0011] On the pixel active region to the right of the reset gate and the readout transistor active region to the right of the readout transistor gate, there are also source metal contact electrodes respectively. On the pixel active region to the right of the main gate, the pixel active region to the left of the reset gate, and the readout transistor active region to the left of the readout transistor gate, there are drain metal contact electrodes respectively. On the substrate ohmic contact region, there is a substrate metal contact electrode, and on the main gate, the reset gate, and the readout transistor gate, there are gate metal contact electrodes respectively.

[0012] Further, both the hybrid substrate and the left substrate are semiconductors, independently selected from silicon, germanium, germanium-silicon, gallium nitride, or indium gallium arsenide.

[0013] Further, the pixel active region, the readout transistor active region, the first top channel region, and the second top channel region also all use semiconductors, and are independently selected from silicon, germanium, germanium-silicon, gallium nitride, or indium gallium arsenide.

[0014] Further, the first buried oxide layer and the second buried oxide layer are independently silicon dioxide, aluminum oxide, or hafnium oxide insulating materials.

[0015] Further, the hybrid substrate and the left substrate are lightly doped P-type, with a doping concentration of 10 15 -10 17 cm -3 。

[0016] Further, the pixel active region and the readout transistor active region are heavily doped N-type, with a doping concentration of 10 19 -10 21 cm -3 。

[0017] Further, the substrate ohmic contact region is heavily doped P-type, with a doping concentration of 10 19 -10 21 cm -3 。

[0018] Further, the antireflection layer is composed of an antireflection SiO2 layer, an antireflection Si3N4 layer, and an antireflection SiO2 layer.

[0019] The second technical solution of the present invention provides a preparation method for a fused vision sensor pixel structure based on a fully depleted silicon-on-insulator substrate, including the following steps:

[0020] (1) On the starting silicon-on-insulator wafer, through etching and epitaxy, a hybrid substrate, a left substrate, a first buried oxide layer, a second buried oxide layer, and a first top channel region and a second top channel region are formed;

[0021] (2) After photolithography and etching, a shallow trench isolation sidewall and two deep trench isolation sidewalls are formed by oxidation growth in the hybrid substrate;

[0022] (3) Photolithography and ion implantation are performed to form a substrate ohmic contact region;

[0023] (4) A gate oxide layer and a gate material are deposited and epitaxially grown on the structure. After photolithography and etching, the main gate, reset gate, and read transistor gate are obtained;

[0024] (5) A protective sidewall is formed by atomic layer deposition;

[0025] (6) The top silicon part covered by the main gate, reset gate, and read transistor gate is removed by photolithography and etching, and then epitaxially grown and in-situ doped to obtain the pixel active region and the read transistor active region;

[0026] (7) Windows of each gate, source-drain contact region, and substrate ohmic contact region are opened by photolithography, and metal is deposited and annealed to form metal contact electrodes on the pixel active region, read transistor active region, and the top of each gate;

[0027] (8) An antireflection layer is deposited and grown.

[0028] The pixel structure formed by the above preparation process has the characteristics of multiple transistors and multiple gates. Except for the main gate of the transistor, the reset gate plays the role of connecting the differential capacitor, and the outermost transistor is the differential signal read transistor. Therefore, the pixel implemented by the present invention can simultaneously realize the fusion readout of the absolute light intensity signal and the differential signal.

[0029] Further, in step (1), the thickness of the first oxidation buried layer and the second oxidation buried layer is 10 nm to 1000 nm.

[0030] Further, in step (1), the thickness of the first top channel region and the second top channel region is 5 nm to 500 nm.

[0031] Further, in step (3), boron or boron fluoride is used for ion implantation, and the dose is 10 13 cm -2 ~10 16 cm -2 , the energy is 1 keV to 100 keV, the ion activation annealing temperature is 900 to 1200 °C, and the time is 1 microsecond to 10 seconds.

[0032] Further, in step (4), the thickness of the gate oxide layer is 1 to 30 nm.

[0033] Further, in step (4), the thickness of the grown gate material is 10 nm to 500 nm.

[0034] Further, in step (7), the deposited metal is aluminum, nickel, titanium or metal silicide, and the annealing temperature is 300 - 900 °C.

[0035] The third technical solution of the present invention provides a signal control method for a fused vision sensor pixel structure based on a fully depleted silicon-on-insulator substrate. The fused vision sensor pixel structure includes a pixel transistor part on a hybrid substrate and a differential signal readout transistor part on a left substrate. The signal control method includes the following steps:

[0036] (a) Connect the gate metal contact electrode on the readout transistor gate to the drain metal contact electrode on the left side of the reset gate. At the same time, bias the source, drain, and gate voltages of the pixel transistor part and the differential signal readout transistor part. Among them, all source electrodes are grounded to GND, and the other two drain electrodes except the drain electrode on the left side of the reset gate are connected to a high-potential power supply V DS , and the main gate is connected to another high-potential power supply V GS , so that the pixel transistor is in an always-on state;

[0037] (b) Before the integration starts, pull the reset gate to a low level, and at the same time, the substrate metal contact electrode is in a high-level state;

[0038] (c) Apply a low-level transient pulse to the substrate metal contact electrode to form a deep depletion region in the hybrid substrate to prepare for collecting photo-generated electrons;

[0039] (d) When the light is turned on, photo-generated carriers start to integrate in the above-mentioned depletion region;

[0040] (e) When the light is turned off, pull the reset gate to a high level. Before the substrate metal contact electrode is reset, read the first frame of differential signal I E1 from the drain of the differential signal readout transistor part; at the same time, read the first frame of absolute signal I out1 from the rightmost drain of the pixel transistor part;

[0041] (f) Pull the substrate metal contact electrode to a high level for reset. The first frame ends, and at the same time, the differential capacitance (the transistor capacitance controlled by the reset gate, correspondingly called the differential capacitance) stores the first frame of light intensity signal; then apply a low-level transient pulse to the substrate metal contact electrode to form a deep depletion region in the hybrid substrate to prepare for collecting photo-generated electrons;

[0042] (g) When the light is turned on, photo-generated carriers start to integrate in the above-mentioned depletion region;

[0043] (h) When the light is turned off, pull the reset gate to a high level; before the substrate metal contact electrode is reset, read the second frame of differential signal I E2, while reading the second-frame absolute signal I from the drain on the right side of the pixel transistor section out2 ;

[0044] (i) Pull the substrate metal contact electrode to a high level for reset. The second frame ends, and at the same time, the differential capacitor stores the second-frame light intensity signal.

[0045] (j) Repeat the above steps, and the middle pixel transistor section can obtain the absolute light intensity signal of each frame, and the differential capacitor on the left can calculate the light intensity differential signal between each frame and the previous frame.

[0046] Compared with the prior art, the present invention forms a virtual photodiode under the buried oxide layer / substrate interface by applying a substrate pulse, introduces an auxiliary reset gate on the pixel active region as a reset switch to implement differential operation inside the pixel, and adds a differential signal readout transistor outside the deep trench isolation surrounded area. Among them, the middle transistor senses the light intensity signal of the substrate virtual diode and amplifies and reads it out. The capacitor connected to the reset gate performs differential operation on the light intensity signals between frames, and the result is amplified and read out through the corresponding differential signal readout transistor. The present invention is based on the structure of a single-transistor optoelectronic in-situ detector (Photoelectron in-situ Sensing Device: PISD), and can simultaneously read out the absolute light intensity signal and the differential signal inside the compact pixel architecture, realizing the fusion of the light intensity data of a traditional image sensor (Active Pixel Sensor: APS) and the event data of a dynamic vision sensor (Dynamic Vision Sensor: DVS), laying a foundation for the application of PISD in the next-generation new dynamic vision sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 It is a structural diagram of the fusion vision sensor pixel of the present invention.

[0048] Figure 2 It is a preparation process diagram of the fusion vision sensor pixel of the present invention.

[0049] Figure 3 It is a signal control method diagram of the fusion vision sensor pixel of the present invention.

[0050] Figure 4 It is the structure of Example 2 of the fusion vision sensor pixel of the present invention.

[0051] Figure 5 It is a signal control method diagram of Example 2 of the fusion vision sensor pixel of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0052] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. This embodiment is implemented on the premise of the technical solution of the present invention, and gives detailed implementation manners and specific operation processes, but the protection scope of the present invention is not limited to the following embodiments.

[0053] Based on the same working principle, the structures of the pixels and the corresponding preparation and signal control methods can be different, and the specific implementation manners are embodied in different embodiments.

[0054] In addition, in the following embodiments, unless otherwise specified for the functional component structures or processing technologies, it means that they are all conventional component structures or conventional processing technologies in the art for realizing the corresponding functions.

[0055] Embodiment 1 (corresponding to Figure 1 the pixel structure of, Figure 2 the process flow of, and Figure 3 the control signal of):

[0056] As Figure 1 shown, the fused vision sensor pixel structure based on a fully depleted silicon-on-insulator substrate provided in this embodiment includes an anti-reflection layer at the bottom (which is composed of a silicon oxide layer 38, a silicon nitride layer 39, and a silicon oxide layer 40), and a hybrid substrate 37 and a left substrate 36 located on the anti-reflection layer. Among them,

[0057] A shallow trench isolation sidewall 33 and a substrate ohmic contact region 30 are formed on the hybrid substrate 37, and support the upper first buried oxide layer 34 and the uppermost first top region. The first top region includes three pixel active regions 27, 28, 29, and first top channel regions 23, 24 located between two adjacent pixel active regions (i.e., pixel active region 27 and pixel active region 28, pixel active region 28 and pixel active region 29). Above the two first top channel regions 23, 24, a reset gate 11 and a body gate 12 are respectively provided. The reset gate 11 is located on the left side of the body gate 12. The body gate 12 and the reset gate 11 respectively control the on and off of the corresponding first top channel regions 23, 24 through the gate oxide layers 21, 20 below them. Protective sidewalls 17, 18, 15, 16 are formed on both sides of the body gate 12 and the reset gate 11. Deep trench isolation sidewalls 32, 35 are formed on the left and right sides of the hybrid substrate 37.

[0058] The left substrate 36 supports the upper second buried oxide layer 31 and the topmost second top region. The second top region includes two sections of read transistor active regions 25, 26, and a second top channel region 22 located between the two read transistor active regions 25, 26. Above the second top channel region 22, there is a read transistor gate 10, and this read transistor gate 10 also controls the on / off of the second top channel region 22 through the gate oxide layer 19 below it. Protective sidewalls 13, 14 are also formed on both sides of the read transistor gate 10.

[0059] Source metal contact electrodes 3, 7 are respectively provided on the pixel active region 28 and the read transistor active region 26, and drain metal contact electrodes 1, 5, 9 are respectively provided on the pixel active region 29, the pixel active region 27, and the read transistor active region 25. A substrate metal contact electrode 6 is provided on the substrate ohmic contact region 30, and gate metal contact electrodes 2, 4, 8 are respectively provided on the main gate 12, the reset gate 11, and the read transistor gate 10.

[0060] As Figure 2 shown, the process flow of Embodiment 1 mainly has the following steps:

[0061] (1) As Figure 2 (a) shown, it is an initial silicon-on-insulator wafer. Its substrate doping is generally weakly p-type doped silicon, and the doping concentration is between 10 15 -10 17 cm -3 . According to different detected optical wavelengths, the substrate can also be materials such as silicon germanium, gallium nitride, or indium gallium arsenide. Its buried layer is generally silicon dioxide, with a thickness between 10 nm and 1000 nm. The upper channel is generally made of materials such as silicon, silicon germanium, gallium nitride, or indium gallium arsenide, with a thickness between 5 nm and 500 nm.

[0062] (2) Using photoresist as a mask, etch the buried oxide layer to the substrate silicon, and then epitaxially grow silicon; photolithograph and open the windows for the substrate sidewall isolation STI and DTI, then use photoresist as a mask to etch the substrate silicon, and then oxidize and grow silicon dioxide. The STI and DTI oxide isolation layers can be formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD) methods, as Figure 2 (b). The etching can be selected from dry or wet methods: dry etching generally uses fluorine-based or halogen element gases such as SF6, Cl2, etc.; while wet etching generally uses strong acids or strong bases such as HF, NH4HF2, etc. solutions.

[0063] (3) Photolithograph and open the windows for the substrate contact region, and perform ion implantation or epitaxial doping on the mixed substrate surface to form the substrate ohmic contact region. Ion implantation generally uses boron or boron fluoride, with a dose of 10 13 cm-2 to 10 16 cm -2 Between, the energy is between 1 keV and 100 keV, the ion activation annealing temperature is generally between 900 degrees and 1200 degrees, and the time is between 1 microsecond and 10 seconds. For example Figure 2 (c);

[0064] (4) Deposit and grow a gate oxide layer and epitaxially grow a gate material on the structure. The oxide layer can be a high-K dielectric material such as hafnium oxide or aluminum oxide, deposited by an atomic layer deposition system (ALD), and its thickness is generally between 1 nm and 30 nm. The gate material can be a polysilicon layer or a composite layer of polysilicon and metal, and its thickness can be between 10 nm and 500 nm.

[0065] (5) Lithographically open the windows of the three gates, and then use photoresist as a mask to etch the grown material in step (4) to form the pattern of the gates, as Figure 2 (d) shown; The etching can be selected from dry or wet methods. Dry etching generally uses fluorine-based or halogen-based gas, such as SF6, CHF3, HBr or Cl2, etc. Wet etching generally uses solutions such as TMAH, KOH, etc.

[0066] (6) Deposit a layer of gate sidewall material, such as commonly used silicon nitride, silicon dioxide, or low dielectric constant dielectrics such as SiOCN and SiBCN. The deposition can use processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. Then perform etching to form the gate sidewall as Figure 2 (e) shown; The etching generally uses reactive ion etching with vertical directionality. Dry etching generally uses fluorine-based gas, such as SF6, CHF3 or CH3F, etc.

[0067] (7) Lithographically open the windows of the pixel and readout transistor active regions, use photoresist as a mask to etch away the top silicon part covered by the gate, and then epitaxially grow silicon. In-situ doping is carried out during epitaxial growth, and the doping concentration is between 10 19 cm -3 to 10 21 cm -3 Between. Finally, form an N-type heavily doped active region (i.e., the pixel active region and the readout transistor active region), as Figure 2 (f).

[0068] (8) Lithographically open the windows of the three gates, source-drain contact regions, and substrate ohmic contact regions, deposit metal and anneal to form electrodes on the top of the N-type heavily doped active region and the three gates as Figure 2 (g) shown; Commonly used metals are aluminum, nickel, titanium or metal silicides, such as nickel silicide, titanium silicide, etc., and the annealing temperature is between 300 and 900 °C;

[0069] (9) Deposit and grow an SiO2 / Si3N4 / SiO2 antireflection layer, which can be formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD), such as Figure 2 (h).

[0070] Such as Figure 3 As shown, the left - hand numbers in the figure are the numbers of each electrode. The signal control method for the pixel structure obtained in the above - mentioned embodiment is as follows:

[0071] Connect and short - circuit the drain metal contact electrode 5 and the gate metal contact electrode 8. First, bias the source, drain, and gate voltages of the pixel transistor and the differential signal read - out transistor at appropriate fixed biases, where all sources (i.e., source metal contact electrodes 3, 7) are grounded to GND; all drains (i.e., drain metal contact electrodes 1, 9) are connected to a high - potential power supply V DS (such as 0.8V); at the same time, the gate (i.e., gate metal contact electrode 2) of the pixel transistor is connected to another high - potential power supply V GS (such as 1.8V) to keep the transistor in the normally - on state.

[0072] Before the integration starts, pull the reset gate (i.e., gate metal contact electrode 4) to a low level; at the same time, the substrate bias of the pixel transistor (i.e., substrate metal contact electrode 6) is in a high - level state;

[0073] Then, apply a low - level transient pulse to the substrate bias to form a deep depletion region (virtual photodiode) in the hybrid substrate 37 to prepare for collecting photo - generated electrons;

[0074] When the light is turned on, photo - generated carriers start to integrate in the above - mentioned depletion region;

[0075] When the light is turned off, pull the reset gate to a high level; before the substrate bias is reset, read the first - frame differential signal I from the drain of the differential signal read - out transistor (i.e., drain metal contact electrode 9) E1 ; at the same time, read the first - frame absolute signal I from the drain of the pixel transistor (i.e., drain metal contact electrode 1) out1 ;

[0076] Pull the substrate bias to a high level for reset. The first frame ends, and at the same time, the differential capacitor records the first - frame light - intensity signal; then apply a low - level transient pulse to the substrate bias to form a deep depletion region (virtual photodiode) in the substrate to prepare for collecting photo - generated electrons;

[0077] When the light is turned on, photo - generated carriers start to integrate in the above - mentioned depletion region;

[0078] When the light is turned off, pull the reset gate to a high level; before the substrate bias is reset, read the second - frame differential signal I from the drain (9) of the differential signal read - out transistor E2; Meanwhile, read the second-frame absolute signal I from the drain of the pixel transistor. out2 ;

[0079] Pull the substrate bias to the high level for reset. The second frame ends, and meanwhile, the differential capacitor records the second-frame light intensity signal.

[0080] Repeat the above steps, and the intermediate pixel transistor can obtain the absolute light intensity signal of each frame, and the differential capacitor on the left can calculate the light intensity differential signal between each frame and the previous frame.

[0081] Embodiment 2 (corresponding to Figure 4 the pixel structure and Figure 5 the control signal):

[0082] As Figure 4 shown, Embodiment 2 is similar to Embodiment 1, except that the substrate is lightly doped N-type, and the transistors in the upper silicon layer are P-type instead of N-type. Therefore, the process flow of this embodiment is similar to that of Embodiment 1, only need to replace the SOI substrate in step (1) and reverse the in-situ doping impurity type during epitaxial growth in steps (3) and (7).

[0083] As Figure 5 shown, for the signal control of Embodiment 2, only need to change the corresponding partial signal control according to the change of the device doping type to complete the corresponding function of Embodiment 2. The signal control is as follows:

[0084] Connect the drain metal contact electrode 5 and the gate metal contact electrode 8 in short circuit. First, bias the source, drain, and gate voltages of the pixel transistor and the differential signal read transistor at appropriate fixed biases, where all sources (i.e., source metal contact electrodes 3, 7) are grounded to GND; all drains (i.e., drain metal contact electrodes 1, 9) are connected to a low-potential power supply V DS (such as -0.8V); meanwhile, the gate of the pixel transistor (i.e., gate metal contact electrode 2) is connected to another low-potential power supply V GS (such as -1.8V) to keep the transistor in the normally open state.

[0085] Before the integration starts, pull the reset gate (i.e., gate metal contact electrode 4) to the high level; meanwhile, the substrate bias of the pixel transistor (i.e., substrate metal contact electrode 6) is in the low-level state;

[0086] Then, apply a high-level transient pulse to the substrate bias to form a deep depletion region (virtual photodiode) in the substrate to prepare for collecting photo-generated electrons;

[0087] Turn on the light, and the photo-generated carriers start to integrate in the above-mentioned depletion region;

[0088] When the illumination ends, the reset gate is pulled to a low level; before the substrate bias is reset, the first frame of differential signal I is read from the drain of the differential signal read transistor (i.e., the drain metal contact electrode 9). E1 ; At the same time, the first frame of absolute signal I is read from the drain of the pixel transistor (i.e., the drain metal contact electrode 1). out1 ;

[0089] The substrate bias is pulled to a low level for reset, and the first frame ends. At the same time, the differential capacitance records the first frame of light intensity signal; then a high-level transient pulse is applied to the substrate bias to form a deep depletion region (virtual photodiode) in the substrate to prepare for collecting photo-generated electrons.

[0090] When the illumination is turned on, photo-generated carriers start to integrate in the above-mentioned depletion region.

[0091] When the illumination ends, the reset gate is pulled to a low level; before the substrate bias is reset, the second frame of differential signal I is read from the drain of the differential signal read transistor. E2 ; At the same time, the second frame of absolute signal I is read from the drain of the pixel transistor. out2 ;

[0092] The substrate bias is pulled to a low level for reset, and the second frame ends. At the same time, the differential capacitance records the second frame of light intensity signal.

[0093] Repeat the above steps, and the middle pixel transistor can obtain the absolute light intensity signal of each frame, and the differential capacitance on the left can calculate the light intensity differential signal between each frame and the previous frame.

[0094] The above description of the embodiments is to enable those of ordinary skill in the art to understand and use the invention. It is obvious that those skilled in the art can easily make various modifications to these embodiments and apply the general principles described herein to other embodiments without creative labor. Therefore, the present invention is not limited to the above embodiments, and the improvements and modifications made by those skilled in the art without departing from the scope of the present invention should be within the protection scope of the present invention.

Claims

1. An asymmetric fusion vision sensor pixel structure, characterized in that It includes an antireflection layer at the bottom, and a hybrid substrate and a left substrate located on the antireflection layer. Among them, a shallow trench isolation sidewall and a substrate ohmic contact region are formed on the hybrid substrate, and the first buried oxide layer above and the topmost first top region are supported. The first top region includes three segments of pixel active regions, a first top channel region located between two adjacent pixel active regions. A body gate and a reset gate are respectively provided above the two first top channel regions. The reset gate is located on the left side of the body gate. The body gate and the reset gate respectively control the on / off of the corresponding first top channel region through the gate oxide layer below them. Protective sidewalls are formed on both sides of the body gate and the reset gate. Deep trench isolation sidewalls are formed on the left and right sides of the hybrid substrate. The left substrate supports the second buried oxide layer above and the topmost second top region. The second top region includes two segments of read transistor active regions and a second top channel region located between the two read transistor active regions. A read transistor gate is provided above the second top channel region. This read transistor gate also controls the on / off of the second top channel region through the gate oxide layer below it. Protective sidewalls are also formed on both sides of the read transistor gate. Source metal contact electrodes are respectively provided on the pixel active region on the right side of the reset gate and the read transistor active region on the right side of the read transistor gate. Drain metal contact electrodes are respectively provided on the pixel active region on the right side of the body gate, the pixel active region on the left side of the reset gate, and the read transistor active region on the left side of the read transistor gate. A substrate metal contact electrode is provided on the substrate ohmic contact region. Gate metal contact electrodes are respectively provided on the body gate, the reset gate, and the read transistor gate.

2. The asymmetric fusion vision sensor pixel structure according to claim 1, characterized in that, The hybrid substrate and the left substrate are both semiconductors, and are respectively independently selected from silicon, germanium, germanium-silicon, gallium nitride, or indium gallium arsenide; The pixel active region, the read transistor active region, the first top channel region, and the second top channel region also adopt semiconductors, and are respectively independently selected from silicon, germanium, germanium-silicon, gallium nitride, or indium gallium arsenide; The first buried oxide layer and the second buried oxide layer are respectively independently silicon dioxide, aluminum oxide, or hafnium oxide insulating materials.

3. The asymmetric fusion vision sensor pixel structure according to claim 1, wherein, The described hybrid substrate and the left substrate are P-type lightly doped with a doping concentration of 10 15 -10 17 cm -3 ; The pixel active region and the readout transistor active region are N-type heavily doped, with a doping concentration of 10 19 -10 21 cm -3 ; The substrate ohmic contact region is P-type heavily doped with a doping concentration of 10 19 -10 21 cm -3 .

4. The preparation method of an asymmetric fusion vision sensor pixel structure according to any one of claims 1-3, characterized in that It includes the following steps: (1) On the starting insulating layer silicon wafer, a hybrid substrate, a left substrate, a first buried oxide layer, a second buried oxide layer, and a first top channel region and a second top channel region are formed through etching and epitaxy; (2) After photolithography and etching, a shallow trench isolation sidewall and two deep trench isolation sidewalls are formed by oxidation growth in the hybrid substrate; (3) Photolithography and ion implantation are carried out to form a substrate ohmic contact region; (4) A gate oxide layer is deposited and grown in the structure, and a gate material is epitaxially grown. After photolithography and etching, a body gate, a reset gate, and a read transistor gate are obtained; (5) Protective sidewalls are formed by atomic layer deposition; (6) The top silicon part covered by the body gate, the reset gate, and the read transistor gate is removed by photolithography and etching, and then epitaxially grown and in-situ doped to obtain a pixel active region and a read transistor active region; (7) Lithographically open the windows of each gate, source-drain contact region, and substrate ohmic contact region, deposit metal and anneal to form metal contact electrodes on top of the pixel active region, the readout transistor active region, and each gate; (8) Deposit and grow an antireflection layer.

5. The manufacturing method of an asymmetric fusion vision sensor pixel structure according to claim 4, characterized in that In step (1), the thickness of the first buried oxide layer and the second buried oxide layer is 10 nm to 1000 nm.

6. The preparation method of an asymmetric fusion vision sensor pixel structure according to claim 4, characterized in that In step (1), the thickness of the first top channel region and the second top channel region is 5 nm to 500 nm.

7. The manufacturing method of an asymmetric fusion vision sensor pixel structure according to claim 4, characterized in that, In step (3), boron or boron fluoride is used for ion implantation, and the dose is 10 13 cm -2 ~10 16 cm -2 , the energy is 1 keV to 100 keV, the ion activation annealing temperature is 900 to 1200 °C, and the time is 1 microsecond to 10 seconds.

8. The preparation method of an asymmetric fusion vision sensor pixel structure according to claim 4, characterized in that, In step (4), the thickness of the gate oxide layer is 1 to 30 nm; The thickness of the grown gate material is 10 nm to 500 nm.

9. The manufacturing method of an asymmetric fusion vision sensor pixel structure according to claim 4, characterized in that In step (7), the deposited metal is aluminum, nickel, titanium, or metal silicide, and the annealing temperature is 300 to 900 °C.

10. A signal control method for an asymmetric fusion vision sensor pixel structure according to any one of claims 1-3, characterized in that, This fused vision sensor pixel structure includes a pixel transistor part on a hybrid substrate and a differential signal readout transistor part on the left substrate. This signal control method includes the following steps: (a) Connect the gate metal contact electrode on the gate of the readout transistor to the drain metal contact electrode on the left side of the reset gate. At the same time, bias the source, drain, and gate voltages of the pixel transistor part and the differential signal readout transistor part, where all sources are grounded to GND, and the other two drains except the drain on the left side of the reset gate are connected to a high-potential power supply V DS , and the main gate is connected to another high-potential power supply V GS , so that the pixel transistor is in the normally open state; (b) Before the integration starts, pull the reset gate to a low level, and at the same time, the substrate metal contact electrode is in a high-level state; (c) Apply a low-level transient pulse to the substrate metal contact electrode to form a deep depletion region in the hybrid substrate to prepare for collecting photo-generated electrons; (d) Turn on the light, and photo-generated carriers start to integrate in the above-mentioned depletion region; (e) At the end of illumination, pull the reset gate to a high level, and read the first-frame differential signal I from the drain of the differential signal read transistor section before the substrate metal contact electrode is reset. E1 At the same time, read the first-frame absolute signal I from the drain of the rightmost pixel transistor section. out1 ; (f) Pull the substrate metal contact electrode to a high level for reset, the first frame ends, and at the same time, the differential capacitor stores the first-frame light intensity signal; then apply a low-level transient pulse to the substrate metal contact electrode to form a deep depletion region in the hybrid substrate to prepare for collecting photo-generated electrons; (g) Turn on the light, and photo-generated carriers start to integrate in the above-mentioned depletion region; (h) At the end of illumination, pull the reset gate to a high level; before resetting the substrate metal contact electrode, read the second-frame differential signal I from the drain of the differential signal read transistor section E2 , and at the same time read the second-frame absolute signal I from the drain on the right side of the pixel transistor section out2 ; (i) Pull the substrate metal contact electrode to a high level for reset, the second frame ends, and at the same time, the differential capacitor stores the second-frame light intensity signal; (j) Repeat the above steps, and the middle pixel transistor part can obtain the absolute light intensity signal of each frame, and the left differential capacitor can calculate the light intensity differential signal between each frame and the previous frame.

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