Vertical gate transistor structure and method of making the same

Abstract

The application provides a vertical gate transistor structure and a preparation method thereof, and the vertical gate transistor structure comprises a substrate, the substrate comprises a plurality of vertical gate transistors arranged in an array, the plurality of vertical gate transistors are spaced apart in a Y direction by a plurality of first isolation structures, are spaced apart in an X direction by a plurality of fifth isolation structures, and are connected with corresponding second isolation structures in a Z direction; a plurality of word lines extend along the Y direction and are arranged in parallel in the X direction, two adjacent word lines are provided with a third isolation structure, and the two adjacent word lines are isolated by a fourth isolation structure and are away from a surface of the substrate by a second distance, wherein the X direction, the Y direction and the Z direction are perpendicular to each other. By embedding the isolation structure between the adjacent word lines, the complete separation of the word lines in the vertical gate transistor structure is ensured, and the isolation reliability is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to a vertical gate transistor structure and its fabrication method. Background Technology

[0002] In the semiconductor field, to achieve higher storage density, it is necessary to fabricate as many transistors as possible within a unit area. Traditional methods of shrinking size have reached their physical limits. In a new vertical gate transistor structure, the source and drain can be placed at the top and bottom ends, respectively, which can reduce the transistor area.

[0003] However, this structure involves a character separation process. Because the connection point between the two character lines is located deep within the groove, it is difficult to completely separate the two character lines. During the self-separation process, if the two character lines are not completely separated at any point along the groove direction, leakage will occur, resulting in a loss of product yield.

[0004] Therefore, how to ensure complete separation of word lines and improve isolation reliability has become an urgent technical problem to be solved. Summary of the Invention

[0005] This invention provides a vertical gate transistor structure and its fabrication method, which is used to ensure complete separation of word lines and improve isolation reliability.

[0006] To address the aforementioned problems, the present invention provides a method for fabricating a vertical gate transistor structure, comprising: providing a substrate, the substrate including a plurality of active regions arranged in an array, the plurality of active regions being spaced apart by a plurality of first isolation structures in the Y direction and spaced apart by a plurality of trenches in the X direction, the X direction being perpendicular to the Y direction; forming a second isolation structure at the bottom of each trench; forming a gate oxide layer on the sidewall of each trench, the gate oxide layer being in contact with the second isolation structure; forming a sacrificial layer on the sidewall and bottom of each trench, the sacrificial layer at least covering the second isolation structure and the gate oxide layer; filling each trench with an isolation material and planarizing it to form a third isolation structure; removing a portion of the sacrificial layer, depositing a conductive material and processing it to form two mutually insulated word lines in each trench, wherein the retained sacrificial layer serves as a fourth isolation structure such that the two word lines are at a first distance from the second isolation structure and at a second distance from the surface of the substrate.

[0007] This invention also provides a vertical gate transistor structure, comprising: a substrate including a plurality of vertical gate transistors arranged in an array, wherein the plurality of vertical gate transistors are spaced apart by a plurality of first isolation structures in the Y direction, spaced apart by a plurality of fifth isolation structures in the X direction, and connected to a corresponding second isolation structure in the Z direction; and a plurality of word lines extending along the Y direction and arranged parallel to each other in the X direction, wherein a third isolation structure is provided between adjacent word lines, and adjacent word lines are isolated from the corresponding second isolation structures by a fourth isolation structure and are at a second distance from the surface of the substrate, wherein the X, Y, and Z directions are all perpendicular to each other. This invention, by embedding isolation structures between adjacent word lines, ensures complete separation of word lines in the vertical gate transistor structure, thereby improving isolation reliability. Attached Figure Description

[0008] To more clearly illustrate the technical solutions of the specific embodiments of the invention, the drawings used in the specific embodiments of the invention will be briefly introduced below. Obviously, the drawings described below are only some specific embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 The diagram shown is a schematic representation of a method for fabricating a vertical gate transistor structure according to an embodiment of the present invention.

[0010] Figures 2A to 2K The diagram shown is a schematic representation of the device structure formed by the main steps of the fabrication method of the vertical gate transistor structure according to an embodiment of the present invention.

[0011] Figure 3 The diagram shown is a schematic representation of the device structure formed by the main steps of the fabrication method of the vertical gate transistor structure according to an embodiment of the present invention.

[0012] Figure 4 The diagram shown is a schematic diagram of a vertical gate transistor structure according to an embodiment of the present invention;

[0013] Figures 5A-5B The diagram shown is a schematic representation of the device structure formed by the main steps following the step of forming two mutually insulated word lines, according to an embodiment of the present invention.

[0014] Figures 6A-6E The diagram shown is a schematic representation of the device structure formed by the main steps of the fabrication method of the vertical gate transistor structure according to another embodiment of the present invention. Detailed Implementation

[0015] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0016] Please refer to the following: Figures 1-3 ,in, Figure 1 This is a method for fabricating the vertical gate transistor structure according to an embodiment of the present invention. Figures 2A to 2K , Figure 3 The diagram shown is a schematic representation of the device structure formed by the main steps of the fabrication method of the vertical gate transistor structure according to an embodiment of the present invention.

[0017] like Figure 1 As shown, the fabrication method described in this embodiment includes: Step S10, providing a substrate, the substrate including a plurality of active regions arranged in an array, the plurality of active regions being separated by a plurality of first isolation structures in the Y direction and separated by a plurality of trenches in the X direction, the X direction being perpendicular to the Y direction; Step S11, forming a second isolation structure at the bottom of each trench; Step S12, forming a gate oxide layer on the sidewall of each trench, the gate oxide layer being in contact with the second isolation structure; Step S13, forming a sacrificial layer on the sidewall and bottom of each trench, the sacrificial layer at least covering the second isolation structure and the gate oxide layer; Step S14, filling each trench with isolation material and planarizing it to form a third isolation structure; Step S15, removing part of the sacrificial layer, depositing conductive material and processing it to form two mutually insulated word lines in each trench; wherein, the retained sacrificial layer serves as a fourth isolation structure such that the two word lines have a first distance from the second isolation structure and a second distance from the surface of the substrate.

[0018] Please refer to step S10. Figure 2A and Figure 2B A substrate 20 is provided, the substrate 20 including a plurality of active regions 200 arranged in an array, the plurality of active regions 200 being spaced apart in the Y direction by a plurality of first isolation structures 201 (e.g., Figure 2A As shown), it is separated by multiple grooves 202 in the X direction (e.g. Figure 2B As shown in the figure, the X direction is perpendicular to the Y direction.

[0019] in, Figure 2A The base 20 with the first isolation structure 201 is shown. (a) is a top view along the Z direction, and (b) is a cross-sectional view along the XY direction with the AA' line in (a) as the cross-section. Figure 2BTo form a base 20 with grooves 202, part (a) is a top view along the Z direction, and part (b) is a cross-sectional view along the XZ direction with the BB' line in part (a) as the cross-section.

[0020] In this embodiment, the active region 200 is made of monocrystalline silicon, and the first isolation structure 201 is made of silicon oxide. In other embodiments of the present invention, the material of the first isolation structure 201 may also be selected from silicon nitride or polycrystalline silicon.

[0021] Please refer to step S11. Figure 2C A second isolation structure 203 is formed at the bottom of each of the trenches 202. Figure 2C Part (a) is a top view along the Z direction, and part (b) is a cross-sectional view along line BB' in part (a) along the XZ direction.

[0022] In this embodiment, the material of the second isolation structure 203 is silicon oxide; in other embodiments of the present invention, the material of the second isolation structure may also be selected from silicon nitride or polycrystalline silicon.

[0023] Please refer to step S12. Figure 2D A gate oxide layer 204 is formed on the sidewall of each trench 202, and the gate oxide layer 204 is connected to the second isolation structure 203. Figure 2D Part (a) is a top view along the Z direction, and part (b) is a cross-sectional view along line BB' in part (a) along the XZ direction.

[0024] In this embodiment, the gate oxide layer 204 can be formed by thermal oxidation. Thermal oxidation is an oxidation process in which an oxidizing agent such as oxygen or water vapor reacts with the exposed substrate 20 at high temperature to generate silicon dioxide, forming an oxide layer, which serves as the gate oxide layer 204. The gate oxide layer 204 formed by thermal oxidation has high repeatability and stability, which is beneficial for improving the reliability of semiconductor devices.

[0025] Please refer to step S13. Figure 2E A sacrificial layer 205 is formed on the sidewalls and bottom of each trench 202, the sacrificial layer 205 at least covering the second isolation structure 203 and the gate oxide layer 204. Figure 2E Part (a) is a top view along the Z direction, and part (b) is a cross-sectional view along line BB' in part (a) along the XZ direction.

[0026] In this embodiment, the sacrificial layer 205 also covers the surface of the active region 200, and the material of the sacrificial layer 205 is silicon nitride; in other embodiments of the present invention, the material of the sacrificial layer 205 may also be selected from silicon oxide polycrystalline silicon; the material of the sacrificial layer 205 may be the same as or different from the first isolation structure 201 and the second isolation structure 203.

[0027] Please refer to step S14. Figure 2F Each of the trenches 202 is filled with insulating material and planarized to form a third insulating structure 206. In this embodiment, the trenches 202 are filled with insulating material and planarized so that the upper surface of the third insulating structure 206 is flush with the upper surface of the sacrificial layer 205. Figure 2F Part (a) is a top view along the Z direction, and part (b) is a cross-sectional view along line BB' in part (a) along the XZ direction.

[0028] In this embodiment, the material of the third isolation structure 206 is silicon oxide; in other embodiments of the present invention, the material of the third isolation structure 206 may also be selected from silicon nitride or polycrystalline silicon; however, the material of the third isolation structure 206 is different from the material of the sacrificial layer 205 so that the sacrificial layer 205 can be processed separately in the future.

[0029] Please refer to step S15. Figure 3 The process involves removing a portion of the sacrificial layer 205, depositing conductive material, and processing it to form two mutually insulated word lines 2091 and 2092 within each trench 202. The retained sacrificial layer 205 serves as a fourth isolation structure 208, such that the two word lines 2091 and 2092 have a first distance H1 from the second isolation structure 203 and a second distance H2 from the substrate surface. Figure 3 Part (a) is a top view along the Z direction, part (b) is a cross-sectional view along the XZ direction with the section BB' in part (a) as the cross section, and part (c) is a cross-sectional view along the XZ direction with the section CC' in part (a) as the cross section.

[0030] Please see Figure 2G In one embodiment, step S15 further includes: removing the sacrificial layer 205 to a first distance H1 from the second isolation structure 203 to form word line gaps 207 in each of the trenches 202, with the remaining sacrificial layer 205 serving as a fourth isolation structure 208. Figure 2G Part (a) is a top view along the Z direction, and part (b) is a cross-sectional view along line BB' in part (a) along the XZ direction.

[0031] The presence of the fourth isolation structure 208 ensures that the character lines deposited in the subsequent trench 202 can be completely separated, avoiding the problem in the prior art where the bottoms of the two character lines are not completely separated. In this embodiment, the fourth isolation structure 208 is a U-shaped structure; in other embodiments of the present invention, the fourth isolation structure 208 may also be a straight structure or an irregular shape.

[0032] In some embodiments of the present invention, the materials of the first isolation structure, the second isolation structure, the third isolation structure and the sacrificial layer are selected from silicon nitride, silicon oxide or polycrystalline silicon, wherein the material of the third isolation structure is different from the material of the sacrificial layer.

[0033] Please see Figure 2H Following the above embodiment, step S15 further includes: depositing conductive material 220 within the word line gap 207. Optionally, the conductive material 220 may fill the word line gap 207 and cover the surface of the active region 200. Figure 2H Part (a) is a top view along the Z direction, and part (b) is a cross-sectional view along line BB' in part (a) along the XZ direction.

[0034] Please see Figure 2I Following the above embodiment, step S15 further includes: removing a portion of the conductive material 220 to form an annular letter line 209 having a second distance H2 from the substrate surface within each of the trenches 202. Figure 2I Part (a) is a top view along the Z direction, and part (b) is a cross-sectional view along line BB' in part (a) along the XZ direction.

[0035] Please see Figure 2J Following the above embodiment, step S15 further includes: filling the word line gaps 207 with insulating material 210 and flattening it. Wherein, Figure 2J Part (a) is a top view along the Z direction, and part (b) is a cross-sectional view along line BB' in part (a) along the XZ direction.

[0036] Then the ring-shaped word line 209 is disconnected, forming two mutually insulated word lines 2091 and 2092, as follows. Figure 3 As shown.

[0037] Please see Figure 2KThe marking of disconnecting the annular letter line 209 to form two mutually insulated letter lines 2091 and 2092 further includes: etching at both opposite ends of the annular letter line 209 until the corresponding sacrificial layer 205 is partially or completely removed, thereby disconnecting the annular letter line 209 and forming two mutually insulated letter lines 2091 and 2092, wherein etching is performed on at least one side of each end; and filling the etched area with insulating material 221 and planarizing it. Figure 2K Part (a) is a top view along the Z direction, and part (b) is a cross-sectional view along the XZ direction with the section taken along line CC' in part (a).

[0038] In this embodiment, each circular character line 209 is broken at two points, 212A and 212B.

[0039] The above Figures 2G to 2K The illustration shows a method of first forming a ring-shaped character line 209, and then breaking it to form two mutually insulated character lines 2091 and 2092. In an embodiment of the present invention, a method of first forming a broken structure and then forming two mutually insulated character lines 2091 and 2092 can also be used.

[0040] Please see Figure 6A In one embodiment, step S15 further includes: partially etching the two opposite ends of the sacrificial layer 205 to form grooves; wherein etching is performed on at least one side of each end. That is, the sacrificial layer 205 is broken, forming two separate sacrificial layers at each groove. Figure 6A Part (a) is a top view along the Z direction, and part (b) is a cross-sectional view along the XZ direction with the CC' line in part (a) as the cross-section. In this embodiment, the sacrificial layer 205 is broken at two locations, grooves 601A and 601B.

[0041] Please continue reading. Figure 6B Following the above embodiment, step S15 further includes: filling the groove with insulating material 602 and flattening it. Wherein, Figure 6B Part (a) is a top view along the Z direction, and part (b) is a cross-sectional view along the XZ direction with the CC' line in part (a) as the cross-section.

[0042] Please continue reading. Figure 6C Following the above embodiment, step S15 further includes: removing a portion of the sacrificial layer 205 to form a word line gap 207 in each of the trenches. The portion of the retained sacrificial layer 205, excluding the area below the trench, serves as a fourth isolation structure 208; the sacrificial layer 205 retained below the trench serves as a sixth isolation structure 603, used to isolate two word lines subsequently formed in the same trench. Figure 6CPart (a) is a top view along the Z direction, part (b) is a cross-sectional view along the XZ direction with the section BB' in part (a) as the cross section, and part (c) is a cross-sectional view along the XZ direction with the section CC' in part (a) as the cross section.

[0043] Please see Figure 6D Following the above embodiment, step S15 further includes: depositing conductive material 220 within the word line gap 207. The conductive material 220 is interrupted at the sixth isolation structure 603 and at the grooves 601A and 601B. Figure 6D Part (a) is a top view along the Z direction, part (b) is a cross-sectional view along the XZ direction with the section BB' in part (a) as the cross section, and part (c) is a cross-sectional view along the XZ direction with the section CC' in part (a) as the cross section.

[0044] Please see Figure 6E Following the above embodiment, step S15 further includes: removing a portion of the conductive material 220 to form two mutually insulated word lines 2091 and 2092 in each trench, having a second distance H2 from the substrate surface; wherein the two word lines 2091 and 2092 are mutually insulated through the sacrificial layer 205 (i.e., the sixth isolation structure 603) retained below the trench; and filling and planarizing the area where a portion of the conductive material 220 has been removed with isolation material. Figure 6E Part (a) is a top view along the Z direction, part (b) is a cross-sectional view along the XZ direction with the section BB' in part (a) as the cross section, and part (c) is a cross-sectional view along the XZ direction with the section CC' in part (a) as the cross section.

[0045] In this embodiment, the two character lines 2091 and 2092 are broken at two locations, groove 601A and 601B.

[0046] Furthermore, in some embodiments, please refer to Figure 4 Multiple fifth isolation structures 400 are formed within the active region 200. Each fifth isolation structure 400 is disposed between two adjacent second isolation structures 203, and the extending direction of the fifth isolation structure 400 is the same as the extending direction of the second isolation structure 203. The fifth isolation structure 400 and the first isolation structure 201 together serve to separate and isolate.

[0047] The material of the fifth isolation structure is selected from silicon nitride, silicon oxide or polycrystalline silicon, or the fifth isolation structure is air-isolated.

[0048] The active region 200 also forms an active / drain S / D and a gate, thereby forming a plurality of vertical gate transistors 401 arranged in an array within the active region 200.

[0049] After completing the steps of disconnecting the ring-shaped word line and forming two mutually insulated word lines using any of the above methods, the method further includes:

[0050] Please see Figure 5A Flip the substrate 20 and thin the substrate 20 on the side of the substrate 20 close to the second isolation structure 203 until the second isolation structure 203 is exposed.

[0051] Please see Figure 5B Bit lines 500 are formed on the thinned surface of the substrate 20, and the bit lines 500 cover the second isolation structure 203.

[0052] The present invention also provides a vertical gate transistor structure, please refer to [reference needed]. Figure 4 As shown, the vertical gate transistor structure is fabricated using any of the methods described above, including:

[0053] The substrate 20 includes a plurality of vertical gate transistors 401 arranged in an array. The plurality of vertical gate transistors 401 are spaced apart by a plurality of first isolation structures 201 in the Y direction, spaced apart by a plurality of fifth isolation structures 400 in the X direction, and connected to a second isolation structure 203 in the Z direction.

[0054] Multiple character lines 2091 and 2092 are provided. The character lines 209 extend along the Y direction and are arranged parallel to each other in the X direction. A third isolation structure 206 is provided between adjacent character lines 2091 and 2092, and adjacent character lines 2091 and 2092 are isolated from the corresponding second isolation structure 203 by a fourth isolation structure 208 and are at a second distance H2 from the substrate surface. Adjacent character lines 2091 and 2092 are at a first distance H1 from the second isolation structure 203 (i.e., the height of the fourth isolation structure 208). The X, Y, and Z directions are all perpendicular to each other.

[0055] The above technical solution ensures complete separation of word lines in the vertical gate transistor structure by embedding an isolation structure between adjacent word lines, thereby improving isolation reliability.

[0056] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a vertical gate transistor structure, characterized in that, include: A substrate is provided, the substrate comprising a plurality of active regions arranged in an array, the plurality of active regions being spaced apart by a plurality of first isolation structures in the Y direction and by a plurality of trenches in the X direction, the X direction being perpendicular to the Y direction; A second isolation structure is formed at the bottom of each of the trenches; A gate oxide layer is formed on the sidewall of each of the trenches, and the gate oxide layer is in contact with the second isolation structure; A sacrificial layer is formed on the sidewall and bottom of each trench, the sacrificial layer at least covering the second isolation structure and the gate oxide layer; Each of the trenches is filled with insulating material and flattened to form a third insulating structure; The sacrificial layer is partially removed, conductive material is deposited and processed to form two mutually insulated word lines in each trench, wherein the retained sacrificial layer serves as a fourth isolation structure such that the two word lines are at a first distance from the second isolation structure and at a second distance from the substrate surface.

2. The method according to claim 1, characterized in that, The step of forming two mutually insulated word lines in each of the trenches further includes: The sacrificial layer is removed to a distance of the first distance from the second isolation structure to form word line gaps in each of the trenches, and the remaining sacrificial layer serves as the fourth isolation structure. Deposit conductive material within the gaps between the word lines; A portion of the conductive material is removed to form an annular letter line having the second distance from the substrate surface within each of the trenches; Fill the gaps between the letter lines with insulating material and flatten them; and Disconnect the ring-shaped word line to form two mutually insulated word lines.

3. The method according to claim 2, characterized in that, The step of disconnecting the ring-shaped word line to form two mutually insulated word lines includes: Etching is performed at both opposite ends of the annular word line until the corresponding sacrificial layer is partially or completely removed, thereby breaking the annular word line and forming two mutually insulated word lines, wherein etching is performed on at least one side of each end; and The etched area is filled with isolation material and planarized.

4. The method according to claim 2, characterized in that, The fourth isolation structure is a U-shaped structure.

5. The method according to claim 1, characterized in that, The step of forming two mutually insulated word lines in each of the trenches further includes: Partial etching is performed at both opposite ends of the sacrificial layer to form grooves, wherein etching is performed on at least one side of each end; Fill the groove with insulating material and flatten it; A portion of the sacrificial layer is removed to form word line gaps in each of the trenches, wherein the portion of the remaining sacrificial layer other than that below the groove serves as a fourth isolation structure; Deposit conductive material within the gaps between the word lines; Removing a portion of the conductive material to form two mutually insulated word lines having a second distance from the substrate surface within each of the trenches, wherein the two word lines are insulated from each other by the sacrificial layer retained below the trench; and The area where part of the conductive material has been removed is filled with insulating material and planarized.

6. The method according to claim 1, characterized in that, The materials of the first isolation structure, the second isolation structure, the third isolation structure, and the sacrificial layer are selected from silicon nitride, silicon oxide, or polycrystalline silicon, wherein the material of the sacrificial layer is different from the material of the third isolation structure.

7. The method according to claim 1, characterized in that, Following the step of forming two mutually insulated word lines within each of the trenches, the method further includes: The substrate is flipped over, and the substrate is thinned on the side closest to the second isolation structure to expose the second isolation structure; Bit lines are formed on the thinned substrate surface, and the bit lines cover the second isolation structure.

8. The method according to claim 1, characterized in that, The method further includes: Multiple fifth isolation structures are formed within the active region. Each fifth isolation structure is disposed between two adjacent second isolation structures, and the extension direction of the fifth isolation structure is the same as the extension direction of the second isolation structure.

9. The method according to claim 8, characterized in that, The material of the fifth isolation structure is selected from silicon nitride, silicon oxide or polycrystalline silicon, or the fifth isolation structure is air-isolated.

10. A vertical gate transistor structure, formed by the method according to any one of claims 1 to 9, characterized in that, include: The substrate includes a plurality of vertical gate transistors arranged in an array, the plurality of vertical gate transistors being spaced apart by a plurality of first isolation structures in the Y direction, spaced apart by a plurality of fifth isolation structures in the X direction, and connected to a corresponding second isolation structure in the Z direction; Multiple character lines extend along the Y direction and are arranged in parallel in the X direction. There is a third isolation structure between adjacent character lines, and adjacent character lines are isolated from the corresponding second isolation structure by a fourth isolation structure and are at a second distance from the substrate surface. The X direction, Y direction, and Z direction are all perpendicular to each other.

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