Array substrate repair method, device, electronic equipment and storage medium

Abstract

Embodiments of the present application provide a kind of array substrate maintenance method, device, electronic equipment and storage medium, the method comprises: the array substrate to be detected is detected, and detection result is obtained;In the detection result indicates the case where the preset switch short circuit in the GOA drive circuit of the array substrate, determine the target capacitance in the GOA drive circuit;The target capacitance is the capacitance for being used to pull up output end opening voltage by capacitance bootstrap;The target capacitance is welded, to make two pole plate of the target capacitance direct conduction.The MOS tube switch in the array substrate GOA region is electrostatically broken down by the above-mentioned method, and the maintenance of array substrate is realized.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to methods, apparatus, electronic devices and storage media for repairing array substrates. Background Technology

[0002] ESD (Electrostatic Discharge) is almost unavoidable in electrical devices. ESD generates a high voltage in a short time, which can cause short circuits in devices such as MOSFETs (MOSFETs) and diodes, resulting in damage. However, there is no effective repair method in the relevant technology for ESD breakdown of MOSFET switches in the GOA (Gate Driver On Array) area of ​​the array substrate. Summary of the Invention

[0003] The purpose of this application is to provide a method, apparatus, electronic device, and storage medium for repairing an array substrate, thereby enabling the repair of the array substrate in the event of electrostatic breakdown of the MOS transistor switches in the GOA region. The specific technical solution is as follows:

[0004] In a first aspect, embodiments of this application provide a method for repairing an array substrate, the method comprising:

[0005] The array substrate to be tested is inspected, and the test results are obtained.

[0006] If the detection result indicates that a preset switch in the GOA driving circuit of the array substrate is short-circuited, the target capacitor in the GOA driving circuit is determined; the target capacitor is a capacitor used to raise the output terminal turn-on voltage through capacitor bootstrapping.

[0007] The target capacitor is welded so that the two plates of the target capacitor are directly connected.

[0008] In one possible implementation, the detection of the array substrate to be detected to obtain the detection result includes at least one of the following processes:

[0009] The array substrate to be tested is illuminated for detection to obtain the pixel area display detection result of the array substrate;

[0010] The Gate line voltage signal of the preset pixel row output by the GOA driving circuit of the array substrate to be tested is detected to obtain the Gate line voltage detection result.

[0011] The voltage of the PU point of the preset pixel row output by the GOA driving circuit of the array substrate to be tested is detected to obtain the PU point voltage detection result. The PU point is a voltage pull-up point.

[0012] The detection results include at least one of the following: the pixel area display detection results, the Gate line voltage detection results, and the PU point voltage detection results.

[0013] In one possible implementation, the detection result is determined to indicate a short circuit in a preset switch in the GOA driving circuit of the array substrate when one or more of the following conditions are met:

[0014] The pixel area display shows that the first row of pixels, the second row of pixels, and the third row of pixels in the detection results are dark pixels;

[0015] In the Gate line voltage detection results, the Gate line voltage signals of the first to third pixel rows belong to the first preset low voltage range;

[0016] In the voltage detection results of the PU points, the voltage of the PU points in the first to third pixel rows belongs to the second preset low voltage range.

[0017] In one possible implementation, the preset switch includes at least one of a charging control switch and a reset control switch in the GOA driving circuit. The charging control switch is used to control the charging of the target capacitor, and the reset control switch is used to control the reset.

[0018] In one possible implementation, welding the target capacitor to make the two plates of the target capacitor directly conductive includes:

[0019] The target capacitor is welded using a laser with a welding area not less than a preset welding area, so that the two plates of the target capacitor are directly connected.

[0020] In one possible implementation, the preset welding area is 3 micrometers × 3 micrometers.

[0021] Secondly, embodiments of this application provide a repair apparatus for an array substrate, the apparatus comprising:

[0022] The acquisition module is used to detect the array substrate to be tested and obtain the detection results;

[0023] The determination module is used to determine the target capacitor in the GOA driving circuit when the detection result indicates that a preset switch in the GOA driving circuit of the array substrate is short-circuited; the target capacitor is a capacitor used to raise the output terminal turn-on voltage through capacitor bootstrapping.

[0024] A welding module is used to weld the target capacitor so that the two plates of the target capacitor are directly connected.

[0025] In one possible implementation, the acquisition module includes at least one of the following processes:

[0026] The array substrate to be tested is illuminated for detection to obtain the pixel area display detection result of the array substrate;

[0027] The Gate line voltage signal of the preset pixel row output by the GOA driving circuit of the array substrate to be tested is detected to obtain the Gate line voltage detection result.

[0028] The voltage of the PU point of the preset pixel row output by the GOA driving circuit of the array substrate to be tested is detected to obtain the PU point voltage detection result. The PU point is a voltage pull-up point.

[0029] The detection results include at least one of the following: the pixel area display detection results, the Gate line voltage detection results, and the PU point voltage detection results.

[0030] In one possible implementation, the detection result is determined to indicate a short circuit in a preset switch in the GOA driving circuit of the array substrate when one or more of the following conditions are met:

[0031] The pixel area display shows that the first row of pixels, the second row of pixels, and the third row of pixels in the detection results are dark pixels;

[0032] In the Gate line voltage detection results, the Gate line voltage signals of the first to third pixel rows belong to the first preset low voltage range;

[0033] In the voltage detection results of the PU points, the voltage of the PU points in the first to third pixel rows belongs to the second preset low voltage range.

[0034] In one possible implementation, the preset switch includes at least one of a charging control switch and a reset control switch in the GOA driving circuit. The charging control switch is used to control the charging of the target capacitor, and the reset control switch is used to control the reset.

[0035] In one possible implementation, the welding module includes:

[0036] The welding submodule is used to weld the target capacitor using a laser with a welding area not less than a preset welding area, so that the two plates of the target capacitor are directly connected.

[0037] In one possible implementation, the preset welding area is 3 micrometers × 3 micrometers.

[0038] Thirdly, embodiments of this application provide an electronic device, including: a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus;

[0039] Memory, used to store computer programs;

[0040] When a processor executes a program stored in memory, it implements any of the steps described in the first aspect above.

[0041] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements any of the steps described in the first aspect above.

[0042] Beneficial effects of the embodiments in this application:

[0043] This application provides a method, apparatus, electronic device, and storage medium for repairing an array substrate. The method includes: inspecting the array substrate to be tested and obtaining a test result; if the test result indicates that a preset switch in the GOA driving circuit of the array substrate is short-circuited, determining a target capacitor in the GOA driving circuit; the target capacitor is a capacitor used to raise the output terminal turn-on voltage through capacitor bootstrapping; and soldering the target capacitor so that the two plates of the target capacitor are directly conductive. By soldering the target capacitor, the two plates of the target capacitor are directly conductive, reducing the load, thereby enabling the repair of the array substrate in cases where the MOS transistor switch in the GOA region of the array substrate is short-circuited due to electrostatic breakdown.

[0044] Of course, implementing any product or method of this application does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these accompanying drawings.

[0046] Figure 1 This is a schematic diagram of the GOA driving circuit for a 65-inch array substrate in related technologies;

[0047] Figure 2 This is a schematic diagram of a PCB (printed circuit board) for a 65-inch array substrate in related technologies;

[0048] Figure 3 This is a schematic flowchart of an array substrate repair method provided in an embodiment of this application;

[0049] Figure 4 for Figure 1 The diagram shows the PU point and OUTPUT signal detection in the GOA driving circuit.

[0050] Figure 5 for Figure 1 A schematic diagram showing the location of the solder capacitor C in the array substrate corresponding to the GOA driving circuit shown.

[0051] Figure 6 This is a schematic diagram of the equivalent circuit of capacitor C before and after welding in the GOA driving circuit;

[0052] Figure 7 for Figure 1 A schematic diagram of via anomalies in the array substrate corresponding to the GOA driving circuit shown.

[0053] Figure 8 This is another schematic diagram of the GOA driving circuit in related technologies;

[0054] Figure 9 This is another schematic diagram of a GOA driving circuit in related technologies;

[0055] Figure 10 This is a schematic diagram of the array substrate repair device provided in an embodiment of this application;

[0056] Figure 11 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0057] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art based on this application are within the scope of protection of this application.

[0058] Currently, the common repair method for GCS defects in array substrates is laser welding of via locations. However, this method can only repair GCS defects caused by via abnormalities. For ESD caused by MOSFET switches in the GOA region, there is no effective repair method. Electrostatic discharge (ESD) in the GOA region of the array substrate manifests as a GCS (gate line and common electrode line defect) penetrating the edge of the LCD panel at Y=1 / 2 / 3 (Y represents the Y-axis of the pixel coordinate system, Y=n represents the nth row pixel). There is no effective repair method for this. Furthermore, in the module manufacturing process, laser equipment can only see the back side of the array substrate circuitry under a microscope. For ESD defects occurring during actual production, the defect can only be found on the front side of the array substrate, making it impossible to effectively pinpoint the actual ESD location on the back side. Therefore, it is impossible to accurately cut the short circuit location using laser welding.

[0059] In one example, such as Figure 1 and Figure 2 As shown, Figure 1 This is a schematic diagram of the GOA driving circuit for a 65-inch array substrate in related technologies, which includes: INPUT (data input terminal) signal, PU point (gate drive circuit pull-up point), STV (first scan enable terminal) signal, VGL (gate voltage terminal, low voltage terminal) signal, OUTPUT (gate output terminal) signal, and capacitor C between PU point and OUTPUT. Figure 2 The diagram shows a PCB (Printed Circuit Board) layout for a 65-inch array substrate in the relevant technology, including the GOA (Gateway Aspect) driving circuit area and the clock signal area. The INPUT signal for the first three Gate rows is directly provided by the STV (Signal TV). When an ESD event occurs in the preset switches (M1 and / or M2) in the first three Gate rows of the array substrate's GOA area, the vias at the STV input terminals will burn out. There will be no INPUT signal input for the first three Gate rows, the PU (Power Input Point) cannot open normally, and it will be continuously pulled low by VGL. The G-out on the opposite side will participate in the cascading on this side, and the LCD product can only be judged as low-grade, resulting in a decrease in yield (pass rate).

[0060] To enable the repair of array substrates, embodiments of this application provide a method, apparatus, electronic device, and storage medium for repairing array substrates.

[0061] First, a method for repairing an array substrate provided in the embodiments of this application will be described in detail, see [link to relevant documentation]. Figure 3 This includes the following steps:

[0062] Step S301: The array substrate to be tested is tested to obtain the test results.

[0063] The purpose of testing the array substrate is to determine whether ESD has occurred in the switches in the GOA region of the array substrate. The detection method here can be an ESD detection method in related technologies, such as voltage detection or lighting detection. There can be one or more detection methods, and the corresponding detection results can also be one or more results. Combining multiple detection methods can improve the accuracy of the final result.

[0064] Step S302: If the detection result indicates that the preset switch in the GOA driving circuit of the array substrate is short-circuited, determine the target capacitor in the GOA driving circuit; the target capacitor is a capacitor used to boost the output terminal turn-on voltage through capacitor bootstrapping.

[0065] The target capacitor is used to boost the output turn-on voltage via capacitor bootstrapping. A bootstrapping capacitor utilizes the property that the voltage across a capacitor cannot change abruptly. When a certain voltage is maintained across the capacitor, increasing the voltage at the negative terminal while maintaining the original voltage difference at the positive terminal is equivalent to the voltage at the negative terminal being "lifted up," thus boosting the output turn-on voltage (the voltage at point PU).

[0066] The preset switch can be a switch for controlling the charging and discharging of the target capacitor. In one possible implementation, the preset switch includes at least one of a charging control switch and a reset control switch in the GOA driving circuit, wherein the charging control switch is used to control the charging of the target capacitor, and the reset control switch is used to control the reset.

[0067] In one example, in the GOA drive circuit such as Figure 1 As shown, the preset switch can be Figure 1 In M31 and / or M32, the target capacitor can be Figure 1 The capacitor C in the circuit. In one example, in the GOA drive circuit such as... Figure 8 As shown, the preset switch can be Figure 8 In M7 and / or M8, the target capacitor can be Figure 8 Capacitor C2 in the circuit. In one example, in the GOA drive circuit such as... Figure 9 As shown, the preset switch can be Figure 9 In T1 and / or T2, the target capacitor can be Figure 9 The capacitor C1 in the middle.

[0068] Step S303: Weld the target capacitor so that the two plates of the target capacitor are directly connected.

[0069] In one example, in the GOA drive circuit such as Figure 1 As shown, the target capacitor can be Figure 1The capacitor C in the diagram is soldered so that its two plates are directly conductive. At this point, the conductive capacitor C can be considered as a wire. Figure 6 This is a schematic diagram of the equivalent circuit before and after the capacitor C in the GOA driving circuit is soldered. When the capacitor C is soldered and connected, the OUTPUTVmax (maximum voltage value) is basically normal, and the pixels in this row are normal.

[0070] In this embodiment, by welding the target capacitor, the two plates of the target capacitor are directly connected, reducing the load. This allows for the repair of the array substrate in the case of electrostatic breakdown and short circuit of the MOS transistor switch in the GOA region of the array substrate.

[0071] In one possible implementation, the detection of the array substrate to be detected to obtain the detection result includes at least one of the following processes:

[0072] The array substrate to be tested is illuminated for detection to obtain the pixel area display detection result of the array substrate;

[0073] The Gate line voltage signal of the preset pixel row output by the GOA driving circuit of the array substrate to be tested is detected to obtain the Gate line voltage detection result.

[0074] The voltage of the PU point of the preset pixel row output by the GOA driving circuit of the array substrate to be tested is detected to obtain the PU point voltage detection result. The PU point is the voltage pull-up point.

[0075] The detection results include at least one of the following: the pixel area display detection results, the Gate line voltage detection results, and the PU point voltage detection results.

[0076] In one example, such as Figure 1 As shown, the OUTPUT signal is the gate output signal. By detecting the OUTPUT signal, the gate line voltage detection result is obtained. The PU point is the pull-up point (voltage pull-up point) of the gate drive circuit. By detecting the voltage at the PU point, the PU point voltage detection result is obtained.

[0077] In the embodiments of this application, the substrate of the array to be tested is tested using different detection methods to obtain the detection results.

[0078] In one possible implementation, the detection result is determined to indicate a short circuit in a preset switch in the GOA driving circuit of the array substrate when one or more of the following conditions are met:

[0079] The pixel area display shows that the first row of pixels, the second row of pixels, and the third row of pixels in the detection results are dark pixels;

[0080] In the Gate line voltage detection results, the Gate line voltage signals of the first to third pixel rows belong to the first preset low voltage range;

[0081] In the voltage detection results of the PU points, the voltage of the PU points in the first to third pixel rows belongs to the second preset low voltage range.

[0082] Dark pixels indicate abnormalities in the first, second, and third rows of pixels on the array substrate.

[0083] The settings of the first and second preset low-voltage ranges are related to the driving voltage of the GOA driving circuit itself in the array substrate. In one example, in the GOA driving circuit... Figure 1 As shown, the first preset low-voltage range can be set to 19V to 19.2V. In one example, in the GOA drive circuit as shown... Figure 1 As shown, the second preset low voltage range can be set to -6.72V to -4.8V.

[0084] In one example, in the GOA drive circuit such as Figure 1 As shown, the array substrate corresponding to the GOA driving circuit is tested. It should be noted that the array substrate includes multiple such... Figure 1 The GOA driving circuit shown is as follows. Figure 4 As shown, five different sets of test results are presented, and experimental verification was conducted before and after repair. Specifically: Figure 4 The experiment was divided into three main groups: the first group was a blank group on the 2160-Gate side; the second group was an experimental group on the 2158-Gate and 2159-Gate sides; and the third group was a control group on the 2155-Gate and 2157-Gate sides. Pixels 2158-2160 (the first to third rows) showed abnormal detection results, indicating a short circuit between M31 and M32 in the GOA driver circuit corresponding to 2158-2160. See [link to documentation] for the labeling of 2155 and 2157-2160. Figure 5 , Figure 5 for Figure 1 The diagram shows the location of the soldered capacitor C in the array substrate corresponding to the GOA driving circuit. The soldering positions are marked with circles.

[0085] 2160 was set as the blank group where capacitor C was not soldered through, 2158 and 2159 were set as the experimental group where capacitor C was soldered through, and 2155 and 2157 were set as the control group where there was no short circuit.

[0086] In the 2160 blank group, before soldering capacitor C in 2158 / 2159 (before repair), the voltage at the PU point is -6.72V, and the voltage at the OUTPUT terminal of the Gate line voltage signal output is 19V; after soldering capacitor C in 2158 / 2159 (after repair), the voltage at the PU point is -5.04V, and the voltage at the OUTPUT terminal of the Gate line voltage signal output is 19.2V.

[0087] In the 2159 experimental group, before soldering capacitor C in 2159 (before repair), the voltage at the PU point was -5.28V, and the voltage at the OUTPUT terminal of the Gate line voltage signal output was 19.2V; after soldering capacitor C in 2159 (after repair), the voltage at the PU point was 30.96V, and the voltage at the OUTPUT terminal of the Gate line voltage signal output was 31V.

[0088] In the 2158 experimental group, before soldering capacitor C in 2158 (before repair), the voltage at the PU point was -4.8V, and the voltage at the OUTPUT terminal of the Gate line voltage signal output was 19V; after soldering capacitor C in 2158 (after repair), the voltage at the PU point was 30.96V, and the voltage at the OUTPUT terminal of the Gate line voltage signal output was 30.8V.

[0089] In the 2157 control group, before soldering capacitor C in 2158 / 2159 (before repair), the voltage at the PU point was 31.44V, and the voltage at the Gate line voltage signal output terminal OUTPUT was 31.2V; after soldering capacitor C in 2158 / 2159 (after repair), the voltage at the PU point was 31.92V, and the voltage at the Gate line voltage signal output terminal OUTPUT was 31.4V.

[0090] In the 2155 control group, before soldering capacitor C in 2158 / 2159 (before repair), the voltage at the PU point was 32.88V, and the voltage at the Gate line voltage signal output terminal OUTPUT was 31.4V; after soldering capacitor C in 2158 / 2159 (after repair), the voltage at the PU point was 43.92V, and the voltage at the Gate line voltage signal output terminal OUTPUT was 31.6V.

[0091] Figure 4 It should be noted that the INPUT on the 2157Gate side is cascaded from the 2160Gate side, so the voltage at the PU point is only 31.92V (which does not reach the normal value of 43.92V).

[0092] After repairing the 2159 Gate side (by soldering capacitor C), which showed abnormal test results, the voltage at the PU point was 30.96V, and the voltage at the OUTPUT output terminal of the Gate line voltage signal was 31V. Similarly, after repairing the 2158 Gate side (also showing abnormal test results) (by soldering capacitor C), the voltage at the PU point was 30.96V, and the voltage at the OUTPUT output terminal of the Gate line voltage signal was 30.8V. Compared to the control group (the 2155 and 2157 Gate sides, which had no short circuits), the voltage values ​​at the PU point and the OUTPUT signal were essentially the same. This demonstrates that soldering capacitor C effectively repaired the array substrate with short circuits.

[0093] In this embodiment of the application, different abnormal conditions are used to determine the detection results, indicating that the preset switch in the GOA driving circuit of the array substrate is short-circuited, thereby repairing the array substrate.

[0094] In one possible implementation, welding the target capacitor to make the two plates of the target capacitor directly conductive includes:

[0095] The target capacitor is welded using a laser with a welding area not less than a preset welding area, so that the two plates of the target capacitor are directly connected.

[0096] The preset welding area is set based on the area between the two plates of the target capacitor, and it is necessary to ensure that the preset welding area is not less than the area between the two plates of the target capacitor.

[0097] In one possible implementation, the preset welding area is 3 micrometers × 3 micrometers.

[0098] Generally, the area between the two plates of the target capacitor is less than 3 micrometers × 3 micrometers. Welding is performed using a laser with a welding area of ​​not less than 3 micrometers × 3 micrometers to ensure that the laser can melt and break through the capacitor.

[0099] In this embodiment, a laser with a welding area of ​​not less than 3 micrometers × 3 micrometers is used to weld the target capacitor to ensure that the laser can melt and break through the capacitor.

[0100] In one example, in the GOA drive circuit such as Figure 1 As shown, during actual testing, the INPUT voltage supplied by STV is 0, there is no input voltage at the PU point, and the short circuit of M2 causes the PU point to be directly connected to VGL (-8V), and the voltage at the PU point is pulled down to a negative voltage. Due to the influence of the capacitor C load, the OUTPUT is only 19V, and the phenomenon that occurs is a GCS that runs through the upper edge (Y=1 / 2 / 3) of the LCD panel.

[0101] Taking the above-mentioned 2158 experimental group as an example, after welding capacitor C with a laser with a welding area of ​​not less than 3 micrometers × 3 micrometers, the PU point is directly connected to the OUTPUT. The OUTPUT is raised to 30.8V (slightly lower than 31.6V in the above-mentioned 2155 control group). The voltage of the PU point can only be raised to 30.96V due to the limited single-sided driving on the other side.

[0102] Figure 6 This is a schematic diagram of the equivalent circuit before and after welding capacitor C in the GOA driving circuit. When capacitor C is laser welded through, OUTPUT Vmax (maximum voltage value) is basically normal, and the pixels in this row are normal. It can be seen that the pixels are normal after repair. The actual repair is simple and does not require additional repair auxiliary lines. It is only necessary to find the capacitor C in the first three pixel rows and weld 2 points in each row. It is not easy to cause new defects, which can improve the grade of LCD products and increase the pass rate.

[0103] Figure 7 for Figure 1 The diagram shown illustrates the via anomaly in the array substrate corresponding to the GOA driving circuit. Figure 2 and Figure 5 It can be seen that the via at the INPUT on the 2158Gate side to the 2160Gate side is abnormal, while the via at the INPUT on the 2157Gate side is OK (normal). The actual measured INPUT voltage supplied by STV is 0. It is determined that the MOSFET M1 has excessive ESD current, which has caused the via to break down.

[0104] In this embodiment, the repair is performed on the MOS transistor switch in the GOA area of ​​the 65-inch array substrate that is short-circuited due to electrostatic breakdown. The actual repair is simple, highly practical, and unlikely to cause new defects, which can improve the grade of LCD products and increase the pass rate.

[0105] The following is a detailed description of the GOA driving circuit involved in this application:

[0106] First of all, Figure 1 The GOA driving circuit shown is described below. This GOA driving circuit includes the 30th MOSFET M30, the 31st MOSFET M31, the 32nd MOSFET M32, the 33rd MOSFET M33, the 34th MOSFET M34, the 35th MOSFET M35, the 36th MOSFET M36, the 37th MOSFET M37, the 38th MOSFET M38, the 39th MOSFET M39, the 40th MOSFET M40, the 41st MOSFET M41, the 42nd MOSFET M42, the 43rd MOSFET M43, the 44th MOSFET M44, the 45th MOSFET M45, the 46th MOSFET M46, and capacitor C.

[0107] Figure 1 The device connection relationships of the GOA driving circuit shown are as follows:

[0108] The gate of the 30th MOSFET M30 is connected to the first scan-on terminal (STV terminal), the first terminal of the 30th MOSFET M30 is connected to the pull-up point (PU point) of the gate drive circuit, and the second terminal of the 30th MOSFET M30 is connected to the gate voltage terminal (VGL terminal).

[0109] The gate of the 31st MOSFET M31 is connected to the data input terminal (INPUT terminal), the first terminal of the 31st MOSFET M31 is connected to the data input terminal (INPUT terminal), and the second terminal of the 31st MOSFET M31 is connected to the pull-up point (PU point) of the gate drive circuit.

[0110] The gate of the 32nd MOSFET M32 is connected to the pull-up reset terminal (RST_PU terminal), the first terminal of the 32nd MOSFET M32 is connected to the pull-up terminal (PU terminal) of the gate drive circuit, and the second terminal of the 32nd MOSFET M32 is connected to the gate voltage terminal (VGL terminal).

[0111] The gate of the 45th MOSFET M45 is connected to the pull-up point (PU point) of the gate drive circuit. The first terminal of the 45th MOSFET M45 is connected to the clock signal terminal (CLK terminal), and the second terminal of the 45th MOSFET M45 is connected to the gate output terminal (OUTPUT terminal).

[0112] The gate of the 33rd MOS transistor M33 is connected to the pull-down point (PD1 point) of the first gate drive circuit, the first end of the 33rd MOS transistor M33 is connected to the first end of the 32nd MOS transistor, and the second end of the 33rd MOS transistor M33 is connected to the gate low voltage end (VGL end).

[0113] The gate of the 34th MOS transistor M34 is connected to the pull-down point (PD2 point) of the second gate drive circuit. The first end of the 34th MOS transistor M34 is connected to the first end of the 33rd MOS transistor. The second end of the 34th MOS transistor M34 is connected to the gate low voltage end (VGL end).

[0114] The gate of the 35th MOSFET M35 is connected to the positive voltage terminal of the first drive voltage (VDDO terminal), the first terminal of the 35th MOSFET M35 is connected to the positive voltage terminal of the first drive voltage (VDDO terminal), and the second terminal of the 35th MOSFET M35 is connected to the pull-down point of the third gate drive circuit (PD_CN1 point).

[0115] The gate of the thirty-sixth MOS transistor M36 is connected to the pull-up point (PU point) of the gate drive circuit. The first end of the thirty-sixth MOS transistor M36 is connected to the second end of the thirty-fifth transistor M35. The second end of the thirty-sixth MOS transistor M36 is connected to the low voltage terminal (VGL terminal) of the gate.

[0116] The gate of the 37th MOS transistor M37 is connected to the second terminal of the 35th transistor M35, the first terminal of the 37th MOS transistor M37 is connected to the positive voltage terminal of the first driving voltage (VDDO terminal), and the second terminal of the 37th MOS transistor M37 is connected to the pull-down point of the first gate driving circuit (PD1 point).

[0117] The gate of the thirty-eighth MOS transistor M38 is connected to the pull-up point (PU point) of the gate drive circuit. The first terminal of the thirty-eighth MOS transistor M38 is connected to the second terminal of the thirty-seventh transistor M37. The second terminal of the thirty-eighth MOS transistor M38 is connected to the low voltage terminal (VGL terminal) of the gate.

[0118] The gate of the 39th MOSFET M39 is connected to the positive voltage terminal of the second drive voltage (VDDE terminal), the first terminal of the 39th MOSFET M39 is connected to the positive voltage terminal of the second drive voltage (VDDE terminal), and the second terminal of the 39th MOSFET M39 is connected to the pull-down point of the fourth gate drive circuit (PD_CN2 point).

[0119] The gate of the 40th MOS transistor M40 is connected to the pull-up point (PU point) of the gate drive circuit. The first end of the 40th MOS transistor M40 is connected to the second end of the 39th transistor M39. The second end of the 40th MOS transistor M40 is connected to the low voltage terminal (VGL terminal) of the gate.

[0120] The gate of the forty-first MOS transistor M41 is connected to the second terminal of the thirty-ninth transistor M39, the first terminal of the forty-first MOS transistor M41 is connected to the positive voltage terminal of the second driving voltage (VDDE terminal), and the second terminal of the forty-first MOS transistor M41 is connected to the pull-down point of the second gate driving circuit (PD2 point).

[0121] The gate of the forty-second MOS transistor M42 is connected to the pull-up point (PU point) of the gate drive circuit. The first end of the forty-second MOS transistor M42 is connected to the second end of the forty-first transistor M41. The second end of the forty-second MOS transistor M42 is connected to the low voltage terminal (VGL terminal) of the gate.

[0122] The gate of the 46th MOSFET M46 is connected to the reset voltage terminal (RESET), the first terminal of the 46th MOSFET M46 is connected to the gate output terminal (OUTPUT terminal), and the second terminal of the 46th MOSFET M46 is connected to the gate low voltage terminal (VGL terminal).

[0123] The gate of the forty-fourth MOS transistor M44 is connected to the pull-down point (PD1 point) of the first gate drive circuit, the first end of the forty-fourth MOS transistor M44 is connected to the first end of the forty-sixth MOS transistor M46, and the second end of the forty-fourth MOS transistor M44 is connected to the gate low voltage end (VGL end).

[0124] The gate of the forty-third MOS transistor M43 is connected to the pull-down point (PD2 point) of the second gate drive circuit, the first end of the forty-third MOS transistor M43 is connected to the first end of the forty-fourth MOS transistor M44, and the second end of the forty-third MOS transistor M43 is connected to the gate low voltage end (VGL end).

[0125] The first end of capacitor C is connected to the pull-up point (PU point) of the gate drive circuit, and the second end of capacitor C is connected to the gate output point (OUTPUT point).

[0126] In one example, each MOSFET can be replaced with a TFT (Thin Film Transistor). In another example, for any MOSFET in this embodiment, the MOSFET can be an N-type MOSFET or a P-type MOSFET, whichever can be selected according to the actual situation; the first terminal of the MOSFET is the source or drain, and the second terminal of the MOSFET is the drain or source corresponding to the first terminal.

[0127] Secondly, for Figure 8 The GOA driving circuit shown will be introduced below. Figure 8 The GOA driving circuit shown includes: first transistor M1, second transistor M2, third transistor M3, fourth transistor M4, fifth transistor M5, sixth transistor M6, seventh transistor M7, eighth transistor M8, ninth transistor M9, tenth transistor M10, eleventh transistor M11, twelfth transistor M12, thirteenth transistor M13, fourteenth transistor M14, fifteenth transistor M15, sixteenth transistor M16, seventeenth transistor M17, eighteenth transistor M18, nineteenth transistor M19, twentieth transistor M20, twenty-first transistor M21, twenty-second transistor M22, twenty-third transistor M23, twenty-fourth transistor M24, twenty-fifth transistor M25, twenty-sixth transistor M26, first capacitor C1, and second capacitor C2.

[0128] Figure 8 The connection relationships of the components in the GOA driving circuit shown are as follows:

[0129] The gate of the seventh transistor M7 is connected to the data input terminal (Input terminal), the first terminal of the seventh transistor M7 is connected to the data input terminal (Input terminal), and the second terminal of the seventh transistor M7 is connected to the pull-up point (PU point) of the gate drive circuit.

[0130] The gate of the eighth transistor M8 is connected to the reset voltage terminal (Reset terminal), the first terminal of the eighth transistor M8 is connected to the pull-up point (PU point) of the gate drive circuit, and the second terminal of the eighth transistor M8 is connected to the gate voltage terminal (LVGL terminal).

[0131] The gate of the ninth transistor M9 is connected to the pull-up point (PU point) of the gate drive circuit, the first terminal of the ninth transistor M9 is connected to the clock signal terminal (CLK terminal), and the second terminal of the ninth transistor M9 is connected to the gate output terminal (Gate Output terminal).

[0132] The gate of the tenth transistor M10 is connected to the pull-down point (PD1 point) of the first gate drive circuit, the first terminal of the tenth transistor M10 is connected to the gate output terminal, and the second terminal of the tenth transistor M10 is connected to the gate low voltage terminal (VGL terminal).

[0133] The gate of the twentieth transistor M20 is connected to the pull-down point (PD2 point) of the second gate drive circuit. The first terminal of the twentieth transistor M20 is connected to the gate output terminal (Gate Output terminal), and the second terminal of the twentieth transistor M20 is connected to the gate low voltage terminal (VGL terminal).

[0134] The gate of the eleventh transistor M11 is connected to the second terminal of the fourteenth transistor M14. The first terminal of the eleventh transistor M11 is connected to the positive voltage terminal of the first driving voltage (VDDO terminal). The second terminal of the eleventh transistor M11 is connected to the pull-down point of the first gate driving circuit (PD1 point).

[0135] The gate of the twenty-first transistor M21 is connected to the second terminal of the twenty-fourth transistor M24. The first terminal of the twenty-first transistor M21 is connected to the positive voltage terminal of the second driving voltage (VDDE terminal). The second terminal of the twenty-first transistor M21 is connected to the pull-down point of the second gate driving circuit (PD2 point).

[0136] The gate of the twelfth transistor M12 is connected to the pull-up point (PU point) of the gate drive circuit, the first terminal of the twelfth transistor M12 is connected to the pull-down point (PD1 point) of the first gate drive circuit, and the second terminal of the twelfth transistor M12 is connected to the gate voltage terminal (LVGL terminal).

[0137] The gate of the 22nd transistor M22 is connected to the pull-up point (PU point) of the gate drive circuit, the first terminal of the 22nd transistor M22 is connected to the pull-down point (PD2 point) of the second gate drive circuit, and the second terminal of the 22nd transistor M22 is connected to the gate voltage terminal (LVGL terminal).

[0138] The gate of the thirteenth transistor M13 is connected to the pull-down point (PD1 point) of the first gate drive circuit, the first terminal of the thirteenth transistor M13 is connected to the pull-up point (PU point) of the gate drive circuit, and the second terminal of the thirteenth transistor M13 is connected to the gate voltage terminal (LVGL terminal).

[0139] The gate of the 23rd transistor M23 is connected to the pull-down point (PD2 point) of the second gate drive circuit, the first terminal of the 23rd transistor M23 is connected to the pull-up point (PU point) of the gate drive circuit, and the second terminal of the 23rd transistor M23 is connected to the gate voltage terminal (LVGL terminal).

[0140] The gate of the fourteenth transistor M14 is connected to the positive voltage terminal of the first driving voltage (VDDO terminal), the first terminal of the fourteenth transistor M14 is connected to the positive voltage terminal of the first driving voltage (VDDO terminal), and the second terminal of the fourteenth transistor M14 is connected to the first terminal of the fifteenth transistor M15.

[0141] The gate of the twenty-fourth transistor M24 is connected to the positive voltage terminal (VDDE terminal) of the second driving voltage, the first terminal of the twenty-fourth transistor M24 is connected to the positive voltage terminal (VDDE terminal) of the second driving voltage, and the second terminal of the twenty-fourth transistor M24 is connected to the first terminal of the twenty-fifth transistor M25.

[0142] The gate of the fifteenth transistor M15 is connected to the pull-up point (PU point) of the gate drive circuit, and the second terminal of the fifteenth transistor M15 is connected to the gate voltage terminal (LVGL terminal).

[0143] The gate of the 25th transistor M25 is connected to the pull-up point (PU point) of the gate drive circuit, and the second terminal of the 25th transistor M25 is connected to the gate voltage terminal (LVGL terminal).

[0144] The gate of the sixteenth transistor M16 is connected to the pull-down point (PD1 point) of the first gate drive circuit. The first terminal of the sixteenth transistor M16 is connected to the second terminal of the seventeenth transistor M17. The second terminal of the sixteenth transistor M16 is connected to the gate voltage terminal (LVGL terminal).

[0145] The gate of the twenty-sixth transistor M26 is connected to the pull-down point (PD2 point) of the second gate drive circuit. The first terminal of the twenty-sixth transistor M26 is connected to the second terminal of the seventeenth transistor M17. The second terminal of the twenty-sixth transistor M26 is connected to the gate voltage terminal (LVGL terminal).

[0146] The gate of the seventeenth transistor M17 is connected to the pull-up point (PU point) of the gate drive circuit, and the first terminal of the seventeenth transistor M17 is connected to the clock signal terminal (CLK terminal).

[0147] The first terminal of the second capacitor C2 is connected to the gate of the ninth transistor M9, and the second terminal of the second capacitor C2 is connected to the gate output terminal.

[0148] The gate of the fifth transistor is connected to the pull-down point (PD1 point) of the first gate drive circuit, the first terminal of the fifth transistor is connected to the first terminal of the first capacitor C1, and the second terminal of the fifth transistor is connected to the gate voltage terminal.

[0149] The gate of the eighteenth transistor is connected to the pull-down point (PD2 point) of the second gate drive circuit, the first terminal of the eighteenth transistor is connected to the first terminal of the first capacitor C1, and the second terminal of the eighteenth transistor is connected to the gate voltage terminal.

[0150] The gate of the sixth transistor is connected to the pull-down point (PD1 point) of the first gate drive circuit, the first terminal of the sixth transistor is connected to the second terminal of the first capacitor C1, and the second terminal of the sixth transistor is connected to the gate voltage terminal.

[0151] The gate of the nineteenth transistor is connected to the pull-down point (PD2 point) of the second gate drive circuit, the first terminal of the nineteenth transistor is connected to the second terminal of the first capacitor C1, and the second terminal of the nineteenth transistor is connected to the gate voltage terminal.

[0152] The gate of the first transistor M1 is connected to the pull-up point (PU point) of the gate driving circuit, the first end of the first transistor M1 is connected to the pull-up point (PU point) of the gate driving circuit, and the second end of the first transistor M1 is connected to the gate of the second transistor M2, the first end of the first capacitor C1, and the first end of the fourth transistor M4, respectively.

[0153] The first terminal of the second transistor M2 is connected to the touch voltage terminal (Touch_EN terminal), and the second terminal of the second transistor M2 is connected to the second terminal of the first capacitor C1, the gate of the third transistor M3, and the first terminal of the third transistor M3, respectively.

[0154] The second terminal of the third transistor M3 is connected to the pull-up point (PU point) of the gate drive circuit;

[0155] The gate of the fourth transistor M4 is connected to the reset voltage terminal (Reset terminal), and the second terminal of the fourth transistor M4 is connected to the gate voltage terminal.

[0156] In one example, each transistor can be a TFT (Thin Film Transistor). In another example, for any transistor in this embodiment, the transistor can be an N-type MOS transistor or a P-type MOS transistor, whichever can be selected according to the actual situation; the first terminal of the transistor is the source or drain, and the second terminal of the transistor is the drain or source corresponding to the first terminal.

[0157] Then, to Figure 9 The GOA driving circuit shown is described below. The GOA driving circuit includes: first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, twelfth transistor T12, thirteenth transistor T13, and first capacitor C1.

[0158] Figure 9 The device connection relationships of the GOA driving circuit shown are as follows:

[0159] The gate of the first transistor T1 is connected to the first scan enable terminal (STV terminal), the first terminal of the first transistor T1 is connected to the first scan control terminal (CN terminal), and the second terminal of the first transistor T1 is connected to the pull-up point of the gate drive circuit (PU_CN point).

[0160] The gate of the second transistor T2 is connected to the second scan enable terminal (RST terminal), the first terminal of the second transistor T2 is connected to the pull-up point of the gate drive circuit (PU_CN point), and the second terminal of the second transistor T2 is connected to the second scan control terminal (CNB terminal).

[0161] The gate of the third transistor T3 is connected to the pull-up point (PU_CN point) of the gate drive circuit, the first terminal of the third transistor T3 is connected to the first clock signal terminal (CLK1 terminal), and the second terminal of the third transistor T3 is connected to the output terminal (OutPut terminal).

[0162] The gate of the fourth transistor T4 is connected to the pull-down point (PD point) of the gate drive circuit, the first terminal of the fourth transistor T4 is connected to the output terminal (OutPut terminal), and the second terminal of the fourth transistor T4 is connected to the DC low-level terminal (VGL_G terminal).

[0163] The gate of the fifth transistor T5 is connected to the pull-down point (PD point) of the gate drive circuit, the first terminal of the fifth transistor T5 is connected to the pull-up point (PU_CN point) of the gate drive circuit, and the second terminal of the fifth transistor T5 is connected to the DC low-level terminal (VGL_G terminal).

[0164] The gate of the sixth transistor T6 is connected to the pull-up point (PU_CN point) of the gate drive circuit, the first terminal of the sixth transistor T6 is connected to the pull-down point (PD point) of the gate drive circuit, and the second terminal of the sixth transistor T6 is connected to the DC low-level terminal (VGL_G terminal).

[0165] The gate of the seventh transistor T7 is connected to the first scan control terminal (CN terminal), the first terminal of the seventh transistor T7 is connected to the second clock signal terminal (CLK2 terminal), and the second terminal of the seventh transistor T7 is connected to the gate of the thirteenth transistor T13.

[0166] The gate of the twelfth transistor T12 is connected to the second scan control terminal (CNB terminal), the first terminal of the twelfth transistor T12 is connected to the gate of the thirteenth transistor T13, and the second terminal of the twelfth transistor T12 is connected to the third clock signal terminal (CLK3 terminal).

[0167] The first terminal of the thirteenth transistor T13 is connected to the DC high-level terminal (VGH_G terminal), and the second terminal of the thirteenth transistor T13 is connected to the pull-down point (PD point) of the gate drive circuit.

[0168] The first terminal of the first capacitor C1 is connected to the gate of the third transistor T3, and the second terminal of the first capacitor C1 is connected to the output terminal (OUTPUT terminal).

[0169] In one example, each transistor can be a TFT (Thin Film Transistor). In another example, for any transistor in this embodiment, the transistor can be an N-type MOS transistor or a P-type MOS transistor, whichever can be selected according to the actual situation; the first terminal of the transistor is the source or drain, and the second terminal of the transistor is the drain or source corresponding to the first terminal.

[0170] Based on the same concept, embodiments of this application also provide a repair device for an array substrate, see [link to relevant documentation]. Figure 10 The device includes:

[0171] The acquisition module 1010 is used to detect the array substrate to be tested and obtain the detection results;

[0172] The determination module 1020 is used to determine the target capacitor in the GOA driving circuit when the detection result indicates that a preset switch in the GOA driving circuit of the array substrate is short-circuited; the target capacitor is a capacitor used to raise the output terminal turn-on voltage through capacitor bootstrapping.

[0173] The welding module 1030 is used to weld the target capacitor so that the two plates of the target capacitor are directly connected.

[0174] In this embodiment, by welding the target capacitor, the two plates of the target capacitor are directly connected, reducing the load. This allows for the repair of the array substrate in the case of electrostatic breakdown and short circuit of the MOS transistor switch in the GOA region of the array substrate.

[0175] In one possible implementation, the acquisition module 1010 includes at least one of the following processes:

[0176] The array substrate to be tested is illuminated for detection to obtain the pixel area display detection result of the array substrate;

[0177] The Gate line voltage signal of the preset pixel row output by the GOA driving circuit of the array substrate to be tested is detected to obtain the Gate line voltage detection result.

[0178] The voltage of the PU point of the preset pixel row output by the GOA driving circuit of the array substrate to be tested is detected to obtain the PU point voltage detection result. The PU point is a voltage pull-up point.

[0179] The detection results include at least one of the following: the pixel area display detection results, the Gate line voltage detection results, and the PU point voltage detection results.

[0180] In the embodiments of this application, the substrate of the array to be tested is tested using different detection methods to obtain the detection results.

[0181] In one possible implementation, the detection result is determined to indicate a short circuit in a preset switch in the GOA driving circuit of the array substrate when one or more of the following conditions are met:

[0182] The pixel area display shows that the first row of pixels, the second row of pixels, and the third row of pixels in the detection results are dark pixels;

[0183] In the Gate line voltage detection results, the Gate line voltage signals of the first to third pixel rows belong to the first preset low voltage range;

[0184] In the voltage detection results of the PU points, the voltage of the PU points in the first to third pixel rows belongs to the second preset low voltage range.

[0185] In this embodiment of the application, different abnormal conditions are used to determine the detection results, indicating that the preset switch in the GOA driving circuit of the array substrate is short-circuited, thereby repairing the array substrate.

[0186] In one possible implementation, the preset switch includes at least one of a charging control switch and a reset control switch in the GOA driving circuit. The charging control switch is used to control the charging of the target capacitor, and the reset control switch is used to control the reset.

[0187] In one possible implementation, the welding module 1030 includes:

[0188] The welding submodule 1110 is used to weld the target capacitor using a laser with a welding area not less than a preset welding area, so that the two plates of the target capacitor are directly connected.

[0189] In one possible implementation, the preset welding area is 3 micrometers × 3 micrometers.

[0190] In this embodiment, a laser with a welding area of ​​not less than 3 micrometers × 3 micrometers is used to weld the target capacitor to ensure that the laser can melt and break through the capacitor.

[0191] This application also provides an electronic device, such as... Figure 11 As shown, it includes a processor 1101, a communication interface 1102, a memory 1103, and a communication bus 1104. The processor 1101, communication interface 1102, and memory 1103 communicate with each other via the communication bus 1104.

[0192] Memory 1103 is used to store computer programs;

[0193] When processor 1101 executes the program stored in memory 1103, it performs the following steps:

[0194] The array substrate to be tested is inspected, and the test results are obtained.

[0195] If the detection result indicates that a preset switch in the GOA driving circuit of the array substrate is short-circuited, the target capacitor in the GOA driving circuit is determined; the target capacitor is a capacitor used to raise the output terminal turn-on voltage through capacitor bootstrapping.

[0196] The target capacitor is welded so that the two plates of the target capacitor are directly connected.

[0197] The communication bus mentioned in the above electronic devices can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not mean that there is only one bus or one type of bus.

[0198] The communication interface is used for communication between the aforementioned electronic devices and other devices.

[0199] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0200] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0201] In another embodiment provided in this application, a computer-readable storage medium is also provided, which stores a computer program that, when executed by a processor, implements the steps of any of the above-described array substrate repair methods.

[0202] In another embodiment provided in this application, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to perform any of the array substrate repair methods described above.

[0203] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk (SSD)).

[0204] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0205] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, the embodiments for apparatus, electronic devices, and storage media are basically similar to the method embodiments, so the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0206] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A method for repairing an array substrate, characterized in that, The method includes: The array substrate to be tested is inspected, and the test results are obtained. If the detection result indicates that a preset switch in the GOA driving circuit of the array substrate is short-circuited, the target capacitor in the GOA driving circuit is determined; the target capacitor is a capacitor used to raise the output terminal turn-on voltage through capacitor bootstrapping. The target capacitor is welded so that the two plates of the target capacitor are directly connected.

2. The method according to claim 1, characterized in that, The process of testing the array substrate to be tested and obtaining the test result includes at least one of the following steps: The array substrate to be tested is illuminated for detection to obtain the pixel area display detection result of the array substrate; The Gate line voltage signal of the preset pixel row output by the GOA driving circuit of the array substrate to be tested is detected to obtain the Gate line voltage detection result. The voltage of the PU point of the preset pixel row output by the GOA driving circuit of the array substrate to be tested is detected to obtain the PU point voltage detection result. The PU point is the voltage pull-up point. The detection results include at least one of the pixel area display detection results, the Gate line voltage detection results, and the PU point voltage detection results.

3. The method according to claim 2, characterized in that, The detection result is determined to indicate a short circuit in a preset switch in the GOA driving circuit of the array substrate when one or more of the following conditions are met: The pixel area display shows that the first row of pixels, the second row of pixels, and the third row of pixels in the detection results are dark pixels; In the Gate line voltage detection results, the Gate line voltage signals of the first to third pixel rows belong to the first preset low voltage range; In the voltage detection results of the PU points, the voltage of the PU points in the first to third rows of pixels belongs to the second preset low voltage range.

4. The method according to claim 1, characterized in that, The preset switch includes at least one of a charging control switch and a reset control switch in the GOA driving circuit. The charging control switch is used to control the charging of the target capacitor, and the reset control switch is used to control the reset.

5. The method according to claim 1, characterized in that, The welding of the target capacitor to make the two plates of the target capacitor directly conductive includes: The target capacitor is welded using a laser with a welding area not less than a preset welding area, so that the two plates of the target capacitor are directly connected.

6. The method according to claim 5, characterized in that, The preset welding area is 3 micrometers × 3 micrometers.

7. A repair device for an array substrate, characterized in that, The device includes: The acquisition module is used to detect the array substrate to be tested and obtain the detection results; The determination module is used to determine the target capacitor in the GOA driving circuit when the detection result indicates that a preset switch in the GOA driving circuit of the array substrate is short-circuited; the target capacitor is a capacitor used to raise the output terminal turn-on voltage through capacitor bootstrapping. A welding module is used to weld the target capacitor so that the two plates of the target capacitor are directly connected.

8. The apparatus according to claim 7, characterized in that, The acquisition module includes at least one of the following processes: The array substrate to be tested is illuminated for detection to obtain the pixel area display detection result of the array substrate; The Gate line voltage signal of the preset pixel row output by the GOA driving circuit of the array substrate to be tested is detected to obtain the Gate line voltage detection result. The voltage of the PU point of the preset pixel row output by the GOA driving circuit of the array substrate to be tested is detected to obtain the PU point voltage detection result. The PU point is the voltage pull-up point. The detection results include at least one of the pixel area display detection results, the Gate line voltage detection results, and the PU point voltage detection results.

9. The apparatus according to claim 8, characterized in that, The detection result is determined to indicate a short circuit in a preset switch in the GOA driving circuit of the array substrate when one or more of the following conditions are met: The pixel area display shows that the first row of pixels, the second row of pixels, and the third row of pixels in the detection results are dark pixels; In the Gate line voltage detection results, the Gate line voltage signals of the first to third pixel rows belong to the first preset low voltage range; In the voltage detection results of the PU points, the voltage of the PU points in the first to third rows of pixels belongs to the second preset low voltage range.

10. The apparatus according to claim 7, characterized in that, The preset switch includes at least one of a charging control switch and a reset control switch in the GOA driving circuit. The charging control switch is used to control the charging of the target capacitor, and the reset control switch is used to control the reset.

11. The apparatus according to claim 7, characterized in that, The welding module includes: The welding submodule is used to weld the target capacitor using a laser with a welding area not less than a preset welding area, so that the two plates of the target capacitor are directly connected.

12. The apparatus according to claim 11, characterized in that, The preset welding area is 3 micrometers × 3 micrometers.

13. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, when executing a program stored in memory, implements the steps of the method described in any one of claims 1-6.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the method described in any one of claims 1-6.

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