A multi-level LDO output voltage circuit with overshoot suppression and adaptive compensation

Abstract

The present invention discloses a multi-level LDO output voltage circuit with overshoot suppression and adaptive compensation, comprising: different reference voltage generation modules, an error amplifier, an intermediate stage, a power transistor, an anti-overshoot module, an adaptive Miller compensation module, and a feedback network. The circuit requires no external off-chip capacitors or added on-chip capacitance, thereby reducing circuit area. The intermediate stage connects the error amplifier and the power output stage, increasing gain and driving capability to improve response speed. The anti-overshoot module provides a bias voltage to the intermediate stage while detecting current, reducing static power consumption and suppressing overshoot at the circuit's output voltage. The adaptive Miller compensation module provides adaptive compensation, improving circuit stability.

Description

Technical Field

[0001] The present invention relates to the technical field of low-noise low-dropout voltage regulator circuits, and in particular to a multi-LDO output voltage circuit with overshoot suppression and adaptive compensation. Background Art

[0002] As technology advances, more and more functions need to be integrated into chips. Low power consumption and miniaturization are inevitable trends in system-on-chip (SoC) technology for advanced electronic devices. To extend battery life and conserve energy, circuit functions within the chip are only used when needed and remain disabled the rest of the time. Furthermore, SoC solutions require fully integrated, low-power power management integrated circuits (PMICs).

[0003] Today's PMICs typically combine a high-efficiency switching DC-DC converter with a low-noise low-dropout regulator (LDO) to generate multiple clean power supplies on-chip. Modern system modules, including high-performance analog-to-digital converters (ADCs) and voltage-controlled oscillators (VCOs), require extremely clean and high-performance voltage sources due to stringent latency requirements and other key performance requirements. Therefore, LDOs used in embedded systems must offer fast response, low noise, minimal overshoot voltage, low power consumption, a wide range of output voltages, and a compact footprint.

[0004] Traditional LDO circuit structure Figure 1 As shown in the figure, it mainly includes the error amplifier (EA), power tube (MP), feedback circuit network and corresponding load. Some of the LDO chips have large external capacitors, which are usually in the uF level; or some have large internal capacitors for system stability when there is no external external capacitor. With the development of chip miniaturization, these traditional LDO structures have long been unable to meet the requirements. However, when there is no large external or internal capacitor, higher requirements are placed on the LDO response speed and overshoot protection performance. In general, the traditional LDO circuit has the following shortcomings: (1) large area due to the large number of capacitors and power tubes added on the chip; (2) high power consumption; (3) slow response speed and weak load capacity; (4) large overshoot voltage, which can easily cause abnormal function of the powered module; (5) poor stability, because when the load current changes, the previous compensation circuit cannot follow its changes. Summary of the Invention

[0005] The purpose of the present invention is to provide a variety of LDO output voltage circuits with overshoot suppression and adaptive compensation, which has the advantages of low power consumption, fast response speed, strong load capacity, small area, and the ability to achieve overshoot suppression and adaptive compensation.

[0006] The purpose of the present invention is achieved through the following technical solutions:

[0007] A circuit for multiple LDO output voltages with overshoot suppression and adaptive compensation includes: different reference voltage generation modules, an error amplifier, an intermediate stage, a power tube, an anti-overshoot module, an adaptive Miller compensation module, and a feedback network; wherein:

[0008] The reference voltage input terminal of the error amplifier is connected to the different reference voltage generation module, and the feedback input terminal of the error amplifier is connected to the first port of the feedback network; the output terminal of the error amplifier is connected to the gate of the power tube via the intermediate stage, and the output terminal of the error amplifier is amplified by the intermediate stage; the power supply terminal of the error amplifier and the source terminal of the power tube are both connected to VDD, and the drain terminal of the power tube and the second port of the feedback network are connected to the output terminal of the circuit;

[0009] The anti-overshoot module is connected to the intermediate stage and the output end of the circuit; the anti-overshoot module provides a bias voltage for the intermediate stage, and the magnitude of the bias voltage is adjusted by the anti-overshoot module according to the magnitude of the voltage at the output end of the circuit. At the same time, the anti-overshoot module suppresses overshoot of the voltage at the output end of the circuit;

[0010] One end of the adaptive Miller compensation module is connected to the output end of the error amplifier, and the other end is connected to the output end of the circuit, and adaptive compensation is performed according to the current of the output end of the error amplifier and the current of the output end of the circuit.

[0011] It can be seen from the technical solution provided by the present invention that: (1) there is no external off-chip capacitor and no added on-chip capacitor, so the circuit area can be reduced; (2) the error amplifier and the power output stage are connected by an intermediate stage, which can increase the gain and enhance the driving capability to improve the response speed; (3) the anti-overshoot module provides a bias voltage to the intermediate stage while detecting the current, thereby reducing the static power consumption and being able to suppress the overshoot of the output voltage of the circuit; (5) the adaptive Miller compensation module performs adaptive compensation, which can improve the circuit stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0013] Figure 1 A schematic diagram of a traditional LDO circuit structure is provided for the background technology of the present invention;

[0014] Figure 2A schematic diagram of a multiple LDO output voltage circuit with overshoot suppression and adaptive compensation provided by an embodiment of the present invention;

[0015] Figure 3 A schematic diagram of the structure of the intermediate stage provided by an embodiment of the present invention;

[0016] Figure 4 A schematic structural diagram of a current detection module provided in an embodiment of the present invention;

[0017] Figure 5 A schematic structural diagram of an overshoot suppression module provided in an embodiment of the present invention;

[0018] Figure 6 A schematic structural diagram of an adaptive Miller compensation module provided in an embodiment of the present invention;

[0019] Figure 7 This is a schematic diagram of the structures of different reference voltage generation modules provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0020] The following is a clear and complete description of the technical solutions in the embodiments of the present invention, in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0021] First, the following terms may be used in this article:

[0022] The terms "include," "comprises," "contains," "has," or other similar expressions should be interpreted as non-exclusive. For example, "including certain technical features (such as raw materials, components, ingredients, carriers, dosage forms, materials, dimensions, parts, components, mechanisms, devices, steps, procedures, methods, reaction conditions, processing conditions, parameters, algorithms, signals, data, products, or manufactured articles, etc.) should be interpreted as including not only the technical features explicitly listed, but also other technical features known in the art that are not explicitly listed.

[0023] The term "consisting of" excludes any technical features not explicitly listed. If used in a claim, this term renders the claim closed, excluding any technical features other than those explicitly listed, except for conventional impurities associated with them. If this term appears only in a clause of a claim, it limits only the elements explicitly listed in that clause; elements listed in other clauses are not excluded from the claim as a whole.

[0024] Unless otherwise specified or limited, the terms "mounted," "connected," "connect," and "fixed" should be interpreted broadly. For example, they can refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediary; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this document based on specific circumstances.

[0025] The following describes in detail a multi-LDO output voltage circuit with overshoot suppression and adaptive compensation provided by the present invention. Any information not described in detail in the embodiments of the present invention is prior art known to those skilled in the art. Where specific conditions are not specified in the embodiments of the present invention, the procedures were performed in accordance with conventional conditions in the art or the conditions recommended by the manufacturer. Reagents or instruments used in the embodiments of the present invention, where the manufacturer is not specified, are all commercially available conventional products.

[0026] The embodiment of the present invention provides a variety of LDO output voltage circuits with overshoot suppression and adaptive compensation, such as Figure 2 As shown in the figure, it mainly includes: different reference voltage generation modules, error amplifier (EA), intermediate stage (Buffer), power tube (Mp), anti-overshoot module (composed of current detection module and overshoot suppression module), adaptive Miller compensation module, and feedback network (composed of resistors R0 and R1); in addition, it also includes some loads. Since there is no external capacitor and no internal capacitor, Figure 2 CL in the figure mainly refers to the parasitic capacitance of the powered circuit, RL and Iload are the load resistance and load current respectively. In general:

[0027] The reference voltage input of the error amplifier is connected to the different reference voltage generation module, and the feedback input of the error amplifier is connected to the first port of the feedback network; the output of the error amplifier is connected to the gate of the power tube via the intermediate stage, and the output of the error amplifier is amplified by the intermediate stage; the power supply of the error amplifier and the source of the power tube are both connected to VDD, and the drain of the power tube and the second port of the feedback network are connected to the output of the circuit (i.e., the output of the entire circuit);

[0028] The anti-overshoot module is connected to the intermediate stage and the output end of the circuit; the anti-overshoot module provides a bias voltage for the intermediate stage, and the magnitude of the bias voltage is adjusted by the anti-overshoot module according to the magnitude of the voltage at the output end of the circuit. At the same time, the anti-overshoot module suppresses overshoot of the voltage at the output end of the circuit;

[0029] One end of the adaptive Miller compensation module is connected to the output end of the error amplifier, and the other end is connected to the output end of the circuit, and adaptive compensation is performed according to the current of the output end of the error amplifier and the current of the output end of the circuit.

[0030] In order to more clearly demonstrate the technical solutions and technical effects provided by the present invention, the structures and related principles of each part of the circuit are introduced below.

[0031] 1. Intermediate level (Buffer).

[0032] In the embodiment of the present invention, a buffer is connected as an intermediate stage between the error amplifier and the power output stage, which can increase the gain and enhance the driving capability to improve the system response speed. Figure 3 As shown in FIG. 1 , a structural example of an intermediate stage is provided, using five MOS transistors and one NPN transistor. The five MOS transistors include: a PMOS transistor PM0, a first PMOS transistor PM1, an NMOS transistor NM0, a first NMOS transistor NM1, and a second NMOS transistor NM2. The NPN transistor is denoted as QN0. Vo1 is the output voltage of the error amplifier, Vg is the gate voltage output by the intermediate stage to the power transistor, the gate voltage Vn1 of the first NMOS transistor NM1 is the bias voltage provided by the current detection module, the diode of the NMOS transistor NM0 (i.e., its gate and drain) are connected as a resistor, and the transistor NM2 serves as a reset.

[0033] The main structure of the intermediate stage is as follows: the PMOS transistor PM0 and the source of the first PMOS transistor PM1 are connected to VDD (the power supply terminal); the gates of the PMOS transistor PM0, the first PMOS transistor PM1, and the second NMOS transistor NM2 are connected, and are also connected to the drain of the PMOS transistor PM0, the drain of the second NMOS transistor NM2, and the collector of the NPN transistor QN0; the drain of the first PMOS transistor PM1, the source of the second NMOS transistor NM2, and the drain of the first NMOS transistor NM1 are connected together as the output of the intermediate stage; the base of the NPN transistor QN0 serves as the input of the intermediate stage and is connected to the output of the error amplifier; the emitter of the NPN transistor QN0 is connected to the gate and drain of the NMOS transistor NM0; the sources of the NMOS transistor NM0 and the first NMOS transistor NM1 are grounded; the first NMOS transistor NM1 serves as the current source of the intermediate stage, and its gate is connected to the output of the current detection module in the anti-overshoot module.

[0034] 2. Anti-overshoot module.

[0035] Due to the change in the current at the circuit output, the LDO feedback loop system cannot react quickly, causing the voltage at the circuit output to overshoot, ultimately affecting the stability of the powered module (load circuit).

[0036] In order to quickly sense the change of current at the output end of the circuit while maintaining a simple structure and low power consumption, a current detection module is added to the circuit. Similarly, to solve the problem of voltage overshoot at the output end of the circuit, an overshoot suppression module is added. The two together constitute the anti-overshoot module. The current detection module and the overshoot suppression module are introduced separately below.

[0037] 1. Current detection module.

[0038] One end of the current detection module is connected to the current source of the intermediate stage, and the other end is connected to the output end of the circuit, and is used to provide a bias voltage for the intermediate stage. Figure 4 An example of a current detection module is provided, which mainly includes two MOS transistors, namely a second PMOS transistor PM2 and a third NMOS transistor NM3. The structure is as follows: the source of the second PMOS transistor PM2 is connected to VDD, the gate is connected to the output end (Vout) of the circuit, and the drain is connected to the drain of the third NMOS transistor NM3; the drain of the third NMOS transistor NM3 is connected to the gate and to the gate of the intermediate current source, and the source is grounded.

[0039] The current detection module's output voltage Vn1 is used to provide a bias voltage for the first NMOS transistor NM1 in the intermediate stage. When the current at the circuit's output suddenly increases, the gate voltage of the second PMOS transistor PM2 decreases, increasing the leakage current of the second MOS transistor PM2. The diode of the second NMOS transistor NM2 (i.e., its gate and drain) is connected as a resistor, increasing the voltage Vn1 and the current of the first NMOS transistor NM1 in the intermediate stage. Ultimately, this results in a rapid discharge at the intermediate stage output (Vg), improving the response speed of the intermediate stage output. The current detection module not only detects current but also provides a bias voltage to the intermediate stage, thereby reducing static power consumption.

[0040] The current detection module and the intermediate stage can effectively prevent the output current of the circuit from suddenly changing from small to large, which would cause the output voltage of the circuit to undershoot, and control the lowest undershoot voltage point within a certain range. At the same time, when the circuit is working normally, the current detection module only acts as a bias circuit to provide bias voltage to the NM1 tube in the intermediate stage, which will not increase additional static power consumption.

[0041] 2. Overshoot suppression module.

[0042] In order to solve the problem that when the current at the output end of the circuit suddenly changes from a large current to a small current, the intermediate stage output end cannot quickly follow the change of the output end of the circuit, and there is a certain difference in the reaction time between the two output ends. During this difference period, the output current is always supplied to the load capacitor, causing the output end voltage of the circuit to overshoot. In the embodiment of the present invention, an overshoot suppression module is designed to solve the above problem. One end of the overshoot suppression module is connected to the output end of the intermediate stage, and the other end is connected to the output end of the circuit to achieve overshoot suppression.

[0043] like Figure 5 As shown in FIG, an example of an overshoot suppression module is provided, which mainly includes: 6 MOS transistors, 1 PNP transistor and 1 NPN transistor. The 6 MOS transistors include: a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a fourth PMOS transistor NM4, a fifth PMOS transistor NM5, and a sixth PMOS transistor NM6. The PNP transistor is denoted as QP0, and the NPN transistor is the first NPN transistor QN1. The main structure is as follows:

[0044] The sources of the third PMOS transistor PM3, the fourth PMOS transistor PM4, and the fifth PMOS transistor PM5 are connected to VDD; the gate and drain of the third PMOS transistor PM3 are connected, and are also connected to the base of the first NPN transistor QN1 and the emitter of the PNP transistor QP0; the gate and drain of the fourth PMOS transistor PM4 are connected, and are also connected to the gate of the fifth PMOS transistor PM5 and the drain of the sixth NMOS transistor NM6; the drain of the fifth PMOS transistor PM5 is connected to the output end of the intermediate stage; the gate of the sixth NMOS transistor NM6 is connected to the collector of the first NPN transistor QN1. The output end of the circuit is connected to the source of the sixth NMOS transistor NM6 as the first external bias voltage input end, and the first external bias voltage Vn2 is inputted thereto; the base of the PNP transistor QP0 is connected to the output end of the intermediate stage, the collector is connected to the drain of the fourth NMOS transistor NM4, the gate of the fourth NMOS transistor NM4 serves as the second external bias voltage input end, and the second external bias voltage Vn3 is inputted thereto; the source of the fourth NMOS transistor NM4 and the source of the fifth NMOS transistor NM5 are grounded; the gate and drain of the fifth NMOS transistor NM5 are connected, and are also connected to the emitter of the first NPN transistor QN1.

[0045] In the embodiment of the present invention, to facilitate description of the principle of overshoot suppression, the overshoot suppression module can be divided into two parts:

[0046] (1) The first part is used to quickly discharge the output voltage of the circuit when the output current of the circuit suddenly changes from large to small, which includes Figure 5When the current at the output end of the circuit suddenly changes from large to small, causing a change in the current at the intermediate stage output end, the third PMOS transistor PM3, the PNP transistor QP0, the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, and the first NPN transistor QN1, among other components, amplify the changing current through the PNP transistor QP0 and transmit it to the first NPN transistor QN1, thereby achieving the purpose of quickly dissipating the voltage at the output end of the current, thereby preventing excess current from continuously charging the load capacitor and raising the output end voltage of the circuit.

[0047] (2) The second part is used to limit the maximum value of the overshoot voltage at the output of the circuit, which includes Figure 5 Regarding the sixth NMOS transistor NM6, the fourth PMOS transistor PM4, the fifth PMOS transistor PM5 and other components in the circuit, when the difference between the overshoot voltage value Vout at the output end of the circuit and the first external bias voltage Vn2 is greater than the threshold voltage of the sixth NMOS transistor NM6, the current mirror circuit formed by the fourth PMOS transistor PM4 and the fifth PMOS transistor PM5 is used to quickly charge the gate of the power transistor, thereby quickly raising the gate voltage (that is, the voltage at the intermediate stage output end), thereby better curbing the peak value of the overshoot voltage.

[0048] In the embodiment of the present invention, both Vn2 and Vn3 are bias voltages provided by an external bias circuit. The first external bias voltage Vn2 varies with the selected output voltage range of the circuit, and ensures that the difference between the circuit's output voltage and Vn2 is less than the threshold voltage of the sixth NMOS transistor NM6 during normal operation. This allows this portion to operate only when the circuit's output current changes from high to low, and remain off at all other times. Similarly, the portion consisting of the third PMOS transistor PM3, the PNP transistor QP0, the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, and the first NPN transistor QN1 also operates only when the output current changes. This prevents the increase in power consumption of the entire circuit due to the addition of the undershoot suppression module.

[0049] 3. Adaptive Miller compensation module.

[0050] Stability is a key performance metric for LDOs, directly determining whether they function properly. Current variations at the circuit's output can cause LDO stability issues, degrading the performance of the entire LDO feedback loop system. To address this issue, an adaptive Miller compensation module circuit is designed in embodiments of the present invention.

[0051] like Figure 6As shown, an example of an adaptive Miller compensation module circuit is provided, which mainly includes: two capacitors, two resistors, two CMOS switches and two inverters. The two capacitors are called capacitor C0 and first capacitor C1, the two resistors are called second resistor R2 and third resistor R3, and the two inverters are called first inverter INV1 and second inverter INV2.

[0052] The structure is as follows: the upper plate of capacitor C0 is connected to the upper plate of the first capacitor C1 and to the output end of the error amplifier; the lower plate of the first capacitor C1 is connected to the first port of the first CMOS switch, and the lower plate of capacitor C0 is connected to the second port of the first CMOS switch; the first port of the second resistor R2 is connected to the first port of the third resistor R3, and is connected to the lower plate of capacitor C0 and the second port of the first CMOS switch; the second port of the third resistor R3 is connected to the first port of the second CMOS switch; the second port of the second resistor R2 is connected to the second port of the second CMOS switch and to the output end (Vout) of the circuit.

[0053] The two CMOS switches have the same structure. The first CMOS switch includes a sixth PMOS transistor PM6 and a seventh NMOS transistor NM7, and the second CMOS switch includes a seventh PMOS transistor PM7 and an eighth NMOS transistor NM8. The structure of the first CMOS switch is as follows: the drain of the sixth PMOS transistor PM6 is connected to the source of the seventh NMOS transistor NM7, serving as the first port of the first CMOS switch; the source of the sixth PMOS transistor PM6 is connected to the drain of the seventh NMOS transistor NM7, serving as the second port of the first CMOS switch; the gate of the sixth PMOS transistor PM6 and the gate of the seventh NMOS transistor NM7 both serve as control signal input ports of the first CMOS switch, and are independently input with the corresponding first control signal swp and second control signal swn. The first control signal swp and the second control signal swn are simultaneously input into the corresponding control signal input ports. The second CMOS switch structure is as follows: the drain of the seventh PMOS transistor PM7 is connected to the source of the eighth NMOS transistor NM8, serving as the first port of the second CMOS switch; the source of the seventh PMOS transistor PM7 is connected to the drain of the eighth NMOS transistor NM8, serving as the second port of the second CMOS switch; the gate of the seventh PMOS transistor PM7 and the gate of the eighth NMOS transistor NM8 both serve as control signal input ports of the second CMOS switch, and are independently input with the corresponding first control signal swp and second control signal swn, and the first control signal swp and the second control signal swn are simultaneously input with the corresponding control signal input ports. The two CMOS switch control signals, namely the first control signal swp and the second control signal swn, are generated by the output voltage Vn1 of the current detection module, respectively, through the second inverter INV2 and the first inverter INV1. Figure 6As shown in the lower part, the output voltage Vn1 of the current detection module generates a first control signal swp through the second inverter INV2, and then generates a second control signal swn through the first inverter INV1.

[0054] The principle is as follows: Capacitor C0, first capacitor C1, and first CMOS switch form an adaptive Miller capacitor circuit, while second resistor R2, third resistor R3, and second CMOS switch form an adaptive zeroing resistor circuit. When the current at the output end of the circuit increases, the bias voltage Vn1 generated by the current detection module in the anti-overshoot module increases, causing the first control signal swp to be low and the second control signal swn to be high. The two CMOS switches are turned on, connecting capacitor C0 and the first capacitor C1 in parallel to increase the Miller compensation capacitance, and connecting the second resistor R2 and the third resistor R3 in parallel to reduce the zeroing resistor. This effectively tracks the zero-pole change caused by the increase in power tube transconductance gm when the output current increases, while improving the bandwidth and increasing the response rate. It can also effectively solve the stability problem of the LDO feedback loop system caused by output current changes. When the current at the output end of the circuit changes from large to small or is operating normally, the first control signal swp is high, the second control signal swn is low, and the two CMOS switches are turned off to ensure the stability of the LDO feedback system at that moment.

[0055] Those skilled in the art will understand that transconductance gm is a property of MOS, which means the change in leakage current of the MOS tube divided by the change in gate-source voltage.

[0056] 4. Different reference voltage generation modules.

[0057] In an embodiment of the present invention, the different reference voltage generation module includes: a resistor divider network, a logic module and a third CMOS switch; wherein: the output end of the resistor divider network and the negative input end of the error amplifier are controlled by the third CMOS switch, one end of the logic module is connected to the external circuit input control signal, and the other end is connected to the control signal input end of the third CMOS switch, that is, when the external circuit inputs different control signals, the logic module generates a control signal to control the third CMOS switch to select and output different gear reference voltages, which are transmitted to the negative input end of the error amplifier, and the Ibias (bias current) of the resistor divider network is provided by the external bias circuit.

[0058] like Figure 7As shown in the figure, examples of different reference voltage generation modules are provided. This example takes 4 bits as an example. The dotted box is a 4-bit logic module. Here, the resistor divider network generates 16 different voltage values, where av_ldo_sel<3:0> is a 4-bit external input control signal. av_ldo_sel<3:0> generates s<7,5,3,1> through the inverter INV3<0:3>, and generates s<6,4,2,0> through the inverter INV4<0:3>. S<7,5,3,1> and S<6,4,2,0> are used to decode the input end of the NAND gate NAND1<0:15> to generate Vref_selb<0:15>. Vref_selb<0:15> generates Vref_sel<0:15> through the inverter INV5<0:15>. Vref_selb<0:15> and Vref_sel<0:15> are used to control the third CMOS The switch is controlled according to different input control signals av_ldo_sel<3:0> to control the third CMOS switch to select different voltage values of the resistor divider network and transmit them to the negative input terminal of the error amplifier, wherein the inverter INV3<0:3>, the inverter INV4<0:3>, the inverter INV5<0:15> and the NAND gate NAND1<0:15> respectively represent 4 inverters INV3 of the same size, 4 inverters INV4 of the same size, 16 inverters INV5 of the same size and 16 NAND gates NAND1 of the same size. Here, there are 16 third CMOS switches, and the 16 third CMOS switches are composed of PMOS transistors PM8<15:0> and NMOS transistors NM9<15:0>. The PMOS transistors PM8<0:15> and the NMOS transistors NM9<0:15> respectively represent 16 PMOS transistors PM8 of the same size and 16 NMOS transistors NM9 of the same size. The related structures are the same as those mentioned above. Figure 6 The CMOS switches in the same, so no further description is given.

[0059] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A multiple LDO output voltage circuit with overshoot suppression and adaptive compensation, characterized in that: include: Different reference voltage generation modules, error amplifiers, intermediate stages, power transistors, overshoot prevention modules, adaptive Miller compensation modules, and feedback networks; wherein: The reference voltage input terminal of the error amplifier is connected to the different reference voltage generation module, and the feedback input terminal of the error amplifier is connected to the first port of the feedback network; the output terminal of the error amplifier is connected to the gate of the power tube via the intermediate stage, and the output terminal of the error amplifier is amplified by the intermediate stage; the power supply terminal of the error amplifier and the source terminal of the power tube are both connected to VDD, and the drain terminal of the power tube and the second port of the feedback network are connected to the output terminal of the circuit; The anti-overshoot module is connected to the intermediate stage and the output end of the circuit; the anti-overshoot module provides a bias voltage for the intermediate stage, and the magnitude of the bias voltage is adjusted by the anti-overshoot module according to the magnitude of the voltage at the output end of the circuit. At the same time, the anti-overshoot module suppresses overshoot of the voltage at the output end of the circuit; the anti-overshoot module includes: an overshoot suppression module and a current detection module; the overshoot suppression module includes: 6 MOS tubes, 1 PNP tube and 1 NPN tube; the gate and drain of the third PMOS tube PM3 are connected, and are connected to the base of the first NPN tube QN1 and the emitter of the PNP tube QP0; the gate and drain of the fourth PMOS tube PM4 are connected, and are connected to the gate of the fifth PMOS tube PM5 and the drain of the sixth NMOS tube NM6, and the drain of the fifth PMOS tube PM5 is connected. The gate of the sixth NMOS transistor NM6 and the collector of the first NPN transistor QN1 are connected to the output end of the circuit, and the source of the sixth NMOS transistor NM6 serves as a first external bias voltage input end, inputting the first external bias voltage Vn2. The overshoot suppression of the voltage at the output end of the circuit includes: when the current at the output end of the circuit suddenly changes from large to small, causing the current at the output end of the intermediate stage to change, the changed current is amplified by the PNP transistor QP0 and transmitted to the first NPN transistor QN1, thereby achieving discharge at the output end of the circuit; when the difference between the overshoot voltage value at the output end of the circuit and the first external bias voltage Vn2 is greater than the threshold voltage of the sixth NMOS transistor NM6, the gate of the power transistor is charged by the current mirror circuit composed of the fourth PMOS transistor PM4 and the fifth PMOS transistor PM5. One end of the adaptive Miller compensation module is connected to the output end of the error amplifier, and the other end is connected to the output end of the circuit, and adaptive compensation is performed according to the current of the output end of the error amplifier and the current of the output end of the circuit.

2. The multiple LDO output voltage circuit with overshoot suppression and adaptive compensation according to claim 1, characterized in that: The intermediate stage includes five MOS transistors and one NPN transistor. The five MOS transistors include: a PMOS transistor PM0, a first PMOS transistor PM1, an NMOS transistor NM0, a first NMOS transistor NM1, and a second NMOS transistor NM2. The NPN transistor is denoted as QN0. The structure is as follows: The PMOS transistor PM0 is connected to the source of the first PMOS transistor PM1 to VDD. The gates of the PMOS transistor PM0, the first PMOS transistor PM1, and the second NMOS transistor NM2 are connected, and are also connected to the drain of the PMOS transistor PM0, the drain of the second NMOS transistor NM2, and the collector of the NPN transistor QN0. The drain of the first PMOS transistor PM1, the source of the second NMOS transistor NM2, and the drain of the first NMOS transistor NM1 are connected together to serve as the output of the intermediate stage. The base of the NPN transistor QN0 serves as the input of the intermediate stage and is connected to the output of the error amplifier. The emitter of the NPN transistor QN0 is connected to the gate and drain of the NMOS transistor NM0. The sources of the NMOS transistor NM0 and the first NMOS transistor NM1 are grounded. The first NMOS transistor NM1 serves as a current source for the intermediate stage, and its gate is connected to the output of the current detection module in the anti-overshoot module.

3. The multiple LDO output voltage circuit with overshoot suppression and adaptive compensation according to claim 1, characterized in that: One end of the current detection module is connected to the current source of the intermediate stage, and the other end is connected to the output end of the circuit, so as to provide a bias voltage for the intermediate stage; One end of the overshoot suppression module is connected to the output end of the intermediate stage, and the other end is connected to the output end of the circuit, so as to achieve overshoot suppression.

4. The multiple LDO output voltage circuit with overshoot suppression and adaptive compensation according to claim 3, characterized in that: The current detection module includes two MOS transistors, namely the second PMOS transistor PM2 and the third NMOS transistor NM3, and the structure is as follows: The source of the second PMOS transistor PM2 is connected to VDD, the gate is connected to the output end of the circuit, and the drain is connected to the drain of the third NMOS transistor NM3; The drain of the third NMOS transistor NM3 is connected to the gate and the gate of the intermediate current source, and the source is grounded.

5. The multiple LDO output voltage circuit with overshoot suppression and adaptive compensation according to claim 3, characterized in that: In the overshoot suppression module, the six MOS transistors include: a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a fourth PMOS transistor NM4, a fifth PMOS transistor NM5, and a sixth PMOS transistor NM6. The PNP transistor is denoted as QP0, and the NPN transistor is the first NPN transistor QN1. The structure is as follows: The sources of the third PMOS transistor PM3, the fourth PMOS transistor PM4, and the fifth PMOS transistor PM5 are connected to VDD; the base of the PNP transistor QP0 is connected to the output end of the intermediate stage, and the collector is connected to the drain of the fourth NMOS transistor NM4. The gate of the fourth NMOS transistor NM4 serves as a second external bias voltage input end, which receives the second external bias voltage Vn3. The source of the fourth NMOS transistor NM4 and the source of the fifth NMOS transistor NM5 are grounded; the gate and drain of the fifth NMOS transistor NM5 are connected, and are also connected to the emitter of the first NPN transistor QN1.

6. The multiple LDO output voltage circuit with overshoot suppression and adaptive compensation according to claim 5, characterized in that: The adaptive Miller compensation module includes: two capacitors, two resistors, two CMOS switches and two inverters. The two capacitors are called capacitor C0 and first capacitor C1, the two resistors are called second resistor R2 and third resistor R3, and the two inverters are called first inverter INV1 and second inverter INV2. The structure is as follows: The upper plate of the capacitor C0 is connected to the upper plate of the first capacitor C1 and to the output end of the error amplifier; the lower plate of the first capacitor C1 is connected to the first port of the first CMOS switch, and the lower plate of the capacitor C0 is connected to the second port of the first CMOS switch; the first port of the second resistor R2 is connected to the first port of the third resistor R3, and is connected to the lower plate of the capacitor C0 and the second port of the first CMOS switch; the second port of the third resistor R3 is connected to the first port of the second CMOS switch; the second port of the second resistor R2 is connected to the second port of the second CMOS switch and to the output end of the circuit; The output voltage Vn1 of the current detection module in the anti-overshoot module is sequentially transmitted through the second inverter INV2 and the first inverter INV1 to generate a first control signal swp and a second control signal swn for controlling the two CMOS switches; wherein the output voltage Vn1 of the current detection module is transmitted through the second inverter INV2 to generate the first control signal swp, and then transmitted through the first inverter INV1 to generate the second control signal swn; each of the two CMOS switches has two control signal input ports, and each control signal input port is separately input with a control signal.

7. The multiple LDO output voltage circuit with overshoot suppression and adaptive compensation according to claim 6, characterized in that: The two CMOS switches have the same structure. The first CMOS switch includes a sixth PMOS transistor PM6 and a seventh NMOS transistor NM7 , and the second CMOS switch includes a seventh PMOS transistor PM7 and an eighth NMOS transistor NM8 . The first CMOS switch has the following structure: the drain of the sixth PMOS transistor PM6 is connected to the source of the seventh NMOS transistor NM7, serving as the first port of the first CMOS switch; the source of the sixth PMOS transistor PM6 is connected to the drain of the seventh NMOS transistor NM7, serving as the second port of the first CMOS switch; the gate of the sixth PMOS transistor PM6 and the gate of the seventh NMOS transistor NM7 both serve as control signal input ports of the first CMOS switch, and are independently input with the corresponding first control signal swp and second control signal swn; The second CMOS switch has the following structure: the drain of the seventh PMOS transistor PM7 is connected to the source of the eighth NMOS transistor NM8, serving as the first port of the second CMOS switch; the source of the seventh PMOS transistor PM7 is connected to the drain of the eighth NMOS transistor NM8, serving as the second port of the second CMOS switch; the gate of the seventh PMOS transistor PM7 and the gate of the eighth NMOS transistor NM8 both serve as control signal input ports of the second CMOS switch, and are separately input with the corresponding first control signal swp and second control signal swn.

8. A multiple LDO output voltage circuit with overshoot suppression and adaptive compensation according to claim 6 or 7, characterized in that: The adaptive compensation method of the adaptive Miller compensation module includes: The capacitor C0, the first capacitor C1 and the first CMOS switch constitute an adaptive Miller capacitor circuit, and the second resistor R2, the third resistor R3 and the second CMOS switch constitute an adaptive zeroing resistor circuit; When the current at the output end of the circuit changes from small to large, the bias voltage Vn1 generated by the current detection module in the anti-overshoot module increases, so that the first control signal swp is low and the second control signal swn is high, and the two CMOS switches are turned on so that the capacitor C0 and the first capacitor C1 are connected in parallel to increase the Miller compensation capacitance, and the second resistor R2 and the third resistor R3 are connected in parallel to reduce the size of the zero adjustment resistance; when the current at the output end of the circuit changes from large to small or operates normally, the first control signal swp is high, the second control signal swn is low, and the two CMOS switches are turned off.

9. The multiple LDO output voltage circuit with overshoot suppression and adaptive compensation according to claim 1, characterized in that: The different reference voltage generation module includes: a resistor voltage divider network, a logic module and a third CMOS switch; wherein: The output end of the resistor divider network and the negative input end of the error amplifier are controlled by a third CMOS switch. One end of the logic module is connected to the external circuit input control signal, and the other end is connected to the control signal input end of the third CMOS switch. That is, when the external circuit inputs different control signals, the logic module generates a control signal to control the third CMOS switch to select the output of different gear reference voltages and transmit them to the negative input end of the error amplifier. The bias current Ibias of the resistor divider network is provided by the external bias circuit.

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