A memory, a control method thereof, and a storage system

Abstract

The application discloses a memory, a control method thereof and a storage system. The control method comprises the following steps: writing data into the memory, and forming a dynamic mapping table in a cache area of the memory according to a mapping relationship between logical addresses and physical addresses of the written data; establishing a first mapping table in a flash area of the memory, and transferring address mapping information of part of the dynamic mapping table to the first mapping table according to whether a storage capacity of the cache area is sufficient; establishing a second mapping table in the cache area, and storing a mapping relationship between the physical addresses and the logical addresses of the first mapping table in the second mapping table; storing snapshot information in the cache area according to the second mapping table, the dynamic mapping table and a valid data amount of a storage unit in the flash area; when the second mapping table is updated, transferring the snapshot information to the flash area; and when an abnormal state occurs in the memory, restoring data of the memory according to the snapshot information. The application can be used for power-on recovery of stored data.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage, in particular to a memory, a control method thereof and a storage system. BACKGROUND

[0002] In today's solid state disk consumer market, the price of solid state disk has gradually approached the price of traditional mechanical hard disk. In order to further reduce the cost of solid state disk, the current consumer-grade solid state disk has gradually evolved from the original external dynamic random access memory (DRAM) architecture design to the architecture design without external DRAM. The benefit of such design is that the entire solid state disk can save the price of one or even multiple DRAMs, thereby further reducing the cost of solid state disk.

[0003] The flash memory mapping table is a mapping table recording the correspondence between the logical address and the physical address, which can be used to manage which physical location in the flash memory the data written in the logical address exists. Therefore, the management of the flash memory mapping table affects the read-write performance of the memory. Especially in the case of abnormal power failure, how to recover the flash memory mapping table after power-on is a problem to be solved. SUMMARY

[0004] The purpose of the present application is to provide a memory, a control method thereof and a storage system, which can quickly and controllably recover all mapping relationships in the mapping table after abnormal power failure of the memory.

[0005] To solve the above technical problems, the present application is realized by the following technical scheme:

[0006] The present application provides a control method of a memory, comprising the following steps:

[0007] writing data into the memory, and forming a dynamic mapping table in the cache area of the memory according to the mapping relationship between the logical address and the physical address of the written data;

[0008] establishing a primary mapping table in the flash memory area of the memory, and transferring part of the address mapping information of the dynamic mapping table to the primary mapping table according to whether the storage capacity of the cache area is sufficient;

[0009] establishing a secondary mapping table in the cache area, and storing the mapping relationship between the physical address and the logical address of the primary mapping table in the secondary mapping table;

[0010] obtaining snapshot information according to the secondary mapping table, the dynamic mapping table and the number of valid data in the storage unit in the flash memory area, and storing the snapshot information in the cache area;

[0011] transferring the snapshot information to the flash area when the secondary mapping table is updated; and

[0012] restoring data of the memory according to the snapshot information when the memory is in an abnormal state.

[0013] In an embodiment of the present application, the step of forming the primary mapping table comprises:

[0014] presetting a flush threshold according to a number of dynamic cache units of the cache area, wherein the dynamic mapping table is stored in the dynamic cache units; and

[0015] transferring address mapping information of part of the dynamic mapping table to the flash area to form the primary mapping table when the number of dynamic cache units is less than the flush threshold.

[0016] In an embodiment of the present application, the step of forming the primary mapping table further comprises:

[0017] setting a flush flag in the cache area when the number of dynamic cache units is less than the flush threshold.

[0018] storing the dynamic mapping table of the written data in the dynamic cache units; and

[0019] transferring address mapping information of the dynamic mapping table to the flash area according to the flush flag, and forming the primary mapping table.

[0020] In an embodiment of the present application, after the primary mapping table is formed, the dynamic mapping table whose information is transferred in the cache area is cleared, and the storage space of the corresponding dynamic cache unit is released.

[0021] In an embodiment of the present application, the step of obtaining the number of valid data comprises:

[0022] when the dynamic mapping table is formed, obtaining the storage unit corresponding to the storage area according to the physical address in the dynamic mapping table; and

[0023] increasing the number of valid data of the storage unit.

[0024] In an embodiment of the present application, the step of obtaining the number of valid data comprises:

[0025] when the storage data is read out from the flash area, keeping the number of valid data of the storage unit corresponding to the storage data unchanged; and

[0026] When the storage data is edited, if the storage data is read from a first storage unit and the storage data is written into a second storage unit after being edited, the valid data quantity of the second storage unit is increased and the valid data quantity of the first storage unit is decreased, wherein the first storage unit and the second storage unit are located in the flash memory area.

[0027] In an embodiment of the present application, the step of reading data from the storage unit comprises:

[0028] When the address mapping information of the read data is located in the cache area, the physical address of the read data is obtained according to the dynamic mapping table;

[0029] When the address mapping information of the read data is located in the flash memory area, the physical address of the corresponding first mapping table is obtained according to the second mapping table; and

[0030] The physical address of the read data is obtained according to the first mapping table.

[0031] In an embodiment of the present application, the step of recovering the data of the storage unit comprises:

[0032] The snapshot information of the flash memory area is transferred to the corresponding position in the cache area; and when the valid data quantity of the storage unit is zero, the storage space of the storage unit is released.

[0033] The present application provides a storage system, comprising:

[0034] A dynamic mapping table generating unit is configured to write data into a flash memory area of a storage unit and form a dynamic mapping table in a cache area of the storage unit according to the mapping relationship between the logical address and the physical address of the written data;

[0035] A first mapping table generating unit is configured to establish a first mapping table in the flash memory area and transfer part of the address mapping information of the dynamic mapping table to the first mapping table according to whether the storage capacity of the cache area is sufficient;

[0036] A second mapping table generating unit is configured to form a second mapping table according to the mapping relationship between the physical address and the logical address of the first mapping table and store the second mapping table in the cache area;

[0037] A snapshot information generating unit is configured to obtain snapshot information according to the valid data quantity of each storage unit in the flash memory area, the second mapping table, the dynamic mapping table and the valid data quantity of the storage unit in the flash memory area and store the snapshot information in the cache area;

[0038] a snapshot information transfer unit, whenever the secondary mapping table is updated, transferring the snapshot information to the flash area; and

[0039] a power-on data recovery unit, when the memory is abnormally powered off, recovering data of the memory according to the snapshot information.

[0040] The application provides a memory, wherein a computer program is stored in the memory, and the computer program is executed by a processor to realize the control method of the memory.

[0041] As described above, the application provides a memory and a control method and a storage system thereof, which can orderly manage address mapping information of read-write data when the read-write data is read and written, and when the memory is abnormally powered off, the memory can quickly and controllably recover all mapping relationships in the mapping table, the recovery process is fast, and no data is missed. The control method of the memory provided by the application can improve the accuracy of data addresses after data storage and calling modification, avoid invalid storage of data due to the lack of data address mapping information, improve the effective storage space of the memory, and improve the use efficiency of the memory in the effective storage space. The control method of the memory provided by the application can quickly and directly recover data to the corresponding position after power recovery of the memory, and the data recovery efficiency after power-on is high.

[0042] Of course, any product implementing the application does not necessarily need to achieve all the advantages described above. BRIEF DESCRIPTION OF DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed to be used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0044] Figure 1 It is a structural schematic diagram of the memory.

[0045] Figure 2 It is a flowchart of the control method of the memory.

[0046] Figure 3 It is a flowchart of step S10.

[0047] Figure 4 It is a flowchart of step S20.

[0048] Figure 5 It is a flowchart of step S40.

[0049] Figure 6 is a flow chart of step S41.

[0050] Figure 7 is a schematic diagram of the data retrieval structure.

[0051] Figure 8 is a flow chart of step S50.

[0052] Figure 9 is a flow chart of step S60.

[0053] Figure 10 is a schematic diagram of the snapshot storage unit.

[0054] Figure 11 is a schematic diagram of the storage system according to the present application.

[0055] In the figure: 1, memory; 2, host; 10, flash area; 11, data storage unit; 12, primary mapping storage unit; 13, snapshot storage unit; 131, secondary mapping table storage module; 132, dynamic mapping table storage module; 133, valid data number storage module; 20, cache area; 21, data cache unit; 22, dynamic cache unit; 23, secondary mapping cache unit; 24, snapshot cache unit; 100, storage system; 101, dynamic mapping table generation unit; 102, primary mapping table generation unit; 103, secondary mapping table generation unit; 104, snapshot information generation unit; 105, snapshot information transfer unit; 106, power-on data recovery unit. DETAILED DESCRIPTION

[0056] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without any creative work fall within the scope of protection of the present application.

[0057] A storage device can be used with a host system to store program and various data information, and the host system can write data to or read data from the storage device. A storage device using flash memory as storage medium does not have the feature of repeated overwriting. Data can only be written after the flash memory is erased, and the writing operation is performed in physical page units, while the erasing operation is performed in physical block units. Therefore, the host system writes data at a specified logical address, which is not stored at a fixed location in the flash memory. In a DRAM-less storage device scheme, the cache resource is more limited than that of a storage device with external DRAM. In the case of abnormal power-off, the power recovery capability of the DRAM-less storage device is limited. In the DRAM-less storage device scheme, the occupation of storage resources during abnormal power-off and power recovery will directly affect the performance of the storage device.

[0058] Referring to Figure 1 The present application provides a memory 1, which can be electrically connected with a host 2, so that the host 2 can read data from or write data to the memory 1. Specifically, the memory 1 and the host 2 can be electrically connected through a data transmission interface or a serial bus. In the embodiment, the memory 1 can be a non-volatile storage device such as a storage card or a solid state drive (SSD). The storage card can be an embedded multi media card (EMMC), for example. The host 2 can be any device that can substantially cooperate with the memory 1 to store data. In the embodiment, the host 2 can be a computer. In other embodiments of the present application, the host 2 can also be a digital camera, a video camera, a communication device, an audio player or a video player. For example, when the host 2 is a digital camera, the non-volatile memory storage device is a secure digital memory card (SD card), a multi-media card (MMC card), a CF card or an embedded storage device used by the digital camera. The embedded storage device can be an EMMC card, for example, and the embedded storage device can be electrically connected to a substrate of the host 2.

[0059] Referring to Figure 1As shown in the embodiment of the present application, the memory 1 comprises a flash memory area 10 and a cache area 20. The flash memory area 10 is a non-volatile storage device, such as an SM card, a CF card, an MMC card, an SD card, a memory stick, an XD card, a micro hard disk, etc. The flash memory area 10 can be a NAND flash memory or a NOR flash memory. The cache area 20 is a high-speed cache storage device. The cache area 20 is electrically connected to the host 2. When the host 2 needs to retrieve data, the data can be retrieved from the cache area 20 first. When the data information needed by the host 2 cannot be directly sought in the cache area 20, the data is retrieved from the flash memory area 10.

[0060] Referring to Figure 1 As shown in the embodiment of the present application, the flash memory area 10 comprises a data storage unit 11, a snapshot storage unit 13 and a first mapping storage unit 12. The flash memory area 10 comprises a plurality of data storage units 11 (not shown in the figure). The flash memory area 10 has physical blocks. The physical blocks can belong to the same memory die or belong to different memory dies. The physical blocks have a plurality of physical pages. In a NAND flash memory, for example, an array of a plurality of transistors forms the NAND flash memory. The transistors are connected in series between adjacent transistors to form a string. The control electrode of each transistor is connected to a word line. According to the arrangement order of each string of transistors, the drain electrode of the transistor at the end of each string of transistors is connected to a bit line, and the source electrode of the transistor at the beginning is connected to a source line. In the embodiment, the transistors on the same word line are in the same physical page, and the array of transistors on the same substrate structure is in the same physical block. The physical pages belonging to the same physical block can be independently written and simultaneously erased. When the memory 1 is applied, the physical addresses of each physical block and physical page can have offset calls, so the mapping relationship between the logical addresses and the physical addresses needs to be stored in order to find the corresponding physical block or physical page according to the called logical address.

[0061] Referring to Figure 1 and Figure 2 As shown, the host 2 writes data into the memory 1. The written data has a logical address and an actual storage physical address. The mapping relationship between the logical address and the physical address is stored in the cache area 20. The data in the cache area 20 will be lost after an abnormal power failure. Therefore, the present application provides a memory control method for managing the mapping relationship between the logical address and the physical address in the memory 1. Before the memory 1 is controlled and managed, the memory 1 can be configured.

[0062] Referring to Figure 1As shown, in an embodiment of the present application, the memory 1 comprises a flash memory area 10 and a cache area 20, and the cache area 20 and the flash memory area 10 can be electrically connected through an interface or a wire harness to exchange data. The flash memory area 10 comprises data storage units 11, a first-level mapping storage unit 12, a snapshot storage unit 13 and a second-level mapping storage unit 14. The data storage units 11 in the flash memory area 10 are multiple, and the data storage units 11 are the minimum erasing units of the flash memory area 10. Specifically, the data storage units 11 can be physical blocks in the memory 1. The data storage units 11 comprise multiple data storage pages. When the host 2 writes data into the flash memory area 10, the data is written into the data storage pages in the data storage units 11. When the flash memory area 10 erases data, the storage information of all the data storage pages in the entire data storage units 11 is synchronously erased. The snapshot storage unit 13 and the second-level mapping storage unit 14 can also be physical blocks in the memory 1. Specifically, in the multiple physical blocks in the memory 1, the physical blocks specially used for storing power failure recovery related data are divided according to the physical addresses to form the snapshot storage unit 13 and the second-level mapping storage unit 14. The number of the snapshot storage unit 13, the first-level mapping storage unit 12 and the second-level mapping storage unit 14 can be determined according to the amount of stored data, and the number of the snapshot storage unit 13 and the second-level mapping storage unit 14 is not limited in the present application.

[0063] Referring to Figure 1 As shown, in an embodiment of the present application, the cache area 20 comprises a data cache unit 21, a dynamic cache unit 22, a second-level mapping cache unit 23 and a snapshot cache unit 24. The data cache unit 21 is used for storing cache storage information which can be directly called by the host 2. The dynamic cache unit 22 is used for storing the mapping relationship between the logical address and the physical address of the written data. The written data refers to the host data written into the data storage units 11 by the host 2. The second-level mapping cache unit 23 corresponds to the first-level mapping cache block 14, and is used for storing the mapping relationship between the logical address and the physical address of the first-level mapping cache block 14. The snapshot cache unit 24 is used for storing power failure recovery related data.

[0064] Referring to Figure 1 and Figure 2 As shown, the present application provides a memory control method, and the memory control method comprises a step S10.

[0065] In step S10, data is written into the memory, and a dynamic mapping table is formed in the cache area of the memory according to the mapping relationship between the logical address and the physical address of the written data.

[0066] Referring to Figure 1 to Figure 3As shown, in an embodiment of the present application, after the host 2 writes host data into the memory 1 in step S10, the logical address of the data and the physical address where the data is actually stored are different, so a mapping relationship is established between the physical address and the logical address of the written data, and the mapping relationship is recorded and stored, so as to facilitate the subsequent developers or users to call the correct data by using the logical address. The host data can be stored in the data storage unit 11. Specifically, step S10 includes steps S11-S14.

[0067] Step S11, write host data into the data storage unit.

[0068] Step S12, establish a dynamic mapping table, and store the address mapping information of the host data in the dynamic mapping table.

[0069] Step S13, apply for a blank dynamic cache unit, and store the dynamic mapping table in the applied dynamic cache unit.

[0070] Step S14, judge whether the number of blank dynamic cache units in the cache area is lower than the lower flush threshold value, if not, execute step 30, if yes, execute step S20.

[0071] Please refer to Figure 1 to Figure 4As shown, in an embodiment of the present application, in step S11, the host 2 writes host data to the data storage unit 11. The logical address of the host data is inconsistent with the actual physical address. Therefore, in step S12, after the host data is written, the logical address of the host data is corresponded to the actual physical address, and a dynamic mapping table is established. In step S13, the dynamic mapping table is stored in the cache area 20 to meet the frequent calling of data. Specifically, the dynamic mapping table is stored in the dynamic cache unit 22. In step S14, it is judged whether the cache area 20 has enough dynamic cache units 22. Specifically, a lower brush threshold is set according to the number of dynamic cache units 22. In this embodiment, the lower brush threshold is, for example, 1 / 5-1 / 4 of the total number of dynamic cache units 22. Specifically, the total number of dynamic cache units 22 in the cache area 20 is, for example, 2000, and the lower brush threshold can be set to, for example, 400. When the number of dynamic cache units 22 is less than or equal to, for example, 400, it is considered that the current dynamic cache unit 22 storage space is insufficient, and after the current dynamic mapping table storage is completed, step S20 is executed to clean out enough dynamic cache space for use to ensure that the address mapping information of the data will not be lost and can be stored completely. When the number of dynamic cache units 22 is greater than, for example, 400, it is considered that the current dynamic cache unit 22 storage space is sufficient, and step S30 is executed. Before step S20 is executed, a lower brush flag can be set in the cache area 20, the dynamic mapping table of the written data is stored completely, and then the address mapping information in part of the dynamic mapping table is transferred to form a primary mapping table. Thus, it is ensured that the related information of the written data is stored completely. Specifically, the memory control method of the present application includes step S20.

[0072] Step S20, a primary mapping table is established in the flash memory area, and according to whether the storage capacity of the cache area is sufficient, the address mapping information of part of the dynamic mapping table is transferred to the primary mapping table.

[0073] Please refer to Figure 1 and Figure 4As shown in the figure, in an embodiment of the present application, when the number of dynamic cache units 22 is less than or equal to the lower threshold in step S12 and step S13, it is considered that the storage space corresponding to the current dynamic cache unit 22 is insufficient. The dynamic mapping table corresponding to the host data currently written is applied to the blank dynamic cache unit 22, and then it is determined whether the information in the dynamic mapping table is to be transferred. In the embodiment, the host 2 establishes a dynamic mapping table every time it writes host data to the memory 1. Therefore, the dynamic cache units 22 in the cache area 20 are specially set to store the dynamic mapping table, so as to distinguish the dynamic mapping table from the remaining cache data. When the storage capacity of the dynamic cache unit 22 is insufficient, step S20 is executed, and a primary mapping table is formed according to the address mapping information of part of the dynamic mapping table and stored in the flash area 10. After the current dynamic mapping table is stored in the dynamic cache unit 22, it is considered that the storage capacity of the dynamic cache unit 22 is insufficient, and therefore the storage space of part of the dynamic cache unit 22 is randomly released. Specifically, step S20 includes steps S21-S30.

[0074] Step S21, a plurality of primary mapping tables are established in the primary mapping storage unit.

[0075] Step S22, part of the dynamic cache units are randomly selected, and the address mapping information of the dynamic mapping table in the dynamic cache unit is obtained.

[0076] Step S23, the address mapping information in the dynamic mapping table is transferred to the primary mapping table, and the corresponding dynamic mapping table is cleared.

[0077] Step S24, whether the number of blank dynamic cache units is lower than the lower threshold.

[0078] Please refer to Figure 1 and Figure 4 As shown in the figure, in an embodiment of the present application, the primary mapping storage unit 12 can be a physical block of the flash area 10, and in step S21, a plurality of blank primary mapping tables are set in the primary mapping storage unit 12. In step S22, part of the dynamic cache units 22 are selected from the dynamic cache units 22 that have been written, for preparation of release. The dynamic cache unit 22 corresponding to the host data currently written can also be selected for release. In step S23, for the dynamic cache unit 22 selected for preparation of release, the address mapping information of the dynamic mapping table in the dynamic cache unit 22 is transferred to the primary mapping table in the primary mapping unit 14 for storage. After the address mapping information of the dynamic mapping table is transferred, the dynamic mapping table can be cleared for the establishment of the next dynamic mapping table. The dynamic mapping table can include the logical address of the host data, the physical address of the host data, and the time of writing of the host data, etc.

[0079] Please refer toFigure 1 and Figure 4 As shown in FIG. 2 and FIG. 3, in an embodiment of the present application, the sizes of the host data are different in step S22 and step S23, and the number of the dynamic cache units 22 occupied by the dynamic mapping tables are also different, so when the address mapping information is transferred from the cache area 20 to the flash area 10, the dynamic cache units 22 are released in the minimum release unit of the dynamic mapping table corresponding to each host data. For example, the sizes of the two types of host data are 16 KB and 256 KB. In the flash area 10, the size of one data storage page is 8 KB, and the size of one data storage unit 11 is 32 KB. The 16 KB host data can use two data storage pages, and the mapping relationship between the logical address and the physical address can be established by, for example, 2 dynamic mapping tables, and the 2 dynamic mapping tables can occupy, for example, 2 dynamic cache units 22. When the dynamic cache units 22 are released, the 2 dynamic cache units 22 should be selected at the same time. Similarly, the 256 KB host data can be stored in, for example, 8 data storage units 11, and the mapping relationship between the logical address and the physical address can be established by, for example, 16 dynamic mapping tables, and the 16 dynamic mapping tables can occupy, for example, 16 dynamic cache units 22. When the dynamic cache units 22 are released, the 16 dynamic cache units 22 should also be selected at the same time.

[0080] Please refer to Figure 1 and Figure 4 As shown in FIG. 2 and FIG. 3, in an embodiment of the present application, the sizes of the host data are different in step S22 and step S23, and the number of the dynamic cache units 22 occupied by the dynamic mapping tables are also different, so when the address mapping information is transferred from the cache area 20 to the flash area 10, the dynamic cache units 22 are released in the minimum release unit of the dynamic mapping table corresponding to each host data. For example, the sizes of the two types of host data are 16 KB and 256 KB. In the flash area 10, the size of one data storage page is 8 KB, and the size of one data storage unit 11 is 32 KB. The 16 KB host data can use two data storage pages, and the mapping relationship between the logical address and the physical address can be established by, for example, 2 dynamic mapping tables, and the 2 dynamic mapping tables can occupy, for example, 2 dynamic cache units 22. When the dynamic cache units 22 are released, the 2 dynamic cache units 22 should be selected at the same time. Similarly, the 256 KB host data can be stored in, for example, 8 data storage units 11, and the mapping relationship between the logical address and the physical address can be established by, for example, 16 dynamic mapping tables, and the 16 dynamic mapping tables can occupy, for example, 16 dynamic cache units 22. When the dynamic cache units 22 are released, the 16 dynamic cache units 22 should also be selected at the same time.

[0081] Step S30, the second mapping table is established in the cache area, and the mapping relationship between the physical address and the logical address of the first mapping table is stored in the second mapping table.

[0082] Please refer to Figure 1 ,Figure 4 and Figure 5 As shown in FIG. 2, in an embodiment of the present application, when the address mapping information of the called data is in the cache area 20, the host 2 can directly call the address mapping information of the corresponding data according to the dynamic mapping table in the dynamic cache unit 22, and then call the required data from the data storage unit 11 according to the physical address of the address mapping information. When the address mapping information of the called data is in the flash area 10, the secondary mapping table is first found from the secondary mapping cache unit 23, and then the primary mapping table is found in the primary mapping storage unit 12 according to the address mapping information in the secondary mapping table. The address mapping information of the corresponding data is called according to the primary mapping table, and the required data is called from the data storage unit 11 according to the physical address of the address mapping information. As shown in FIG. 3, in this embodiment, the dynamic cache unit 22 can store, for example, n dynamic mapping tables, and the primary mapping storage unit 12 can store, for example, n primary mapping tables. Wherein, n is a natural number greater than or equal to 1, and the present application does not limit the specific value of n. Figure 5

[0083] Please refer to Figure 1 , Figure 2 and Figure 5 As shown in FIG. 2, in an embodiment of the present application, the primary mapping table is located in the flash area 10 and can not be lost in the case of abnormal power failure. While the secondary mapping table and the dynamic mapping table are stored in the cache area 20, and it is difficult to recover the secondary mapping table and the dynamic mapping table after abnormal power failure and power on. Therefore, the memory control method of the present application comprises step S40. And step S40 comprises step S41 and step S42.

[0084] Step S40, according to the secondary mapping table, the dynamic mapping table and the number of valid data of the storage unit in the flash area, the snapshot information is obtained and stored in the cache area.

[0085] Step S41, the number of valid data of each data storage unit in the flash area is obtained and stored in the snapshot cache unit.

[0086] Step S42, the address mapping information in the secondary mapping table and the dynamic mapping table is obtained and stored in the snapshot cache unit.

[0087] Please refer to Figure 1 , Figure 2 and Figure 5 ​In an embodiment of the present application, in step S41, the number of valid data in each memory cell in the flash area 10 is confirmed according to the recorded address mapping information. Specifically, according to the mapping relationship between the logical address and the physical address in the dynamic mapping table and the primary mapping table, the data memory cell 11 corresponding to the physical address is found. Each time the data memory cell 11 is found, the corresponding data memory cell 11 is counted once. After the dynamic mapping table and the primary mapping table are traversed, the number of valid data in each data memory cell 11 is counted and recorded, so as to facilitate the verification and processing of the recovered data when the data is recovered after power-off. When the data already stored in the data memory cell 11 is evicted, according to the evicted physical address or logical address, the primary mapping table or the dynamic mapping table corresponding to the evicted data is found from the primary mapping memory cell 12 and the dynamic cache cell 22. Then, according to the change of the evicted data, the primary mapping table, the dynamic mapping table and the secondary mapping table are adjusted. Specifically, step S41 includes steps S411-S416.

[0088] Step S411, after the evicted data is modified, the evicted data is written into the flash area again.

[0089] Step S412, whether the size of the modified evicted data is changed.

[0090] Step S413, the primary mapping table or the dynamic mapping table corresponding to the evicted data is read out, and the physical address corresponding to the logical address of the evicted data is modified.

[0091] Step S414, the primary mapping table or the dynamic mapping table is stored to the original storage position.

[0092] Step S415, the mapping relationship pair corresponding to the evicted data in the primary mapping table or the dynamic mapping table is cleared.

[0093] Please refer to Figure 1 and Figure 2 , and Figure 5 and Figure 6As shown in the figure, in an embodiment of the present application, in step S411, after the host 2 processes the data to be evicted, the data to be evicted is stored back into the data storage unit 11. In step S412, when the data to be evicted is processed by the host 2, the size of the data to be evicted does not change, and thus the size of the occupied space in the data storage unit 11 also does not change. Therefore, in order to reduce the work load of the memory 1, in step S413, the physical address corresponding to the logical address of the data to be evicted is modified based on the original dynamic mapping table or the original primary mapping table. In step S414, the modified primary mapping table and dynamic mapping table are stored back into the original storage location, and the snapshot information is modified accordingly. In step S412, when the data to be evicted is processed by the host 2, the size of the data to be evicted changes, and thus the size of the occupied space in the data storage unit 11 can change. Therefore, in step S415, the mapping relationship corresponding to the data to be evicted in the primary mapping table is deleted, or the dynamic mapping table corresponding to the data to be evicted is deleted. Then the data to be evicted is written back, i.e., returning to step S10 and performing steps S10 to S40. When the data is evicted from the data storage unit 11, the number of valid data in the data storage unit 11 is reduced by 1.

[0094] As shown in the figure, in an embodiment of the present application, the method for controlling the memory comprises step S50. Figure 1 Figure 2 As shown in the figure, in an embodiment of the present application, the method for controlling the memory comprises step S50.

[0095] In step S50, when the secondary mapping table is updated, the snapshot information is transferred to the flash area.

[0096] As shown in the figure, in an embodiment of the present application, in step S20, when the partial dynamic cache unit 22 is released, the address mapping information in the cache area 20 is transferred to the flash area 10, and the secondary mapping table in the cache area 20 is updated. In this embodiment, the mapping relationship between the logical address and the physical address in the secondary mapping table can be arranged according to the order of establishment. In the present application, step 50 comprises steps S51 to S54. Figure 1 Figure 2 In step S51, it is determined whether the address mapping information in the secondary mapping table is updated. If the address mapping information in the secondary mapping table is updated, steps S52 and S53 are performed. If the address mapping information in the secondary mapping table is not updated, step S53 is performed. Figure 7 Figure 8 In step S52, the snapshot information in the snapshot cache unit is transferred to the snapshot storage unit.

[0097] In step S52, the snapshot information in the snapshot cache unit is transferred to the snapshot storage unit.

[0098] In step S52, the snapshot information in the snapshot cache unit is transferred to the snapshot storage unit.

[0099] ​​​Step S53, clearing the snapshot information in the snapshot cache unit.

[0100] Referring to Figure 1 and Figure 2 , and Figure 7 and Figure 8 , in an embodiment of the present application, the secondary mapping table has, for example, n pairs of mapping relationship between logical addresses and physical addresses. Wherein n is a natural number greater than or equal to 1. In this embodiment, each primary mapping table can store a single address mapping information, or can store multiple address mapping information. Whenever the partial dynamic cache unit 22 dynamic mapping table is released, a primary mapping table in the primary mapping storage unit 13 will be added. And with the increase of the address mapping information of the primary mapping table, the secondary mapping table will also be updated. Therefore, in step S51, it is judged whether the address mapping information in the secondary mapping table is updated. Wherein the update of the secondary mapping table can be the increase and deletion of the address mapping information, or the change of the address mapping information. In step S52, when the secondary mapping table is updated, the snapshot information in the cache area 20 is transferred to the flash storage area 10 for storage. Specifically, the snapshot information is transferred from the snapshot cache unit 24 to the snapshot storage unit 13 for storage. In step S53, the snapshot information that has been transferred is cleared to facilitate the storage of the next batch of snapshot information. Wherein the address mapping information corresponding to the currently written host data can be stored in the dynamic cache table, or can be transferred to the primary mapping table after being stored in the dynamic cache table. And if the secondary mapping table is updated after the current host data is written, the address mapping information of the current host data can be stored in the dynamic cache table, or can be stored in the primary mapping table. Whenever the snapshot information is transferred to the flash storage area 10, the address mapping information of the currently written host data will also be transferred to the flash storage area 10. If power failure occurs at this time, the newly written data information can also be completely recovered after power on.

[0101] Referring to Figure 1 and Figure 2 , in an embodiment of the present application, when the memory 1 has an abnormal power failure, the data information in the memory 1 needs to be recovered after power on again. The data stored in the data storage unit 11 has a non-volatile characteristic and can be recovered after power on. But the stored data in the cache area 20 will be completely lost with power failure and is difficult to recover. Therefore, the control method of the memory described in the present application comprises step S60.

[0102] Step S60, when the memory has an abnormal state, recovering the data of the memory according to the snapshot information.

[0103] Referring to Figure 1 , Figure 2 and Figure 9As shown in the figure, in an embodiment of the present application, when the memory 1 is in an abnormal state, for example, after an abnormal power-off, the data stored in the memory 1 needs to be recovered, and part of the data in the cache area 20 needs to be recovered, so that the host 2 can retrieve the data. Specifically, step S60 includes steps S61-S63.

[0104] Step S61, find the latest snapshot information in the flash area.

[0105] Step S62, transfer the content in the snapshot information to the corresponding position in the cache area.

[0106] Step S63, according to the number of valid data of each storage unit in the snapshot information, release the space of the storage unit.

[0107] As shown in the figure Figure 1 and Figure 2 and Figure 9 and Figure 10 As shown in the figure, in an embodiment of the present application, after the memory 1 is powered on again, in step S61, the snapshot information with the latest update time is found in the snapshot storage unit 13 of the flash area 10. As for the storage of snapshot information, the snapshot information is stored in a fixed physical address of the memory 1, and the snapshot storage unit 13 can be fixed in address, so as to be accurately retrieved when powered on. Specifically, the snapshot storage unit 13 includes a secondary mapping table storage module 131, a dynamic mapping table storage module 132 and a valid data number storage module 133. The secondary mapping table is stored in the secondary mapping table storage module 131, the dynamic mapping table is stored in the dynamic mapping table storage module 132, and the number of valid data in each data storage unit 11 can be stored in the valid data number storage module 133. As for the update of snapshot information, the next batch of snapshot information is transferred to the snapshot storage unit 13, and the previous batch of snapshot information is stored in the snapshot storage unit 13 in the order of transfer.

[0108] As shown in the figure Figure 1 and Figure 2 and Figure 9 and Figure 10 As shown in the figure, in an embodiment of the present application, in step S62, the content in the snapshot information is transferred to the corresponding position in the cache area 20. Specifically, the data in the secondary mapping table storage module 131 is transferred to the secondary mapping cache unit 23, and the data in the dynamic mapping table storage module 132 is transferred to the dynamic cache unit 22. Among them, the number of valid data of each storage unit is extracted from the valid data number storage module 133. In step S63, after the data in the cache area 20 is recovered, the data storage unit 11 with the number of valid data being 0 is released, so as to eliminate invalid data and improve the read-write performance of the memory 1.

[0109] As shown in the figureFigure 1 、 Figure 2 and Figure 9 As shown in FIG. 1, FIG. 2, FIG. 3, and FIG. 4, in an embodiment of the present application, after the memory 1 is powered on, the storage information in the snapshot storage unit 13 can be cleared to release the storage space of the memory 1 and improve the read-write performance of the memory 1. In other embodiments of the present application, the storage information in the snapshot storage unit 13 can be retained and the steps S10 to S50 can be continuously executed. The snapshot information of different power-off periods can be overwritten by the snapshot information of the next period to cope with continuous power-off when the power-on recovery is not completed. The snapshot information in the same power-off period can be stored in the order of time when the snapshot information is transferred to the flash area 10.

[0110] As shown in FIG. 1, FIG. 2, FIG. 3, and FIG. 4, in an embodiment of the present application, after the memory 1 is powered on, the storage information in the snapshot storage unit 13 can be cleared to release the storage space of the memory 1 and improve the read-write performance of the memory 1. In other embodiments of the present application, the storage information in the snapshot storage unit 13 can be retained and the steps S10 to S50 can be continuously executed. The snapshot information of different power-off periods can be overwritten by the snapshot information of the next period to cope with continuous power-off when the power-on recovery is not completed. The snapshot information in the same power-off period can be stored in the order of time when the snapshot information is transferred to the flash area 10. Figure 1 and Figure 11 As shown in FIG. 1, FIG. 2, FIG. 3, and FIG. 4, in an embodiment of the present application, after the memory 1 is powered on, the storage information in the snapshot storage unit 13 can be cleared to release the storage space of the memory 1 and improve the read-write performance of the memory 1. In other embodiments of the present application, the storage information in the snapshot storage unit 13 can be retained and the steps S10 to S50 can be continuously executed. The snapshot information of different power-off periods can be overwritten by the snapshot information of the next period to cope with continuous power-off when the power-on recovery is not completed. The snapshot information in the same power-off period can be stored in the order of time when the snapshot information is transferred to the flash area 10.

[0111] The application provides a memory and a control method thereof, and a storage system, which can manage the mapping relationship between the logical address and the physical address of the written data when a host writes data into a flash memory area of the memory, and has the power-on data recovery capability after abnormal power-off. Specifically, after the flash memory area of the memory is written with data, a dynamic mapping table is formed according to the mapping relationship between the logical address and the physical address of the written data, and the dynamic mapping table is stored in a cache area of the memory. Then, whether to transfer part of the information of the dynamic mapping table to the flash memory area is determined according to whether the storage space of the blank dynamic cache unit of the current cache area is sufficient. Specifically, if the storage space of the blank dynamic cache unit of the current cache area is insufficient, a primary mapping table is established in the flash memory area, the address mapping information in part of the dynamic mapping table is transferred to the primary mapping table, and the storage space of the corresponding dynamic cache unit is released. Then, a secondary mapping table is established in the cache area according to the mapping relationship between the logical address and the physical address of the established primary mapping table. After the storage of the current written data is completed, the number of valid data of each storage unit in the flash memory area is obtained, and then snapshot information is formed according to the number of valid data of each storage unit in the flash memory area, the secondary mapping table and the dynamic mapping table. The snapshot information is stored in the cache area, and the snapshot information is transferred to the flash memory area whenever the secondary mapping table is updated. When the memory is abnormally powered off, the data of the memory can be recovered according to the snapshot information.

[0112] The above disclosed embodiments of the application are only used to help explain the application. The embodiments do not describe all the details, nor limit the application to the specific embodiments. Obviously, according to the content of the specification, many modifications and changes can be made. The specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the application, so that those skilled in the art can well understand and utilize the application. The application is limited by the claims and their entire scope and equivalents.

Claims

1. A method for controlling a memory, characterized in that, Includes the following steps: Data is written to the memory, and a dynamic mapping table is formed in the cache of the memory according to the mapping relationship between the logical address and physical address of the written data. A first-level mapping table is established in the flash memory area of ​​the memory, and according to whether the storage space of the cache area is sufficient, part of the address mapping information of the dynamic mapping table is transferred to the first-level mapping table; A secondary mapping table is established in the cache area, and the mapping relationship between the physical address and logical address of the primary mapping table is stored in the secondary mapping table in pairs; Based on the secondary mapping table, the dynamic mapping table, and the number of valid data units in the flash memory area, snapshot information is obtained and stored in the cache area; When the secondary mapping table is updated, the snapshot information is transferred to the flash memory area; as well as When the memory is in an abnormal state, the data in the memory is restored according to the snapshot information; The step of restoring the data in the memory includes: transferring the snapshot information of the flash memory area to the corresponding location in the cache area; and releasing the storage space of the storage unit when the number of valid data in the storage unit is zero.

2. The memory control method according to claim 1, characterized in that, The steps for forming the first-level mapping table include: Based on the number of dynamic cache units in the cache area, a preset flush threshold is determined, wherein the dynamic cache units store the dynamic mapping table; and When the number of dynamic cache units is less than the refresh threshold, some of the address mapping information of the dynamic mapping table is transferred to the flash memory area to form the first-level mapping table.

3. The memory control method according to claim 2, characterized in that, The steps for forming the first-level mapping table also include: When the number of dynamic cache units is less than the flush threshold, a flush flag is set in the cache area; The dynamic mapping table containing the written data is stored in the dynamic cache unit; and According to the brush flag, the address mapping information of the dynamic mapping table is transferred to the flash memory area, and the first-level mapping table is formed.

4. The memory control method according to claim 2, characterized in that, After the first-level mapping table is formed, the dynamic mapping table in the cache area where the information has been transferred is cleared, and the storage space of the corresponding dynamic cache unit is released.

5. The memory control method according to claim 1, characterized in that, The steps for obtaining the number of valid data points include: When forming the dynamic mapping table, the storage unit corresponding to the flash memory area is obtained according to the physical address in the dynamic mapping table; and Increase the amount of valid data in the storage unit.

6. The memory control method according to claim 5, characterized in that, The steps for obtaining the number of valid data points include: When reading stored data from the flash memory area, the number of valid data units corresponding to the stored data remains unchanged; and When the stored data is edited, if the stored data is read from the first storage unit and written to the second storage unit after being edited, the effective data quantity of the second storage unit is increased and the effective data quantity of the first storage unit is decreased, wherein the first storage unit and the second storage unit are located in the flash memory area.

7. The memory control method according to claim 1, characterized in that, The steps for reading data from the storage unit include: When the address mapping information of the read data is located in the cache area, the physical address of the read data is obtained according to the dynamic mapping table; When the address mapping information of the read data is located in the flash memory area, the physical address of the corresponding primary mapping table is obtained according to the secondary mapping table; and The physical address of the read data is obtained according to the first-level mapping table.

8. A storage system, characterized in that, include: The dynamic mapping table generation unit is used to write data to the flash memory area of ​​the memory and form a dynamic mapping table in the cache area of ​​the memory according to the mapping relationship between the logical address and physical address of the written data. The first-level mapping table generation unit is used to establish a first-level mapping table in the flash memory area, and to transfer some of the address mapping information of the dynamic mapping table to the first-level mapping table according to whether the storage space of the cache area is sufficient. The secondary mapping table generation unit is used to form a secondary mapping table based on the mapping relationship between the physical address and logical address of the primary mapping table and store the secondary mapping table in the cache area; A snapshot information generation unit is used to generate snapshot information based on the number of valid data in each storage cell in the flash memory area, the secondary mapping table, the dynamic mapping table, and the number of valid data in the storage cells of the flash memory area. The snapshot information transfer unit transfers the snapshot information to the flash memory area when the secondary mapping table is updated. as well as A power-on data recovery unit is used to recover the data in the memory based on the snapshot information when the memory is in an abnormal state. The step of restoring the data in the memory includes: transferring the snapshot information of the flash memory area to the corresponding location in the cache area; and releasing the storage space of the storage unit when the number of valid data in the storage unit is zero.

9. A memory, characterized in that, The memory stores a computer program, which, when executed by a processor, implements the memory control method as described in any one of claims 1 to 7.

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