Pixel circuit and display device including the same

Abstract

A pixel circuit and a display device including the same are disclosed. The pixel circuit of the disclosure includes a driving element including a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a second electrode connected to a third node, and configured to provide a current to a light emitting element; a first switching element configured to be turned on according to a gate-on voltage of a scan pulse to provide a data voltage to the second node; and a second switching element configured to be turned off according to a gate-off voltage of a light emission control pulse generated in phase opposition to the scan pulse.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2021-0089923, filed on July 8, 2021, and Korean Patent Application No. 10-2021-0166802, filed on November 29, 2021, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to pixel circuits and display devices including such pixel circuits. Background Technology

[0004] Electroluminescent display devices can be classified into inorganic and organic light-emitting display devices based on the material of their light-emitting layer. Active-matrix organic light-emitting display devices include self-emissive organic light-emitting diodes (OLEDs) and possess advantages such as fast response time, high luminous efficiency, high brightness, and wide viewing angle. In organic light-emitting display devices, OLEDs are formed in each pixel. Organic light-emitting display devices feature fast response time, excellent luminous efficiency, excellent brightness, and excellent viewing angle; furthermore, because black can be represented as pure black, they also exhibit excellent contrast and color reproduction.

[0005] The pixel circuit of an organic light-emitting display device includes: a light-emitting element, a driving element for driving the light-emitting element, and one or more switching elements. The switching elements are turned on / off according to the gate voltage to connect or block the main node of the pixel circuit. The driving element and the switching element can be implemented as transistors.

[0006] A low-potential power supply voltage is commonly applied to the pixels of an organic light-emitting display device. In the pixel circuitry, when a switching element connected to the low-potential power supply voltage via a capacitor is turned on, ripple may be generated in the low-potential power supply voltage. In this case, the current flowing through the light-emitting element may change, which in turn may lead to variations in pixel brightness. When an image with a crosstalk pattern is displayed on the screen, the ripple of the low-potential power supply voltage may cause uneven charging states between pixel lines, resulting in brightness differences between pixel lines. Summary of the Invention

[0007] This disclosure is made to address the aforementioned necessity and / or deficiencies.

[0008] This disclosure provides a pixel circuit capable of preventing image quality degradation due to ripple from a low-potential power supply voltage commonly applied between pixels, and a display device including the pixel circuit.

[0009] The defects addressed by this disclosure are not limited to those described above, but other defects that this disclosure can resolve will become apparent to those skilled in the art from the following description.

[0010] A pixel circuit according to an embodiment of the present disclosure includes: a driving element comprising a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a second electrode connected to a third node, and configured to provide current to a light-emitting element; a first switching element configured to be turned on according to a gate turn-on voltage of a scan pulse to provide a data voltage to the second node; a second switching element configured to be turned off according to a gate turn-off voltage of a light-emitting control pulse generated inversely to the scan pulse; and a capacitor configured to be connected between the second node and the third node.

[0011] A pixel circuit according to another embodiment of this disclosure includes: a driving element comprising a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a second electrode connected to a third node, and configured to provide current to a light-emitting element; a first switching element configured to turn on according to a gate on-state voltage of a scan pulse to provide a data voltage to the second node; a second switching element configured to turn off according to a gate off-state voltage of a light-emitting control pulse; a third switching element configured to turn on according to a gate on-state voltage of a sensing pulse to provide a reference voltage to the third node; and a capacitor configured to be connected between the second node and the third node. The light-emitting control pulse is generated as an inverted pulse of the sensing pulse.

[0012] A pixel circuit according to another embodiment of the present disclosure includes: a driving element comprising a first electrode connected to a first node to which a first constant voltage is applied, a gate electrode connected to a second node, and a second electrode connected to a third node, and configured to provide current to a light-emitting element; a first switching element configured to be turned on according to a gate turn-on voltage of a first gate pulse to provide a data voltage to the second node; a second switching element configured to be turned off according to a gate turn-off voltage of a second gate pulse; a third switching element configured to be turned on according to a gate turn-on voltage of a third gate pulse to provide a second constant voltage to the third node; a fourth switching element configured to be turned on according to a gate turn-on voltage of a fourth gate pulse to apply a third constant voltage to the second node; and a capacitor configured to be connected between the second node and the third node.

[0013] The second gate pulse is inverted to the gate turn-off voltage when the third gate pulse is inverted to the gate turn-on voltage, and is also inverted to the gate turn-on voltage when the first gate pulse is inverted to the gate turn-on voltage.

[0014] A pixel circuit according to another embodiment of this disclosure includes: a driving element comprising a first electrode connected to a first node, a first gate electrode connected to a second node, a second electrode connected to a third node, and a second gate electrode connected to a fourth node; a light-emitting element comprising an anode electrode connected to the fourth node and a cathode electrode to which a low-potential power supply voltage is applied, and configured to be driven according to a current from the driving element; a first switching element configured to be turned on according to a gate turn-on voltage of a first scan pulse to provide a data voltage to a fifth node; a second switching element connected between the third and fourth nodes to be turned off according to a gate turn-off voltage of a second light-emitting control pulse; and a third switching element configured to be turned on according to a gate turn-on voltage of a third scan pulse. A first switch element is configured to provide a reference voltage to the third node; a fourth switch element is configured to be turned on according to the gate turn-on voltage of the second scan pulse to connect the first gate electrode of the driving element to the first electrode of the driving element; a fifth switch element is configured to be turned off according to the gate turn-off voltage of the first light emission control pulse to block the current path between the power line of the applied pixel driving voltage and the first node; a sixth switch element is configured to be turned on according to the gate turn-on voltage of the second scan pulse to provide an initialization voltage to the fifth node; a seventh switch element is configured to be turned on according to the gate turn-on voltage of the third scan pulse to provide an initialization voltage to the fourth node; a first capacitor is connected between the second node and the fifth node; and a second capacitor is connected between the third node and the fifth node.

[0015] The second light emission control pulse is generated as a gate turn-off voltage when at least one of the second scan pulse and the third scan pulse is a gate on voltage, or the second light emission control pulse is generated as a gate turn-off voltage only when the second scan pulse is a gate on voltage.

[0016] A pixel circuit according to another embodiment of the present disclosure includes: a driving element comprising a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node, and configured to provide current to a light-emitting element; a first switching element configured to be turned on according to a gate turn-on voltage of a first scan pulse to provide a data voltage to the second node; a second switching element configured to be turned off according to a gate turn-off voltage of a second light emission control pulse to block a current path between the driving element and the light-emitting element; a third switching element configured to be turned on according to a gate turn-on voltage of a third scan pulse to provide an initialization voltage to the third node; a fourth switching element configured to be turned on according to a gate turn-on voltage of the second scan pulse to provide a reference voltage to the second node; a fifth switching element configured to be turned on according to a gate turn-on voltage of the first light emission control pulse to provide a pixel driving voltage to the first node; a first capacitor connected between the second node and the fourth node; and a second capacitor having one end connected to the fourth node and the other end to which a pixel driving voltage is applied. The second light emission control pulse is inverted to the gate turn-off voltage when the third scan pulse is inverted to the gate turn-on voltage, and is also inverted to the gate turn-on voltage when the first scan pulse is inverted to the gate turn-on voltage.

[0017] The display device disclosed herein includes at least one of the pixel circuits described above.

[0018] This disclosure can mitigate low-potential power supply voltage ripple defects by blocking the current path between the driving element and the light-emitting element in the portion of the low-potential power supply voltage commonly applied to the pixel where ripple may occur.

[0019] This disclosure enables a narrow bezel for a display device by generating a signal for controlling a switching element that blocks a current path via the output signal of a shift register that receives and outputs an additional gate pulse.

[0020] The effects of this disclosure are not limited to those described above, and those skilled in the art will clearly understand from the appended claims other effects not mentioned above. Attached Figure Description

[0021] The above and other objects, features and advantages of the present invention will become more apparent to those skilled in the art from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0022] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0023] Figure 2 It shows Figure 1 A cross-sectional view of the display panel structure shown;

[0024] Figure 3 This is a diagram illustrating a shift register of a gate driver according to an embodiment of the present disclosure and an EM generator connected to the output node of the shift register;

[0025] Figure 4 It shows Figure 3 The waveform diagram of the input / output signals of the shift register shown is shown.

[0026] Figure 5 This is a circuit diagram showing a pixel circuit according to a first embodiment of the present disclosure;

[0027] Figure 6 It shows the application to Figure 5 The waveform diagram of the gate signal of the pixel circuit shown;

[0028] Figure 7 It shows the generation applied to Figure 5 The circuit diagram of the EM pulse generator for the pixel circuit shown.

[0029] Figure 8 This is a circuit diagram showing a pixel circuit according to a second embodiment of the present disclosure;

[0030] Figure 9 It shows the application to Figure 8 The waveform diagram of the gate signal of the pixel circuit shown;

[0031] Figure 10 It shows the generation applied to Figure 8 The circuit diagram of the EM pulse generator for the pixel circuit shown.

[0032] Figure 11 This is a circuit diagram showing a pixel circuit according to a third embodiment of the present disclosure;

[0033] Figure 12 It shows the application to Figure 11 The waveform diagram of the gate signal of the pixel circuit shown;

[0034] Figure 13 It shows the generation applied to Figure 11 The circuit diagram of the EM pulse generator for the pixel circuit shown.

[0035] Figure 14 This is a circuit diagram showing a pixel circuit according to a fourth embodiment of the present disclosure;

[0036] Figure 15 It shows the application to Figure 14 The waveform diagram of the gate signal of the pixel circuit shown;

[0037] Figure 16 It shows the generation applied to Figure 14 The circuit diagram of the EM pulse generator for the pixel circuit shown.

[0038] Figure 17 This is a circuit diagram showing a pixel circuit according to a fifth embodiment of the present disclosure;

[0039] Figure 18 It shows the application to Figure 17 The waveform diagram of the gate signal of the pixel circuit shown;

[0040] Figure 19 It shows the generation applied to Figure 17 The circuit diagram of the EM generator for the second EM pulse of the pixel circuit shown;

[0041] Figure 20 This is a circuit diagram showing a pixel circuit according to a sixth embodiment of the present disclosure;

[0042] Figure 21 It shows the application to Figure 20 The waveform diagram of the gate signal of the pixel circuit shown; and

[0043] Figure 22 and Figure 23 It shows the generation applied to Figure 20 The circuit diagram of the EM generator for the second EM pulse of the pixel circuit shown. Detailed Implementation

[0044] The advantages and features of this disclosure, as well as the methods for implementing these advantages and features, will become more readily understood from the embodiments described below with reference to the accompanying drawings. However, this disclosure is not limited to the embodiments described below, but can be implemented in various different forms. Rather, these embodiments will complete the disclosure and will allow those skilled in the art to fully understand its scope. This disclosure is defined only within the scope of the appended claims.

[0045] The shapes, dimensions, ratios, angles, numbers, etc., shown in the accompanying drawings to illustrate embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout this specification, similar reference numerals generally refer to similar elements. Furthermore, in describing this disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure.

[0046] Terms such as “comprising,” “including,” “having,” and “consisting of” used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Any reference to the singular may include the plural unless explicitly stated otherwise.

[0047] The component is interpreted to include the normal tolerance range, even if not explicitly stated.

[0048] When using terms such as “on top of”, “above”, “below”, and “next to” to describe the positional relationship between two parts, one or more parts may be located between the two parts, unless these terms are used with the terms “immediately adjacent” or “directly”.

[0049] The terms “first”, “second”, etc., can be used to distinguish components from each other, but the function or structure of a component is not limited by the serial number or name preceding the component.

[0050] Throughout this disclosure, the same reference numerals may refer to substantially the same elements.

[0051] The following implementations can be combined or integrated with each other, either partially or completely, and can be technically linked and operated in various ways. The implementations can be performed independently of each other or can be performed in conjunction with each other.

[0052] Each pixel can include multiple subpixels of different colors to reproduce the colors of an image on the screen of a display panel. Each subpixel includes a transistor that functions as a switching or driving element. Such a transistor can be implemented as a TFT (thin-film transistor).

[0053] The driving circuit of the display device writes pixel data of the input image to pixels on the display panel. For this purpose, the driving circuit of the display device may include: a data driving circuit configured to provide data signals to data lines; a gate driving circuit configured to provide gate signals to gate lines, and so on.

[0054] In the display device of this disclosure, the pixel circuit and gate driving circuit may include multiple transistors. The transistors may be implemented as oxide thin-film transistors (oxide TFTs) including oxide semiconductors, low-temperature polycrystalline silicon (LTPS) TFTs including low-temperature polycrystalline silicon, etc. In this embodiment, an example of implementing the transistors based on the pixel circuit and gate driving circuit as n-channel oxide TFTs will be described, but this disclosure is not limited thereto.

[0055] Typically, a transistor is a three-electrode device comprising a gate, a source, and a drain. The source is the electrode that supplies charge carriers to the transistor. In a transistor, charge carriers begin to flow from the source. The drain is the electrode through which charge carriers leave the transistor. In a transistor, charge carriers flow from the source to the drain. In the case of an n-channel transistor, since the charge carriers are electrons, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. An n-channel transistor has a current direction from the drain to the source. In the case of a p-channel transistor, since the charge carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can change depending on the applied voltage. Therefore, this disclosure is not limited to the source and drain of a transistor. In the following description, the source and drain of a transistor will be referred to as the first electrode and the second electrode.

[0056] The gate signal oscillates between the gate on-voltage and the gate off-voltage. The gate on-voltage is set to a voltage higher than the transistor's threshold voltage, and the gate off-voltage is set to a voltage lower than the transistor's threshold voltage.

[0057] The transistor turns on in response to a gate on-voltage and turns off in response to a gate off-voltage. In the case of an n-channel transistor, the gate on-voltage can be the gate high voltage VGH, and the gate off-voltage can be the gate low voltage VGL.

[0058] In the following description, various embodiments of this disclosure will be described with reference to the accompanying drawings. While the following embodiments will primarily describe display devices with respect to organic light-emitting display devices, this disclosure is not limited thereto. Furthermore, the scope of this disclosure is not intended to be limited by the names of components or signals in the following embodiments and claims.

[0059] Reference Figure 1 and Figure 2 The display device according to embodiments of the present disclosure includes: a display panel 100; a display panel driver for writing pixel data to pixels of the display panel 100; and a power supply 140 for generating power required to drive the pixels and the display panel driver.

[0060] Display panel 100 may be a panel having a rectangular structure with a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. Display panel 100 includes a pixel array for displaying an input image on the screen. The pixel array includes multiple data lines 102, multiple gate lines 103 intersecting the data lines 102, and pixels arranged in a matrix. Display panel 100 may also include power lines commonly connected to the pixels. The power lines provide a constant voltage required to drive the pixels 101. For example, display panel 100 may include a VDD line to which a pixel driving voltage ELVDD is applied and a VSS line to which a low-potential power supply voltage ELVSS is applied. Furthermore, the power lines may also include a REF line to which a reference voltage Vref is applied and an INIT line to which an initialization voltage Vinit is applied.

[0061] like Figure 2 As shown, the cross-sectional structure of the display panel 100 may include a circuit layer 12, a light-emitting element layer 14, and an encapsulation layer 16 stacked on the substrate 10.

[0062] Circuit layer 12 may include: a TFT array including pixel circuitry connected to wiring such as data lines, gate lines, power lines, etc.; a demultiplexer array 112; a gate driver 120, etc. The wiring and circuit elements of circuit layer 12 may include: multiple insulating layers; two or more metal layers separated by an insulating layer; and an active layer comprising semiconductor material. All transistors formed in circuit layer 12 can be implemented as n-channel oxide TFTs.

[0063] The light-emitting element layer 14 may include light-emitting elements EL driven by pixel circuitry. The light-emitting elements EL may include red (R) light-emitting elements, green (G) light-emitting elements, and blue (B) light-emitting elements. In another embodiment, the light-emitting element layer 14 may include white light-emitting elements and color filters. The light-emitting elements EL of the light-emitting element layer 14 may be covered by multiple protective layers in which organic and inorganic layers are stacked.

[0064] Encapsulation layer 16 covers light-emitting element layer 14 to seal circuit layer 12 and light-emitting element layer 14. Encapsulation layer 16 may also have a multilayer insulating film structure in which organic and inorganic films are stacked alternately. The inorganic film blocks the penetration of moisture and oxygen. The organic film planarizes the surface of the inorganic film. When organic and inorganic layers are stacked in multiple layers, the movement path of moisture or oxygen becomes longer than that of a single layer, thereby effectively blocking the penetration of moisture and oxygen that affect light-emitting element layer 14.

[0065] The touch sensor layer, omitted from the accompanying drawings, can be formed on the encapsulation layer 16, and a polarizer or color filter layer can be disposed on the touch sensor layer. The touch sensor layer may include a capacitive touch sensor that senses touch input based on capacitance changes before and after the touch input. The touch sensor layer may include an insulating layer and a metal wiring pattern forming the capacitor of the touch sensor. The insulating layer can insulate the intersections of the metal wiring pattern and can planarize the surface of the touch sensor layer. The polarizer can improve visibility and contrast by converting the polarization of external light reflected by the metal of the touch sensor layer and the circuit layer. The polarizer can be implemented as a circular polarizer or a polarizer combining a linear polarizer and a phase retardation film. A cover glass can be adhered to the polarizer. The color filter layer may include red, green, and blue color filters. The color filter layer may also include a black matrix pattern. The color filter layer absorbs a portion of the wavelengths of light reflected from the circuit layer and the touch sensor layer, thereby replacing the polarizer and increasing the color purity of the image reproduced in the pixel array.

[0066] The pixel array comprises multiple pixel lines L1 to Ln. Each of pixel lines L1 to Ln comprises a row of pixels arranged along the row direction (X-axis direction) in the pixel array of the display panel 100. Pixels arranged in a pixel row share a gate line 103. Sub-pixels arranged along the data line direction in the column direction Y share the same data line 102. A horizontal time period is obtained by dividing a frame time period by the total number of pixel lines L1 to Ln.

[0067] The display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. A transmissive display panel can be used in transparent display devices that display images on a screen while allowing the actual background to be seen. The display panel 100 can be manufactured as a flexible display panel.

[0068] Each of pixel 101 can be divided into red, green, and blue sub-pixels to achieve color. Each pixel may also include a white sub-pixel. Each sub-pixel includes pixel circuitry. In the following text, "pixel" can be interpreted as having the same meaning as "sub-pixel." Each pixel circuit is connected to data lines, gate lines, and power lines.

[0069] Pixels can be arranged as real-color pixels and pentile pixels. Pentile pixels can achieve higher resolution than real-color pixels by using a preset pixel rendering algorithm to drive two sub-pixels with different colors as a single pixel 101. The pixel rendering algorithm can compensate for the insufficient color representation in each pixel by using the colors of light emitted from neighboring pixels.

[0070] Power supply 140 generates the direct current (DC) voltage (or constant voltage) required to drive the pixel array and display panel driver of display panel 100 using a DC-DC converter. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc. Power supply 140 generates the DC voltage (or constant voltage) by adjusting the level of the DC input voltage applied from the host system (not shown), such as gamma reference voltage VGMA, gate on voltage VGH, gate off voltage VGL, pixel drive voltage ELVDD, low-level power supply voltage ELVSS, initialization voltage Vinit, reference voltage Vref, etc. The gamma reference voltage VGMA is provided to data driver 110. The gate on voltage VGH and gate off voltage VGL are provided to gate driver 120. Constant voltages such as pixel drive voltage ELVDD, low-level power supply voltage ELVSS, initialization voltage Vinit, reference voltage Vref, etc., are provided to pixel 101 via power lines connected to pixel 101 via a common ground. The constant voltage applied to the pixel circuitry may have different voltage levels.

[0071] Under the control of the timing controller 130, the display panel driver writes the pixel data of the input image into the pixels of the display panel 100.

[0072] The display panel driver includes a data driver 110 and a gate driver 120. The display panel driver may also include a demultiplexer array 112 disposed between the data driver 110 and the data line 102.

[0073] The demultiplexer array 112 uses multiple demultiplexers (DEMUX) to sequentially provide data voltages output from the channels of the data driver 110 to the data line 102. The demultiplexers may include multiple switching elements disposed on the display panel 100. When the demultiplexers are disposed between the output terminals of the data driver 110 and the data line 102, the number of channels of the data driver 110 can be reduced. The demultiplexer array 112 may be omitted.

[0074] The display panel driver may also include a touch sensor driver for driving the touch sensor. Figure 1 The touch sensor driver is omitted. The data driver 110 and the touch sensor driver can be integrated into a single driver integrated circuit (IC). In mobile or wearable devices, the timing controller 130, power supply 140, data driver 110, etc., can be integrated into a single driver IC.

[0075] The display panel driver can operate in a low-speed drive mode under the control of the timing controller 130. By analyzing the input image, the low-speed drive mode can be set when the input image does not change a preset number of frames, thereby reducing the power consumption of the display device. In the low-speed drive mode, when a still image is input for a predetermined time or longer, the power consumption of the display panel driver and the display panel 100 can be reduced by decreasing the pixel refresh rate. The low-speed drive mode is not limited to inputting a still image. For example, when the display device operates in standby mode, or when a user command or input image is not input to the display panel driver circuit for a predetermined time or longer, the display panel driver circuit can operate in the low-speed drive mode.

[0076] Data driver 110 receives pixel data of the input image as a digital signal from timing controller 130 and outputs a data voltage. Data driver 110 generates the data voltage Vdata by converting the pixel data of the input image into a gamma-compensated voltage at each frame interval using a digital-to-analog converter (DAC). The gamma reference voltage VGMA is divided into gamma-compensated voltages for each grayscale level by a voltage divider circuit. The gamma-compensated voltage for each grayscale level is provided to the DAC of data driver 110. The data voltage Vdata is output from each channel of data driver 110 through an output buffer.

[0077] The gate driver 120 can be implemented as an in-board gate (GIP) circuit formed together with the wiring of the TFT array and pixel array in the circuit layer 12 on the display panel 100. The gate driver 120 can be disposed on the bezel BZ, which is a non-display area of ​​the display panel 100, or it can be distributed in the pixel array that reproduces the input image. Under the control of the timing controller 130, the gate driver 120 sequentially outputs gate signals to the gate line 103. The gate driver 120 can sequentially provide gate signals to the gate line 103 while shifting the gate signals using a shift register. The gate signals can include various gate pulses, such as scan pulses, sensing pulses, initialization pulses, light emission control pulses (hereinafter referred to as "EM pulses"), etc.

[0078] The gate driver 120 also includes: a shift register for outputting a gate signal; and a light emission control signal generator (hereinafter referred to as the "generator") 122, which receives the gate signal output from the shift register and generates an EM pulse. During periods when ripple of the low-potential power supply voltage ELVSS applied to the pixel 100 can be generated, the EM pulse can be generated as a gate turn-off voltage to prevent the supply of current EL to the light-emitting element, thereby mitigating the ripple defects of the low-potential power supply voltage. The gate signal output from the shift register of the gate driver 120 can be applied to a gate line, and the EM pulse output from the EM generator 122 can be applied to another gate line.

[0079] The timing controller 130 receives digital video data DATA of the input image from the host system, as well as timing signals synchronized with the digital video data DATA. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock CLK, and a data enable signal DE. Since the vertical and horizontal time periods can be determined by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE has a period of one horizontal time period (1H).

[0080] The host system can be any of a TV system, tablet computer, laptop computer, navigation system, personal computer (PC), home theater system, mobile device, wearable device, or vehicle system. The host system can scale the image signal from the video source to fit the resolution of the display panel 100 and can transmit it to the timing controller 130 along with timing signals.

[0081] In normal drive mode, timing controller 130 can multiply the input frame frequency by i (where i is a natural number), thereby controlling the operation timing of the display panel driver at a frame frequency of input frame frequency × i Hz. The input frame frequency is 60 Hz in the NTSC (National Television Standards Committee) scheme and 50 Hz in the PAL (Intersecting Lines) scheme.

[0082] Compared to the normal drive mode, the timing controller 130 reduces the frequency of the frame rate at which pixel data is written to pixels in the low-speed drive mode. For example, in the normal drive mode, the data refresh frame frequency for writing pixel data to pixels can occur at a frequency of 60Hz or higher, such as any of 60Hz, 120Hz, and 144Hz, and the data refresh frame (DRF) in the low-speed drive mode can occur at a lower refresh rate than in the normal drive mode. For example, in the low-speed drive mode, the timing controller 130 can reduce the drive frequency of the display panel driver by reducing the frame frequency to a frequency between 1Hz and 30Hz, thereby reducing the pixel refresh rate.

[0083] The timing controller 130 generates, based on timing signals Vsync, Hsync, and DE received from the host system, a data timing control signal for controlling the operation timing of the data driver 110, a control signal for controlling the operation timing of the demultiplexer array 112, and a gate timing control signal for controlling the operation timing of the gate driver 120. The timing controller 130 controls the operation timing of the display panel driver to synchronize the data driver 110, the demultiplexer array 112, the touch sensor driver, and the gate driver 120.

[0084] The gate timing control signal generated from the timing controller 130 can be input to the shift register of the gate driver 120 via a level shifter (not shown). The level shifter can receive the gate timing control signal, generate a start pulse and a shift clock, and provide them to the shift register.

[0085] Figure 3 This is a diagram illustrating a shift register of a gate driver according to an embodiment of the present disclosure, and an EM generator connected to the output node of the shift register. Figure 4 It shows Figure 3 The waveform diagram of the input / output signals of the shift register is shown in the figure.

[0086] Reference Figure 3 and Figure 4 Gate driver 120 includes a shift register that sequentially outputs gate signals Gout(n-1) to Gout(n+2) in synchronization with the shift clock CLK. The gate signals may include any of a scan pulse, a sense pulse, and an initialization pulse. Gate driver 120 may include multiple shift registers that output different gate signals. Figure 3 As shown, each of the shift registers receives the start signal VST and the shift clocks CLK1 to CLK4, outputs the gate signal, and shifts the gate signal synchronously with the shift clock.

[0087] The shift register includes signal transfer sections ST(n-1) to ST(n+2) connected in relation to each other. Each of the signal transfer sections ST(n-1) to ST(n+2) includes a VST node to which the start signal VST is input, a CLK node to which the shift clocks CLK1 to CLK4 are input, and so on.

[0088] The start signal VST is typically input to the first signal transmission section. Figure 3 In this context, the (n-1)th signal transmission section ST(n-1) can be the first signal transmission section that receives the start signal VST. The shift clocks CLK1 to CLK4 can be as follows: Figure 4 The four-phase clock shown can be replaced by, for example, a shift clock, which can be a k-phase clock (where k is a natural number).

[0089] The signal transmission sections ST(n) to ST(n+2), which are connected to the (n-1)th signal transmission section ST(n-1), receive the carry signal CAR as a start signal from the previous signal transmission section and begin to be driven. The signal transmission sections ST(n-1) to ST(n+2) can output gate signals Gout(n-1) to Gout(n+2) respectively through output nodes, and can simultaneously output the carry signal CAR through other output nodes.

[0090] The buffer BUF includes a first transistor TR1 and a second transistor TR2 connected to the output node from which the gate signal is output, and outputs one of the gate signals Gout(n-1) to Gout(n+2) through the output node. The output node is connected to the gate line 103 and to the input node of the EM generator 122.

[0091] The first transistor TR1 is a pull-up transistor, and the second transistor TR2 is a pull-down transistor. The first transistor TR1 includes a gate electrode connected to a first control node Q, a first electrode connected to a first power node to which a gate drive voltage GVDD is applied, and a second electrode connected to an output node. The second transistor TR2 is connected to the first transistor TR1, with the output node located therebetween. The second transistor TR2 includes a gate electrode connected to a second control node QB, a first electrode connected to the output node, and a second electrode connected to a second power node to which a gate reference voltage GVSS is applied.

[0092] An EM generator 122 is connected between the output node of the shift register and the gate line to which the EM pulse is applied. The EM generator 122 can be connected to each of the output nodes of the shift register. The EM generator 122 can receive gate signals Gout(n-1) to Gout(n+2) output from the shift register and can output EM pulses EM(n-1) to EM(n+2) in response to the gate signals Gout(n-1) to Gout(n+2). The (n-1)th EM generator 122 outputs the (n-1)th EM pulse EM(n-1) in response to the (n-1)th gate signal Gout(n-1). The nth EM generator 122 outputs the nth EM pulse EM(n) in response to the nth gate signal Gout(n). The (n+1)th EM generator 122 outputs the (n+1)th EM pulse EM(n+1) in response to the (n+1)th gate signal Gout(n+1). A gate drive voltage VDD and a gate reference voltage VSS are input to each of the EM generators 122. The EM pulse EM(n-1) to EM(n+2) oscillates between the gate drive voltage VDD and the gate reference voltage VSS.

[0093] Since the EM generator 122 does not operate as a shift register, it does not need to receive the start signal and shift clock.

[0094] The gate drive voltages GVDD and VDD applied to the shift register of gate driver 120 and EM generator 122 can be set to the gate turn-on voltage VGH. The gate reference voltages GVSS and VSS can be set to the gate turn-off voltage VGL.

[0095] Due to variations in device characteristics and processes during the manufacturing of the display panel 100, differences may exist in the electrical characteristics of the driving elements between pixels, and these differences may increase over time as the pixels drive. To compensate for these variations in the electrical characteristics of the driving elements between pixels, an internal compensation circuit can be built into the pixel circuit, or an external compensation circuit can be connected to the pixel circuit. The internal compensation circuit samples the electrical characteristics of the driving element of each sub-pixel using an internal compensation circuit implemented in each pixel circuit, and compensates for the gate-source voltage Vgs of the driving element using these electrical characteristics. The external compensation circuit compensates for the variations in the electrical characteristics of the driving element by generating a compensation value based on the result of sensing the electrical characteristics of the driving element using an external compensation circuit connected to the pixel circuit.

[0096] Figures 5 to 23 This is a diagram illustrating various pixel circuits and their driving signals that can be used for pixels in this disclosure.

[0097] Figure 5 This is a circuit diagram illustrating a pixel circuit according to a first embodiment of the present disclosure. Figure 6 It shows that it is applied to Figure 5 The waveform diagram of the gate signal of the pixel circuit shown is shown. Figure 7 This shows that generation is applied to Figure 5 The circuit diagram shows the EM generator 122 for the EM pulse EM(n) of the pixel circuit shown. The gate signals include the scan pulse SCAN(n) and the EM pulse EM(n).

[0098] Reference Figure 5 and Figure 6 The pixel circuit includes: a light-emitting element EL; a driving element DT configured to supply current to the light-emitting element EL; a first switching element M01 configured to supply a data voltage Vdata to the gate electrode of the driving element DT in response to a scan pulse SCAN(n); a second switching element M02 configured to block the current path between the driving element DT and the light-emitting element EL in response to an EM pulse EM(n); and a capacitor Cst connected between a second node DRG and a third node DRS. In this pixel circuit, the driving element DT and the switching elements M01 and M02 can be implemented as an n-channel oxide TFT.

[0099] A constant voltage, such as the pixel drive voltage ELVDD or the low-level supply voltage ELVSS, is applied to the pixel circuit. The pixel drive voltage ELVDD is higher than the low-level supply voltage ELVSS. The gate turn-on voltage VGH can be set to a voltage higher than the pixel drive voltage ELVDD. The gate turn-off voltage VGL can be set to a voltage lower than the low-level supply voltage ELVSS.

[0100] Gate driver 120 may include a shift register that sequentially outputs scan pulses SCAN(n). EM generator 122 may, as... Figure 6 and Figure 7 As shown, a small number of transistors are used to generate the EM pulse EM(n).

[0101] A light-emitting element (EL) can be implemented as an OLED comprising an anode electrode, a cathode electrode, and an organic compound layer connecting these electrodes. The organic compound layer includes, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emissive layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). When a voltage is applied to the anode and cathode electrodes, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the emissive layer (EML) to form excitons, thereby emitting visible light from the emissive layer (EML). The anode electrode of the EL can be connected to the second electrode of a second switching element MO2, and its cathode electrode can be applied with a low-potential power supply voltage ELVSS. The OLED used as a light-emitting element (EL) can have a tandem structure in which multiple emissive layers are stacked. The tandem structure of the OLED can improve pixel brightness and lifetime.

[0102] The driving element DT generates a current I to drive the light-emitting element EL based on the gate-source voltage Vgs. EL The driving element DT includes a gate electrode connected to the second node DRG, a first electrode connected to the first node DRD to which the pixel driving voltage ELVDD is applied, and a second electrode connected to the third node DRS. A capacitor Cst is connected between the second node DRG and the third node DRS to store the gate-source voltage Vgs of the driving element DT.

[0103] The scan pulse SCAN(n) oscillates between the gate on-state voltage VGH and the gate off-state voltage VGL. The scan pulse SCAN generates the gate on-state voltage VGH during the data addressing step ADDR. The first switching element M01 is turned on according to the gate on-state voltage VGH of the scan pulse SCAN(n) to provide the data voltage Vdata to the second node DRG. The first switching element M01 includes a gate electrode connected to the first gate line to which the scan pulse SCAN(n) is applied, a first electrode connected to the data line to which the pixel data data voltage Vdata is applied, and a second electrode connected to the second node DRG.

[0104] The EM pulse EM(n) oscillates between the gate turn-on voltage VGH and the gate turn-off voltage VGL. The EM pulse EM(n) generates the gate turn-off voltage VGL during the data addressing step ADDR and the gate turn-on voltage VGH during the light emission step EMIS. During the data addressing step ADDR, the second switching element MO2 is turned off according to the gate turn-off voltage VGL of the EM pulse EM(n), thus blocking the current path between the driving element DT and the light-emitting element EL. During the light emission step EMIS, the second switching element MO2 is turned on according to the gate turn-on voltage VGH of the EM pulse EM(n), thus forming a current path between the driving element DT and the light-emitting element EL. In this case, the light-emitting element EL can be affected by the current I from the driving element DT. EL Light emission. The second switching element M02 includes a gate electrode connected to the second gate line to which the EM pulse EM(n) is applied, a first electrode connected to the third node DRS, and a second electrode connected to the anode electrode of the light-emitting element EL.

[0105] When the scan pulse SCAN(n) is inverted to the gate on-state voltage VGH, capacitive coupling through parasitic capacitance may generate ripple in the low-potential supply voltage ELVSS. The emission pulse EM(n) is generated as an inverted pulse relative to the scan pulse SCAN(n), thereby preventing current from being applied to the light-emitting element EL when ripple is generated in the low-potential supply voltage ELVSS. In this case, since the light-emitting element EL cannot emit light, brightness variations in the light-emitting element EL caused by the ripple of the low-potential supply voltage ELVSS can be prevented.

[0106] EM generator 122 may include Figure 7 The circuit shown.

[0107] Reference Figure 7 The EM generator 122 includes a first EM switching element T01 and a second EM switching element T02. The first EM switching element T01 provides the gate drive voltage VDD to the output node connected to the second gate line. Switching elements T01 and T02 can be implemented as n-channel oxide TFTs.

[0108] A gate drive voltage VDD is applied to the first electrode of the first EM switching element T01. The gate drive voltage VDD can be the gate turn-on voltage VGH. The gate electrode and the second electrode of the first EM switching element T01 are connected to the output node. The second EM switching element T02 is turned on according to the gate turn-on voltage VGH of the scan pulse SCAN(n) to discharge the voltage of the output node to the gate reference voltage VSS. The gate reference voltage VSS can be the gate turn-off voltage VGL. The second EM switching element T02 includes a gate electrode to which the scan pulse SCAN(n) is applied, a first electrode connected to the output node, and a second electrode connected to the VSS node to which the gate reference voltage VSS is applied. Therefore, the EM generator 122 can generate an EM pulse EM(n) that is inversely phase to the scan pulse SCAN(n) in response to the scan pulse SCAN(n).

[0109] To drive Figure 5 The pixel circuit shown includes a gate driver 120 comprising a shift register for outputting a scan pulse SCAN(n) and an EM generator 122 comprising two switching elements T01 and T02. The gate driver 120 does not require a separate shift register to output and shift the EM pulse EM(n). Therefore, the bezel BZ of the display panel 100 can be narrowed due to the reduced circuit area occupied by the gate drive circuit.

[0110] Figures 8 to 13 This diagram illustrates a pixel circuit connected to an external compensation circuit and an EM generator that generates EM pulses applied to the pixel circuit. The external compensation circuit includes: a REF line RL connected to the pixel circuit; and an analog-to-digital converter (ADC) that converts the sensed voltage stored in the REF line RL into digital data. The sensed voltage may include electrical characteristics of the driving element DT, such as threshold voltage and / or mobility. An integrator may be connected to the input terminal of the ADC. The timing controller 130 employing the external compensation circuit can generate a compensation value to compensate for changes in the electrical characteristics of the driving element DT based on the sensed data input from the ADC, and can compensate for changes in the electrical characteristics of the driving element DT by adding or multiplying the compensation value with pixel data of the input image. The ADC may be integrated into the data driver 110.

[0111] Figure 8 This is a circuit diagram illustrating a pixel circuit according to a second embodiment of the present disclosure. Figure 9 It shows that it was applied to Figure 8 The waveform diagram of the gate signal of the pixel circuit shown is shown. Figure 10 This shows that generation is applied to Figure 8The circuit diagram shows the EM generator 122 for the EM pulse EM(n) of the pixel circuit shown. In this embodiment, the gate signals include the scan pulse SCAN(n), the sensing pulse SENSE(n), and the EM pulse EM(n).

[0112] Reference Figure 8 and Figure 9 The pixel circuit includes: a light-emitting element EL; a driving element DT configured to supply current to the light-emitting element EL; a first switching element M11 configured to supply a data voltage Vdata to the gate electrode of the driving element DT in response to a scan pulse SCAN(n); a second switching element M12 configured to block the current path between the driving element DT and the light-emitting element EL in response to an EM pulse EM(n); a third switching element M13 configured to connect a third node DRS to the REF line RL in response to a sensing pulse SENSE(n); and a capacitor Cst connected between the second node DRG and the third node DRS. In this pixel circuit, the driving element DT and the switching elements M11, M12, and M13 can be implemented as an n-channel oxide TFT.

[0113] A constant voltage, such as the pixel drive voltage ELVDD or the low-level supply voltage ELVSS, is applied to the pixel circuit. The pixel drive voltage ELVDD is higher than the low-level supply voltage ELVSS. The gate turn-on voltage VGH can be set to a voltage higher than the pixel drive voltage ELVDD. The gate turn-off voltage VGL can be set to a voltage lower than the low-level supply voltage ELVSS. The reference voltage Vref can be set to a low-level voltage close to the low-level supply voltage ELVSS.

[0114] The driving phase of a pixel circuit can be divided into the initialization step (INIT), the programming step (PR), the sensing step (SENSE), the sampling step (SMPL), and the emission step (EMIS).

[0115] The scan pulse SCAN(n) is synchronized with the pixel data voltage Vdata and is generated as the gate on-state voltage VGH in the programming step PR. The scan pulse SCAN(n) may rise to the gate on-state voltage VGH near the end of the initialization step INIT. The scan pulse SCAN(n) is the gate off-state voltage VGL in the sensing step SENSE, sampling step SMPL, and emission step EMIS. The sensing pulse SENSE(n) rises to the gate on-state voltage VGH in the initialization step INIT and maintains the gate on-state voltage VGH during the programming step PR and the sensing step SENSE. The sensing pulse SENSE(n) is the gate off-state voltage VGL in the sampling step SMPL and the emission step EMIS.

[0116] The EM pulse EM(n) is generated inversely to the sensing pulse SENSE(n). Therefore, the EM pulse EM(n) is inverted to the gate turn-off voltage VGL in the initialization step INIT to maintain the gate turn-off voltage VGL during the programming step PR and the sensing step SENSE. The EM pulse EM(n) is the gate turn-on voltage VGH in the sampling step SMPL and the emission step EMIS.

[0117] The reference voltage switching element SPRE and the sampling switching element SAM can be connected to the REF line RL to which the reference voltage Vref is applied. The reference voltage switching element SPRE and the sampling switching element SAM are turned on under the control of the timing controller 130. The reference voltage switching element SPRE is turned on in the initialization step INIT and the programming step PR to provide the reference voltage Vref to the REF line RL. The sampling switching element SAM is turned on in the sampling step SMPL to connect the REF line RL to the ADC.

[0118] The light-emitting element (EL) can be implemented as an OLED comprising an anode electrode, a cathode electrode, and an organic compound layer connected between these electrodes. The anode electrode of the light-emitting element EL can be connected to the second electrode of the second switching element M12, and its cathode electrode can be applied with a low potential power supply voltage ELVSS.

[0119] The driving element DT generates a current to drive the light-emitting element EL based on the gate-source voltage Vgs. The driving element DT includes a gate electrode connected to the second node DRG, a first electrode connected to the first node DRD to which the pixel driving voltage ELVDD is applied, and a second electrode connected to the third node DRS. A capacitor Cst is connected between the second node DRG and the third node DRS.

[0120] In programming step PR, the first switching element M11 is turned on according to the gate turn-on voltage VGH of the scan pulse SCAN(n) to provide the data voltage Vdata to the second node DRG. The first switching element M11 includes a gate electrode connected to the first gate line to which the scan pulse SCAN(n) is applied, a first electrode connected to the data line to which the data voltage Vdata is applied, and a second electrode connected to the second node DRG.

[0121] The second switching element M12 is turned off according to the gate turn-off voltage VGL of the EM pulse EM(n) during the initialization step INIT, programming step PR, and sensing step SENSE, thereby blocking the current path between the driving element DT and the light-emitting element EL. The second switching element M12 is turned on according to the gate turn-on voltage VGH of the EM pulse EM(n) during the light-emitting step EMIS, thereby forming a current path between the driving element DT and the light-emitting element EL. The second switching element M12 includes a gate electrode connected to the second gate line to which the EM pulse EM(n) is applied, a first electrode connected to the third node DRS, and a second electrode connected to the anode electrode of the light-emitting element EL.

[0122] The third switching element M13 is turned on during the programming step PR and the sensing step SENSE according to the gate on-state voltage VGH of the sensing pulse SENSE(n), so as to connect the REF line RL to which the reference voltage Vref is applied to the third node DRS. In the sensing step SENSE, the voltage of the third node DRS is stored in the capacitor Csen of the REF line RL, such that the electrical characteristics of the driving element DT are stored in the REF line RL, and the voltage of the REF line RL is converted into digital data by the ADC in the sampling step SMPL. The third switching element M13 includes a gate electrode connected to the third gate line to which the sensing pulse SENSE(n) is applied, a first electrode connected to the third node DRS, and a second electrode connected to the REF line RL.

[0123] When the sensing pulse SENSE(n) is inverted to the gate on-state voltage VGH, ripple may be generated in the low-potential supply voltage ELVSS due to capacitive coupling via parasitic capacitance. The emission pulse EM(n) is generated as an inverted pulse relative to the sensing pulse SENSE(n), thereby preventing current from being applied to the light-emitting element EL when ripple may be generated in the low-potential supply voltage ELVSS. In this case, since the light-emitting element EL cannot emit light, brightness variations in the light-emitting element EL caused by the ripple of the low-potential supply voltage ELVSS can be prevented.

[0124] EM generator 122 may include Figure 10 The circuit shown.

[0125] Reference Figure 10 The EM generator 122 includes a first EM switching element T11 and a second EM switching element T12. The switching elements T11 and T12 can be implemented as n-channel oxide TFTs.

[0126] The first EM switching element T11 provides a gate drive voltage VDD to the output node connected to the second gate line. The gate drive voltage VDD is applied to the first electrode of the first EM switching element T11. The gate drive voltage VDD can be a gate turn-on voltage VGH. The gate electrode and the second electrode of the first EM switching element T11 are connected to the output node. The second EM switching element T12 turns on according to the gate turn-on voltage VGH of the sensing pulse SENSE(n) to discharge the voltage of the output node to the gate reference voltage VSS. The gate reference voltage VSS can be a gate turn-off voltage VGL. The second EM switching element T12 includes a gate electrode to which the sensing pulse SENSE(n) is applied, a first electrode connected to the output node, and a second electrode connected to the VSS node. Therefore, the EM generator 122 can generate an EM pulse EM(n) that is inversely phase to the sensing pulse SENSE(n) in response to the sensing pulse SENSE(n).

[0127] To drive Figure 8 The pixel circuit shown may include a gate driver 120 that sequentially outputs scan pulses SCAN(n) and a second shift register that sequentially outputs sensing pulses SENSE(n). The EM generator 122 may be as follows: Figure 9 and Figure 10 As shown, a small number of transistors are used to generate the EM pulse EM(n). The gate driver 120 does not require a separate shift register to output and shift the EM pulse EM(n). Therefore, the bezel BZ of the display panel 100 can be narrowed because the circuit area occupied by the gate drive circuit is reduced.

[0128] Figure 11 This is a circuit diagram illustrating a pixel circuit according to a third embodiment of the present disclosure. Figure 12 It shows that it is applied to Figure 11 The waveform diagram of the gate signal of the pixel circuit shown is shown. Figure 13 It shows the generation applied to Figure 11 The diagram shows the circuit diagram of the EM generator 122 for the EM pulse EM(n) of the pixel circuit shown. In this embodiment, the gate signal includes the scan pulse SCAN(n) and the EM pulse EM(n). The pixel circuit according to the third embodiment of this disclosure is substantially the same as the pixel circuit of the second embodiment, except that the second switching element M21 and the third switching element M23 are simultaneously turned on / off in response to the scan pulse SCAN(n). In the pixel circuit according to the third embodiment of this disclosure, detailed descriptions of parts substantially the same as those in the second embodiment described above will be omitted.

[0129] Reference Figure 11 and Figure 12The pixel circuit includes: a light-emitting element EL; a driving element DT configured to supply current to the light-emitting element EL; a first switching element M21 configured to supply a data voltage Vdata to the gate electrode of the driving element DT in response to a scan pulse SCAN(n); a second switching element M22 configured to block the current path between the driving element DT and the light-emitting element EL in response to an EM pulse EM(n); a third switching element M23 configured to connect a third node DRS to the REF line RL in response to a scan pulse SCAN(n); and a capacitor Cst connected between the second node DRG and the third node DRS. In this pixel circuit, the driving element DT and the switching elements M21, M22, and M23 can be implemented as an n-channel oxide TFT.

[0130] The scan pulse SCAN(n) is generated as the gate on-state voltage VGH in the programming step PR, sensing step SENSE, and sampling step SMPL. The scan pulse SCAN(n) is the gate off-state voltage VGL in the initialization step INIT and emission step EMIS. The EM pulse EM(n) is generated in reverse phase with the scan pulse SCAN(n). Therefore, the EM pulse EM(n) is generated as the gate off-state voltage VGL in the programming step PR, sensing step SENSE, and sampling step SMPL. The EM pulse EM(n) is the gate on-state voltage VGH in the initialization step INIT and emission step EMIS.

[0131] The reference voltage switching element SPRE is turned on during the initialization step INIT and programming step PR to provide the reference voltage Vref to the REF line RL. The sampling switching element SAM is turned on during the sampling step SMPL to connect the REF line RL to the ADC.

[0132] The first switching element M21 is turned on according to the gate on-state voltage VGH of the scan pulse SCAN(n) during the programming step PR, the sensing step SENSE, and the sampling step SMPL, so as to connect the second node DRG to the data line to which the data voltage Vdata is applied. The first switching element M21 includes a gate electrode connected to the first gate line to which the scan pulse SCAN(n) is applied, a first electrode connected to the data line to which the data voltage Vdata is applied, and a second electrode connected to the second node DRG.

[0133] The second switching element M22 is turned off during the programming step PR, sensing step SENSE, and sampling step SMPL according to the gate turn-off voltage VGL of the EM pulse EM(n) to block the current path between the driving element DT and the light-emitting element EL. During the light-emitting step EMIS, the second switching element M22 is turned on according to the gate turn-on voltage VGH of the EM pulse EM(n) to form a current path between the driving element DT and the light-emitting element EL. The second switching element M22 includes a gate electrode connected to the second gate line to which the EM pulse EM(n) is applied, a first electrode connected to the third node DRS, and a second electrode connected to the anode electrode of the light-emitting element EL.

[0134] The third switching element M23 is turned on according to the gate on-state voltage VGH of the scan pulse SCAN(n) during the programming step PR, the sensing step SENSE, and the sampling step SMPL, so as to connect the third node DRS to the REF line RL to which the reference voltage Vref is applied. The third switching element M23 includes a gate electrode connected to the first gate line to which the scan pulse SCAN(n) is applied, a first electrode connected to the third node DRS, and a second electrode connected to the REF line RL.

[0135] When the scan pulse SCAN(n) is inverted to the gate on-state voltage VGH, ripple may be generated in the low-potential supply voltage ELVSS. The light-emitting pulse EM(n) is generated as an inverted pulse relative to the scan pulse SCAN(n), thereby preventing current from being applied to the light-emitting element EL when ripple is generated in the low-potential supply voltage ELVSS.

[0136] EM generator 122 may include Figure 13 The circuit shown.

[0137] Reference Figure 13 The EM generator 122 includes a first EM switching element T21 and a second EM switching element T22. The switching elements T21 and T22 can be implemented as n-channel oxide TFTs.

[0138] The first EM switching element T21 provides a gate drive voltage VDD to the output node connected to the second gate line. The gate drive voltage VDD is applied to the first electrode of the first EM switching element T21. The gate drive voltage VDD can be the gate turn-on voltage VGH. The gate electrode and the second electrode of the first EM switching element T21 are connected to the output node. The second EM switching element T22 turns on according to the gate turn-on voltage VGH of the scan pulse SCAN(n) to discharge the voltage of the output node to the gate reference voltage VSS. The gate reference voltage VSS can be the gate turn-off voltage VGL. Therefore, the EM generator 122 can generate an EM pulse EM(n) that is inversely phase to the scan pulse SCAN(n) in response to the scan pulse SCAN(n).

[0139] To drive Figure 11 The pixel circuit shown may include a gate driver 120 that sequentially outputs scan pulses SCAN(n), and includes, for example, a shift register. Figure 13 The EM generator 122 shown is a small number of transistors. The EM generator 122 can be used as follows: Figure 12 and Figure 13 As shown, a small number of transistors are used to generate the EM pulse EM(n). The gate driver 120 does not require a separate shift register to output and shift the EM pulse EM(n). Therefore, the bezel BZ of the display panel 100 can be narrowed because the circuit area occupied by the gate drive circuit is reduced.

[0140] Figures 14 to 16 This is a diagram showing the pixel circuit, including the internal compensation circuitry, and its driving signals. Figure 14 This is a circuit diagram illustrating a pixel circuit according to a fourth embodiment of the present disclosure.

[0141] Figure 15 It shows that it is applied to Figure 14 The waveform diagram of the gate signal of the pixel circuit shown is shown. Figure 16 This shows that generation is applied to Figure 14 The circuit diagram shows the EM generator 122 for the EM pulse EM(n) of the pixel circuit shown. In this embodiment, the gate signals include the initialization pulse INIT(n), the scan pulse SCAN(n), the sensing pulse SENSE(n), and the EM pulse EM(n).

[0142] Reference Figure 14 and Figure 15 The pixel circuit includes: a light-emitting element EL; a driving element DT configured to supply current to the light-emitting element EL; a first switching element M31 configured to supply a data voltage Vdata to the gate electrode of the driving element DT in response to a scan pulse SCAN(n); a second switching element M32 configured to block the current path between the driving element DT and the light-emitting element EL in response to an EM pulse EM(n); a third switching element M33 configured to connect a third node DRS to the REF line RL in response to a sensing pulse SENSE(n); a fourth switching element M34 configured to provide an initialization voltage Vinit to a second node DRG in response to an initialization pulse INIT(n); and a capacitor Cst connected between the second node DRG and the third node DRS. In this pixel circuit, the driving element DT and the switching elements M31 to M34 can be implemented as an n-channel oxide TFT.

[0143] A constant voltage, such as the pixel drive voltage ELVDD, the low-level supply voltage ELVSS, the reference voltage Vref, and the initialization voltage Vinit, is applied to the pixel circuit. The pixel drive voltage ELVDD is higher than the low-level supply voltage ELVSS. The gate turn-on voltage VGH can be set to a voltage higher than the pixel drive voltage ELVDD. The gate turn-off voltage VGL can be set to a voltage lower than the low-level supply voltage ELVSS. The reference voltage Vref can be set to a low-level voltage close to the low-level supply voltage ELVSS. The initialization voltage Vinit can be set to a voltage that turns on the driving element DT.

[0144] The driving phase of the pixel circuit can be divided into the initialization step (INIT), the sensing step (SENSE), the addressing step (WR), the boosting step (BOOST), and the emission step (EMIS). In the initialization step (INIT), the driving element DT is turned on. In the sensing step (SENSE), when the voltage of the third node DRS rises and the gate-source voltage Vgs of the driving element DT becomes lower than the threshold voltage Vth, the driving element DT is turned off. When the driving element DT is turned off in the sensing step (SENSE), the threshold voltage Vth of the driving element DT is sampled to the capacitor Cst. When the data voltage Vdata is applied to the second node DRG in the addressing step (WR), the data voltage Vdata compensated by the threshold voltage Vth is applied as the gate voltage of the driving element DT. After the voltages of the floating second node DRG and the third node DRS rise in the boosting step (BOOST), a current for driving the emission element EL is generated from the driving element DT based on the gate-source voltage Vgs compensated by the threshold voltage Vth of the driving element DT.

[0145] The initialization pulse INIT(n) is generated as the gate on-state voltage VGH in the initialization step INIT and the sensing step SENSE. The initialization pulse INIT(n) is the gate off-state voltage VGL in the addressing step WR, the boosting step BOOST, and the emission step EMIS. The scan pulse SCAN(n) is synchronized with the pixel data voltage Vdata and is generated as the gate on-state voltage VGH in the addressing step WR. The scan pulse SCAN(n) is the gate off-state voltage VGL in the initialization step INIT, the sensing step SENSE, the boosting step BOOST, and the emission step EMIS. The sensing pulse SENSE(n) is generated as the gate on-state voltage VGH in the initialization step INIT. The sensing pulse SENSE(n) is the gate off-state voltage VGL in the sensing step SENSE, the addressing step WR, the boosting step BOOST, and the emission step EMIS.

[0146] The EM pulse EM(n) is inverted as the gate turn-on voltage VGH when the sensing pulse SENSE(n) is inverted, and is also inverted as the gate turn-on voltage VGH when the scanning pulse SCAN(n) is inverted. Therefore, the EM pulse EM(n) is generated as the gate turn-off voltage VGL in the initialization step INIT and the sensing step SENSE. The EM pulse EM(n) is the gate turn-on voltage VGH in the addressing step WR, the boost step BOOST, and the emission step EMIS.

[0147] The light-emitting element (EL) can be implemented as an OLED comprising an anode electrode, a cathode electrode, and an organic compound layer connected between these electrodes. The anode electrode of the light-emitting element EL can be connected to the second electrode of the second switching element M32, and its cathode electrode can be applied with a low potential power supply voltage ELVSS.

[0148] The driving element DT generates a current to drive the light-emitting element EL based on the gate-source voltage Vgs. The driving element DT includes a gate electrode connected to the second node DRG, a first electrode connected to the first node DRD to which the pixel driving voltage ELVDD is applied, and a second electrode connected to the third node DRS. A capacitor Cst is connected between the second node DRG and the third node DRS.

[0149] In the addressing step WR, the first switching element M31 is turned on according to the gate on-state voltage VGH of the scan pulse SCAN(n) to provide the data voltage Vdata to the second node DRG. The first switching element M31 includes a gate electrode connected to the first gate line to which the scan pulse SCAN(n) is applied, a first electrode connected to the data line to which the data voltage Vdata is applied, and a second electrode connected to the second node DRG.

[0150] The second switching element M32 is turned off during the initialization step INIT and the sensing step SENSE according to the gate turn-off voltage VGL of the EM pulse EM(n), thereby blocking the current path between the driving element DT and the light-emitting element EL. The second switching element M32 is turned on during the addressing step WR, the boost step BOOST, and the light-emitting step EMIS according to the gate turn-on voltage VGH of the EM pulse EM(n), thereby forming a current path between the driving element DT and the light-emitting element EL. The second switching element M32 includes a gate electrode connected to the second gate line to which the EM pulse EM(n) is applied, a first electrode connected to the third node DRS, and a second electrode connected to the anode electrode of the light-emitting element EL.

[0151] In the initialization step INIT, the third switching element M33 is turned on according to the gate on-state voltage VGH of the sensing pulse SENSE(n) to connect the third node DRS to the REF line RL to which the reference voltage Vref is applied. The third switching element M33 includes a gate electrode connected to the third gate line to which the sensing pulse SENSE(n) is applied, a first electrode connected to the third node DRS, and a second electrode connected to the REF line RL.

[0152] The fourth switching element M34 is turned on according to the gate on-state voltage VGH of the initialization pulse INIT(n) in the initialization step INIT and the sensing step SENSE, so as to provide the initialization voltage Vinit to the second node DRG. The fourth switching element M34 includes a gate electrode connected to the fourth gate line to which the initialization pulse INIT(n) is applied, a first electrode connected to the INI line to which the initialization voltage Vinit is applied, and a second electrode connected to the second node DRG.

[0153] EM generator 122 may include Figure 16 The circuit shown.

[0154] Reference Figure 16 The EM generator 122 includes a first switching element to a sixth switching element T31 to T36. Switching elements T31 and T36 can be implemented as n-channel oxide TFTs.

[0155] When the voltage of the pull-up control node 161 is charged to the gate on-state voltage, the first EM switch element T31 is turned on to provide the gate drive voltage VDD to the output node connected to the second gate line. At this time, the voltage of the EM pulse EM(n) rises to the gate on-state voltage VGH. The gate drive voltage VDD is applied to the first electrode of the first EM switch element T31. The gate drive voltage VDD can be the gate on-state voltage VGH. The first EM switch element T31 includes a gate electrode connected to the pull-up control node 161, a first electrode to which the gate drive voltage VDD is applied, and a second electrode connected to the output node.

[0156] When the pull-down control node 162 is charged to the gate turn-on voltage, the second EM switch element T32 turns on to connect the output node to the VSS node to which the gate reference voltage VSS is applied, and discharges the output node. The gate reference voltage VSS can be the gate turn-off voltage VGL. When the second EM switch element T32 turns on, the voltage of the EM pulse EM(n) drops to the gate turn-off voltage VGL. The second EM switch element T32 includes a gate electrode connected to the pull-down control node 162, a first electrode connected to the output node, and a second electrode connected to the VSS node.

[0157] The third EM switch element T33 is turned on by the gate on-state voltage VGH of the scan pulse SCAN(n) to charge the pull-up control node 161. The fourth EM switch element T34 is turned on by the gate on-state voltage VGH of the sensing pulse SENSE(n) to discharge the pull-up control node 161. When the third EM switch element T33 is on and the fourth EM switch element T34 is off, the first EM switch element T31 is turned on. When the third EM switch element T33 is off and the fourth EM switch element T34 is on, the pull-up control node 161 is discharged, causing the first EM switch element T31 to turn off. When both the third EM switch element T33 and the fourth EM switch element T34 are off, the pull-up control node 161 is floated to maintain its previous state.

[0158] The third EM switching element T33 includes a gate electrode to which a scan pulse SCAN(n) is applied, a first electrode to which a gate drive voltage VDD is applied, and a second electrode connected to a pull-up control node 161. The fourth EM switching element T34 includes a gate electrode to which a sensing pulse SENSE(n) is applied, a first electrode connected to a pull-up control node 161, and a second electrode connected to a VSS node.

[0159] The fifth EM switch element T35 is turned on by the gate on-state voltage VGH of the sensing pulse SENSE(n) to charge the pull-down control node 162. The sixth EM switch element T36 is turned on by the gate on-state voltage VGH of the scan pulse SCAN(n) to discharge the pull-down control node 162. When the fifth EM switch element T35 is on and the sixth EM switch element T36 is off, the second EM switch element T32 is turned on. When the fifth EM switch element T35 is off and the sixth EM switch element T36 is on, the pull-down control node 162 is discharged to turn off the second EM switch element T32. When both the fifth switch element T35 and the sixth EM switch element T36 are off, the pull-down control node 162 is floated to maintain its previous state.

[0160] The fifth EM switching element T35 includes a gate electrode to which a sensing pulse SENSE(n) is applied, a first electrode to which a gate drive voltage VDD is applied, and a second electrode connected to a pull-down control node 162. The sixth EM switching element T36 includes a gate electrode to which a scan pulse SCAN(n) is applied, a first electrode connected to a pull-down control node 162, and a second electrode connected to a VSS node.

[0161] To drive Figure 14The pixel circuit shown includes a gate driver 120 comprising a first shift register for sequentially outputting initialization pulses INIT(n), a second shift register for sequentially outputting scan pulses SCAN(n), and a third shift register for sequentially outputting sensing pulses SENSE(n). The EM generator 122 can be configured as follows: Figure 15 and Figure 16 As shown, a small number of transistors T31 to T36 are used to generate the EM pulse EM(n). The gate driver 120 does not require a separate shift register to output and shift the EM pulse EM(n). Therefore, the bezel BZ of the display panel 100 can be narrowed because the circuit area occupied by the gate drive circuit is reduced.

[0162] Figure 17 This is a circuit diagram illustrating a pixel circuit according to a fifth embodiment of the present disclosure. Figure 18 It shows that it is applied to Figure 17 The waveform diagram of the gate signal of the pixel circuit shown is shown. Figure 19 It shows the generation applied to Figure 17 The circuit diagram shows the EM generator 122 for the second EM pulse EM2(n) of the pixel circuit shown. In this embodiment, the gate signal includes the first scan pulse SCAN1(n), the second scan pulse SCAN2(n), the third scan pulse SCAN3(n), the first EM pulse EM1(n), and the second EM pulse EM2(n).

[0163] Reference Figure 17 and Figure 18 The pixel circuit includes: a light-emitting element EL; a driving element DT configured to supply current to the light-emitting element EL; a first switching element M41 configured to supply a data voltage Vdata to the gate electrode of the driving element DT in response to a first scan pulse SCAN1(n); a second switching element M42 configured to block the current path between the driving element DT and the light-emitting element EL in response to a second EM pulse EM2(n); a third switching element M43 configured to connect a third node DRS to an initialization line INI in response to a third scan pulse SCAN3(n); a fourth switching element M44 configured to supply a reference voltage Vref to a second node DRG in response to a second scan pulse SCAN2(n); a fifth switching element M45 configured to supply a pixel driving voltage ELVDD to a first node DRD in response to a first EM pulse EM1(n); a first capacitor Cst connected between the second node DRG and a fourth node n4; and a second capacitor Cd connected between the fourth node and the VDD node. The VDD node is connected to the VDD line to which the pixel driving voltage ELVDD is applied.

[0164] In this pixel circuit, the driving element DT and the switching elements M31 to M34 can be implemented as an n-channel oxide TFT.

[0165] A constant voltage, such as the pixel drive voltage ELVDD, the low-level supply voltage ELVSS, the reference voltage Vref, and the initialization voltage Vinit, is applied to the pixel circuit. The pixel drive voltage ELVDD is higher than the low-level supply voltage ELVSS. The gate turn-on voltage VGH can be set to a voltage higher than the pixel drive voltage ELVDD. The gate turn-off voltage VGL can be set to a voltage lower than the low-level supply voltage ELVSS. The initialization voltage Vinit can be set to a low-level voltage close to the low-level supply voltage ELVSS. The reference voltage Vref can be set to a voltage that enables the drive element DT to turn on.

[0166] The driving period of this pixel circuit can be divided into the initialization step INIT, the sampling step SMPL, the addressing step WR, and the emission step EMIS.

[0167] The first scan pulse SCAN1(n) is synchronized with the pixel data voltage Vdata and is generated as the gate on-state voltage VGH in the addressing step WR. The first scan pulse SCAN1(n) is the gate off-state voltage VGL in the initialization step INIT, the sampling step SMPL, and the emission step EMIS. The second scan pulse SCAN2(n) is generated as the gate on-state voltage VGH in the initialization step INIT and the sampling step SMPL. The second scan pulse SCAN2(n) is the gate off-state voltage VGL in the addressing step WR and the emission step EMIS. The third scan pulse SCAN3(n) is generated as the gate on-state voltage VGH in the initialization step INIT. The third scan pulse SCAN3(n) is the gate off-state voltage VGL in the sampling step SMPL, the addressing step WR, and the emission step EMIS.

[0168] The first EM pulse EM1(n) is generated as the gate turn-off voltage VGL in the initialization step INIT and the addressing step WR. The first EM pulse EM1(n) is the gate turn-on voltage VGH for the sampling step SMPL and the emission step EMIS.

[0169] The second EM pulse EM2(n) is inverted to the gate turn-off voltage VGL when the third scan pulse SCAN3(n) is inverted to the gate turn-on voltage VGH, and also when the first scan pulse SCAN1(n) is inverted to the gate turn-on voltage VGH. Therefore, the second EM pulse EM2(n) is generated as the gate turn-off voltage VGL in the initialization step INIT and the sampling step SMPL. The second EM pulse EM2(n) is the gate turn-on voltage VGH in the addressing step WR and the emission step EMIS.

[0170] The light-emitting element (EL) can be implemented as an OLED comprising an anode electrode, a cathode electrode, and an organic compound layer connected between these electrodes. The anode electrode of the EL can be connected to a fourth node n4, and its cathode electrode can be supplied with a low potential power supply voltage ELVSS.

[0171] The driving element DT generates a current for driving the light-emitting element EL based on the gate-source voltage Vgs. The driving element DT includes a gate electrode connected to the second node DRG, a first electrode connected to the first node DRD, and a second electrode connected to the third node DRS.

[0172] The first capacitor Cst is connected between the second node DRG and the fourth node n4. The second capacitor Cd is connected between the fourth node n4 and the VDD node.

[0173] In the addressing step WR, the first switching element M41 is turned on according to the gate on-state voltage VGH of the first scan pulse SCAN1(n) to provide the data voltage Vdata to the second node DRG. The first switching element M41 includes a gate electrode connected to the first gate line to which the first scan pulse SCAN1(n) is applied, a first electrode connected to the data line DL to which the data voltage Vdata is applied, and a second electrode connected to the second node DRG.

[0174] The second switching element M42 is turned off during the initialization step INIT and the sampling step SMPL according to the gate turn-off voltage VGL of the second EM pulse EM2(n), thereby blocking the current path between the driving element DT and the light-emitting element EL. The second switching element M42 is turned on during the addressing step WR and the light-emitting step EMIS according to the gate turn-on voltage VGH of the second EM pulse EM2(n), thereby forming a current path between the driving element DT and the light-emitting element EL. The second switching element M42 includes a gate electrode connected to the second gate line to which the second EM pulse EM2(n) is applied, a first electrode connected to the third node DRS, and a second electrode connected to the anode electrode of the light-emitting element EL via the fourth node n4.

[0175] In the initialization step INIT, the third switching element M43 is turned on according to the gate on-state voltage VGH of the third scan pulse SCAN3(n) to connect the third node DRS to the INIT line INI to which the initialization voltage Vinit is applied. The third switching element M43 includes a gate electrode connected to the third gate line to which the third scan pulse SCAN3(n) is applied, a first electrode connected to the third node DRS, and a second electrode connected to the INIT line INI.

[0176] The fourth switching element M44 is turned on according to the gate on-state voltage VGH of the second scan pulse SCAN2(n) during the initialization step INIT and the sampling step SMPL, so as to provide the reference voltage Vref to the second node DRG. The fourth switching element M44 includes a gate electrode connected to the fourth gate line to which the second scan pulse SCAN2(n) is applied, a first electrode to which the reference voltage Vref is applied, and a second electrode connected to the second node DRG.

[0177] The fifth switching element M45 is turned off in the initialization step INIT and the addressing step WR according to the gate turn-off voltage VGL of the first EM pulse EM1(n), thereby blocking the current path between the first node DRD and the VDD line to which the pixel driving voltage ELVDD is applied. The fifth switching element M45 is turned on in the sampling step SMPL and the emission step EMIS according to the gate turn-on voltage VGH of the first EM pulse EM1(n), thereby connecting the VDD line to the first node DRD. The fifth switching element M45 includes a gate electrode connected to the fifth gate line to which the first EM pulse EM1(n) is applied, a first electrode connected to the VDD line, and a second electrode connected to the first node DRD.

[0178] EM generator 122 may include Figure 19 The circuit shown.

[0179] Reference Figure 19 The EM generator 122 includes first to sixth switching elements T41 to T46. Switching elements T41 to T46 can be implemented as n-channel oxide TFTs. The EM generator 122 receives a first scan pulse and third scan pulses SCAN1(n) and SCAN3(n), and outputs a second EM pulse EM2(n).

[0180] The first EM switching element T41 includes a gate electrode connected to the pull-up control node 191, a first electrode to which a gate drive voltage VDD is applied, and a second electrode connected to the output node. The second EM switching element T42 includes a gate electrode connected to the pull-down control node 192, a first electrode connected to the output node, and a second electrode connected to the VSS node to which a gate reference voltage VSS is applied.

[0181] The third EM switching element T43 is turned on by the gate on-state voltage VGH of the first scan pulse SCAN1(n) to charge the pull-up control node 191. The fourth EM switching element T44 is turned on by the gate on-state voltage VGH of the third scan pulse SCAN3(n) to discharge the pull-up control node 191. The third EM switching element T43 includes a gate electrode to which the first scan pulse SCAN1(n) is applied, a first electrode to which a gate drive voltage VDD is applied, and a second electrode connected to the pull-up control node 191. The fourth EM switching element T44 includes a gate electrode to which the third scan pulse SCAN3(n) is applied, a first electrode connected to the pull-up control node 191, and a second electrode connected to the VSS node.

[0182] The fifth EM switching element T45 is turned on by the gate on-state voltage VGH of the third scan pulse SCAN3(n) to charge the pull-down control node 192. The sixth EM switching element T46 is turned on by the gate on-state voltage VGH of the first scan pulse SCAN1(n) to discharge the pull-down control node 192. The fifth EM switching element T45 includes a gate electrode to which the third scan pulse SCAN3(n) is applied, a first electrode to which a gate drive voltage VDD is applied, and a second electrode connected to the pull-down control node 192. The sixth EM switching element T46 includes a gate electrode to which the first scan pulse SCAN1(n) is applied, a first electrode connected to the pull-down control node 192, and a second electrode connected to the VSS node.

[0183] To drive Figure 17 The pixel circuit shown includes a gate driver 120 that may include a first shift register for sequentially outputting a first scan pulse SCAN1(n), a second shift register for sequentially outputting a second scan pulse SCAN2(n), a third shift register for sequentially outputting a third scan pulse SCAN3(n), and a fourth shift register for sequentially outputting a first EM pulse EM1(n). The EM generator 122 may be as follows: Figure 18 and Figure 19 As shown, a small number of transistors T41 to T46 are used to generate the second EM pulse EM2(n). The gate driver 120 does not require a separate shift register to output and shift the second EM pulse EM2(n). Therefore, the bezel BZ of the display panel 100 can be narrowed because the circuit area occupied by the gate drive circuit is reduced.

[0184] Figure 20 This is a circuit diagram illustrating a pixel circuit according to a sixth embodiment of the present disclosure. Figure 21 It shows that it is applied to Figure 20 The waveform diagram of the gate signal of the pixel circuit shown is shown. Figure 22 and Figure 23 It shows the generation applied to Figure 20 The circuit diagram shows the EM generator 122 for the second EM pulse EM2(n) of the pixel circuit shown. The gate signals include the first scan pulse SC1(n), the second scan pulse SC2(n), the third scan pulse SC3(n), the first EM pulse EM1(n), and the second EM pulses EM2-1(n) and EM2-2(n).

[0185] In a sixth embodiment of this disclosure, the threshold voltage of the driving element DT can be shifted to a senseable voltage range by applying a preset voltage to the second gate electrode of the driving element DT in the internal compensation circuit of the diode connection method. Therefore, according to this disclosure, the threshold voltage Vth of the driving element DT, which is shifted to 0V or less, can be shifted to a senseable voltage.

[0186] Reference Figure 20 and Figure 21 The pixel circuit includes a light-emitting element EL, a driving element DT, a first capacitor C1 and a second capacitor C2, and a first to a seventh switching element M51 to M57. The driving element DT and the switching elements M51 to M57 can be implemented as an n-channel oxide TFT.

[0187] For this pixel circuit, the pixel data voltage Vdata, scan pulses SC1(n), SC2(n), and SC3(n), EM pulses EM1(n), EM2-1(n), and EM2-2(n), and constant voltages (e.g., pixel drive voltage ELVDD, low-potential supply voltage ELVSS, reference voltage Vref, initialization voltage Vinit, etc.) are provided. The voltages of the scan pulses SC1(n), SC2(n), and SC3(n) and the EM pulses EM1(n), EM2-1(n), and EM2-2(n) oscillate between the gate turn-on voltage VGH and the gate turn-off voltage VGL.

[0188] The constant voltage commonly applied to the pixel can be set to ELVDD>Vref>Vinit>ELVSS, but is not limited to this. The reference voltage Vref can be set to a voltage higher than the initialization voltage Vinit, thereby applying a negative back-bias to the driving element DT in the sampling step SMPL. The gate turn-on voltage VGH can be set to a voltage higher than the pixel drive voltage VDD. The gate turn-off voltage VGL can be set to a voltage lower than the low-potential supply voltage ELVSS.

[0189] The driving phase of the pixel circuit can be divided into: the initialization step INIT, in which the pixel circuit is initialized; the sampling step SMPL, in which the threshold voltage Vth of the driving element DT is sampled; the addressing step WR, in which the data voltage Vdata is charged and the pixel data is written; and the emission step EMIS, in which the emission element EL emits light.

[0190] The first scan pulse SC1(n) can be generated as a gate turn-on voltage VGH synchronized with the data voltage Vdata in the addressing step WR. The first scan pulse SC1(n) can be a gate turn-off voltage VGL in the initialization step INIT, the sampling step SMPL, and the emission step EMIS.

[0191] The second scan pulse SC2(n) can rise to the gate on-state voltage VGH before the third scan pulse SC3(n), and can fall to the gate off-state voltage VGL before the falling edge of the third scan pulse SC3(n). The second scan pulse SC2(n) can be generated as the gate on-state voltage VGH in the initialization step INIT and the sampling step SMPL. The second scan pulse SC2(n) can be the gate off-state voltage VGL in the addressing step WR and the emission step EMIS.

[0192] The third scan pulse SC3(n) can be generated as the gate on-state voltage VGH in the sampling step SMPL and the addressing step WR. In the addressing step WR, the gate on-state voltage portion of the third scan pulse SC3(n) can overlap with the gate on-state voltage portion of the first scan pulse SC1(n). After rising to the gate on-state voltage VGH after the rising edge of the second scan pulse SC2(n), the third scan pulse SC3(n) can fall to the gate off-state voltage VGL after the falling edge of the second scan pulse SC2(n). The third scan pulse SC3(n) can be the gate off-state voltage VGL in the initialization step INIT and the emission step EMIS.

[0193] The first EM pulse EM1(n) can be generated as the gate on-state voltage VGH in the initialization step INIT and the emission step EMIS. The first EM pulse EM1(n) can be generated as the gate off-state voltage VGL in the sampling step SMPL and the addressing step WR.

[0194] The second EM pulses EM2-1(n) and EM2-2(n) can be generated as either the second-1 EM pulse EM2-1(n) or the second-2 EM pulse EM2-2(n).

[0195] The 2-1EM pulse EM2-1(n) can be generated as the gate turn-off voltage VGL in the initialization step INIT, the sampling step SMPL, and the addressing step WR, while it can be the gate turn-on voltage VGH in the emission step EMIS.

[0196] The 2-2EM pulse EM2-2(n) can be generated as the gate turn-off voltage VGL in the initialization step INIT and the sampling step SMPL, while it can be the gate turn-on voltage VGH in the addressing step WR and the emission step EMIS.

[0197] The anode of the light-emitting element EL can be connected to the fourth node n4, and the low potential power supply voltage ELVSS can be applied to the cathode of the light-emitting element EL.

[0198] The first capacitor C1 can be connected between the second node n2 and the fifth node n5. The first capacitor C1 stores the threshold voltage Vth of the driving element DT during the sampling step SMPL. During the addressing step WR, the data voltage Vdata is transmitted to the first gate electrode of the driving element DT through the first capacitor C1.

[0199] The second capacitor C2 is connected between the third node DRS and the fifth node n5. The second capacitor C2 stores the second electrode voltage of the driving element DT, i.e., the source voltage, at the beginning of the light emission step EMIS, and maintains the gate-source voltage Vgs of the driving element DT during the light emission step EMIS.

[0200] The driving element DT can be a dual-gate MOSFET. The driving element DT includes a first gate electrode connected to the second node DRG, a second gate electrode connected to the fourth node n4, a first electrode connected to the first node DRD, and a second electrode connected to the third node DRS. The first and second gate electrodes of the driving element DT can overlap each other, wherein a semiconductor pattern forms a semiconductor channel between the first and second gate electrodes of the driving element DT.

[0201] The first switching element M51 includes a first electrode connected to the data line to which the data voltage Vdata is applied, a second electrode connected to the fifth node n5, and a gate electrode to which a first scan pulse SC1(n) is applied. The first switching element M51 is turned on in the addressing step WR in response to the gate on-state voltage VGH of the first scan pulse SC1(n) to provide the data voltage Vdata to the fifth node n5. During the initialization step INIT, sampling step SMPL, and emission step EMIS, in which the first switching element M51 is turned off, the current path between the data line and the fifth node n5 is blocked.

[0202] The second switching element M52 includes a first electrode connected to the third node DRS, a second electrode connected to the fourth node n4, and a gate electrode to which second EM pulses EM2-1(n) and EM2-2(n) are applied. The second switching element M52 is turned on in response to the gate on-state voltage VGH of the second EM pulses EM2-1(n) and EM2-2(n) during the light-emitting step EMIS or the addressing step WR and the light-emitting step EMIS, thereby forming a current path between the driving element DT and the light-emitting element EL. When the second switching element M52 is in the off state, the current path between the driving element DT and the light-emitting element EL is blocked, causing the light-emitting element EL to not emit light.

[0203] The third switching element M53 includes a first electrode connected to the third node DRS, a second electrode to which a reference voltage Vref is applied, and a gate electrode to which a third scan pulse SC3(n) is applied. The third switching element M53 is turned on in response to the gate on-state voltage VGH of the third scan pulse SC3(n) during the sampling step SMPL and the addressing step WR to provide the reference voltage Vref to the third node DRS. The current path between the REF line to which the reference voltage Vref is applied and the third node DRS is blocked during the initialization step INIT and the emission step EMIS when the third switching element M53 is turned off.

[0204] The fourth switching element M54 includes a first electrode connected to the first node DRD, a second electrode connected to the second node DRG, and a gate electrode to which a second scan pulse SC2(n) is applied. The fourth switching element M54 is turned on in response to the gate on-state voltage VGH of the second scan pulse SC2(n) during the initialization step INIT and the sampling step SMPL to connect the first node DRD to the second node DRG. When the fourth switching element M54 is turned on, the first gate electrode and the first electrode are connected to each other, causing the driving element DT to operate as a diode.

[0205] The fifth switching element M55 includes a first electrode to which a pixel driving voltage ELVDD is applied, a second electrode connected to the first node DRD, and a gate electrode to which a first EM pulse EM1(n) is applied. The fifth switching element M55 is turned on in response to the gate on-state voltage VGH of the first EM pulse EM1(n) during the initialization step INIT and the emission step EMIS to provide the pixel driving voltage ELVDD to the first node DRD. The current path between the VDD line to which the pixel driving voltage ELVDD is applied and the first node DRD is blocked during the sampling step SMPL and the addressing step WR, where the fifth switching element M55 is turned off.

[0206] The sixth switching element M56 includes a first electrode to which an initialization voltage Vinit is applied, a second electrode connected to the fifth node n5, and a gate electrode to which a second scan pulse SC2(n) is applied. The sixth switching element M56 is turned on in response to the gate on-state voltage VGH of the second scan pulse SC2(n) in the initialization step INIT and the sampling step SMPL to provide the initialization voltage Vinit to the fifth node n5. The current path between the INIT line to which the initialization voltage Vinit is applied and the fifth node n5 is blocked in the addressing step WR and the emission step EMIS, where the sixth switching element M56 is turned off.

[0207] The seventh switching element M57 includes a first electrode to which an initialization voltage Vinit is applied, a second electrode connected to the fourth node n4, and a gate electrode to which a third scan pulse SC3(n) is applied. The seventh switching element M57 is turned on in response to the gate-on voltage VGH of the third scan pulse SC3(n) during the sampling step SMPL and the addressing step WR to provide the initialization voltage Vinit to the fourth node n4. When the seventh switching element M57 is turned on, the reference voltage Vref is applied to the third node DRS through the third switching element M53. The current path between the INIT line to which the initialization voltage Vinit is applied and the fourth node n4 is blocked during the initialization step INIT and the emission step EMIS when the seventh switching element M57 is turned off.

[0208] In a sixth embodiment of this disclosure, the threshold voltage Vth of the driving element DT can be sampled by applying a reference voltage Vref to the third node DRS in the sampling step SMPL, and the sampling step SMPL and the addressing step WR can be separated by applying a data voltage Vdata to the fifth node n5 in the addressing step WR. Therefore, the sixth embodiment ensures that the sampling step SMPL lasts for a sufficiently long time, for example, up to two or more horizontal time intervals.

[0209] EM generator 122 may include Figure 22 and Figure 23 The circuit shown.

[0210] Reference Figure 22 The EM generator 122 includes first to third switching elements T51, T52, and T53. The EM generator 122 receives second and third scan pulses SC2(n) and SC3(n) and outputs a second-to-first EM pulse EM2-1(n). The EM switching elements T51, T52, and T53 can be implemented as n-channel oxide TFTs.

[0211] The second-1EM pulse EM2-1(n) is generated as the gate turn-off voltage VGL when at least one of the second scan pulse SC2(n) and the third scan pulse SC3(n) is the gate turn-on voltage VGH. The second-1EM pulse EM2-1(n) is generated as the gate turn-on voltage during at least some periods of the EMIS emission step.

[0212] A gate drive voltage VDD is applied to the first electrode of the first EM switching element T51. The gate electrode and the second electrode of the first EM switching element T51 are connected to the output node. The second EM switching element T52 is turned on according to the gate turn-on voltage VGH of the second scan pulse SCAN2(n) to discharge the voltage of the output node to the gate reference voltage VSS. The second EM switching element T52 includes a gate electrode to which the second scan pulse SC2(n) is applied, a first electrode connected to the output node, and a second electrode connected to the VSS node. The third EM switching element T53 is turned on according to the gate turn-on voltage VGH of the third scan pulse SCAN3(n) to discharge the voltage of the output node to the gate reference voltage VSS. The third EM switching element T53 includes a gate electrode to which the third scan pulse SC3(n) is applied, a first electrode connected to the output node, and a second electrode connected to the VSS node.

[0213] Reference Figure 23 The EM generator 122 includes a first EM switching element to a sixth EM switching element T61 to T66. The EM generator 122 receives a first scan pulse and a second scan pulse SC1(n) and SC2(n), and outputs a second-second EM pulse EM2-2(n). The EM switching elements T61 and T66 can be implemented as n-channel oxide TFTs.

[0214] The second-second EM pulse EM2-2(n) is generated as the gate turn-off voltage VGL when the second scan pulse SC2(n) is the gate turn-on voltage VGH, and as the gate turn-on voltage during at least some periods in the addressing step WR and the light emission step EMIS.

[0215] The first EM switch element T61 is turned on when the pull-up control node 231 is charged to provide the gate on-state voltage VGH to the output node from which the second-2 EM pulse EM2-2(n) outputs. When the pull-down control node 232 is charged, the second EM switch element T62 is turned on to discharge the output node. The third EM switch element T63 is turned on according to the gate on-state voltage VGH of the first scan pulse SC1(n) to charge the pull-up control node 231. The fourth EM switch element T64 is turned on according to the gate on-state voltage VGH of the second scan pulse SC2(n) to discharge the pull-up control node 231. The fifth EM switch element T65 is turned on according to the gate on-state voltage VGH of the second scan pulse SC2(n) to charge the pull-down control node 232. The sixth EM switch element T66 is turned on according to the gate on-state voltage VGH of the first scan pulse SC1(n) to discharge the pull-down control node 232.

[0216] The first EM switching element T61 includes a gate electrode connected to the pull-up control node 231, a first electrode to which a gate drive voltage VDD is applied, and a second electrode connected to the output node. The second EM switching element T62 includes a gate electrode connected to the pull-down control node 232, a first electrode connected to the output node, and a second electrode connected to the VSS node to which the gate reference voltage VSS is applied.

[0217] The third EM switching element T63 is turned on by the gate on-state voltage VGH of the first scan pulse SC1(n) to charge the pull-up control node 231. The fourth EM switching element T64 is turned on by the gate on-state voltage VGH of the second scan pulse SC2(n) to discharge the pull-up control node 231. The third EM switching element T63 includes a gate electrode to which the first scan pulse SC1(n) is applied, a first electrode to which a gate drive voltage VDD is applied, and a second electrode connected to the pull-up control node 231. The fourth EM switching element T64 includes a gate electrode to which the second scan pulse SC2(n) is applied, a first electrode connected to the pull-up control node 231, and a second electrode connected to the VSS node.

[0218] The fifth EM switching element T65 is turned on by the gate on-state voltage VGH of the second scan pulse SC2(n) to charge the pull-down control node 232. The sixth EM switching element T66 is turned on by the gate on-state voltage VGH of the first scan pulse SC1(n) to discharge the pull-down control node 232. The fifth EM switching element T65 includes a gate electrode to which the second scan pulse SC2(n) is applied, a first electrode to which a gate drive voltage VDD is applied, and a second electrode connected to the pull-down control node 232. The sixth EM switching element T66 includes a gate electrode to which the first scan pulse SC1(n) is applied, a first electrode connected to the pull-down control node 232, and a second electrode connected to the VSS node.

[0219] To drive Figure 20 The pixel circuit shown includes a gate driver 120 that may include a first shift register for sequentially outputting a first scan pulse SC1(n), a second shift register for sequentially outputting a second scan pulse SC2(n), a third shift register for sequentially outputting a third scan pulse SC3(n), and a fourth shift register for sequentially outputting a first EM pulse EM1(n). The EM generator 122 may be as follows: Figures 21 to 23 As shown, a small number of transistors T51 to T53 and T61 to T66 are used to generate the second EM pulses EM2-1(n) and EM2-2(n). The gate driver 120 does not require a separate shift register to output and shift the second EM pulses EM2-1(n) and EM2-2(n). Therefore, the bezel BZ of the display panel 100 can be narrowed because the circuit area occupied by the gate drive circuit is reduced.

[0220] The purpose, means and effects of this disclosure do not specify the essential features of the claims, and therefore the scope of the claims is not limited to the disclosure.

[0221] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed herein are for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are exemplary in all respects and do not limit the present disclosure. The scope of protection of the present disclosure should be understood based on the appended claims, and all technical concepts within the equivalent scope thereof should be understood to fall within the scope of the present disclosure.

Claims

1. A pixel circuit, comprising: A driving element includes a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a second electrode connected to a third node, and is configured to provide current to a light-emitting element; A first switching element is configured to turn on according to the gate turn-on voltage of the scan pulse to provide a data voltage to the second node; The second switching element is configured to turn off according to the gate turn-off voltage of the light emission control pulse; A third switching element is configured to turn on according to the gate turn-on voltage of the sensing pulse to provide a reference voltage to the third node; as well as A capacitor is configured to be connected between the second node and the third node. Wherein, the light emission control pulse is generated as the inverse pulse of the sensing pulse, and The scanning pulse rises to the gate turn-on voltage at a timing different from that at which the light emission control pulse drops to the gate turn-off voltage.

2. The pixel circuit according to claim 1, wherein, The first switching element includes a gate electrode connected to a first gate line to which the scan pulse is applied, a first electrode connected to a data line to which the data voltage is applied, and a second electrode connected to the second node. The second switching element includes a gate electrode connected to the second gate line to which the light-emitting control pulse is applied, a first electrode connected to the third node, and a second electrode connected to the anode electrode of the light-emitting element. The third switching element includes a gate electrode connected to a third gate line to which the sensing pulse is applied, a first electrode connected to the third node, and a second electrode connected to a power line to which the reference voltage is applied.

3. A pixel circuit, comprising: A driving element includes a first electrode connected to a first node to which a first constant voltage is applied, a gate electrode connected to a second node, and a second electrode connected to a third node, and is configured to provide current to a light-emitting element; A first switching element is configured to turn on according to the gate turn-on voltage of a first gate pulse to provide a data voltage to the second node; The second switching element is configured to turn off according to the gate turn-off voltage of the second gate pulse; A third switching element is configured to turn on according to the gate turn-on voltage of a third gate pulse to provide a second constant voltage to the third node; A fourth switching element is configured to turn on according to the gate turn-on voltage of a fourth gate pulse to apply a third constant voltage to the second node; as well as A capacitor is configured to be connected between the second node and the third node. Wherein, the second gate pulse is inverted to become the gate turn-off voltage when the third gate pulse is inverted to become the gate turn-on voltage, and the second gate pulse is inverted to become the gate turn-on voltage when the first gate pulse is inverted to become the gate turn-on voltage. Wherein, the fourth gate pulse is a gate turn-off voltage at a timing different from that of the first gate pulse, which is the gate turn-on voltage.

4. A pixel circuit, comprising: The driving element includes a first electrode connected to a first node, a first gate electrode connected to a second node, a second electrode connected to a third node, and a second gate electrode connected to a fourth node. The light-emitting element includes an anode electrode connected to the fourth node and a cathode electrode to which a low potential power supply voltage is applied, and is configured to be driven according to the current from the driving element; A first switching element is configured to turn on according to the gate turn-on voltage of the first scan pulse to provide a data voltage to the fifth node; A second switching element is connected between the third node and the fourth node to be turned off according to the gate turn-off voltage of the second light emission control pulse; A third switching element is configured to turn on according to the gate turn-on voltage of the third scan pulse to provide a reference voltage to the third node; A fourth switching element is configured to be turned on according to the gate turn-on voltage of the second scan pulse to connect the first gate electrode of the driving element to the first electrode of the driving element. The fifth switching element is configured to be turned off according to the gate turn-off voltage of the first light emission control pulse to block the current path between the power line to which the pixel driving voltage is applied and the first node. A sixth switching element is configured to turn on according to the gate turn-on voltage of the second scan pulse to provide an initialization voltage to the fifth node; A seventh switching element is configured to turn on according to the gate turn-on voltage of the third scan pulse to provide the initialization voltage to the fourth node; A first capacitor is configured to be connected between the second node and the fifth node; as well as A second capacitor is configured to be connected between the third node and the fifth node. Wherein, the second light emission control pulse is generated as a gate turn-off voltage when at least one of the second scan pulse and the third scan pulse is a gate on voltage, or The second light emission control pulse is generated as a gate turn-off voltage only when the second scan pulse is a gate on voltage.

5. A display device, comprising: The display panel includes multiple data lines, multiple gate lines intersecting the data lines, multiple power lines, and multiple pixel circuits connected to the data lines, the gate lines, and the power lines. A data driver configured to provide a data voltage for pixel data to the data line; as well as A gate driver configured to provide scan pulses and light emission control pulses to the gate line. Each of the pixel circuits includes: A driving element includes a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a second electrode connected to a third node, and is configured to provide current to a light-emitting element; A first switching element is configured to turn on according to the gate turn-on voltage of the scan pulse to provide a data voltage to the second node; The second switching element is configured to turn off according to the gate turn-off voltage of the light emission control pulse; A capacitor, configured to be connected between the second node and the third node; and A third switching element, configured to turn on according to the gate on-state voltage of the scan pulse, to provide a reference voltage to the third node, and The light emission control pulse is generated in opposite phase to the scanning pulse.

6. The display device according to claim 5, wherein, The gate driver includes: A first EM switching element includes a first electrode, a second electrode to which a gate on-voltage is applied, and a gate electrode connected to an output node, wherein the light-emitting control pulse is output from the output node; and The second EM switching element includes a gate electrode to which the scan pulse is applied, a first electrode connected to the output node, and a second electrode to which a gate turn-off voltage is applied.

7. A display device, comprising: The display panel includes multiple data lines, multiple gate lines intersecting the data lines, multiple power lines, and multiple pixel circuits connected to the data lines, the gate lines, and the power lines. A data driver configured to provide a data voltage for pixel data to the data line; as well as A gate driver configured to provide scan pulses, sensing pulses, and light emission control pulses to the gate line. Each of the pixel circuits includes: A driving element includes a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a second electrode connected to a third node, and is configured to provide current to a light-emitting element; A first switching element is configured to turn on according to the gate turn-on voltage of the scan pulse to provide a data voltage to the second node; The second switching element is configured to turn off according to the gate turn-off voltage of the light emission control pulse; A third switching element, configured to turn on according to the gate on-state voltage of the sensing pulse, to provide a reference voltage to the third node; and A capacitor, configured to be connected between the second node and the third node, and Wherein, the light emission control pulse is generated as the inverse pulse of the sensing pulse, and The scanning pulse rises to the gate turn-on voltage at a timing different from that at which the light emission control pulse drops to the gate turn-off voltage.

8. The display device according to claim 7, wherein, The gate driver includes: A first EM switching element includes a first electrode, a second electrode to which a gate on-voltage is applied, and a gate electrode connected to an output node, wherein the light-emitting control pulse is output from the output node; and The second EM switching element includes a gate electrode to which the sensing pulse is applied, a first electrode connected to the output node, and a second electrode to which a gate turn-off voltage is applied.

9. A display device, comprising: The display panel includes multiple data lines, multiple gate lines intersecting the data lines, multiple power lines, and multiple pixel circuits connected to the data lines, the gate lines, and the power lines. A data driver configured to provide a data voltage for pixel data to the data line; as well as A gate driver configured to provide a first gate pulse, a second gate pulse, a third gate pulse, and a fourth gate pulse to the gate line. Each of the pixel circuits includes: A driving element includes a first electrode connected to a first node to which a first constant voltage is applied, a gate electrode connected to a second node, and a second electrode connected to a third node, and is configured to provide current to a light-emitting element; A first switching element is configured to turn on according to the gate turn-on voltage of the first gate pulse to provide a data voltage to the second node; The second switching element is configured to turn off according to the gate turn-off voltage of the second gate pulse; A third switching element is configured to turn on according to the gate turn-on voltage of the third gate pulse to provide a second constant voltage to the third node; A fourth switching element, configured to turn on according to the gate turn-on voltage of the fourth gate pulse, to apply a third constant voltage to the second node; and A capacitor, configured to be connected between the second node and the third node, and Wherein, the second gate pulse is inverted to become the gate turn-off voltage when the third gate pulse is inverted to become the gate turn-on voltage, and the second gate pulse is inverted to become the gate turn-on voltage when the first gate pulse is inverted to become the gate turn-on voltage. Wherein, the fourth gate pulse is a gate turn-off voltage at a timing different from that of the first gate pulse, which is the gate turn-on voltage.

10. The display device according to claim 9, wherein, The gate driver includes: A first EM switching element is configured to turn on when the pull-up control node is charged to provide a gate turn-on voltage to the output node from which the second gate pulse is output; A second EM switching element is configured to turn on to discharge the output node when the pull-down control node is charged. A third EM switching element is configured to turn on according to the gate turn-on voltage of the first gate pulse to charge the pull-up control node; A fourth EM switching element is configured to turn on according to the gate turn-on voltage of the third gate pulse to discharge the pull-up control node; A fifth EM switching element, configured to turn on according to the gate turn-on voltage of the third gate pulse, to charge the pull-down control node; and A sixth EM switching element is configured to turn on according to the gate turn-on voltage of the first gate pulse to discharge the pull-down control node.

11. A display device, comprising: The display panel includes multiple data lines, multiple gate lines intersecting the data lines, multiple power lines, and multiple pixel circuits connected to the data lines, the gate lines, and the power lines. A data driver configured to provide a data voltage for pixel data to the data line; as well as A gate driver configured to provide the gate line with a first scan pulse, a second scan pulse, a third scan pulse, a first light emission control pulse, and a second light emission control pulse. Each of the pixel circuits includes: The driving element includes a first electrode connected to a first node, a first gate electrode connected to a second node, a second electrode connected to a third node, and a second gate electrode connected to a fourth node. The light-emitting element includes an anode electrode connected to the fourth node and a cathode electrode to which a low potential power supply voltage is applied, and is configured to be driven according to the current from the driving element; A first switching element is configured to turn on according to the gate turn-on voltage of the first scan pulse to provide a data voltage to the fifth node; A second switching element is configured to be connected between the third node and the fourth node to be turned off according to the gate turn-off voltage of the second light emission control pulse; A third switching element is configured to turn on according to the gate turn-on voltage of the third scan pulse to provide a reference voltage to the third node; A fourth switching element is configured to be turned on according to the gate turn-on voltage of the second scan pulse to connect the first gate electrode of the driving element to the first electrode of the driving element. The fifth switching element is configured to be turned off according to the gate turn-off voltage of the first light emission control pulse to block the current path between the power line to which the pixel driving voltage is applied and the first node. A sixth switching element is configured to turn on according to the gate turn-on voltage of the second scan pulse to provide an initialization voltage to the fifth node; A seventh switching element is configured to turn on according to the gate turn-on voltage of the third scan pulse to provide the initialization voltage to the fourth node; A first capacitor, configured to be connected between the second node and the fifth node; and A second capacitor is configured to be connected between the third node and the fifth node, and Wherein, the second light emission control pulse is generated as a gate turn-off voltage when at least one of the second scan pulse and the third scan pulse is a gate on voltage, or The second light emission control pulse is generated as a gate turn-off voltage only when the second scan pulse is a gate on voltage.

12. The display device according to claim 11, wherein, The gate driver includes: A first EM switching element includes a first electrode, a second electrode to which a gate turn-on voltage is applied, and a gate electrode connected to an output node, wherein the second light emission control pulse is output from the output node; A second EM switching element is configured to discharge the output node in response to the second scan pulse; and A third EM switching element is configured to discharge the output node in response to the third scan pulse.

13. The display device according to claim 11, wherein, The gate driver includes: A first EM switching element is configured to turn on when the pull-up control node is charged, so as to provide a gate turn-on voltage to the output node from which the second light emission control pulse is output; A second EM switching element is configured to turn on to discharge the output node when the pull-down control node is charged. A third EM switching element is configured to turn on according to the gate turn-on voltage of the first scan pulse to charge the pull-up control node; A fourth EM switching element is configured to turn on according to the gate turn-on voltage of the second scan pulse to discharge the pull-up control node; A fifth EM switching element, configured to turn on according to the gate on-state voltage of the second scan pulse, to charge the pull-down control node; and A sixth EM switching element is configured to turn on according to the gate turn-on voltage of the first scan pulse to discharge the pull-down control node.

14. A pixel circuit, comprising: A driving element includes a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node, and is configured to provide current to a light-emitting element; A first switching element is configured to turn on according to the gate turn-on voltage of the first scan pulse to provide a data voltage to the second node; The second switching element is configured to turn off according to the gate turn-off voltage of the second light-emitting control pulse to block the current path between the driving element and the light-emitting element; A third switching element is configured to turn on according to the gate turn-on voltage of the third scan pulse to provide an initialization voltage to the third node; A fourth switching element is configured to turn on according to the gate turn-on voltage of the second scan pulse to provide a reference voltage to the second node; A fifth switching element is configured to turn on according to the gate turn-on voltage of the first light emission control pulse to provide a pixel driving voltage to the first node; A first capacitor is connected between the second node and the fourth node; as well as The second capacitor has one end connected to the fourth node, and the other end is subjected to the pixel driving voltage. Specifically, the second light emission control pulse is inverted to the gate turn-off voltage when the third scan pulse is inverted to the gate turn-on voltage, and is also inverted to the gate turn-on voltage when the first scan pulse is inverted to the gate turn-on voltage.

15. A display device comprising a pixel circuit according to any one of claims 1 to 4 and 14.

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