A chip bonding method and a semiconductor chip structure

Abstract

Embodiments of the present application disclose a chip bonding method and a semiconductor chip structure. The method includes: providing a first chip; the first chip includes a first contact pad; the first contact pad includes a first portion and a second portion, the first portion is lower than the first surface of the first substrate, and the second portion is higher than the first surface of the first substrate to form a stepped first contact pad; providing a second chip; the second chip includes a second contact pad; the second contact pad includes a third portion and a fourth portion, the third portion is lower than the third surface of the second substrate, and the fourth portion is higher than the third surface of the second substrate to form a stepped second contact pad; bonding the first chip and the second chip, wherein the first portion and the second portion of the first chip are respectively in contact with the fourth portion and the third portion of the second chip.

Description

Technical Field

[0001] This application relates to the technical field of chip packaging processes, and particularly to a chip bonding method and a semiconductor chip structure. Background Art

[0002] In the process of integrated circuit manufacturing, stacking multiple chips and establishing mechanical and electrical connections is an important method to reduce the volume of integrated circuits. The current practice usually involves fabricating TSVs (Through-Silicon Vias) for each chip to be stacked first, then forming contact pads for each TSV, and finally using the chip-to-chip or chip-to-wafer method for positioning bonding to achieve electrical connection between the upper chip and the lower chip through the respective contact pads and TSVs. Currently, how to achieve wafer or chip bonding efficiently and with high quality has become an important research direction. Summary of the Invention

[0003] In view of this, embodiments of the present application provide a chip bonding method and a semiconductor chip structure.

[0004] According to a first aspect of the embodiments of the present application, a chip bonding method is provided. The method includes:

[0005] Providing a first chip; the first chip includes a first substrate, the first substrate includes opposite first and second surfaces; the first chip further includes a first groove in the first substrate on one side of the first surface, and a first contact pad in the first groove; the first contact pad includes a first part and a second part, the first part is lower than the first surface of the first substrate, and the second part is higher than the first surface of the first substrate, so as to form the stepped first contact pad;

[0006] Providing a second chip; the second chip includes a second substrate, the second substrate includes opposite third and fourth surfaces; the second chip further includes a second groove in the second substrate on one side of the third surface, and a second contact pad in the second groove; the second contact pad includes a third part and a fourth part, the third part is lower than the third surface of the second substrate, and the fourth part is higher than the third surface of the second substrate, so as to form the stepped second contact pad;

[0007] Bonding the first chip and the second chip, wherein the first part and the second part of the first chip are respectively in contact with the fourth part and the third part of the second chip.

[0008] In some embodiments, the method further includes:

[0009] After bonding the first chip and the second chip, a void is formed between the first contact pad and the second contact pad.

[0010] In some embodiments, a second portion of the first contact pad that is higher than a first surface of the first substrate is arc-shaped on a side close to the first substrate;

[0011] A fourth portion of the second contact pad that is higher than a third surface of the second substrate is arc-shaped on a side close to the second substrate.

[0012] In some embodiments, the first chip further includes a first via structure located within the first substrate on a side of a second surface of the first substrate; in a projection along a direction perpendicular to a plane of the first substrate, a projected image of the void falls within a projected image of the first via structure;

[0013] The second chip further includes a second via structure located within the second substrate on a side of a fourth surface of the second substrate; in a projection along a direction perpendicular to a plane of the second substrate, a projected image of the void falls within a projected image of the second via structure.

[0014] In some embodiments, in a projection along a direction perpendicular to a plane of the first substrate, a projected image of the first via structure falls within a projected image of the first contact pad;

[0015] In a projection along a direction perpendicular to a plane of the second substrate, a projected image of the second via structure falls within a projected image of the second contact pad.

[0016] In some embodiments, in a projection along a direction perpendicular to a plane of the first substrate, the shape of the first contact pad is circular or rectangular;

[0017] In a projection along a direction perpendicular to a plane of the second substrate, the shape of the second contact pad is circular or rectangular.

[0018] In some embodiments, along a direction in which the step extends, a width of the first portion is greater than half of a width of the first contact pad; a width of the third portion is greater than half of a width of the second contact pad.

[0019] In some embodiments, a height of a portion of the second portion that is higher than the first portion ranges from 100 nm to 500 nm;

[0020] A height of a portion of the fourth portion that is higher than the third portion ranges from 100 nm to 500 nm.

[0021] In some embodiments, providing the first chip includes:

[0022] Form a first substrate, the first substrate including a first substrate body, a first via structure penetrating the first substrate body, and a first dielectric layer covering the upper surfaces of the first substrate body and the first via structure;

[0023] Etch the first substrate to form a first groove, the first groove being located above the first via structure;

[0024] Fill the first groove to form a first contact pad prelayer;

[0025] Etch part of the first contact pad prelayer to form a first contact pad;

[0026] Provide the second chip, including:

[0027] Form a second substrate, the second substrate including a second substrate body, a second via structure penetrating the second substrate body, and a second dielectric layer covering the upper surfaces of the second substrate body and the second via structure;

[0028] Etch the second substrate to form a second groove, the second groove being located above the second via structure;

[0029] Fill the second groove to form a second contact pad prelayer;

[0030] Etch part of the second contact pad prelayer to form a second contact pad.

[0031] In some embodiments, bond the first chip and the second chip; including: bonding the first chip and the second chip in an up-down manner in a mirror image manner.

[0032] In some embodiments, forming a gap between the first contact pad and the second contact pad includes: forming a gap between a second part of the first contact pad and a fourth part of the second contact pad.

[0033] According to a second aspect of the embodiments of the present application, there is provided a semiconductor chip structure, the semiconductor chip including:

[0034] A first chip, the first chip including a first substrate, the first substrate including opposite first and second surfaces; the first chip further includes a first groove in the first substrate on one side of the first surface, and a first contact pad in the first groove;

[0035] A second chip, the second chip including a second substrate, the second substrate including opposite third and fourth surfaces; the second chip further includes a second groove in the second substrate on one side of the third surface, and a second contact pad in the second groove;

[0036] The first contact pad of the first chip contacts the second contact pad of the second chip, and a gap is formed between the first contact pad and the second contact pad.

[0037] In some embodiments, the portion of the first contact pad protruding from the first surface of the first substrate is arc-shaped on the side close to the first substrate; the portion of the second contact pad protruding from the third surface of the second substrate is arc-shaped on the side close to the second substrate.

[0038] In some embodiments, the first chip further includes a first via structure, and the first via structure is located in the first substrate on the side of the second surface of the first substrate; in the projection in the direction perpendicular to the plane of the first substrate, the projection image of the gap falls within the projection image of the first via structure;

[0039] The second chip further includes a second via structure, and the second via structure is located in the second substrate on the side of the fourth surface of the second substrate; in the projection in the direction perpendicular to the plane of the second substrate, the projection image of the gap falls within the projection image of the second via structure.

[0040] In some embodiments, in the projection in the direction perpendicular to the plane of the first substrate, the projection image of the first via structure falls within the projection image of the first contact pad;

[0041] In the projection in the direction perpendicular to the plane of the second substrate, the projection image of the second via structure falls within the projection image of the second contact pad.

[0042] In some embodiments, in the projection in the direction perpendicular to the plane of the first substrate, the shape of the first contact pad is circular or rectangular;

[0043] In the projection in the direction perpendicular to the plane of the second substrate, the shape of the second contact pad is circular or rectangular.

[0044] In the embodiments of the present application, by designing both the first contact pad of the first chip and the second contact pad of the second chip into stepped contact pads, and using the contact pads with height differences as the bonding surfaces during bonding, an interlocking structure can be formed to prevent displacement during the bonding process, thereby improving the overall reliability. In addition, in some embodiments of the present application, a relatively large gap is formed between the first contact pad and the second contact pad. In this way, the gap buffer zone for the thermal expansion of the metal during the bonding of the contact pads can be increased, the problem of bonding delamination caused by the thermal expansion of the metal can be reduced, and at the same time, the stepped contact pads can also improve the connection effect of the two chips after bonding. Description of the Drawings

[0045] Figure 1aSchematic diagram of the bonding process of a semiconductor chip structure in the related art;

[0046] Figures 1b to 1c Cross-sectional schematic diagram of a semiconductor chip structure in the related art;

[0047] Figure 2 Flow schematic diagram of the chip bonding method provided by an embodiment of the present application;

[0048] Figures 3a to 3h Schematic diagram of the device structure during the bonding process of the chip bonding method provided by an embodiment of the present application;

[0049] Figures 4a to 4b Top view of the first chip of the semiconductor chip structure provided by an embodiment of the present application;

[0050] Figure 5a and Figure 5b Partial enlarged view of the second part of the first chip provided by an embodiment of the present application.

[0051] Explanation of reference numerals:

[0052] 1 - Contact pad; 2 - Through-hole structure;

[0053] 10 - First substrate; 101 - First base plate; 102 - First dielectric layer; 103 - First groove; 104 - First surface; 105 - Second surface;

[0054] 11 - First through-hole structure; 111 - First conductive layer; 112 - First insulating layer;

[0055] 12 - First contact pad pre-layer; 120 - First contact pad; 121 - First part; 122 - Second part;

[0056] 13 - First mask layer;

[0057] 20 - Second substrate; 201 - Second base plate; 202 - Second dielectric layer; 204 - Third surface; 205 - Fourth surface;

[0058] 21 - Second through-hole structure; 211 - Second conductive layer; 212 - Second insulating layer;

[0059] 220 - Second contact pad; 221 - Third part; 222 - Fourth part;

[0060] 30 - Gap. Detailed implementation manners

[0061] Exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present application can be more thoroughly understood and the scope of the present application disclosed can be fully conveyed to those skilled in the art.

[0062] In the following description, numerous specific details are given to provide a more thorough understanding of the present application. However, it will be apparent to one of ordinary skill in the art that the present application may be practiced without one or more of these details. In other instances, well-known features of some technologies are not described in order to avoid confusion with the present application; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0063] In the drawings, for clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. The same reference numerals throughout the drawings denote the same elements.

[0064] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part. And when discussing the second element, component, region, layer, or part, it does not necessarily mean that there is a first element, component, region, layer, or part in the present application.

[0065] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures with other elements or features. It should be understood that the spatial relationship terms are intended to include different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the drawings is flipped, then an element or feature described as "under other elements" or "beneath them" or "under it" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both the upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0066] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present application. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0067] To fully understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solutions of the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may have other embodiments.

[0068] In the related art, Figure 1a is a schematic process diagram of the bonding of a semiconductor chip structure in the related art. When chip hybrid bonding is performed, the depth of the contact surface of the contact pad 1 needs to be controlled. However, the depth of the contact pad 1 needs to be controlled within 1 nm to 5 nm, which is quite difficult to control. In the manufacturing process of the back via exposure device of the via structure 2, problems of the stability of the back CMP control are likely to occur, resulting in problems in the connection between the contact pads 1 of the two chips during hybrid bonding. For example, as Figure 1b shown, if the depth of the contact pad 1 is too deep, an open circuit is formed between the contact pads; or, as Figure 1c shown, if the depth of the contact pad 1 is too shallow, the material in the contact pad is extruded from the bonding surface, causing bonding separation or contact with adjacent contact pads, resulting in a short circuit.

[0069] Based on this, an embodiment of the present application provides a chip bonding method. For details, please refer to the attached Figure 2, as shown in the figure, the method includes the following steps:

[0070] Step 201: Provide a first chip; the first chip includes a first substrate, the first substrate includes opposite first and second surfaces; the first chip further includes a first groove in the first substrate on one side of the first surface, and a first contact pad in the first groove; the first contact pad includes a first part and a second part, the first part is lower than the first surface of the first substrate, and the second part is higher than the first surface of the first substrate, so as to form the stepped first contact pad;

[0071] Step 202: Provide a second chip; the second chip includes a second substrate, the second substrate includes opposite third and fourth surfaces; the second chip further includes a second groove in the second substrate on one side of the third surface, and a second contact pad in the second groove; the second contact pad includes a third part and a fourth part, the third part is lower than the third surface of the second substrate, and the fourth part is higher than the third surface of the second substrate, so as to form the stepped second contact pad;

[0072] Step 203: Bond the first chip and the second chip, wherein the first part and the second part of the first chip are respectively in contact with the fourth part and the third part of the second chip, and a gap is formed between the first contact pad and the second contact pad.

[0073] The chip bonding method provided by the embodiments of the present application will be further described in detail below in conjunction with specific embodiments.

[0074] Figures 3a to 3h It is a schematic diagram of the device structure during the bonding process of the chip bonding method provided by the embodiments of the present application.

[0075] First, as Figures 3a to 3f , execute Step 201 to provide a first chip.

[0076] In one embodiment, the first chip includes a first substrate 10. Here, the first substrate can be a single-element semiconductor material substrate (such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a compound semiconductor material substrate (such as a silicon-germanium (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.

[0077] First, refer to Figure 3a , the first substrate 10 includes a first substrate 101 and a first via structure 11 penetrating the first substrate 101.

[0078] In actual operation, before forming the first via structure 11 penetrating the first substrate 101, the method further includes: grinding the lower surface of the first substrate 101 to thin the first substrate 101.

[0079] Next, etch the first substrate 101 from the upper surface of the first substrate 101 to form a first via hole (not shown in the figure).

[0080] Specifically, a mask layer can be grown on the upper surface of the first substrate 101 first, and then the mask layer is patterned to show the first via hole pattern to be etched on the mask layer. The mask layer can be patterned by a photolithography process. The mask layer can be a photoresist mask or a hard mask patterned based on a photolithography mask; when the mask layer is a photoresist mask, the mask layer is specifically patterned through steps such as exposure, development, and resist stripping. Then, the first via hole penetrating the first substrate is etched according to the via hole pattern to be etched.

[0081] Then, a first insulating layer 112 is formed on the sidewall of the first via hole. The material of the first insulating layer 112 can include but is not limited to related integrated circuit insulating materials such as silicon oxide or silicon nitride.

[0082] After that, after the first insulating layer is formed, a barrier layer and a seed layer (not shown in the figure) need to be formed in sequence. The material of the barrier layer is one or any combination of Ta, TaN, Ti, and TiN, and the material of the seed layer is copper with a thickness of 1 nm - 10 nm. A conductive material is filled on the sidewall of the first insulating layer 112 to form a first conductive layer 111 penetrating the first substrate 101. The material of the first conductive layer 111 can include related integrated circuit conductive materials such as copper or tungsten.

[0083] Next, refer to Figure 3b , a first dielectric layer 102 covering the upper surfaces of the first substrate 101 and the first via structure 11 is formed. The first substrate 101 and the first dielectric layer 102 constitute a first substrate 10.

[0084] The first substrate 10 includes opposite first surface 104 and second surface 105. The first surface is the upper surface of the first dielectric layer 102, and the second surface is the lower surface of the first substrate 101.

[0085] Next, refer to Figure 3c , etch the first substrate 10 to form a first groove 103, and the first groove 103 is located above the first via structure 11.

[0086] In one embodiment, etching the first substrate 10 to form a first groove 103 specifically includes: etching the first dielectric layer 102 to form the first groove 103.

[0087] In another embodiment, the first dielectric layer may not be formed, and the first substrate 101 may be directly etched to form a first groove, and the first groove exposes the first via structure. Specifically, etching the first substrate to form a first groove includes: etching away a part of the first substrate and a part of the first via structure from the upper surface of the first substrate to form the first groove.

[0088] In this embodiment, the first surface is the upper surface of the first substrate 101, and the second surface is the lower surface of the first substrate 101.

[0089] Next, referring to Figure 3d , the first groove 103 is filled to form a first contact pad pre-layer 12.

[0090] In actual operation, the first contact pad pre-layer 12 can be formed by methods such as sputtering or electroplating.

[0091] The upper surface of the first contact pad pre-layer 12 is higher than the first surface 104 of the first substrate 10.

[0092] Next, referring to Figure 3e and 3f , a part of the first contact pad pre-layer 12 is etched to form a first contact pad 120.

[0093] Specifically, a first mask layer 13 can be grown on the first surface 104 of the first substrate 10 and a part of the first contact pad pre-layer 12, and then the first mask layer 13 is patterned to expose the first contact pad pattern to be removed on the first mask layer 13. The first mask layer can be patterned by a photolithography process. The first mask layer can be a photoresist mask or a hard mask patterned based on a photolithography mask; when the first mask layer is a photoresist mask, the first mask layer is specifically patterned through steps such as exposure, development, and resist stripping, and then the first contact pad 120 is etched according to the first contact pad pattern to be etched.

[0094] Here, for example, a wet or dry etching process can be used to form the first contact pad 120.

[0095] Finally, the first mask layer 13 is removed to form a first chip.

[0096] The first chip includes a first groove 103 within the first substrate 10 on one side of the first surface 104, and a first contact pad 120 within the first groove 103; the first contact pad 120 includes a first portion 121 and a second portion 122, the first portion 121 being lower than the first surface 104 of the first substrate 10, and the second portion 122 being higher than the first surface 104 of the first substrate 10, so as to form the stepped first contact pad 120.

[0097] Next, as Figure 3g shown, step 202 is performed to provide a second chip.

[0098] It should be noted that before bonding the first chip and the second chip, the manufacturing steps of the first chip and the second chip are basically the same. Therefore Figures 3a to 3f only the manufacturing steps of the first chip are shown, and the manufacturing steps of the second chip can refer to the schematic diagram of the first chip.

[0099] In one embodiment, the second chip includes a second substrate 20. Here, the second substrate can be a single-element semiconductor material substrate (such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a compound semiconductor material substrate (such as a germanium-silicon (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.

[0100] The second substrate 20 includes a second substrate 201 and a second via structure 21 penetrating through the second substrate 201.

[0101] In actual operation, before forming the second via structure 21 penetrating through the second substrate 201, the method further includes: grinding the lower surface of the second substrate 201 to thin the second substrate 201.

[0102] Next, the second substrate 201 is etched from the upper surface of the second substrate 201 to form a second via.

[0103] Specifically, a mask layer can be grown on the upper surface of the second substrate 201 first, and then the mask layer is patterned to show the second via pattern to be etched on the mask layer. The mask layer can be patterned by a photolithography process. The mask layer can be a photoresist mask or a hard mask patterned based on a photolithography mask; when the mask layer is a photoresist mask, the mask layer is specifically patterned through steps such as exposure, development, and resist stripping. Then, the second via penetrating through the second substrate is etched according to the via pattern to be etched.

[0104] Then, a second insulating layer 212 is formed on the sidewall of the second through-hole. The material of the second insulating layer 212 may include, but is not limited to, related integrated circuit insulating materials such as silicon oxide or silicon nitride.

[0105] After that, after the formation of the second insulating layer, a barrier layer and a seed layer (not shown in the figure) need to be formed in sequence. The material of the barrier layer is one or any combination of Ta, TaN, Ti, and TiN, and the material of the seed layer is copper, with a thickness of 1 nm - 10 nm. A conductive material is filled on the sidewall of the second insulating layer 212 to form a second conductive layer 211 that penetrates the second substrate 201. The material of the second conductive layer 211 may include related integrated circuit conductive materials such as copper or tungsten.

[0106] Next, a second dielectric layer 202 is formed to cover the upper surface of the second substrate 201 and the second through-hole structure 21.

[0107] The second substrate 20 includes opposite third and fourth surfaces 204 and 205. The third surface is the upper surface of the second dielectric layer 202, and the fourth surface is the lower surface of the second substrate 201.

[0108] Next, the second substrate 20 is etched to form a second groove, and the second groove is located above the second through-hole structure 21.

[0109] In one embodiment, etching the second substrate 20 to form the second groove specifically includes: etching the second dielectric layer 202 to form the second groove.

[0110] In another embodiment, the second dielectric layer may not be formed, and the second substrate 201 may be directly etched to form a second groove that exposes the second through-hole structure. Specifically, etching the second substrate to form the second groove includes: etching and removing a part of the second substrate and a part of the second through-hole structure from the upper surface of the second substrate to form the second groove.

[0111] In this embodiment, the third surface is the upper surface of the second substrate 201, and the fourth surface is the lower surface of the second substrate 201.

[0112] Next, the second groove is filled to form a second contact pad pre-layer.

[0113] In actual operation, the second contact pad pre-layer can be formed by methods such as sputtering or electroplating.

[0114] The upper surface of the second contact pad pre-layer is higher than the third surface 204 of the second substrate 20.

[0115] Next, a part of the second contact pad pre-layer is etched to form a second contact pad 220.

[0116] Specifically, a second mask layer can be grown on the third surface 204 of the second substrate 20 and a part of the second contact pad pre-layer first, and then the second mask layer is patterned to show the second contact pad pattern to be etched on the second mask layer. The second mask layer can be patterned by a photolithography process. The second mask layer can be a photoresist mask or a hard mask patterned based on a photolithography mask; when the second mask layer is a photoresist mask, the second mask layer is specifically patterned through steps such as exposure, development, and resist stripping, and then the second contact pad 220 is etched according to the second contact pad pattern to be etched.

[0117] Here, for example, a wet or dry etching process can be used to form the second contact pad 220.

[0118] Finally, the second mask layer is removed to form the second chip.

[0119] The second chip includes a second groove in the second substrate 20 on one side of the third surface 204, and a second contact pad 220 in the second groove; the second contact pad includes a third part 221 and a fourth part 222, the third part 221 is lower than the third surface 204 of the second substrate 20, and the fourth part 222 is higher than the third surface 204 of the second substrate 20 to form the stepped second contact pad 220.

[0120] Next, as Figure 3h shown, step 203 is performed to bond the first chip and the second chip, wherein the first part 121 and the second part 122 of the first chip are respectively in contact with the fourth part 222 and the third part 221 of the second chip.

[0121] The bonding method provided by the embodiment of the present application designs both the first contact pad of the first chip and the second contact pad of the second chip as stepped contact pads, and uses the contact pads with height differences as the bonding surfaces during bonding, which can form an interlocking structure to prevent displacement during the bonding process, so as to improve the overall reliability. At the same time, the stepped contact pads can also improve the connection effect of the two chips after bonding. In addition, compared with the narrow process window with a depth that needs to be controlled within 1 nm to 5 nm in the related art, the design of the contact pads with height differences in the present application does not require strict control of the size to the nanometer level, broadens the process window, reduces the process difficulty, and improves the process efficiency and yield.

[0122] In an embodiment, the method further includes: after bonding the first chip and the second chip, a gap 30 is formed between the first contact pad 120 and the second contact pad 220.

[0123] In the embodiments of the present application, a relatively large gap can be formed between the first contact pad and the second contact pad. This gap can increase the gap buffer for the thermal expansion of the metal during contact pad bonding, thereby reducing the problem of bonding delamination caused by metal thermal expansion.

[0124] In one embodiment, the part of the second portion 122 of the first contact pad 120 that is higher than the first surface 104 of the first substrate 10 is arc-shaped on the side close to the first substrate 10.

[0125] The part of the fourth portion 222 of the second contact pad 220 that is higher than the third surface 204 of the second substrate 20 is arc-shaped on the side close to the second substrate 20. In this way, compared with a right-angled shape, the arc shape can, during subsequent bonding, avoid cracking the first substrate and the second substrate due to the smooth characteristic of its arc-shaped structure even when expansion extrusion occurs.

[0126] Figure 5a and Figure 5b is a partial enlarged view of the second portion of the first chip provided by the embodiments of the present application.

[0127] The arc-shaped part in the second portion 122 may be as Figure 5a shown, not extending to the inner sidewall of the first substrate 10, or may be as Figure 5b shown, extending to the inner sidewall of the first substrate 10. It should be noted that the shape of the fourth portion 222 is the same as that of the second portion 122.

[0128] In one embodiment, in the projection in the direction perpendicular to the plane of the first substrate 10, the shape of the first contact pad 120 is circular or rectangular.

[0129] In the projection in the direction perpendicular to the plane of the second substrate 20, the shape of the second contact pad 220 is circular or rectangular.

[0130] Specifically, as Figure 4a and Figure 4b shown, in the embodiment shown in Figure 4a , in the projection in the direction perpendicular to the plane of the first substrate 10, the shape of the first contact pad 120 is circular; in the embodiment shown in Figure 4b , in the projection in the direction perpendicular to the plane of the first substrate 10, the shape of the first contact pad 120 is rectangular. It should be noted that the shape of the second contact pad 220 is the same as that of the first contact pad 120.

[0131] It should be noted that the shapes of the first contact pad and the second contact pad can be circular or rectangular, but are not limited to circular or rectangular. In actual operation, the shapes of the first contact pad and the second contact pad can be determined by the photolithography process.

[0132] In one embodiment, along the direction of extension of the step, the width of the first portion 121 is greater than half of the width of the first contact pad 120. When the shape of the first contact pad 120 is circular, the maximum width of the first contact pad 120 is defined as the width of the first portion 121, and the maximum width of the first contact pad 120 is defined as the width of the first contact pad 120.

[0133] Along the direction of extension of the step, the width of the third portion 221 is greater than half of the width of the second contact pad 220. When the shape of the second contact pad 220 is circular, the maximum width of the second contact pad 220 is defined as the width of the third portion 221, and the maximum width of the second contact pad 220 is defined as the width of the second contact pad 220.

[0134] In one embodiment, the height range of the part where the second portion 122 is higher than the first portion 121 is 100 nm - 500 nm. Specifically, refer to Figure 3f , that is, the height range of h1 in the figure is 100 nm - 500 nm.

[0135] The height range of the part where the fourth portion 222 is higher than the third portion 221 is 100 nm - 500 nm. Specifically, refer to Figure 3g , that is, the height range of h2 in the figure is 100 nm - 500 nm.

[0136] In one embodiment, the first chip includes a first via structure 11, and the first via structure 11 is located in the first substrate 10 on one side of the second surface 105 of the first substrate 10; in the projection along the direction perpendicular to the plane of the first substrate 10, the projection image of the gap 30 falls within the projection image of the first via structure 11.

[0137] The second chip includes a second via structure 21, and the second via structure 21 is located in the second substrate 20 on one side of the fourth surface 205 of the second substrate 20; in the projection along the direction perpendicular to the plane of the second substrate 20, the projection image of the gap 30 falls within the projection image of the second via structure 21.

[0138] It should be explained that the plane where the upper surface and the lower surface of the substrate are located, or strictly speaking, the central plane in the thickness direction of the substrate, is determined as the substrate plane.

[0139] In one embodiment, in a projection in a direction perpendicular to the plane of the first substrate 10, a projected image of the first via structure 11 falls within a projected image of the first contact pad 120;

[0140] In a projection in a direction perpendicular to the plane of the second substrate 20, a projected image of the second via structure 21 falls within a projected image of the second contact pad 220.

[0141] In one embodiment, bonding the first chip and the second chip includes: bonding the first chip and the second chip in an up-and-down mirror image manner.

[0142] In one embodiment, forming a gap 30 between the first contact pad 120 and the second contact pad 220 includes: forming a gap 30 between a second portion 122 of the first contact pad 120 and a fourth portion 222 of the second contact pad 220.

[0143] An embodiment of the present application further provides a semiconductor chip structure, as Figure 3h shown, the semiconductor chip structure includes:

[0144] A first chip, the first chip includes a first substrate 10, the first substrate 10 includes opposite first and second surfaces 104 and 105; the first chip further includes a first groove 103 within the first substrate 10 on one side of the first surface 104, and a first contact pad 120 located within the first groove 103;

[0145] A second chip, the second chip includes a second substrate 20, the second substrate 20 includes opposite third and fourth surfaces 204 and 205; the second chip further includes a second groove within the second substrate 20 on one side of the third surface 204, and a second contact pad 220 located within the second groove;

[0146] The first contact pad 120 of the first chip contacts the second contact pad 220 of the second chip, and a gap 30 is formed between the first contact pad 120 and the second contact pad 220.

[0147] In one embodiment, a portion of the first contact pad 120 protruding from the first surface 104 of the first substrate 10 is arc-shaped on the side close to the first substrate 10.

[0148] A portion of the second contact pad 220 protruding from the third surface 204 of the second substrate 20 is arc-shaped on the side close to the second substrate 20. Thus, compared with a right-angled shape, the arc shape can, during subsequent bonding, even if expansion and extrusion occur, due to the smooth characteristic of its arc-shaped structure, avoid cracking the first substrate and the second substrate.

[0149] The arc-shaped portion in the first contact pad 120 may be as Figure 5a shown and does not extend to the inner sidewall of the first substrate 10, or may be as Figure 5b shown and extend to the inner sidewall of the first substrate 10.

[0150] In one embodiment, the first chip further includes a first via structure 11 located in the first substrate 10 on one side of the second surface 105 of the first substrate 10; in a projection in a direction perpendicular to the plane of the first substrate 10, the projected image of the gap 30 falls within the projected image of the first via structure 11;

[0151] The second chip further includes a second via structure 21 located in the second substrate 20 on one side of the fourth surface 205 of the second substrate 20; in a projection in a direction perpendicular to the plane of the second substrate 20, the projected image of the gap 30 falls within the projected image of the second via structure 21.

[0152] In one embodiment, in a projection in a direction perpendicular to the plane of the first substrate 10, the projected image of the first via structure 11 falls within the projected image of the first contact pad 120;

[0153] In a projection in a direction perpendicular to the plane of the second substrate 20, the projected image of the second via structure 21 falls within the projected image of the second contact pad 220.

[0154] In one embodiment, in a projection in a direction perpendicular to the plane of the first substrate 10, the shape of the first contact pad 120 is circular or rectangular;

[0155] In a projection in a direction perpendicular to the plane of the second substrate 20, the shape of the second contact pad 220 is circular or rectangular.

[0156] Specifically, as Figure 4a and Figure 4b shown, in the embodiment shown in Figure 4a , in a projection in a direction perpendicular to the plane of the first substrate 10, the shape of the first contact pad 120 is circular; in the embodiment shown in Figure 4b , in a projection in a direction perpendicular to the plane of the first substrate 10, the shape of the first contact pad 120 is rectangular. It should be noted that the shape of the second contact pad 220 is the same as that of the first contact pad 120.

[0157] It should be noted that the shapes of the first contact pad and the second contact pad can be circular or rectangular, but are not limited to circular or rectangular. In actual operation, the shapes of the first contact pad and the second contact pad can be determined by a lithography process.

[0158] The above is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A chip bonding method, characterized in that, comprising: providing a first chip; the first chip includes a first substrate, the first substrate includes opposite first and second surfaces; the first chip further includes a first groove in the first substrate on one side of the first surface, and a first contact pad in the first groove; the first contact pad includes a first part and a second part, the first part is lower than the first surface of the first substrate, and the second part is higher than the first surface of the first substrate, so as to form the stepped first contact pad; providing a second chip; the second chip includes a second substrate, the second substrate includes opposite third and fourth surfaces; the second chip further includes a second groove in the second substrate on one side of the third surface, and a second contact pad in the second groove; the second contact pad includes a third part and a fourth part, the third part is lower than the third surface of the second substrate, and the fourth part is higher than the third surface of the second substrate, so as to form the stepped second contact pad; bonding the first chip and the second chip, wherein the first part and the second part of the first chip are respectively in contact with the fourth part and the third part of the second chip; after bonding the first chip and the second chip, a void is formed between the first contact pad and the second contact pad; wherein, the first chip further includes a first via structure in the first substrate on one side of the second surface of the first substrate; in a projection along a direction perpendicular to the plane of the first substrate, the projection image of the void falls within the projection image of the first via structure; the first groove is located above the first via structure; the second chip further includes a second via structure in the second substrate on one side of the fourth surface of the second substrate; in a projection along a direction perpendicular to the plane of the second substrate, the projection image of the void falls within the projection image of the second via structure; the second groove is located above the second via structure.

2. The method according to claim 1, characterized in that, the part of the second part of the first contact pad that is higher than the first surface of the first substrate is arc-shaped on the side close to the first substrate; the part of the fourth part of the second contact pad that is higher than the third surface of the second substrate is arc-shaped on the side close to the second substrate.

3. The method according to claim 1, characterized in that, in a projection along a direction perpendicular to the plane of the first substrate, the projection image of the first via structure falls within the projection image of the first contact pad; in a projection along a direction perpendicular to the plane of the second substrate, the projection image of the second via structure falls within the projection image of the second contact pad.

4. The method according to claim 1, characterized in that, in a projection along a direction perpendicular to the plane of the first substrate, the shape of the first contact pad is circular or rectangular; In a projection in a direction perpendicular to the plane of the second substrate, the shape of the second contact pad is circular or rectangular.

5. The method according to claim 1, wherein along the direction in which the step extends, the width of the first portion is greater than half of the width of the first contact pad; the width of the third portion is greater than half of the width of the second contact pad.

6. The method according to claim 5, wherein the height of the portion of the second portion that is higher than the first portion ranges from 100 nm to 500 nm; the height of the portion of the fourth portion that is higher than the third portion ranges from 100 nm to 500 nm.

7. The method according to claim 1, wherein providing the first chip includes: forming a first substrate, the first substrate including a first base plate, a first via structure penetrating the first base plate, and a first dielectric layer covering the upper surfaces of the first base plate and the first via structure; etching the first substrate to form a first groove, the first groove being located above the first via structure; filling the first groove to form a first contact pad pre-layer; etching a part of the first contact pad pre-layer to form a first contact pad; providing the second chip includes: forming a second substrate, the second substrate including a second base plate, a second via structure penetrating the second base plate, and a second dielectric layer covering the upper surfaces of the second base plate and the second via structure; etching the second substrate to form a second groove, the second groove being located above the second via structure; filling the second groove to form a second contact pad pre-layer; etching a part of the second contact pad pre-layer to form a second contact pad.

8. The method according to claim 1, wherein bonding the first chip and the second chip; includes: bonding the first chip and the second chip in an up-down manner in a mirror image manner.

9. The method according to claim 1, wherein forming a gap between the first contact pad and the second contact pad includes: forming a gap between the second portion of the first contact pad and the fourth portion of the second contact pad.

10. A semiconductor chip structure, wherein comprising: a first chip, the first chip including a first substrate, the first substrate including opposite first and second surfaces; the first chip further includes a first groove in the first substrate on one side of the first surface, and a first contact pad in the first groove; a second chip, the second chip including a second substrate, the second substrate including opposite third and fourth surfaces; the second chip further includes a second groove in the second substrate on one side of the third surface, and a second contact pad in the second groove; the first contact pad of the first chip contacts the second contact pad of the second chip, and a gap is formed between the first contact pad and the second contact pad; Wherein, the first chip further includes a first via structure, and the first via structure is located in the first substrate on one side of the second surface of the first substrate; in a projection in a direction perpendicular to the plane of the first substrate, a projected image of the void falls within a projected image of the first via structure; the first groove is located above the first via structure. The second chip further includes a second via structure, and the second via structure is located in the second substrate on one side of the fourth surface of the second substrate; in a projection in a direction perpendicular to the plane of the second substrate, a projected image of the void falls within a projected image of the second via structure; the second groove is located above the second via structure.

11. The semiconductor chip structure according to claim 10, wherein a portion of the first contact pad protruding from the first surface of the first substrate is arc-shaped on the side close to the first substrate; a portion of the second contact pad protruding from the third surface of the second substrate is arc-shaped on the side close to the second substrate.

12. The semiconductor chip structure according to claim 10, wherein in a projection in a direction perpendicular to the plane of the first substrate, a projected image of the first via structure falls within a projected image of the first contact pad; in a projection in a direction perpendicular to the plane of the second substrate, a projected image of the second via structure falls within a projected image of the second contact pad.

13. The semiconductor chip structure according to claim 10, wherein in a projection in a direction perpendicular to the plane of the first substrate, the shape of the first contact pad is circular or rectangular; in a projection in a direction perpendicular to the plane of the second substrate, the shape of the second contact pad is circular or rectangular.

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