Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same are disclosed. The method includes: forming a first groove at the boundary between a first device region and a second device region, the first groove extending through a channel stack and a substrate of a first predetermined thickness, the bottom of the first groove being located within the substrate; forming a first protective layer on the sidewalls of the first groove; etching a substrate of a second predetermined thickness at the boundary between the first and second device regions, using the first protective layer as a mask, to form a second groove in the substrate, the sidewalls of the second groove protruding outward relative to the sidewalls of the first groove, and the top of the second groove communicating with the bottom of the first groove; and forming dielectric walls in the first and second grooves. This improves the electrical isolation effect of the dielectric walls between well regions in the substrate of the first device region and well regions in the substrate of the second device region, thereby improving the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor transistors are evolving towards higher device density and higher integration, and semiconductor process nodes are continuously shrinking in accordance with Moore's Law. Transistors, as the most basic semiconductor material, are currently widely used. Therefore, as the device density and integration of semiconductor transistors increase, the channel length of transistors must be continuously shortened to adapt to the shrinking process nodes.

[0003] To better adapt to the requirement of proportionally shrinking transistor dimensions, semiconductor manufacturing processes have gradually transitioned from planar transistors to more efficient three-dimensional transistors, such as FinFETs and Gate-all-around (GAA) transistors. GAA transistors include vertical and horizontal types. In a GAA transistor, the gate surrounds the channel region from all sides. Compared to planar transistors, GAA transistors offer stronger control over the channel and better suppress short-channel effects.

[0004] As device sizes continue to shrink, improving the electrical isolation effect of dielectric walls on well regions in the substrate of adjacent device areas becomes increasingly difficult and challenging. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial for further improving semiconductor performance.

[0006] To address the aforementioned problems, the present invention provides a semiconductor structure comprising: a substrate, the substrate including a base and fins protruding from the base, the substrate including adjacent first device regions and second device regions; a channel structure layer suspended above the fins of the first and second device regions, the channel structure layer including one or more spaced-apart channel layers in a longitudinal direction; an isolation layer located on the substrate of the first and second device regions and exposing the sidewalls of the channel structure layer; and a dielectric wall penetrating the channel structure at the junction of the first and second device regions. The system comprises a layer, fins, and a substrate of a certain thickness. The dielectric wall includes a bottom dielectric wall located in the substrate and a top dielectric wall located on top of the bottom dielectric wall, the sidewalls of the bottom dielectric wall being recessed inward relative to the sidewalls of the channel structure layer; a gate dielectric layer conformally covering a portion of the top, a portion of the sidewalls and a portion of the bottom of the channel structure layer, the exposed dielectric wall sidewalls of the channel layer, and the top of the isolation layer; and a gate electrode layer located on top of the isolation layer and spanning the channel structure layer and the dielectric wall, the gate electrode layer surrounding and covering the gate dielectric layer.

[0007] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a substrate and fins protruding from the substrate, the substrate including adjacent first device regions and second device regions, one or more longitudinally stacked channel stacks being formed on the substrate of the first device regions and the second device regions, each channel stack including a sacrificial layer and a channel layer located on the sacrificial layer, the substrate including the first device regions and the second device regions; forming a first groove at the junction of the first device regions and the second device regions, the first groove extending through the channel stacks and the substrate to a first predetermined thickness, the bottom of the first groove being located in the substrate; forming a first protective layer on the sidewall of the first groove; at the junction of the first device regions and the second device regions, using the first protective layer as a mask, etching the substrate to a second predetermined thickness at the bottom of the first groove, forming a second groove in the substrate, the sidewall of the second groove protruding outward relative to the sidewall of the first groove, and the top of the second groove communicating with the bottom of the first groove; forming dielectric walls in the first groove and the second groove.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] This invention provides a semiconductor structure in which a dielectric wall penetrates a channel structure layer, a fin, and a portion of the substrate at the boundary between a first device region and a second device region. The dielectric wall includes a bottom dielectric wall located within the substrate and a top dielectric wall located above the bottom dielectric wall. The sidewall of the bottom dielectric wall is recessed inward relative to the sidewall of the channel structure layer. A well region is typically formed in the substrate. Compared to current solutions where the sidewalls of the top and bottom dielectric walls are flush, the dielectric wall in this invention includes a bottom dielectric wall located within the substrate, and the sidewall of the bottom dielectric wall is recessed inward relative to the sidewall of the channel structure layer. By making the lateral dimension of the bottom dielectric wall larger than that of the top dielectric wall, the bottom dielectric wall, while maintaining electrical isolation between the first and second device regions, increases the distance between the well regions in the first and second device region substrates. This improves the electrical isolation effect of the dielectric wall between the well regions in the first and second device region substrates, thereby improving the performance of the semiconductor structure.

[0010] Accordingly, embodiments of the present invention provide a method for forming a semiconductor structure, wherein a first groove is formed at the junction of a first device region and a second device region, the first groove being formed through a channel stack and a substrate of a first predetermined thickness, the bottom of the first groove being located in the substrate; a first protective layer is formed on the sidewall of the first groove; at the junction of the first device region and the second device region, using the first protective layer as a mask, the substrate of a second predetermined thickness is etched to form a second groove in the substrate, the sidewall of the second groove protruding outward relative to the sidewall of the first groove, and the top of the second groove communicating with the bottom of the first groove; and a dielectric wall is formed in the first groove and the second groove. Well regions are typically formed in the substrate. Compared to the current approach where the sidewalls of the first and second grooves formed in the channel stack and substrate are flush, in this embodiment of the invention, the sidewall of the second groove protrudes outward relative to the sidewall of the first groove, making the lateral dimension of the second groove larger than that of the first groove. This correspondingly increases the lateral dimension of the dielectric wall formed in the second groove. As a result, the dielectric wall formed in the second groove, while satisfying the electrical isolation effect between the first and second device regions, increases the distance between the well regions in the first and second device region substrates. This improves the electrical isolation effect of the dielectric wall between the well regions in the first and second device region substrates, thereby improving the performance of the semiconductor structure. Attached Figure Description

[0011] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0012] Figure 4 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0013] Figures 5 to 22 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0014] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of a semiconductor structure needs further improvement, using a specific semiconductor structure formation method as an example.

[0015] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0016] refer to Figure 1 A substrate is provided, the substrate including a substrate 10 and fins 11 protruding from the substrate 10. The substrate includes adjacent first device regions 10A and second device regions 10B. One or more longitudinally stacked channel stacks 15 are formed on the fins 11 of the first device regions 10A and the second device regions 10B. Each channel stack 15 includes a sacrificial layer 12 and a channel layer 13 located on the sacrificial layer 12. A hard mask layer 14 is formed on the top of the channel stack 15. An isolation layer 16 is formed on the exposed substrate 10 of the channel stack. The isolation layer 16 covers the sidewalls of the channel stack 15.

[0017] refer to Figure 2 At the junction of the first device region 10A and the second device region 10B, a groove 17 is formed that penetrates the channel stack 15 and a portion of the thickness of the substrate.

[0018] refer to Figure 3 Dielectric walls 18 are formed in the groove 17.

[0019] Research has revealed that well regions are typically formed in the substrate. Due to the shrinking of process nodes, while the dielectric wall 18 formed in the groove 17 satisfies the electrical isolation effect between the first device region 10A and the second device region 10B, the continuous shrinking of the dielectric wall 18 in the substrate makes the distance between the well regions in the first device region 10A and the second device region 10B smaller and smaller. This reduces the electrical isolation effect of the dielectric wall 18 between the well regions in the first device region 10A and the second device region 10B in the substrate, thereby affecting the performance of the semiconductor structure.

[0020] To address the technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a substrate and fins protruding from the substrate, the substrate including adjacent first device regions and second device regions, one or more longitudinally stacked channel layers forming on the substrate of the first device regions and the second device regions, each channel layer including a sacrificial layer and a channel layer located on the sacrificial layer, the substrate including the first device regions and the second device regions; forming a first groove at the junction of the first device regions and the second device regions, penetrating the channel layers and the substrate of a first predetermined thickness, the bottom of the first groove being located in the substrate; forming a first protective layer on the sidewall of the first groove; at the junction of the first device regions and the second device regions, using the first protective layer as a mask, etching a substrate of a second predetermined thickness at the bottom of the first groove to form a second groove in the substrate, the sidewall of the second groove protruding outward relative to the sidewall of the first groove, and the top of the second groove communicating with the bottom of the first groove; forming dielectric walls in the first groove and the second groove.

[0021] In this embodiment of the invention, the sidewall of the second groove protrudes outward relative to the sidewall of the first groove, making the lateral dimension of the second groove larger than that of the first groove. This correspondingly increases the lateral dimension of the dielectric wall formed in the second groove. As a result, while satisfying the electrical isolation effect between the first device region and the second device region, the dielectric wall formed in the second groove increases the distance between the well regions in the substrate of the first device region and the well regions in the substrate of the second device region. This improves the electrical isolation effect of the dielectric wall between the well regions in the substrate of the first device region and the well regions in the substrate of the second device region, thereby improving the performance of the semiconductor structure.

[0022] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0023] Figure 4 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0024] The semiconductor structure includes: a substrate, comprising a substrate 200 and fins 201 protruding from the substrate 200, the substrate including adjacent first device region 200A and second device region 200B; a channel structure layer 290, suspended on the fins 201 of the first device region 200A and second device region 200B, the channel structure layer 290 including one or more spaced-apart channel layers 203 in the longitudinal direction; an isolation layer 206 located on the substrate 200 of the first device region 200A and second device region 200B, and exposing the sidewalls of the channel structure layer 290; and a dielectric wall 219 penetrating the channel structure layer 290 at the junction of the first device region 200A and second device region 200B. The fin 201 and a partial thickness of the substrate 200, the dielectric wall 219 includes a bottom dielectric wall 270 located in the substrate 200 and a top dielectric wall 280 located on top of the bottom dielectric wall 270, the sidewall of the bottom dielectric wall 270 being recessed inward relative to the sidewall of the channel structure layer 290; the gate dielectric layer 224 conformally covers part of the top, part of the sidewall and part of the bottom of the channel structure layer 290, the sidewall of the dielectric wall 219 exposed in the channel layer 203, and the top of the isolation layer 206; the gate electrode layer 225 is located on top of the isolation layer 206 and spans the channel structure layer 290 and the dielectric wall 219, the gate electrode layer 225 surrounding and covering the gate dielectric layer 224.

[0025] In this embodiment of the invention, the dielectric wall 219 includes a bottom dielectric wall 270 located in the substrate 200, and the sidewall of the bottom dielectric wall 270 is recessed inward relative to the sidewall of the channel structure layer 290. By making the lateral dimension of the bottom dielectric wall 270 larger than the lateral dimension of the top dielectric wall 280, the bottom dielectric wall 270, while satisfying the electrical isolation effect between the first device region 200A and the second device region 200B, increases the distance between the well region in the substrate of the first device region 200A and the well region in the substrate of the second device region 200B, thereby improving the electrical isolation effect of the dielectric wall 219 between the well region in the substrate of the first device region 200A and the well region in the substrate of the second device region 200B, and thus improving the performance of the semiconductor structure.

[0026] In this embodiment, the first device region 200A is used to form a first type transistor, and the second device region 200B is used to form a second type transistor. The first type transistor and the second type transistor have different channel conductivity types.

[0027] In this embodiment, the first type transistor is an NMOS transistor and the second type transistor is a PMOS transistor; in other embodiments, the first type transistor is a PMOS transistor and the second type transistor is an NMOS transistor.

[0028] In this embodiment, the substrate has a three-dimensional structure, including a substrate 200 and fins 201 disposed on the substrate 200 in the first device region 200A and the second device region 200B. In other embodiments, the substrate may also be a planar substrate. In this embodiment, the substrate 200 is a silicon substrate, and the fins 201 are made of the same material as the substrate 200, namely silicon.

[0029] In this embodiment, the channel structure layer 290 is suspended on the fins 201 of the first device region 200A and the second device region 200B, and the channel structure layer 290 includes one or more channel layers 203 arranged at intervals in the longitudinal direction.

[0030] In this embodiment, the channel layer 203 is used to provide conductive channels for the first type transistor and the second type transistor.

[0031] In this embodiment, the material of the channel layer 203 includes one or more of silicon, silicon germanide, germanium, and group III-V semiconductor materials. The material of the channel layer 203 is determined according to the channel conductivity type and performance of the transistor. As an example, the channel layer 203 of the first device region 200A and the second device region 200B is made of the same material, silicon. In other embodiments, the channel layer materials of the first device region and the second device region may be different.

[0032] In this embodiment, there are two channel layers 203. In other embodiments, the number of channel layers may be other numbers.

[0033] In this embodiment, the dielectric wall 219 penetrates the channel structure layer 290, the fin 201, and a portion of the substrate 200 at the junction of the first device region 200A and the second device region 200B. The dielectric wall 219 includes a bottom dielectric wall 270 located in the substrate 200 and a top dielectric wall 280 located on top of the bottom dielectric wall 270. The sidewall of the bottom dielectric wall 270 is recessed inward relative to the sidewall of the channel structure layer 290.

[0034] In this embodiment, the dielectric wall 219 is made of one or both of silicon oxide and silicon boron carbonitride.

[0035] It should be noted that, taking the direction perpendicular to the extension direction of the channel structure layer 290 as the lateral direction, the lateral dimension of the inward indentation of the sidewall of the bottom dielectric wall 270 relative to the sidewall of the channel structure layer 290 should not be too large or too small. If the lateral dimension of the inward indentation of the sidewall of the bottom dielectric wall 270 relative to the sidewall of the channel structure layer 290 is too large, it will easily lead to the substrate 200 below the channel structure layer 290 being too small, which will result in a more severe self-heating effect of the semiconductor device, thereby affecting the performance of the semiconductor structure. If the lateral dimension of the inward indentation of the sidewall of the bottom dielectric wall 270 relative to the sidewall of the channel structure layer 290 is too small, the electrical isolation effect of the bottom dielectric wall 270 between the well region in the first device region 200A substrate and the well region in the second device region 200B substrate will decrease, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the lateral dimension of the inward indentation of the sidewall of the bottom dielectric wall 270 relative to the sidewall of the channel structure layer 290 is 3 nanometers to 20 nanometers. For example, the lateral dimension of the inward indentation of the sidewall of the bottom dielectric wall 270 relative to the sidewall of the channel structure layer 290 is 7 nanometers, 10 nanometers, or 15 nanometers.

[0036] It should also be noted that the thickness of the bottom dielectric wall 270 should not be too large or too small. If the thickness of the bottom dielectric wall 270 is too large, it may cause the substrate 200 in the first device region 200A to be completely isolated from the substrate 200 in the second device region 200B, thereby affecting the performance of the semiconductor structure. If the thickness of the bottom dielectric wall 270 is too small, it may cause the electrical isolation effect between the well region in the substrate of the first device region 200A and the well region in the substrate of the second device region 200B to decrease, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the bottom dielectric wall 270 is 8 nanometers to 30 nanometers.

[0037] In this embodiment, the top dielectric wall 280 includes a first sub-dielectric wall 217 located in the fin 201 and a portion of the thickness of the substrate 200, and a second sub-dielectric wall 218 located on top of the first sub-dielectric wall 217. The sidewall of the first sub-dielectric wall 217 protrudes outward relative to the sidewall of the channel structure layer 290.

[0038] The sidewall of the first sub-dielectric wall 217 protrudes outward relative to the sidewall of the channel structure layer 290. That is, the direction perpendicular to the extension direction of the channel structure layer 290 is the lateral direction. The lateral dimension of the first sub-dielectric wall 217 is small. Therefore, while ensuring that the first sub-dielectric wall 217 plays an isolation role between the first device region 200A and the second device region 200B, the volume of the fins 201 and the substrate 200 on both sides of the first sub-dielectric wall 217 is increased, thereby improving the self-heating effect of the semiconductor device.

[0039] The direction perpendicular to the extension direction of the channel structure layer 290 is defined as the lateral direction. The lateral dimension of the sidewall of the first sub-dielectric wall 217 protruding outward relative to the sidewall of the channel structure layer 290 should not be too large or too small. If the lateral dimension of the sidewall of the first sub-dielectric wall 217 protruding outward relative to the sidewall of the channel structure layer 290 is too large, it can easily lead to a decrease in the electrical isolation effect between the well region in the substrate of the first device region 200A and the well region in the substrate of the second device region 200B, thereby affecting the performance of the semiconductor structure. If the lateral dimension of the sidewall of the first sub-dielectric wall 217 protruding outward relative to the sidewall of the channel structure layer 290 is too small, it can easily lead to poor improvement of the self-heating effect of the semiconductor device, reducing the performance of the semiconductor structure. Therefore, in this embodiment, the direction perpendicular to the extension direction of the channel structure layer 290 is defined as the lateral direction, and the lateral dimension of the sidewall of the first sub-dielectric wall 217 protruding outward relative to the sidewall of the channel structure layer 290 is 1 nanometer to 5 nanometers.

[0040] In this embodiment, the first sub-dielectric wall 217 and the bottom dielectric wall 270 are an integral structure, and the dielectric constant of the material of the second sub-dielectric wall 218 is greater than that of the material of the first sub-dielectric wall 217.

[0041] To achieve electrical isolation between the well regions in the first device region 200A substrate and the well regions in the second device region 200B substrate, and to reduce stress on the substrate, the first sub-dielectric wall 217 and the bottom dielectric wall 270 are integrally structured. Both the first sub-dielectric wall 217 and the bottom dielectric wall 270 are made of dielectric materials that generate low stress. As an example, the materials for the first sub-dielectric wall 217 and the bottom dielectric wall 270 are silicon oxide.

[0042] In this embodiment, the second sub-dielectric wall 218 serves to isolate the channel structure layers 290 of the first device region 200A and the second device region 200B, and also to reduce the probability of damage to the bottom dielectric wall 270 and the first sub-dielectric wall 217. Therefore, the material of the second sub-dielectric wall 218 is a dielectric material with high hardness, such as one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, and silicon boron carbonitride. In this embodiment, the material of the second sub-dielectric wall 218 is silicon boron carbonitride. Using silicon boron carbonitride allows the second sub-dielectric wall 218 to have high hardness while reducing the stress exerted by the second sub-dielectric wall 218 on the channel structure layers 290 on both sides.

[0043] It should be noted that the distance from the bottom of the dielectric wall 219 to the top of the substrate 200 should not be too large or too small. If the distance is too large, it increases the difficulty of filling the bottom dielectric wall 270 during its formation, thereby increasing the probability of void defects forming in the bottom dielectric wall 270. Consequently, this can easily lead to a decrease in the electrical isolation effect between the dielectric wall and the well regions in the first device region 200A and the second device region 200B substrates, thus affecting the performance of the semiconductor structure. Conversely, if the distance is too small, it can easily lead to a decrease in the electrical isolation effect between the dielectric wall and the well regions in the first device region 200A and the second device region 200B substrates, thus affecting the performance of the semiconductor structure. Therefore, in this embodiment, the distance from the bottom of the dielectric wall 219 to the top of the substrate 200 is between 5 nanometers and 300 nanometers.

[0044] In this embodiment, the semiconductor structure further includes an isolation layer 206 located on the substrate 200 of the first device region 200A and the second device region 200B, and exposing the sidewall of the channel structure layer 290.

[0045] The isolation layer 206 is used to isolate adjacent devices. Therefore, the material of the isolation layer 206 is a dielectric material, which may include silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation layer 206 is silicon oxide.

[0046] In this embodiment, the isolation layer 206 contains doped ions, including Si.

[0047] Since the dielectric wall 219 includes a bottom dielectric wall 270 and a top dielectric wall 280 located on top of the bottom dielectric wall 270, the process of forming the dielectric wall 219 during the formation of the semiconductor structure typically includes a step of etching back the material corresponding to the bottom dielectric wall 270. By introducing doped ions into the isolation layer, the etch resistance of the isolation layer 206 is improved, thereby reducing the probability of the isolation layer 206 being damaged in the etching back step. This helps ensure that the thickness and quality of the isolation layer 206 meet performance requirements.

[0048] In this embodiment, the gate dielectric layer 224 conformally covers part of the top, part of the sidewalls and part of the bottom of the channel structure layer 290, the exposed dielectric wall 219 sidewall of the channel layer 203, and the top of the isolation layer 206. The gate dielectric layer 224 is used to isolate the gate electrode layer 225 and the channel.

[0049] In this embodiment, the material of the gate dielectric layer 224 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0050] In this embodiment, the gate electrode layer 225 is located on top of the isolation layer 206 and spans the channel structure layer 290 and the dielectric wall 219, surrounding and covering the gate dielectric layer 224. Specifically, the gate dielectric layer 224 may include a high-k gate dielectric layer and a gate oxide layer located between the high-k gate dielectric layer and the channel layer 203. The high-k gate dielectric layer is made of a high-k dielectric material, which refers to a dielectric material with a relative permittivity greater than that of silicon oxide. For example, the high-k gate dielectric layer may be made of HfO2, and the gate oxide layer may be made of SiO2.

[0051] In this embodiment, the gate electrode layer 225 is located on top of the isolation layer 206 and spans the channel structure layer 290 and the dielectric wall 219, and the gate electrode layer 225 surrounds and covers the gate dielectric layer 224. The gate electrode layer 225 is used for subsequent electrical connection with external interconnect structures. The material of the gate electrode layer 225 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0052] As an example, the gate electrode layer 225 may include a work function layer and an electrode layer located on the work function layer, wherein the work function layer is used to adjust the threshold voltage of the transistor. In other embodiments, the gate electrode layer may also include only the work function layer.

[0053] In this embodiment, the semiconductor structure further includes a sidewall 220 located on the sidewall of the gate electrode layer 225. Specifically, the sidewall 220 is located on the sidewall of the gate dielectric layer 224. The sidewall 220 is used to protect the sidewalls of the gate dielectric layer 224 and the gate electrode layer 225. The sidewall 220 can be a single-layer structure or a multilayer structure, and the material of the sidewall 220 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall 220 is a single-layer structure, and the material of the sidewall 220 is silicon nitride.

[0054] In this embodiment, the semiconductor structure further includes an interlayer dielectric layer 221, located on top of the gate electrode layer 225 and the exposed isolation layer 206 of the sidewall 220, with the interlayer dielectric layer 221 covering the sidewall of the sidewall 220.

[0055] Interlayer dielectric layer 221 is used to isolate adjacent devices. The material of interlayer dielectric layer 221 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of interlayer dielectric layer 221 is silicon oxide.

[0056] In this embodiment, the semiconductor structure further includes a protective layer 209 located between the sidewall of the top dielectric wall 280 and the sidewall of the channel structure layer 290, and between the sidewall of the top dielectric wall 280 and the gate dielectric layer 224. During the formation process of the top dielectric wall 280, the protective layer 209 protects the sidewall of the channel structure layer 290, reducing the probability of damage to the channel structure layer 290 caused by related etching processes. Therefore, the material of the protective layer 209 is a dielectric material, such as one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, and silicon boron carbonitride. In this embodiment, the material of the protective layer 209 is silicon boron carbonitride.

[0057] It should be noted that, taking the direction perpendicular to the extension direction of the channel structure layer 290 as the lateral direction, the lateral dimension of the protective layer 209 should not be too large or too small. If the lateral dimension of the protective layer 209 is too large, it will easily lead to increased difficulty in forming the top dielectric wall 280 due to the smaller process window; if the lateral dimension of the protective layer 209 is too small, it will easily lead to a decrease in the protective effect of the protective layer 209 on the channel structure layer 290. Therefore, in this embodiment, taking the direction perpendicular to the extension direction of the channel structure layer 290 as the lateral direction, the lateral dimension of the protective layer 209 is 1 nanometer to 3 nanometers.

[0058] Figures 5 to 22 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0059] refer to Figures 5 to 6 A substrate is provided, the substrate including a substrate 100 and fins 101 protruding from the substrate 100. The substrate includes adjacent first device regions 100A and second device regions 100B. One or more longitudinally stacked channel stacks 105 are formed on the fins 101 of the first device regions 100A and the second device regions 100B. Each channel stack 105 includes a sacrificial layer 102 and a channel layer 103 located on the sacrificial layer 102.

[0060] The substrate provides a process platform for the fabrication process. In this embodiment, the first device region 100A is used to form a first-type transistor, and the second device region 100B is used to form a second-type transistor. The first-type transistor and the second-type transistor have different channel conductivity types. In this embodiment, the first-type transistor is an NMOS transistor, and the second-type transistor is a PMOS transistor; in other embodiments, the first-type transistor is a PMOS transistor, and the second-type transistor is an NMOS transistor.

[0061] In this embodiment, the material of the sacrificial layer 102 includes one or more of SiGe, SiC, and GaAs; the material of the channel layer 103 includes one or more of silicon, silicon germanide, germanium, and group III-V semiconductor materials. The material of the channel layer 103 is determined according to the channel conductivity type and performance of the transistor. As an example, the channel layer 103 of the first device region 100A and the second device region 100B is made of the same material, silicon. In other embodiments, the channel layer materials of the first device region and the second device region may be different.

[0062] In this embodiment, the substrate has a three-dimensional structure, including a substrate 100 and fins 101 disposed on the substrate 100 in the first device region 100A and the second device region 100b. In other embodiments, the substrate may also be a planar substrate. In this embodiment, the substrate 100 is a silicon substrate, and the fins 101 are made of the same material as the substrate 100, namely silicon.

[0063] In this embodiment, the steps of forming the substrate and channel stack 105 include: as follows Figure 5 As shown, an initial substrate 190 is provided, which includes adjacent first device region 100A and second device region 100B. One or more longitudinally stacked channel material stacks 193 are formed on the initial substrate 190. Each channel material stack 193 includes a sacrificial material layer 191 and a channel material layer 192 located on the sacrificial material layer 191. A hard mask layer 194 is formed on the channel material stack 193. Figure 6 As shown, the hard mask layer 194 is patterned, and the initial substrate 190 and the channel material stack 193 located on the initial substrate 190 are patterned using the patterned hard mask layer 194 as a mask. The initial substrate 190 is patterned as a substrate, which includes a substrate 100 and fins 101 on the substrate 100, which are respectively located on the first device region 100A and the second device region 100b. The channel material stack 193 is patterned as a channel stack 105 located on the fins 101.

[0064] In this embodiment, a channel stack 105 is formed on the fin 101, and the extension direction of the channel stack 105 is the same as the extension direction of the fin 101. The stacking direction of the plurality of channel stacks 105 is perpendicular to the surface of the substrate 100.

[0065] The channel stack 105 provides a technological basis for the subsequent formation of a channel layer with suspended space partitions.

[0066] As an example, the number of channel stacks 105 is two. In other embodiments, the number of channel stacks may also be other numbers.

[0067] In this embodiment, the channel layer 103 of the first device region 100A is used to provide a conductive channel for the first type of transistor, and the sacrificial layer 102 is used to support the channel layer 103. After the sacrificial layer 102 of the first device region 100A is subsequently removed, the channel layer 103 can be suspended in a spaced manner. The sacrificial layer 102 of the first device region 100A also occupies space for the subsequent formation of the gate dielectric layer and the gate electrode layer.

[0068] In this embodiment, the channel layer 103 of the second device region 100B is used to provide a conductive channel for the second type transistor, and the sacrificial layer 102 is used to support the channel layer 103. After the sacrificial layer 102 of the second device region 100B is subsequently removed, the channel layer 103 can be suspended in a spaced manner. The sacrificial layer 102 of the second device region 100B also occupies space for the subsequent formation of the gate dielectric layer and the gate electrode layer.

[0069] In this embodiment, the number of sacrificial layers 102 and channel layers 103 are the same.

[0070] refer to Figure 7 An isolation layer 106 is formed on top of the exposed substrate 100 of the channel stack 105, and the isolation layer 106 covers the sidewalls of the channel stack 105.

[0071] The isolation layer 106 protects the top of the substrate during the subsequent formation of the dielectric wall. In this embodiment, the material of the isolation layer 106 is a dielectric material. As an example, the material of the isolation layer 106 is silicon oxide.

[0072] refer to Figures 8 to 10 At the junction of the first device region 100A and the second device region 100B, a first groove 112 is formed that penetrates the channel stack 105 and the substrate of the first preset thickness H1. The bottom of the first groove 112 is located in the substrate 100.

[0073] The first groove 112 provides some space for the subsequent formation of the dielectric wall.

[0074] In this embodiment, in the step of forming the first groove 112, the first groove 112 includes a first sub-groove 108 that penetrates the channel stack 105 and a second sub-groove 110 located in the substrate of the first preset thickness H1.

[0075] In this embodiment, the step of forming the first groove 112 includes: as follows Figure 8 As shown, the trench stack 105 at the junction of the first device region 100A and the second device region 100B is etched to form a first sub-groove 108 penetrating the trench stack 105; as Figure 9 As shown, a second protective layer 109 is formed on the sidewall of the first sub-groove 108; using the second protective layer 109 as a mask, a substrate of a first preset thickness H1 at the bottom of the first sub-groove 108 is etched to form a second sub-groove 110 in the substrate. The sidewall of the second sub-groove 110 is recessed inward relative to the sidewall of the first sub-groove 108, and the top of the second sub-groove 110 is connected to the bottom of the first sub-groove 108. The second sub-groove 110 and the first sub-groove 108 constitute the first groove 112.

[0076] The sidewall of the second sub-groove 110 is recessed inward relative to the sidewall of the first sub-groove 108. That is, the direction perpendicular to the extension direction of the channel stack 105 is lateral. The lateral dimension of the second sub-groove 110 is small. Therefore, while ensuring that the dielectric wall subsequently formed in the second sub-groove 110 plays an isolation role between the first device region 100A and the second device region 100B, the volume of the fins 101 and the substrate 100 on both sides of the second sub-groove 110 is increased, thereby improving the self-heating effect of the semiconductor device.

[0077] In this embodiment, the process for forming the first sub-groove 108 includes a dry etching process.

[0078] Dry etching processes include anisotropic dry etching processes, which possess the characteristics of anisotropic etching. That is, the longitudinal etching rate is greater than the transverse etching rate, which can ensure the morphological quality of the exposed sidewalls of the trench stack 105 while forming the first sub-groove 108.

[0079] In this embodiment, the process of forming the second sub-groove 110 includes a dry etching process to improve the morphological quality of the sidewall of the second sub-groove 110.

[0080] It should be noted that the first preset thickness H1 of the second sub-groove 110 in the substrate should not be too large or too small. If the first preset thickness H1 is too large, it will easily occupy too much space of the subsequently formed second groove. Given that the bottom position of the second groove is determined, this reduces the electrical isolation effect of the dielectric wall formed in the second groove between the well regions in the first device region substrate and the well regions in the second device region substrate, thereby affecting the performance of the semiconductor structure. If the first preset thickness H1 is too small, it will easily cause the subsequently formed second groove to be located in the fin 101. Since the lateral dimension of the second groove is larger than the lateral dimension of the first groove 112, the effective area of ​​the fin 101 will be reduced, thereby affecting the carrier migration rate and thus affecting the performance of the semiconductor structure. Therefore, in this embodiment, the first preset thickness H1 of the second sub-groove 110 in the substrate is 2 nanometers to 270 nanometers. For example, the first preset thickness H1 of the second sub-groove 110 in the substrate is 50 nanometers, 100 nanometers, or 200 nanometers.

[0081] refer to Figure 9 After the first sub-groove 108 is formed and before the second sub-groove 110 is formed, the method further includes forming a second protective layer 109 on the sidewall of the first sub-groove 108.

[0082] During the formation of the second sub-groove 110, the second protective layer 109 protects the sidewalls of the channel stack 105, reducing the probability of damage to the channel layer 103 during the etching process. At the same time, during the formation of the second sub-groove 110, the second protective layer 109 acts as an etching mask, thereby enabling the formation of a second sub-groove 110 with a smaller lateral dimension.

[0083] It should be noted that, since the second protective layer 109 will be retained subsequently, the material of the second protective layer 109 is a dielectric material, such as one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, and silicon boronitride. In this embodiment, the material of the second protective layer 109 is silicon boronitride.

[0084] refer to Figure 11 A first protective layer 111 is formed on the sidewall of the first groove 112.

[0085] The first protective layer 111 protects the substrate exposed on the sidewall of the first groove 112, reducing the probability of damage to the exposed substrate caused by the relevant etching process in the subsequent step of forming the second groove.

[0086] In this embodiment, the step of forming the first protective layer 111 includes: forming a first protective material layer (not shown) on the top of the isolation layer 106 and the hard mask layer 194, and on the sidewall and bottom of the first groove 112; removing the first protective material layer on the top of the isolation layer 106 and the hard mask layer 194, and on the bottom of the first groove 112, with the remaining first protective material layer serving as the first protective layer 111.

[0087] In this embodiment, the process for forming the first protective material layer includes atomic layer deposition.

[0088] To reduce the probability of damage to the exposed substrate caused by subsequent etching processes, the first protective layer 111 needs to be made of a material with high hardness. Therefore, the material of the first protective layer 111 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, and silicon boron carbonitride. As an example, the material of the first protective layer 111 is silicon carbide.

[0089] It should be noted that the lateral dimension of the first protective layer 111 should not be too large or too small. If the lateral dimension of the first protective layer 111 is too large, the remaining space of the first groove 112 will be too small. Consequently, during the subsequent formation of the second groove, the small process window will increase the difficulty of forming the second groove, making it impossible for the lateral dimension of the second groove to meet the process requirements, thus affecting the performance of the semiconductor structure. If the lateral dimension of the first protective layer 111 is too small, the protective effect of the first protective layer 111 on the substrate exposed by the first groove 112 will be weakened during the subsequent formation of the second groove, increasing the probability of damage to the substrate exposed by the etching process, thus affecting the performance of the semiconductor structure. Therefore, in this embodiment, the lateral dimension of the first protective layer 111 is 1 nanometer to 3 nanometers, with the direction perpendicular to the extension direction of the channel stack 105 defined as the lateral direction. For example, the lateral dimension of the first protective layer 111 is 2 nanometers.

[0090] refer to Figure 12 At the junction of the first device region 100A and the second device region 100B, using the first protective layer 111 as a mask, a substrate 100 of a second preset thickness H2 is etched at the bottom of the first groove 112, forming a second groove 113 in the substrate 100. The sidewall of the second groove 113 protrudes outward relative to the sidewall of the first groove 112, and the top of the second groove 113 is connected to the bottom of the first groove 112.

[0091] In this embodiment, the sidewall of the second groove 113 protrudes outward relative to the sidewall of the first groove 112, making the lateral dimension of the second groove 113 larger than that of the first groove 112. This correspondingly increases the lateral dimension of the dielectric wall subsequently formed in the second groove 113. As a result, the dielectric wall subsequently formed in the second groove, while satisfying the electrical isolation effect between the first device region 100A and the second device region 100B, increases the distance between the well region in the substrate of the first device region 100A and the well region in the substrate of the second device region 100B. This improves the electrical isolation effect of the dielectric wall between the well regions in the substrate of the first device region 100A and the well regions in the substrate of the second device region 100B, thereby improving the performance of the semiconductor structure.

[0092] In this embodiment, the substrate 100 with a second preset thickness H2 at the bottom of the first groove 112 is etched, and the process of forming the second groove 113 in the substrate 100 includes a wet etching process.

[0093] The wet etching process has the advantages of simple operation and high efficiency. Moreover, the wet etching process has isotropic etching characteristics, so that during the formation of the second groove 113, the sidewall of the second groove 113 can protrude outward relative to the sidewall of the first groove 112.

[0094] In this embodiment, the distance by which the sidewall of the second groove 113 protrudes outward relative to the sidewall of the first groove 112 should not be too large or too small. If the distance by which the sidewall of the second groove 113 protrudes outward relative to the sidewall of the first groove 112 is too large, it will easily lead to an insufficient substrate volume under the channel stack 105, resulting in a more severe self-heating effect of the semiconductor device, thereby affecting the performance of the semiconductor structure. If the distance by which the sidewall of the second groove 113 protrudes outward relative to the sidewall of the first groove 112 is too small, the dielectric wall subsequently formed in the second groove 113 will reduce the electrical isolation effect between the well region in the first device region 100A substrate and the well region in the second device region 100B substrate, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the distance by which the sidewall of the second groove 113 is recessed inward relative to the sidewall of the first groove 112 is 3 nanometers to 20 nanometers. For example, the distance by which the sidewall of the second groove 113 is recessed inward relative to the sidewall of the first groove 112 is 7 nanometers, 10 nanometers, or 15 nanometers.

[0095] refer to Figures 13 to 15 A filling layer 115 is formed in the first groove 112 and the second groove 113.

[0096] During the subsequent ion implantation of the isolation layer 106, the probability of ion implantation causing damage to the substrate exposed by the first groove 112 and the second groove 113 is reduced.

[0097] Following ion implantation, the filler layer 115 will be removed. To facilitate this removal, the filler layer 115 is made of an easily removable material. As an example, the filler layer material is an organic material. For instance, the filler layer material is spin-on carbon (SOC).

[0098] refer to Figure 14 After the filling layer 115 is formed, the isolation layer 106 is ion implanted 116 to improve the etching resistance of the isolation layer 106.

[0099] During the subsequent formation of the bottom dielectric wall in the second groove 113 and the second sub-groove 110, since the material properties of the bottom dielectric wall are the same as those of the isolation layer, in order to reduce the probability of damage to the isolation layer 106 caused by the etching process of the bottom dielectric wall, ion implantation 116 is performed on the isolation layer 106 to change the etching rate of the isolation layer 106, improve the etching resistance of the isolation layer 106, and improve the etching selectivity between the bottom dielectric wall and the isolation layer 106.

[0100] In this embodiment, the implanted ions in the step of ion implantation 116 of the isolation layer 106 include Si.

[0101] Since Si ions are inert ions, after doping the top of the isolation layer 106, the etching rate of the ion-doped isolation layer 106 is reduced, and the impact on the insulation performance of the isolation layer 106 is small.

[0102] In this embodiment, the ion implantation process parameters include: ion implantation energy range of 1 keV to 10 keV; and ion implantation dose range of 1.0 E15 atom / cm. 2 Up to 8.0E16atom / cm 2 .

[0103] It should be noted that the ion implantation energy should not be too high or too low. If the ion implantation energy is too high, the etching rate of the ion-doped isolation layer 106 will be too low, increasing the difficulty of removing the isolation layer 106 to expose the channel stack 105 during the subsequent removal of a portion of the isolation layer 106, thus affecting the performance of the semiconductor structure. If the ion implantation energy is too low, the etching selectivity between the ion-doped isolation layer 106 and the bottom dielectric wall will be relatively small, increasing the probability of damage to the isolation layer 106 during the formation of the bottom dielectric wall in the second groove 113 and the second sub-groove 110, thus affecting the performance of the semiconductor structure. Therefore, in this embodiment, the ion implantation energy ranges from 1.0 keV to 10 keV.

[0104] It should also be noted that the ion implantation dose should not be too high or too low. If the ion implantation dose is too high, the etching rate of the ion-doped isolation layer 106 will be too low, increasing the difficulty of removing the isolation layer 106 to expose the channel stack 105 during the subsequent removal of a portion of the isolation layer 106, thus affecting the performance of the semiconductor structure. If the ion implantation dose is too low, the etching selectivity between the ion-doped isolation layer 106 and the bottom dielectric wall will be relatively small, increasing the probability of damage to the isolation layer 106 during the formation of the bottom dielectric wall in the second groove 113 and the second sub-groove 110, thus affecting the performance of the semiconductor structure. Therefore, in this embodiment, the ion implantation dose range is 1.0E15 atom / cm. 2 Up to 8.0E16atom / cm 2 .

[0105] refer to Figure 15 In this embodiment, after ion implantation 116 is performed on the isolation layer 106, the filling layer 115 is removed.

[0106] Continue to refer to Figure 15 Before forming dielectric walls in the first groove 112 and the second groove 113, the process further includes: removing the first protective layer 111.

[0107] Specifically, after removing the filler layer 115, the first protective layer 111 is removed.

[0108] The removal of the first protective layer 111 provides space for the subsequent formation of the dielectric wall.

[0109] In this embodiment, the process for removing the first protective layer 111 includes a wet etching process.

[0110] refer to Figures 16 to 18 Dielectric walls 119 are formed in the first groove 112 and the second groove 113.

[0111] The dielectric wall 119 can isolate the channel stack 105 between the first device region 100A and the second device region 100B. The dielectric wall 119 is used to isolate the first type transistor and the second type transistor, which is beneficial to achieve a smaller spacing between the first type transistor and the second type transistor.

[0112] In this embodiment, the dielectric wall 119 is also located in the substrate at the junction of the first device region 100A and the second device region 100B. This allows the dielectric wall 119 to not only satisfy the electrical isolation effect between the first device region 100A and the second device region 100B, but also increase the distance between the well regions in the substrate of the first device region 100A and the second device region 100B. Consequently, the dielectric wall 119 improves the electrical isolation effect between the well regions in the substrate of the first device region 100A and the second device region 100B, thereby improving the performance of the semiconductor structure.

[0113] In this embodiment, the step of forming dielectric walls 119 in the first groove 112 and the second groove 113 includes: as follows Figure 16 As shown, a bottom dielectric wall 117 is formed in the first groove 112 and the second groove 113; as Figure 17 As shown, remove the bottom dielectric wall 117 in the first sub-groove 108; as Figure 18 As shown, after removing the bottom dielectric wall 117 in the first sub-groove 108, a top dielectric wall 118 is formed in the first sub-groove 108. The dielectric constant of the material of the top dielectric wall 118 is greater than that of the material of the bottom dielectric wall 117. The top dielectric wall 118 and the bottom dielectric wall 117 constitute a dielectric wall 119.

[0114] The bottom dielectric wall 117 is designed to provide electrical isolation between the well regions in the first device region 100A substrate and the well regions in the second device region 100B substrate, while also reducing stress on the substrate. Therefore, the bottom dielectric wall 117 is made of a dielectric material that generates minimal stress. As an example, the material of the bottom dielectric wall 117 is silicon oxide.

[0115] The top dielectric wall 118 serves to isolate the channel stack 105 between the first device region 100A and the second device region 100B, and also reduces the probability of damage to the bottom dielectric wall 117 during subsequent manufacturing processes. Therefore, the top dielectric wall 118 is made of a dielectric material with high hardness, such as one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, and silicon boron carbonitride. In this embodiment, the top dielectric wall 118 is made of silicon boron carbonitride.

[0116] In this embodiment, the process of removing the bottom dielectric wall 117 in the first sub-groove 108 includes a dry etching process, which is beneficial for precise control of the etching amount and for improving the flatness of the top surface of the remaining bottom dielectric wall 117.

[0117] refer to Figure 19After forming the dielectric wall 119, the forming method further includes: in the first device region 100A and the second device region 100B, removing a portion of the thickness of the isolation layer 106 to expose all the sidewalls of the channel stack 105.

[0118] A portion of the isolation layer 106 is removed to provide space for the subsequent formation of the gate structure.

[0119] In this embodiment, after removing part of the thickness of the isolation layer 106, the top of the remaining isolation layer 106 is flush with the top of the fin 101.

[0120] In this embodiment, the process of removing a portion of the isolation layer 106 includes a dry etching process.

[0121] It should be noted that after removing part of the thickness of the isolation layer 106, the process also includes removing the hard mask layer 194 on top of the channel stack 105.

[0122] refer to Figure 20 After removing a portion of the isolation layer 106, the formation further includes: forming a dummy gate 122 that spans the channel stack 105 and the dielectric wall 119, the dummy gate 122 covering a portion of the top and a portion of the sidewalls of the channel stack 105.

[0123] The pseudo-gate 122 occupies space for the subsequent formation of the gate structure.

[0124] In this embodiment, the dummy gate 122 spans the channel stack 105 and the dielectric wall 119. That is, the dummy gate 122 covers part of the top of the channel stack 105 and the dielectric wall 119, part of the sidewall of the dielectric wall 119, and part of the sidewall of the channel stack 105 opposite to the dielectric wall 119.

[0125] In this embodiment, the dummy gate 119 includes a dummy gate layer. The material of the dummy gate layer includes polysilicon.

[0126] In this embodiment, the pseudo gate 119 is a strip structure, and the extension direction of the pseudo gate 119 is the same as the extension direction of the channel stack 105.

[0127] In this embodiment, after forming the dummy gate 119, the forming method further includes forming a sidewall 120 on the sidewall of the dummy gate 119.

[0128] Sidewall 120 is used to protect the sidewalls of the subsequently formed gate structure. Sidewall 120 can be a single-layer structure or a multilayer structure, and the material of sidewall 120 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, sidewall 120 is a single-layer structure, and the material of sidewall 120 is silicon nitride.

[0129] In this embodiment, after forming the sidewall 120, the formation method further includes: forming a source / drain doped layer (not shown) in the channel stack 105 on both sides of the dummy gate 122. The conductivity type of the doped ions in the source / drain doped layer is the same as the channel conductivity type of the transistor in the same region. The specific description of the source / drain doped layer will not be repeated here in this embodiment.

[0130] In this embodiment, the forming method further includes: forming an interlayer dielectric layer 121 on top of the isolation layer 106 exposed on the pseudo gate 122 and the sidewall 120, wherein the interlayer dielectric layer 121 covers the sidewall of the sidewall 120.

[0131] Interlayer dielectric layer 121 is used to isolate adjacent devices. The material of interlayer dielectric layer 121 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of interlayer dielectric layer 121 is silicon oxide.

[0132] refer to Figure 21 Remove the dummy gate 122 to form the gate opening 123.

[0133] The gate opening 123 provides space for the subsequent formation of the gate structure. Furthermore, after removing the dummy gate 122, the gate opening 123 exposes the channel stack 105, facilitating the subsequent removal of the sacrificial layer 102 through the gate opening 123. Specifically, the process for removing the dummy gate 122 includes one or both of dry etching and wet etching processes.

[0134] It should also be noted that after forming the gate opening 123, the process also includes: removing the sacrificial layer 102 from the first device region 100A and the second device region 100B.

[0135] refer to Figure 22 After removing the sacrificial layer 102 exposed by the gate opening 123, a gate dielectric layer 124 is formed in the gate opening 123 to conformally cover part of the top, part of the sidewalls and part of the bottom of the channel layer 103. After forming the gate dielectric layer 124, a gate electrode layer 125 is formed in the gate opening 123 that spans the channel layer 103 and the dielectric wall 119. The gate electrode layer 125 surrounds the gate dielectric layer 124. The gate dielectric layer 124 and the gate electrode layer 125 constitute the gate structure 126.

[0136] Specifically, when the device is in operation, the gate structure 126 is used to control the opening or closing of the conductive channels of the first type transistor in the first device region 100A and the second type transistor in the second device region 100B.

[0137] In this embodiment, the material of the gate dielectric layer 124 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0138] Specifically, the gate dielectric layer 124 includes a gate oxide layer that conformally covers a portion of the top, a portion of the sidewalls, and a portion of the bottom of the channel layer 103, and a high-k gate dielectric layer that conformally covers the gate oxide layer. The high-k gate dielectric layer is made of a high-k dielectric material, which refers to a dielectric material with a relative permittivity greater than that of silicon oxide.

[0139] It should be noted that the gate dielectric layer 124 also conformally covers part of the top of the isolation layer 106 and part of the sidewall of the dielectric wall 119.

[0140] In this embodiment, a gate electrode layer 125 is formed in the gate opening 123, spanning the channel layer 103 and the dielectric wall 119, and the gate electrode layer 125 surrounds and covers the gate dielectric layer 124.

[0141] The gate electrode layer 125 is used for subsequent electrical connection with external interconnect structures. The material of the gate electrode layer 125 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. Specifically, the gate electrode layer 125 may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer 125 may only include a work function layer.

[0142] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, the substrate including a substrate and fins protruding from the substrate, the substrate including an adjacent first device region and a second device region; A channel structure layer is suspended on the fins of the first device region and the second device region, and the channel structure layer includes one or more channel layers spaced apart in the longitudinal direction; An isolation layer is located on the substrate of the first device region and the second device region, and exposes the sidewalls of the channel structure layer; A dielectric wall extends through the channel structure layer, fins, and a portion of the substrate at the junction of the first and second device regions. The dielectric wall includes a bottom dielectric wall in the substrate and a top dielectric wall at the top of the bottom dielectric wall. The sidewall of the bottom dielectric wall is recessed inward relative to the sidewall of the channel structure layer. A gate dielectric layer conformally covers a portion of the top, a portion of the sidewalls and a portion of the bottom of the channel structure layer, the exposed dielectric wall sidewalls of the channel layer, and the top of the isolation layer; A gate electrode layer is located on top of the isolation layer and spans the channel structure layer and the dielectric wall, the gate electrode layer surrounding and covering the gate dielectric layer.

2. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: a protective layer located between the sidewall of the top dielectric wall and the sidewall of the channel structure layer, and between the sidewall of the top dielectric wall and the gate dielectric layer.

3. The semiconductor structure as described in claim 1, characterized in that, The top dielectric wall includes a first sub-dielectric wall located in the substrate within the fin and a portion of its thickness, and a second sub-dielectric wall located on top of the first sub-dielectric wall, the sidewall of the first sub-dielectric wall protruding outward relative to the sidewall of the channel structure layer.

4. The semiconductor structure as described in claim 3, characterized in that, The first sub-dielectric wall and the bottom dielectric wall are an integral structure, and the dielectric constant of the material of the second sub-dielectric wall is greater than that of the material of the first sub-dielectric wall.

5. The semiconductor structure as described in claim 1, characterized in that, With the direction perpendicular to the extension direction of the channel structure layer as the lateral direction, the lateral dimension of the sidewall of the bottom dielectric wall being recessed inward relative to the sidewall of the channel structure layer is 3 nanometers to 20 nanometers.

6. The semiconductor structure as described in claim 2, characterized in that, With the direction perpendicular to the extension direction of the channel structure layer as the lateral direction, the lateral dimension of the protective layer is 1 nanometer to 3 nanometers.

7. The semiconductor structure as described in claim 3, characterized in that, With the direction perpendicular to the extension direction of the channel structure layer as the lateral direction, the lateral dimension of the sidewall of the first sub-dielectric wall protruding outward relative to the sidewall of the channel structure layer is 1 nanometer to 5 nanometers.

8. The semiconductor structure as described in claim 1, characterized in that, The distance from the bottom of the dielectric wall to the top of the substrate is 5 nanometers to 300 nanometers; the thickness of the bottom dielectric wall is 8 nanometers to 30 nanometers.

9. The semiconductor structure as claimed in claim 1, characterized in that, The dielectric wall is made of one or both of silicon oxide and silicon boron carbonitride.

10. The semiconductor structure as described in claim 2, characterized in that, The material of the protective layer includes one or more of SiBCN, SiCN, and SiON.

11. The semiconductor structure as claimed in claim 1, characterized in that, The isolation layer contains doped ions, including Si.

12. The semiconductor structure as claimed in claim 1, characterized in that, The channel layer material includes one or more of silicon, silicon germanide, germanium, and group III-V semiconductor materials; The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3; The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

13. The semiconductor structure as claimed in claim 1, characterized in that, The first device region is used to form a first type transistor, and the second device region is used to form a second type transistor. The first type transistor and the second type transistor have different channel conductivity types.

14. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a substrate and fins protruding from the substrate, the substrate including adjacent first device region and second device region, one or more longitudinally stacked channel stacks are formed on the substrate of the first device region and the second device region, each channel stack including a sacrificial layer and a channel layer located on the sacrificial layer, the substrate including the first device region and the second device region; At the junction of the first device region and the second device region, a first groove is formed that penetrates the channel stack and the substrate with a first predetermined thickness, and the bottom of the first groove is located in the substrate; A first protective layer is formed on the sidewall of the first groove; At the junction of the first device area and the second device area, using the first protective layer as a mask, the substrate of the second preset thickness at the bottom of the first groove is etched to form a second groove in the substrate. The sidewall of the second groove is recessed inward relative to the sidewall of the first groove, and the top of the second groove is connected to the bottom of the first groove. Dielectric walls are formed in the first and second grooves.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The step of forming the first groove includes: etching the channel stack at the junction of the first device region and the second device region to form a first sub-groove penetrating the channel stack; A second protective layer is formed on the sidewall of the first sub-groove; Using the second protective layer as a mask, the substrate with a first preset thickness at the bottom of the first sub-groove is etched to form a second sub-groove in the substrate. The sidewall of the second sub-groove is recessed inward relative to the sidewall of the first sub-groove, and the top of the second sub-groove is connected to the bottom of the first sub-groove. The second sub-groove and the first sub-groove constitute a first groove.

16. The method for forming a semiconductor structure as described in claim 14, characterized in that, Prior to forming the first groove, the method further includes forming an isolation layer on top of the substrate exposed by the trench stack, the isolation layer covering the sidewalls of the trench stack.

17. The method for forming a semiconductor structure as described in claim 15, characterized in that, In the step of forming the first groove, the first groove includes a first sub-groove penetrating the channel stack and a second sub-groove located in the base of the first preset thickness; The step of forming a dielectric wall in the first groove and the second groove includes: forming a bottom dielectric wall in the first groove and the second groove; removing the bottom dielectric wall in the first sub-groove; and after removing the bottom dielectric wall in the first sub-groove, forming a top dielectric wall in the first sub-groove, wherein the dielectric constant of the material of the top dielectric wall is greater than that of the material of the bottom dielectric wall, and the top dielectric wall and the bottom dielectric wall constitute the dielectric wall.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, Before forming the first groove, the method further includes: forming an isolation layer on top of the substrate exposed by the trench stack, the isolation layer covering the sidewalls of the trench stack; After forming the second groove and before forming the bottom dielectric wall in the first and second grooves, the method further includes: forming a fill layer in the first and second grooves; after forming the fill layer, performing ion implantation on the isolation layer to improve the etching resistance of the isolation layer; and removing the fill layer after ion implantation on the isolation layer.

19. The method for forming a semiconductor structure as described in claim 18, characterized in that, In the step of ion implantation of the isolation layer, the implanted ions include Si, and the ion implantation process parameters include: ion implantation energy range of 1 keV to 10 keV; ion implantation dose range of 1.0 E15 atom / cm 2 Up to 8.0E16atom / cm 2 .

20. The method for forming a semiconductor structure as described in claim 14, characterized in that, Before forming dielectric walls in the first and second grooves, the method further includes: removing the first protective layer.

21. The method for forming a semiconductor structure as described in claim 14, characterized in that, With the direction perpendicular to the extension direction of the channel stack as the lateral direction, the lateral dimension of the first protective layer is 1 nanometer to 3 nanometers.

22. The method for forming a semiconductor structure as described in claim 14, characterized in that, The first device region is used to form a first type transistor, and the second device region is used to form a second type transistor. The first type transistor and the second type transistor have different channel conductivity types.

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