Low trigger high holding voltage bidirectional thyristor electrostatic discharge protection device and manufacturing method

Abstract

The embodiment of the application provides a bidirectional thyristor electrostatic protection device with low trigger voltage and high maintaining voltage and a manufacturing method thereof, which comprises a P-type substrate, an N-type buried layer and an N-type well; a first P-well is arranged on the left side of the N-type buried layer, and a second P-well is arranged on the right side of the N-type buried layer; a first P+ injection area, a first N+ injection area and a first floating P+ injection area are arranged in the first P-well; an N-type well is arranged between the first P-well and the second P-well; a middle N+ injection area is arranged at the middle position of the N-type well; meanwhile, a first P-type shallow well PB and a second P-type shallow well PB are arranged to cross the middle positions of the first P-well, the N-type well and the second P-well, respectively; a first high-voltage N-well and a second high-voltage N-well are arranged on the left side and the right side of the N-type buried layer, respectively; the first P+ injection area and the first N+ injection area are connected together and serve as an anode of the device; and the second P+ injection area and the second N+ injection area are connected together and serve as a cathode of the device; thus, the device can effectively protect the core circuit of a chip and is far away from the risk of latching.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electrostatic protection, in particular to a low-trigger high-maintenance voltage bidirectional silicon controlled rectifier electrostatic protection device and a manufacturing method thereof. BACKGROUND

[0002] With the progress of semiconductor process technology, ESD causes integrated circuit chips and electronic products to fail more and more seriously. ESD protection for electronic products and integrated circuit chips has become one of the main problems faced by product engineers.

[0003] Compared with other ESD devices, the traditional silicon controlled rectifier (SCR) has a double-conductivity modulation mechanism, high unit area discharge efficiency, small unit parasitic capacitance, and the best robustness. However, the traditional silicon controlled rectifier has the disadvantages of high trigger voltage and low maintenance voltage after hysteresis, which will cause the protection device to fail to protect the core circuit in time and the low maintenance voltage will cause the device to latch, which cannot guarantee the integrity of the I / O port signal transmission.

[0004] The bidirectional silicon controlled rectifier device is improved on the basis of the traditional silicon controlled rectifier and can be considered as an integration of some anti-parallel connected ordinary silicon controlled rectifiers. Its working principle is the same as that of the traditional unidirectional silicon controlled rectifier, and it can clamp the voltage in both positive and negative directions. The cross-sectional view of the traditional bidirectional silicon controlled rectifier electrostatic protection device is shown in Figure 1 , and the equivalent circuit diagram is shown in Figure 2 . When the ESD pulse is applied to the anode of the bidirectional SCR, the N-type deep well and the third P+ implantation region form a reverse-biased PN junction. When the pulse voltage is higher than the avalanche breakdown voltage of the PN junction, a large amount of avalanche current is generated inside the device, and the current flows through the second P-well parasitic resistance to the other end, i.e. the cathode. When the voltage across the parasitic well resistance is higher than the forward conduction voltage of the vertical NPN transistor, the transistor is turned on. After the transistor is turned on, the base current is provided for the horizontal PNP transistor, and the horizontal PNP transistor is also turned on to provide base current for the vertical NPN transistor, forming a positive feedback loop. Therefore, even if there is no avalanche current after that, the device can still discharge static electricity due to the conduction of the transistor. The bidirectional SCR is a symmetrical structure, and when an ESD pulse occurs at the cathode, the PN junction avalanche breakdown of the N-type deep well and the second P+ implantation region causes the PNP transistor and the NPN transistor to be turned on in sequence to discharge static electricity. However, the traditional SCR has the disadvantages of high trigger voltage and low maintenance voltage, which will cause the device to easily exceed the design window and cause latch-up effect, so it is necessary to reduce the trigger voltage to ensure that the device opens in time to protect the core circuit when the ESD current comes, and to increase the maintenance voltage of the bidirectional silicon controlled rectifier to avoid latch-up effect. SUMMARY

[0005] The application provides a low-trigger high-maintenance voltage bidirectional thyristor static protection device and a manufacturing method thereof.

[0006] To achieve the above object, the technical scheme of the embodiment of the application is as follows:

[0007] The low-trigger high-maintenance voltage bidirectional thyristor static protection device provided by the embodiment of the application comprises a P-type substrate.

[0008] An N-type buried layer is arranged in the P-type substrate.

[0009] An N-type well is arranged in the middle of the N-type buried layer.

[0010] A first P-well is arranged on the left side of the N-type buried layer, and a second P-well is arranged on the right side of the N-type buried layer.

[0011] A first P+ injection area, a first N+ injection area and a first floating P+ injection area are arranged in the first P-well, wherein the first P+ injection area is arranged on the left side of the first P-well, the first N+ injection area is arranged on the right side of the first P+ injection area and is attached together, and the first floating P+ injection area is arranged on the right side of the first N+ injection area.

[0012] A second P+ injection area, a second N+ injection area and a second floating P+ injection area are arranged in the second P-well, wherein the second P+ injection area is arranged on the right side of the second P-well, the second N+ injection area is arranged on the left side of the second P+ injection area and is attached together, and the second floating P+ injection area is arranged on the left side of the second N+ injection area.

[0013] An N-type well is arranged between the first P-well and the second P-well, an intermediate N+ injection area is arranged at the middle position of the N-type well, and a first P-type shallow well PB and a second P-type shallow well PB are arranged to span the middle positions of the first P-well, the N-type well and the second P-well, respectively.

[0014] A first high-voltage N-well and a second high-voltage N-well are arranged on the left side and the right side of the N-type buried layer, respectively.

[0015] The first P+ injection area and the first N+ injection area are connected together and serve as an anode of the device, and the second P+ injection area and the second N+ injection area are connected together and serve as a cathode of the device.

[0016] The first P+ injection area is provided with the first field oxygen isolation area between the left side of the first P+ injection area and the left side edge of the P-type substrate, the first N+ injection area is connected to the right side of the first P+ injection area, and the second field oxygen isolation area is provided between the left side of the first floating P+ injection area and the right side of the first N+ injection area; the second P+ injection area is connected to the left side of the second N+ injection area, and the fifth field oxygen isolation area is provided between the right side of the second N+ injection area and the left side of the second floating P+ injection area; the third field oxygen isolation area is provided between the right side of the first floating P+ injection area and the left side of the first P-type shallow well PB; the fourth field oxygen isolation area is provided between the left side of the second floating P+ injection area and the right side of the second P-type shallow well PB; and the sixth field oxygen isolation area is provided between the right side of the second P+ injection area and the right side edge of the P-type substrate.

[0017] The left part of the first field oxygen isolation area is located on the surface of the P-type substrate, and the right part of the first field oxygen isolation area is located on the surface of the first P well; the left part of the sixth field oxygen isolation area is located on the surface of the second P well, and the right part of the sixth field oxygen isolation area is located on the surface of the P-type substrate; the second field oxygen isolation area and the third field oxygen isolation area are located on the surface of the first P well, and the fourth field oxygen isolation area and the fifth field oxygen isolation area are located on the surface of the second P well.

[0018] When a high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the first N+ injection area, the first P well and the N-type well form a longitudinal NPN-type transistor, the first P well, the N-type well and the second P well form a transverse PNP-type transistor structure, the second N+ injection area, the second P well and the N-type well form a longitudinal NPN-type transistor, and the first P well, the N-type buried layer and the second P well form a transverse PNP-type transistor.

[0019] When a high-voltage ESD pulse reaches the anode of the device, the cathode of the device is connected to a ground potential, and the ESD current flows along the P+ injection area to the first P well, the first P-type shallow well PB and the intermediate N+ injection area to form a forward-biased diode.

[0020] The embodiment of the application also provides a manufacturing method of the bidirectional thyristor ESD protection device with low trigger voltage and high maintenance voltage, and the method comprises the following steps:

[0021] Step 1: forming an N-type buried layer in the P-type substrate;

[0022] Step 2: generating an N-type well in the middle of the N-type buried layer;

[0023] Step 3: sequentially generating a first field oxygen isolation area, a second field oxygen isolation area, a third field oxygen isolation area, a fourth field oxygen isolation area, a fifth field oxygen isolation area and a sixth field oxygen isolation area in the P-type substrate from left to right.

[0024] Step four: generate a first high-voltage N well, a second high-voltage N well, a first P well and a second P well on both sides of the N-type buried layer respectively;

[0025] Step five: generate a first P-type shallow well and a second P-type shallow well on both sides of the N-type well;

[0026] Step six: form a first P+ injection area, a first N+ injection area, a first floating P+ injection area and a first P-type shallow well PB in the first P well from left to right in order, form a second P-type shallow well PB, a second floating P+ injection area, a second N+ injection area, a second P+ injection area in the second P well from left to right in order, and form an N+ injection area between the first P-type shallow well and the second P-type shallow well; the left side of the first field oxide isolation region is in contact with the left side edge of the P-type substrate, the right side of the first field oxide isolation region is in contact with the left side of the first P+ injection area, the right side of the first P+ injection area is connected with the left side of the first N+ injection area, the right side of the first N+ injection area is in contact with the left side of the second field oxide isolation region, and the right side of the second field oxide isolation region is in contact with the left side of the first floating P+ injection area; the right side of the second P-type shallow well PB is in contact with the left side of the third field oxide isolation region, the right side of the third field oxide isolation region is in contact with the left side of the second floating P+ injection area, the right side of the second floating P+ injection area is in contact with the fifth field oxide isolation region, the right side of the fifth field oxide isolation region is in contact with the left side of the second N+ injection area, the right side of the second N+ injection area is in contact with the left side of the second P+ injection area, the right side of the second P+ injection area is in contact with the left side of the sixth field oxide isolation region, and the right side of the sixth field oxide isolation region is in contact with the right side edge of the P-type substrate;

[0027] Step seven: perform annealing treatment on the first P+ injection area, the first N+ injection area, the first floating P+ injection area, the N+ injection area in the N-type well, the second floating P+ injection area, the second N+ injection area and the second P+ injection area to eliminate the migration of impurities in the injection area;

[0028] Step eight: connect the first P+ injection area and the first N+ injection area together and use them as an anode of the device, and connect the second N+ injection area and the second P+ injection area together and use them as a cathode of the device.

[0029] The method further comprises the following steps before the above steps:

[0030] A silicon dioxide film is grown on the P-type substrate, and then a silicon nitride layer is deposited; a photoresist layer is spin-coated on the wafer, and the photoresist layer is exposed and developed with a mask to form an isolation shallow trench; the silicon dioxide, the silicon nitride and the isolation shallow trench are etched, the photoresist layer is removed, a silicon dioxide layer is deposited, and then chemical mechanical polishing is performed until the silicon nitride layer is removed.

[0031] The embodiment of the present application provides a low-trigger high-maintenance voltage bidirectional silicon controlled rectifier electrostatic protection device and a manufacturing method thereof, and the beneficial effect is that:

[0032] 1. The present application can change the internal structure level without changing the layout area, so as to realize the purpose of reducing the trigger voltage and improving the maintenance voltage, the reverse PN junction breakdown voltage of the N+ injection area in the first P-type shallow well PB and N well TB and the second P-type shallow well PB is small, and the structure can effectively reduce the trigger voltage of the device, and the first floating P+ injection area and the second floating P+ injection area can adjust the base area concentration of the parasitic transistor of the silicon controlled rectifier path of the device, and then improve the maintenance voltage of the device.

[0033] 2. The size S6 of the N+ injection in the N-type well of the present application can be adjusted, when S6 is reduced, the breakdown surface of the electrostatic protection device will change to the N-type well and the P-type shallow well PB, but the trigger voltage will be increased but not obvious due to the influence of the concentration of the N+ injection area, therefore, the trigger voltage of the electrostatic protection device will increase with the decrease of the size S6.

[0034] 3. The size S3 of the first P+ injection area and the second P+ injection area in the first P well and the second P well of the present application can be adjusted, when S3 is increased, the P+ injection area will affect the concentration of the first P well and the second P well, that is, the base area concentration of the parasitic transistor NPN is increased to affect the current gain of the transistor, and finally the maintenance voltage of the device is increased, therefore, the maintenance voltage of the device will increase with the increase of the size S3. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 It is a sectional view of a known bidirectional SCR electrostatic protection device;

[0036] Figure 2 It is an equivalent circuit diagram of a known bidirectional SCR electrostatic protection device;

[0037] Figure 3 It is a sectional view of a low-trigger high-maintenance voltage bidirectional silicon controlled rectifier electrostatic protection device provided by an embodiment of the present application;

[0038] Figure 4 It is an equivalent circuit diagram of a low-trigger high-maintenance voltage bidirectional silicon controlled rectifier electrostatic protection device provided by an embodiment of the present application. Detailed Implementation

[0039] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0041] like Figure 3 As shown, a bidirectional thyristor electrostatic discharge (ESD) device with low trigger voltage and high sustaining voltage includes a P-type substrate 101; an N-type buried layer 201 is disposed in the substrate; an N-type well 301 is located above and in the middle of the N-type buried layer 201; a first P-well 401 is disposed on the left side of the N-type buried layer 201, and a second P-well 402 is disposed on the right side of the N-type buried layer 201; the first P-well 401 contains a first P+ injection region 701, a first N+ injection region 702, and a first floating P+ injection region 703, wherein the first P+ injection region 701 is located on the left side of the first P-well 401, the first N+ injection region 702 is located on the right side of the first P+ injection region 701 and is attached to it, and the first floating P+ injection region 703 is located on the right side of the first N+ injection region 702; the second P-well 402 contains a second P+ injection region 703. 07. A second N+ injection region 706 and a second floating P+ injection region 705, wherein the second P+ injection region 707 is located to the right of the second P-well 402, the second N+ injection region 706 is located to the left of the second P+ injection region 707 and they are attached together, and the second floating P+ injection region 705 is located to the left of the second N+ injection region 706; an N-type well 301 is provided between the first P-well 401 and the second P-well 402, and an N+ injection region 704 is provided in the middle of the N-type well 301. At the same time, a first P-type shallow well PB501 and a second P-type shallow well PB502 are respectively arranged across the middle of the first P-well 401, the N-type well 301 and the second P-well 402; a first high-pressure N-well 601 and a second high-pressure N-well 602 are respectively provided on the leftmost and rightmost sides above the N-type buried layer 201.

[0042] The first P+ injection region 701 and the first N+ injection region 702 are connected together and serve as the anode of the device, while the second P+ injection region 707 and the second N+ injection region 706 are connected together and serve as the cathode of the device.

[0043] The first field oxide isolation region 801 is located between the left side of the first P+ implantation region 701 and the left side edge of the P-type substrate 101 and the first high-voltage N well 601, the right side of the first P+ implantation region 701 is connected with the left side of the first N+ implantation region 702, and the left side of the first N+ implantation region 702 is provided with the second field oxide isolation region 802 with the left side of the first floating P+ implantation region 703; the left side of the second P+ implantation region 707 is connected with the right side of the second N+ implantation region 706, the left side of the second N+ implantation region 706 is provided with the fifth field oxide isolation region 805 with the right side of the second floating P+ implantation region 705; the right side of the first floating P+ implantation region 703 is provided with the third field oxide isolation region 803 with the left side of the first P-type shallow well PB501; the left side of the second floating P+ implantation region 705 is provided with the fourth field oxide isolation region 804 with the right side of the second P-type shallow well PB502; the right side of the second P+ implantation region 707 is provided with the sixth field oxide isolation region 806 between the P-type substrate 101 and the right side edge of the second high-voltage N well 602.

[0044] The left part of the first field oxide isolation region 801 is located on the surface of the first high-voltage N well 601, and the right part of the first field oxide isolation region 801 is located on the surface of the first P well 401; the left part of the sixth field oxide isolation region 806 is located on the surface of the second P well 402, and the right part of the sixth field oxide isolation region 806 is located on the surface of the second high-voltage N well 602; the second field oxide isolation region 802 and the third field oxide isolation region 803 are located on the surface of the first P well 401, and the fourth field oxide isolation region 804 and the fifth field oxide isolation region 805 are located on the surface of the second P well 402.

[0045] As shown in the equivalent circuit diagram, Figure 4 When the high-voltage ESD pulse reaches the anode of the device, and the cathode of the device is connected to a low potential, the first N+ implantation region 702, the first P well 401 and the N-type well 301 form a longitudinal NPN transistor, the first P well 401, the N-type well 301 and the second P well 402 form a transverse PNP transistor structure, and the second N+ implantation region 706, the second P well 402 and the N-type deep well 301 form a longitudinal NPN transistor. The longitudinal parasitic NPN tubes in the first P well 401 and the parasitic longitudinal NPN tubes in the second P well 402 can be combined with the transverse PNP tube to form a bidirectional SCR structure.

[0046] When the high-voltage ESD pulse reaches the anode of the device, the first P+ implantation region 701 and the first N+ implantation region 702 are high potential, the other end of the second N+ implantation region 706 and the second P+ implantation region 707 are low potential cathode, the N+ implantation region 704 in the N-type well 301 and the second P-type shallow well 502 are reverse biased, when the pulse voltage is higher than the avalanche breakdown voltage of the reverse biased PN junction composed of the N+ implantation region 704 and the second P-type shallow well 502, a large amount of avalanche current will be generated in the device, the avalanche current flows through the parasitic resistance of the second P well 402 and flows into the cathode, and the equivalent circuit diagramFigure 4 As can be seen, when the voltage drop caused by the avalanche current on the parasitic resistance of the second P-well 402 is large enough, the parasitic transistor T3 is turned on, and the parasitic transistor T3, after being turned on, provides a current for the base of the parasitic transistor T2, and the two form a positive feedback loop, and the positive SCR structure is turned on to discharge static electricity. Similarly, when a positive ESD pulse occurs at the cathode, the reverse-biased PN junction composed of the N+ implantation region 704 and the second P-type shallow well 502 is avalanche breakdown, and the avalanche current flows through the parasitic resistance of the first P-well 401 and flows into the anode, as shown in the equivalent circuit diagram Figure 4 As can be seen, when the voltage drop caused by the avalanche current on the parasitic resistance of the first P-well 401 is large enough, the parasitic transistor T1 is turned on, and the parasitic transistor T1, after being turned on, provides a current for the base of the parasitic transistor T2, and the two form a positive feedback loop, and the positive SCR structure is turned on to discharge static electricity. Similarly, when a positive ESD pulse occurs at the cathode, the reverse-biased PN junction composed of the N+ implantation region 704 and the second P-type shallow well 502 is avalanche breakdown, and the avalanche current flows through the parasitic resistance of the first P-well 401 and flows into the anode, as shown in the equivalent circuit diagram

[0047] Compared with the conventional bidirectional thyristor ESD protection device, the device changes the structure of the traditional thyristor avalanche breakdown surface, and the reverse-biased PN junction composed of the N+ implantation region 704 and the first P-type shallow well 501 and the second P-type shallow well 502 enables the device to have a lower trigger voltage, and the floating P+ implantation region in the first P-well 401 and the second P-well 402 can improve the base region concentration of the longitudinal parasitic transistor PNP, thereby improving the holding voltage of the device.

[0048] The device can adjust the trigger voltage of the device by controlling the size of S6 according to the requirements of the ESD design window in different application scenarios. The size S6 of the N-type well N+ implantation can be adjusted. When S6 is reduced, the breakdown surface of the electrostatic protection device changes to the N-type well and the P-type shallow well PB, but the trigger voltage is affected by the concentration of the N+ implantation region and is not obvious. Therefore, the trigger voltage of the electrostatic protection device increases as the size S6 decreases.

[0049] Similarly, the size S3 of the first P+ implantation region and the second P+ implantation region in the first P-well and the second P-well can be adjusted. When S3 is increased, the P+ implantation region will affect the concentration of the first P-well and the second P-well, that is, the base region concentration of the parasitic transistor NPN is increased, which affects the current gain of the transistor, and finally leads to the increase of the holding voltage of the device. Therefore, the holding voltage of the electrostatic protection device increases as the size S3 increases.

[0050] The embodiment of the application also provides a manufacturing method of a low-trigger high-holding-voltage bidirectional thyristor electrostatic protection device, which comprises the following steps:

[0051] Step one: grow a layer of silicon dioxide film on P-type substrate 101, then deposit a layer of silicon nitride; spin on photoresist layer on wafer, add mask to expose and develop it, form isolation shallow trench; etch silicon dioxide, silicon nitride and isolation shallow trench, remove photoresist layer, deposit a layer of silicon dioxide, then chemical mechanical polishing until the silicon nitride layer, remove the silicon nitride layer

[0052] Step two: determine the size S6 of N+ implantation region 704 and the size S3 of first floating P+ implantation region 703 and second floating P+ implantation region 705 according to specific guard window;

[0053] Step three: generate first field oxide isolation region 801, second field oxide isolation region 802, third field oxide isolation region 803, fourth field oxide isolation region 804, fifth field oxide isolation region 805 and sixth field oxide isolation region 806 in P-type substrate from left to right in order;

[0054] Step four: form N-type buried layer 201 in P-type substrate 101;

[0055] Step five: generate N-type well 301 in the middle and first high-voltage N well 601, first P well 401, second P well 402 and second high-voltage N well 602 on both sides above N-type buried layer 201;

[0056] Step six: generate first P-type shallow well 501 and second P-type shallow well 502 on both sides of N-type well 301;

[0057] Step 7: In the first P-well 401, from left to right, a first P+ implantation region 701, a first N+ implantation region 702, a first floating P+ implantation region 703, and a first P-type shallow well PB501 are formed sequentially. In the second P-well 402, from left to right, a second P-type shallow well PB502, a second floating P+ implantation region 705, a second N+ implantation region 706, and a second P+ implantation region 707 are formed sequentially. Simultaneously, an N+ implantation region 704 is formed between the first P-type shallow well PB501 and the second P-type shallow well PB502. The left side of the first field oxygen isolation region 801 contacts the left edge of the P-type substrate 101, the right side of the first field oxygen isolation region 801 contacts the left side of the first P+ implantation region 701, and the right side of the first P+ implantation region 701 is connected to the left side of the first N+ implantation region 702. The right side of the N+ implantation region 702 contacts the left side of the second field oxygen isolation region 802, and the right side of the second field oxygen isolation region 802 contacts the left side of the first floating P+ implantation region 703; the right side of the second P-type shallow well PB502 contacts the left side of the third field oxygen isolation region 803, the right side of the third field oxygen isolation region 803 contacts the left side of the second floating P+ implantation region 705, the right side of the second floating P+ implantation region 705 contacts the fifth field oxygen isolation region 805, the right side of the fifth field oxygen isolation region 805 contacts the left side of the second N+ implantation region 706, the right side of the second N+ implantation region 706 contacts the left side of the second P+ implantation region 707, the right side of the second P+ implantation region 707 contacts the left side of the sixth field oxygen isolation region 806, and the right side of the sixth field oxygen isolation region 806 contacts the right edge of the P-type substrate 101;

[0058] Step 8: Anneal the first P+ injection region 701, the first N+ injection region 702, the first floating P+ injection region 703, the N+ injection region 704 in the N-type trap, the second floating P+ injection region 705, the second N+ injection region 706, and the second P+ injection region 707 to eliminate the migration of impurities in the injection regions.

[0059] Step 9: Connect the first P+ injection region 701 and the first N+ injection region 702 together as the anode of the device, and connect the second N+ injection region 706 and the second P+ injection region 707 together as the cathode of the device.

[0060] Optionally, the method may further include:

[0061] A silicon dioxide thin film is grown on the P-type substrate, followed by the deposition of a silicon nitride layer; a photoresist layer is spin-coated onto the wafer, and a mask is used to expose and develop it to form a shallow isolation trench; the silicon dioxide, silicon nitride, and shallow isolation trench are etched to remove the photoresist layer, a silicon dioxide layer is deposited, and then chemical polishing is performed until the silicon nitride layer is removed.

[0062] The manufacturing method of the bidirectional thyristor electrostatic protection device with low trigger voltage and high sustain voltage is simple in process and convenient in operation. The bidirectional thyristor electrostatic protection device has a reverse avalanche breakdown surface with low breakdown voltage, and can effectively reduce the trigger voltage of the device. Meanwhile, the addition of the floating P+ implantation can effectively improve the sustain voltage of the device. According to the requirements of the ESD design window in different application scenarios, the trigger voltage of the device can be adjusted by controlling the size of the breakdown surface N+ implantation area, and the sustain voltage of the device can be adjusted by controlling the size of the floating P+ implantation area. The device can be used in ESD protection design, effectively protecting the internal chip and avoiding the risk of latch-up. The example device of the application adopts a 0.25μm BCDMOS process.

[0063] The above merely describes preferred embodiments of the present application, but is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A low trigger high holding voltage bidirectional thyristor electrostatic discharge protection device, characterized in that, The application relates to a high-voltage ESD protection device, which comprises a P-type substrate; an N-type buried layer is arranged in the P-type substrate; an N-type well is arranged above the N-type buried layer; a first P-well is arranged on the left side of the N-type buried layer, and a second P-well is arranged on the right side of the N-type buried layer; a first P+ injection area, a first N+ injection area and a first floating P+ injection area are arranged in the first P-well, wherein the first P+ injection area is located on the left side of the first P-well, the first N+ injection area is located on the right side of the first P+ injection area and is attached together, and the first floating P+ injection area is located on the right side of the first N+ injection area; a second P+ injection area, a second N+ injection area and a second floating P+ injection area are arranged in the second P-well, wherein the second P+ injection area is located on the right side of the second P-well, the second N+ injection area is located on the left side of the second P+ injection area and is attached together, and the second floating P+ injection area is located on the left side of the second N+ injection area; an N-type well is arranged between the first P-well and the second P-well, and an intermediate N+ injection area is arranged at the middle position of the N-type well; meanwhile, a first P-type shallow well PB and a second P-type shallow well PB are arranged to span the middle positions of the first P-well, the N-type well and the second P-well; a first high-voltage N-well and a second high-voltage N-well are arranged on the left side and the right side of the N-type buried layer; the first P+ injection area and the first N+ injection area are connected together and serve as an anode of the device, the second P+ injection area and the second N+ injection area are connected together and serve as a cathode of the device; a first field oxide isolation area is arranged between the left side of the first P+ injection area and the left side edge of the P-type substrate, the right side of the first P+ injection area is connected with the left side of the first N+ injection area, the right side of the first N+ injection area is provided with a second field oxide isolation area on the left side of the first floating P+ injection area; the left side of the second P+ injection area is connected with the right side of the second N+ injection area, the left side of the second N+ injection area is provided with a fifth field oxide isolation area on the right side of the second floating P+ injection area; the right side of the first floating P+ injection area is provided with a third field oxide isolation area on the left side of the first P-type shallow well PB; the left side of the second floating P+ injection area is provided with a fourth field oxide isolation area on the right side of the second P-type shallow well PB; the right side of the second P+ injection area is provided with a sixth field oxide isolation area between the right side edge of the P-type substrate; when a high-voltage ESD pulse reaches the anode of the device, the cathode of the device is grounded, and ESD current flows into the first P-well, the first P-type shallow well PB and the intermediate N+ injection area to form a forward biased diode. The left part of the first field oxide isolation area is located on the surface of the P-type substrate, and the right part of the first field oxide isolation area is located on the surface of the first P-well; the left part of the sixth field oxide isolation area is located on the surface of the second P-well, and the right part of the sixth field oxide isolation area is located on the surface of the P-type substrate; the second field oxide isolation area and the third field oxide isolation area are located on the surface of the first P-well, and the fourth field oxide isolation area and the fifth field oxide isolation area are located on the surface of the second P-well. ​ ​ ​ 2. The low trigger high holding voltage bidirectional thyrisitor ESD protection device of claim 1, wherein, ​ 3. The low trigger high holding voltage bidirectional thyrisitor ESD protection device of claim 1, wherein, When a high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the first N+ implantation region, the first P well, and the N-type well form a longitudinal NPN-type transistor, the first P well, the N-type well, and the second P well form a lateral PNP-type transistor structure, the second N+ implantation region, the second P well, and the N-type well form a longitudinal NPN-type transistor, and the first P well, the N-type buried layer, and the second P well form a lateral PNP-type transistor.

4. A method of manufacturing a low trigger high holding voltage bidirectional thyristor electrostatic discharge protection device as claimed in any one of claims 1 to 3, characterized in that, The method comprises: Step 1: forming an N-type buried layer in a P-type substrate; Step 2: generating an N-type well above the N-type buried layer; Step 3: sequentially generating a first field oxide isolation region, a second field oxide isolation region, a third field oxide isolation region, a fourth field oxide isolation region, a fifth field oxide isolation region, and a sixth field oxide isolation region in the P-type substrate from left to right; Step 4: generating a first high-voltage N well, a second high-voltage N well, a first P well, and a second P well on both sides above the N-type buried layer; Step 5: generating a first P-type shallow well and a second P-type shallow well on both sides of the N-type well; Step 6: sequentially forming a first P+ implantation region, a first N+ implantation region, a first floating P+ implantation region, and a first P-type shallow well PB in the first P well from left to right, sequentially forming a second P-type shallow well PB, a second floating P+ implantation region, a second N+ implantation region, and a second P+ implantation region in the second P well from left to right, and forming an N+ implantation region between the first P-type shallow well and the second P-type shallow well; and the left side of the first field oxide isolation region is in contact with the left edge of the P-type substrate, the right side of the first field oxide isolation region is in contact with the left side of the first P+ implantation region, the right side of the first P+ implantation region is connected to the left side of the first N+ implantation region, the right side of the first N+ implantation region is in contact with the left side of the second field oxide isolation region, and the right side of the second field oxide isolation region is in contact with the left side of the first floating P+ implantation region; the right side of the second P-type shallow well PB is in contact with the left side of the third field oxide isolation region, the right side of the third field oxide isolation region is in contact with the left side of the second floating P+ implantation region, the right side of the second floating P+ implantation region is in contact with the fifth field oxide isolation region, the right side of the fifth field oxide isolation region is in contact with the left side of the second N+ implantation region, the right side of the second N+ implantation region is in contact with the left side of the second P+ implantation region, the right side of the second P+ implantation region is in contact with the left side of the sixth field oxide isolation region, and the right side of the sixth field oxide isolation region is in contact with the right edge of the P-type substrate; Step 7: performing annealing treatment on the first P+ implantation region, the first N+ implantation region, the first floating P+ implantation region, the N+ implantation region in the N-type well, the second floating P+ implantation region, the second N+ implantation region, and the second P+ implantation region to eliminate the migration of impurities in the implantation region; Step 8: connecting the first P+ implantation region and the first N+ implantation region together and taking them as the anode of the device, and connecting the second N+ implantation region and the second P+ implantation region together and taking them as the cathode of the device.

5. The method of claim 4, wherein, The method further comprises: A silicon dioxide film is grown on the P-type substrate, and then a silicon nitride layer is deposited; a photoresist layer is spin-coated on the wafer, and the photoresist layer is exposed and developed with a mask to form an isolation shallow trench; the silicon dioxide, the silicon nitride and the isolation shallow trench are etched, the photoresist layer is removed, a silicon dioxide layer is deposited, and then chemical mechanical polishing is performed until the silicon nitride layer is removed.

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