Layout forming method of sensitive amplifier and layout of sensitive amplifier

Abstract

The application relates to a layout forming method of a sensitive amplifier and a layout of the sensitive amplifier. The method comprises the following steps: providing a first active region pattern layer, the first active region pattern layer comprising a bridge pattern, and a first active region pattern area and a second active region pattern area which are spaced apart along a first direction and symmetrically arranged along a central axis of the bridge pattern; the first active region pattern area comprises a first active region pattern for defining a first pull-down transistor of a first storage unit structure; the second active region pattern area comprises a first symmetric active region pattern for defining a second pull-down transistor of a second storage unit structure; the first active region pattern is adjacent to the first symmetric active region pattern and is communicated via the bridge pattern, so that a source of the first pull-down transistor and a source of the second pull-down transistor are electrically connected via the bridge pattern. The application reduces the area of the isolation space between the active regions of adjacent devices, and improves the uniformity of the pattern shape on the layout.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and particularly to a layout forming method of a sense amplifier and a layout of the sense amplifier. BACKGROUND

[0002] With the rapid development of integrated circuit manufacturing, the requirement for the integration of semiconductor products is higher and higher. With the integration of semiconductor products, the size of a single semiconductor device and the area of the isolation space between active regions of adjacent devices are required to be continuously reduced to ensure that the volume of the integrated circuit product meets the application requirements.

[0003] However, in the traditional integrated circuit product, the isolation space between the active regions of adjacent devices is relatively large, which easily introduces a large interference factor, resulting in a large single cell area and array area. The multi-layer process is relatively complex, the design rules of each layer layout are relatively high, and the pattern shape on the layout is not uniform, resulting in a relatively high complexity of the photolithography process. SUMMARY

[0004] Therefore, it is necessary to provide a layout forming method of a sense amplifier and a layout of the sense amplifier to connect the source of the pull-down transistor of two adjacent memory cell structures through an active region, reduce the area of the isolation space between the active regions of adjacent devices, improve the uniformity of the pattern shape on the layout, reduce the design rule requirements of each layer layout, and reduce the complexity of the photolithography process, so as to improve the yield and reliability of the manufactured semiconductor product.

[0005] To achieve the above object and other related objects, one aspect of the present application provides a layout forming method of a sense amplifier, comprising:

[0006] providing a first active region pattern layer, the first active region pattern layer comprising a bridge pattern, and a first active region pattern area and a second active region pattern area which are spaced apart along a first direction and symmetrically arranged along a central axis of the bridge pattern;

[0007] The first active region pattern area is used to define a first memory cell structure, and the first active region pattern area comprises a first active region pattern for defining a first pull-down transistor of the first memory cell structure.

[0008] The second active region pattern area is used to define a second memory cell structure, and the second active region pattern area comprises a first symmetric active region pattern for defining a second pull-down transistor of the second memory cell structure.

[0009] The first active area pattern is adjacent to the first symmetric active area pattern and is connected via the bridge pattern, so that the source of the first pull-down transistor and the source of the second pull-down transistor are electrically connected via the bridge pattern.

[0010] In the layout forming method of the sensitive amplifier in the above embodiment, the first active area pattern region in the first active area pattern layer and the second active area pattern region are spaced apart along a first direction and symmetrically arranged along a central axis of the bridge pattern; the first active area pattern region is used to define a first memory cell structure, and the first active area pattern region includes a first active area pattern for defining a first pull-down transistor of the first memory cell structure; the second active area pattern region is used to define a second memory cell structure, and the second active area pattern region includes a first symmetric active area pattern for defining a second pull-down transistor of the second memory cell structure; the first active area pattern is adjacent to the first symmetric active area pattern and is connected via the bridge pattern, so that the source of the first pull-down transistor and the source of the second pull-down transistor are electrically connected via the bridge pattern. With respect to the conventional semiconductor structure in which a metal contact is arranged in an active area for arranging a pull-down transistor, the application can effectively reduce the area of the active area for arranging the pull-down transistor, so as to reduce the area of a single cell and the area of an array region; since the area of the isolation space between adjacent pull-down transistors is reduced, a larger interference factor can be avoided; since the first active area pattern region and the second active area pattern region are symmetrically arranged along the central axis of the bridge pattern, the uniformity of the pattern shape on the layout can be improved, the design rule requirement for each layer of layout is reduced, and the complexity of the photolithography process is reduced.

[0011] In one of the embodiments, the layout forming method of the sensitive amplifier further includes:

[0012] forming a connection hole pattern layer on the first active area pattern layer;

[0013] forming a gate bar pattern layer on a surface of the connection hole pattern layer away from the first active area pattern layer, wherein the gate bar pattern layer partially overlaps the first active area pattern layer and is used to form the first pull-down transistor and the second pull-down transistor.

[0014] In one of the embodiments, the first active region pattern area further comprises a second active region pattern, a third active region pattern and a fourth active region pattern arranged in sequence and spaced apart along the first direction, wherein the second active region pattern is adjacent to the first active region pattern; the gate bar pattern layer comprises a first gate bar pattern, a second gate bar pattern, a third gate bar pattern and a fourth gate bar pattern; wherein the first gate bar pattern and the third gate bar pattern are arranged in sequence and spaced apart along the first direction, and the second gate bar pattern and the fourth gate bar pattern are arranged in sequence and spaced apart along the first direction; the first gate bar pattern and the second gate bar pattern are arranged in sequence and spaced apart along the second direction, and the third gate bar pattern and the fourth gate bar pattern are arranged in sequence and spaced apart along the second direction; the first active region pattern overlaps with the third gate bar pattern and the fourth gate bar pattern respectively, the second active region pattern overlaps with the first gate bar pattern and the fourth gate bar pattern respectively, the third active region pattern overlaps with the first gate bar pattern and the fourth gate bar pattern respectively, and the fourth active region pattern overlaps with the first gate bar pattern and the second gate bar pattern respectively.

[0015] In one of the embodiments, the first gate bar pattern and the fourth active region pattern located on both sides thereof along the second direction are used to form a fifth MOS tube, the second gate bar pattern and the fourth active region pattern located on both sides thereof along the second direction are used to form a first MOS tube, the first gate bar pattern and the third active region pattern located on both sides thereof along the second direction are used to form a third MOS tube, the fourth gate bar pattern and the second active region pattern located on both sides thereof along the second direction are used to form a fourth MOS tube, the third gate bar pattern and the first active region pattern located on both sides thereof along the second direction are used to form a second MOS tube, and the fourth gate bar pattern and the first active region pattern located on both sides thereof along the second direction are used to form a sixth MOS tube.

[0016] In one of the embodiments, the connection hole pattern layer includes a first connection hole pattern, a second connection hole pattern, a third connection hole pattern, a fourth connection hole pattern, a fifth connection hole pattern, a sixth connection hole pattern, a seventh connection hole pattern, an eighth connection hole pattern, a ninth connection hole pattern, and a tenth connection hole pattern; the first connection hole pattern is located in the first active area pattern on the side of the third gate strip pattern away from the fourth gate strip pattern, and the second connection hole pattern is located in the first active area pattern between the third gate strip pattern and the fourth gate strip pattern; the second active area pattern overlaps the first gate strip pattern and is used to form a first overlapping area, and the third connection hole pattern covers the first overlapping area; the fourth connection hole pattern is located in the second active area pattern on the side of the fourth gate strip pattern away from the first gate strip pattern; the fifth connection hole pattern is located in the third active area pattern on the side of the first gate strip pattern away from the fourth gate strip pattern; the third active area pattern overlaps the fourth gate strip pattern and is used to form a second overlapping area, and the sixth connection hole pattern covers the second overlapping area; the seventh connection hole pattern is located in the fourth active area pattern on the side of the first gate strip pattern away from the second gate strip pattern; the eighth connection hole pattern is located in the fourth active area pattern between the first gate strip pattern and the second gate strip pattern; the ninth connection hole pattern is located in the fourth active area pattern on the side of the second gate strip pattern away from the first gate strip pattern; and the tenth connection hole pattern is located in the third gate strip pattern between the first active area pattern and the first symmetric active area pattern.

[0017] In one of the embodiments, the layout forming method of the sensitive amplifier further includes: forming a metal pattern layer on the surface of the gate strip pattern layer away from the first active area pattern layer; the metal pattern layer includes a first metal pattern, a second metal pattern, a third metal pattern, a fourth metal pattern, a fifth metal pattern, a sixth metal pattern, a seventh metal pattern, and an eighth metal pattern; the first metal pattern covers the first connection hole pattern; the second metal pattern covers the second connection hole pattern and part of the third connection hole pattern; the third metal pattern covers the fourth connection hole pattern; the fourth metal pattern covers the fifth connection hole pattern; the fifth metal pattern covers part of the sixth connection hole pattern and the eighth connection hole pattern; the sixth metal pattern covers the seventh connection hole pattern; the seventh metal pattern covers the ninth connection hole pattern; and the eighth metal pattern covers the tenth connection hole pattern.

[0018] In one of the embodiments, the second active region pattern area includes a fifth gate pattern, a sixth gate pattern, a seventh gate pattern and an eighth gate pattern; the fifth gate pattern is symmetrically arranged with the first gate pattern along the first direction, and the symmetric axis is the symmetric axis of the first active region pattern area and the second active region pattern area along the first direction; the sixth gate pattern is symmetrically arranged with the second gate pattern along the first direction; the seventh gate pattern is symmetrically arranged with the third gate pattern along the first direction; and the eighth gate pattern is symmetrically arranged with the fourth gate pattern along the first direction.

[0019] In one of the embodiments, the bridge pattern is in a rectangular shape.

[0020] In one of the embodiments, the bridge pattern extends along the first direction.

[0021] In one of the embodiments, the length of the bridge pattern along the second direction is greater than or equal to a preset width threshold.

[0022] In one of the embodiments, the layout forming method of the sense amplifier further includes: providing a first symmetric active region pattern layer, which is spaced apart from and symmetrically arranged with the first active region pattern layer along a second direction, the second direction being perpendicular to the first direction.

[0023] In one of the embodiments, the first storage unit structure is a 6T SRAM; and / or the second storage unit structure is a 6T SRAM.

[0024] Another aspect of the present application provides a layout of a sense amplifier, including a first active region pattern layer; the first active region pattern layer includes a bridge pattern, and a first active region pattern area and a second active region pattern area which are spaced apart along a first direction and symmetrically arranged along a central axis of the bridge pattern; the first active region pattern area is used to define a first storage unit structure, and includes a first active region pattern for defining a first pull-down transistor of the first storage unit structure; the second active region pattern area is used to define a second storage unit structure, and includes a first symmetric active region pattern for defining a second pull-down transistor of the second storage unit structure; wherein the first active region pattern is adjacent to the first symmetric active region pattern and is connected via the bridge pattern, so that the source of the first pull-down transistor and the source of the second pull-down transistor are electrically connected via the bridge pattern.

[0025] In the layout of the sense amplifier in the above embodiment, the first active region pattern area and the second active region pattern area in the first active region pattern layer are arranged along the first direction and symmetrically along the central axis of the bridge pattern; the first active region pattern area is used to define the first memory cell structure, and the first active region pattern area includes a first active region pattern used to define a first pull-down transistor of the first memory cell structure; the second active region pattern area is used to define the second memory cell structure, and the second active region pattern area includes a first symmetric active region pattern used to define a second pull-down transistor of the second memory cell structure; the first active region pattern is adjacent to the first symmetric active region pattern and is connected via the bridge pattern, so that the source of the first pull-down transistor and the source of the second pull-down transistor are electrically connected via the bridge pattern. Compared with the conventional semiconductor structure in which a metal contact is arranged in an active region for arranging a pull-down transistor, the application can effectively reduce the area of the active region for arranging the pull-down transistor, thereby reducing the area of a single cell and the area of an array region; since the area of the isolation space between adjacent pull-down transistors is reduced, a larger interference factor can be avoided; since the first active region pattern area and the second active region pattern area are symmetrically arranged along the central axis of the bridge pattern, the uniformity of the pattern shape on the layout can be improved, the design rule requirement for each layer of layout can be reduced, and the complexity of the photolithography process can be reduced.

[0026] In one embodiment, the layout of the sense amplifier further includes a connection hole pattern layer and a gate bar pattern layer, the connection hole pattern layer is located on the first active region pattern layer, and the gate bar pattern layer is located on the surface of the connection hole pattern layer away from the first active region pattern layer, wherein the gate bar pattern layer partially overlaps the first active region pattern layer and is used to form the first pull-down transistor and the second pull-down transistor.

[0027] In one of the embodiments, the first active region pattern area further comprises a second active region pattern, a third active region pattern and a fourth active region pattern arranged along the first direction in sequence, wherein the second active region pattern is adjacent to the first active region pattern; the gate bar pattern layer comprises a first gate bar pattern, a second gate bar pattern, a third gate bar pattern and a fourth gate bar pattern; wherein the first gate bar pattern and the third gate bar pattern are arranged along the first direction in sequence, and the second gate bar pattern and the fourth gate bar pattern are arranged along the first direction in sequence; the first gate bar pattern and the second gate bar pattern are arranged along the second direction in sequence, and the third gate bar pattern and the fourth gate bar pattern are arranged along the second direction in sequence; the first active region pattern overlaps with the third gate bar pattern and the fourth gate bar pattern respectively, the second active region pattern overlaps with the first gate bar pattern and the fourth gate bar pattern respectively, the third active region pattern overlaps with the first gate bar pattern and the fourth gate bar pattern respectively, and the fourth active region pattern overlaps with the first gate bar pattern and the second gate bar pattern respectively; the first gate bar pattern and the fourth active region pattern located on both sides of the first gate bar pattern along the second direction are used to form a fifth MOS tube, the second gate bar pattern and the fourth active region pattern located on both sides of the second gate bar pattern along the second direction are used to form a first MOS tube, the first gate bar pattern and the third active region pattern located on both sides of the first gate bar pattern along the second direction are used to form a third MOS tube, the fourth gate bar pattern and the second active region pattern located on both sides of the fourth gate bar pattern along the second direction are used to form a fourth MOS tube, the third gate bar pattern and the first active region pattern located on both sides of the third gate bar pattern along the second direction are used to form a second MOS tube, and the fourth gate bar pattern and the first active region pattern located on both sides of the fourth gate bar pattern along the second direction are used to form a sixth MOS tube.

[0028] In one of the embodiments, the connection hole pattern layer includes a first connection hole pattern, a second connection hole pattern, a third connection hole pattern, a fourth connection hole pattern, a fifth connection hole pattern, a sixth connection hole pattern, a seventh connection hole pattern, an eighth connection hole pattern, a ninth connection hole pattern, and a tenth connection hole pattern; the first connection hole pattern is located in the first active area pattern on the side of the third gate strip pattern away from the fourth gate strip pattern, and the second connection hole pattern is located in the first active area pattern between the third gate strip pattern and the fourth gate strip pattern; the second active area pattern overlaps the first gate strip pattern to form a first overlapping area, and the third connection hole pattern covers the first overlapping area; the fourth connection hole pattern is located in the second active area pattern on the side of the fourth gate strip pattern away from the first gate strip pattern; the fifth connection hole pattern is located in the third active area pattern on the side of the first gate strip pattern away from the fourth gate strip pattern; the third active area pattern overlaps the fourth gate strip pattern to form a second overlapping area, and the sixth connection hole pattern covers the second overlapping area; the seventh connection hole pattern is located in the fourth active area pattern on the side of the first gate strip pattern away from the second gate strip pattern; the eighth connection hole pattern is located in the fourth active area pattern between the first gate strip pattern and the second gate strip pattern; the ninth connection hole pattern is located in the fourth active area pattern on the side of the second gate strip pattern away from the first gate strip pattern; and the tenth connection hole pattern is located in the third gate strip pattern between the first active area pattern and the first symmetric active area pattern.

[0029] In one of the embodiments, the layout of the sensitive amplifier further includes a metal pattern layer located on the surface of the gate strip pattern layer away from the first active area pattern layer; the metal pattern layer includes a first metal pattern, a second metal pattern, a third metal pattern, a fourth metal pattern, a fifth metal pattern, a sixth metal pattern, a seventh metal pattern, and an eighth metal pattern; the first metal pattern covers the first connection hole pattern; the second metal pattern covers the second connection hole pattern and part of the third connection hole pattern; the third metal pattern covers the fourth connection hole pattern; the fourth metal pattern covers the fifth connection hole pattern; the fifth metal pattern covers part of the sixth connection hole pattern and the eighth connection hole pattern; the sixth metal pattern covers the seventh connection hole pattern; the seventh metal pattern covers the ninth connection hole pattern; and the eighth metal pattern covers the tenth connection hole pattern.

[0030] In one of the embodiments, the second active region pattern area includes a fifth gate pattern, a sixth gate pattern, a seventh gate pattern and an eighth gate pattern; the fifth gate pattern is symmetrically arranged with the first gate pattern along the first direction, and the symmetric axis is the symmetric axis of the first active region pattern area and the second active region pattern area along the first direction; the sixth gate pattern is symmetrically arranged with the second gate pattern along the first direction; the seventh gate pattern is symmetrically arranged with the third gate pattern along the first direction; and the eighth gate pattern is symmetrically arranged with the fourth gate pattern along the first direction.

[0031] In one of the embodiments, the bridge pattern extends along the first direction; and the length of the bridge pattern along the second direction is greater than or equal to a preset width threshold.

[0032] In one of the embodiments, the layout of the sensitive amplifier further includes a first symmetric active region pattern layer, which is symmetrically arranged with the first active region pattern layer along a second direction, and the second direction is perpendicular to the first direction. BRIEF DESCRIPTION OF DRAWINGS

[0033] For better describing and illustrating the embodiments and / or examples of the disclosed application, reference can be made to one or more drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed application, the presently described embodiments and / or examples, and the best mode presently understood of these applications.

[0034] Figure 1 A top view schematic diagram of a layout of a sensitive amplifier provided in an embodiment of the present application is shown;

[0035] Figure 2 A top view schematic diagram of a layout of a sensitive amplifier provided in another embodiment of the present application is shown;

[0036] Figure 3 A top view schematic diagram of a layout of a sensitive amplifier provided in yet another embodiment of the present application is shown;

[0037] Figure 4 A schematic diagram of a storage cell circuit provided in an embodiment of the present application is shown;

[0038] Figure 5 A top view schematic diagram of a layout of a conventional sensitive amplifier is shown;

[0039] Figure 6a A schematic diagram of a layout of a sensitive amplifier provided in an embodiment of the present application is shown; Figure 3 A schematic diagram of a layout of a sensitive amplifier provided in an embodiment of the present application is shown;

[0040] A schematic diagram of a layout of a sensitive amplifier provided in an embodiment of the present application is shown;Figure 6b For Figure 5 A schematic diagram of the cross-sectional structure along the direction of AA';

[0041] Explanation of reference signs:

[0042] 100, first active region pattern layer; 10, first active region pattern area; 20, second active region pattern area; 30, bridge pattern; 11, first active region pattern; 12, second active region pattern; 13, third active region pattern; 14, fourth active region pattern; 21, first symmetrical active region pattern; 22, second symmetrical active region pattern; 23, third symmetrical active region pattern; 24, fourth symmetrical active region pattern; 41, first gate strip pattern; 42, second gate strip pattern; 43, third gate strip pattern; 44, fourth gate strip pattern; 45, fifth gate strip pattern; 46, sixth gate strip pattern; 47, seventh gate strip pattern; 48, eighth gate strip pattern; 511, first connection hole pattern; 512, second connection hole pattern; 513, third connection hole pattern; 514, fourth connection hole pattern; 515, fifth connection hole pattern; 516, sixth connection hole pattern; 517, seventh connection hole pattern; 518, eighth connection hole pattern; 519, ninth connection hole pattern; 510, tenth connection hole pattern; 5101, eleventh connection hole pattern; 521, first symmetrical connection hole pattern; 522, second symmetrical connection hole pattern; 523, third symmetrical connection hole pattern; 524, fourth symmetrical connection hole pattern; 525, fifth symmetrical connection hole pattern; 526, sixth symmetrical connection hole pattern; 527, seventh symmetrical connection hole pattern; 528, eighth symmetrical connection hole pattern; 529, ninth symmetrical connection hole pattern; 520, tenth symmetrical connection hole pattern; 5201, twelfth connection hole pattern; 611, first metal pattern; 612, second metal pattern; 613, third metal pattern; 614, fourth metal pattern; 615, fifth metal pattern; 616, sixth metal pattern; 617, seventh metal pattern; 618, eighth metal pattern; 619, conductive metal line; 621, first symmetrical metal pattern; 622, second symmetrical metal pattern; 623, third symmetrical metal pattern; 624, fourth symmetrical metal pattern; 625, fifth symmetrical metal pattern; 626, sixth symmetrical metal pattern; 627, seventh symmetrical metal pattern; 628, eighth symmetrical metal pattern. DETAILED DESCRIPTION

[0043] For the purpose of promoting the understanding of the present application, the present application will be more fully described by reference to the following drawings. Therein the preferred embodiments of the present application are shown. However, the present application can be carried out in many different forms and is not limited to those illustrated in the specification. Rather, these embodiments are provided so that this disclosure will be thorough and complete. It will be apparent that those skilled in the art, upon attending to the disclosure, will have no difficulty devising their own applications that are fairly within the scope of the present application.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0045] It will be understood that when an element or layer is referred to as being "on" or "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0046] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0047] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0048] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the application.

[0049] Referring now to the drawings, there is shown in Figures 1-6b It is to be understood that the drawings are only schematic and that actual implementations can differ from the specific embodiments disclosed in the drawings. It is to be understood that the

[0050] Referring now to the drawings, there is shown in Figure 1 In one embodiment of the present application, a layout forming method of a sense amplifier is provided, comprising: providing a first active region pattern layer 100, the first active region pattern layer 100 comprising a bridge pattern 30, and a first active region pattern area 10 and a second active region pattern area 20 which are spaced apart along a first direction and symmetrically arranged along a central axis of the bridge pattern 30; the first active region pattern area 10 is used for defining a first memory cell structure (not shown), and the first active region pattern area 10 comprises a first active region pattern 11 used for defining a first pull-down transistor of the first memory cell structure; the second active region pattern area 20 is used for defining a second memory cell structure (not shown), and the second active region pattern area 20 comprises a first symmetric active region pattern 21 used for defining a second pull-down transistor of the second memory cell structure; wherein the first active region pattern 11 is adjacent to the first symmetric active region pattern 21 and is connected via the bridge pattern 30, so that a source of the first pull-down transistor and a source of the second pull-down transistor are electrically connected via the bridge pattern 30.

[0051] In particular, reference is made to Figure 1, the first active region pattern layer 100 is provided with a first active region pattern area 10 and a second active region pattern area 20 which are spaced apart along a first direction, for example, Ox, and are symmetrically arranged along a central axis of the bridge pattern 30; the first active region pattern area 10 is used to define a first memory cell structure, and the first active region pattern area 10 includes a first active region pattern 11 used to define a first pull-down transistor of the first memory cell structure; the second active region pattern area 20 is used to define a second memory cell structure, and the second active region pattern area 20 includes a first symmetric active region pattern 21 used to define a second pull-down transistor of the second memory cell structure; the first active region pattern 11 is adjacent to the first symmetric active region pattern 21 and is connected via the bridge pattern 30, so that a source of the first pull-down transistor and a source of the second pull-down transistor are electrically connected via the bridge pattern 30. Compared with a conventional semiconductor structure in which a metal contact is provided in an active region used to define a pull-down transistor, the application can effectively reduce the area of the active region used to define the pull-down transistor, so as to reduce the area of a single cell and the area of an array region; since the area of the isolation space between adjacent pull-down transistors is reduced, a larger interference factor can be avoided; since the first active region pattern area 10 and the second active region pattern area 20 are symmetrically arranged along the central axis of the bridge pattern 30, the uniformity of the pattern shape on the layout can be improved, the design rule requirement for each layer of layout can be reduced, and the complexity of the photolithography process can be reduced.

[0052] Further, please refer to Figure 2 In an embodiment of the application, the layout forming method of the sense amplifier further includes: forming a connection hole pattern layer on the first active region pattern layer 100, and forming a fence pattern layer on a surface of the connection hole pattern layer away from the first active region pattern layer 100, wherein the fence pattern layer partially overlaps the first active region pattern layer 100 and is used to form the first pull-down transistor M1 and the second pull-down transistor M2.

[0053] As an example, please continue to refer to Figure 2In an embodiment of the present application, the first active region pattern area 10 further comprises a second active region pattern 12, a third active region pattern 13 and a fourth active region pattern 14 arranged along the first direction, such as the ox direction, in sequence and at intervals, wherein the second active region pattern 12 is adjacent to the first active region pattern 11; the gate bar pattern layer comprises a first gate bar pattern 41, a second gate bar pattern 42, a third gate bar pattern 43 and a fourth gate bar pattern 44; wherein the first gate bar pattern 41 and the third gate bar pattern 43 are arranged along the first direction in sequence and at intervals, and the second gate bar pattern 42 and the fourth gate bar pattern 44 are arranged along the first direction in sequence and at intervals; the first gate bar pattern 41 and the second gate bar pattern 42 are arranged along the second direction, such as the oy direction, in sequence and at intervals, and the third gate bar pattern 43 and the fourth gate bar pattern 44 are arranged along the second direction in sequence and at intervals; the first active region pattern 11 overlaps with the third gate bar pattern 43 and the fourth gate bar pattern 44 respectively, the second active region pattern 12 overlaps with the first gate bar pattern 41 and the fourth gate bar pattern 44 respectively, the third active region pattern 13 overlaps with the first gate bar pattern 41 and the fourth gate bar pattern 44 respectively, and the fourth active region pattern 14 overlaps with the first gate bar pattern 41 and the second gate bar pattern 42 respectively.

[0054] For example, please continue to refer to Figure 2 In an embodiment of the present application, the first gate bar pattern 41 and the fourth active region pattern 14 located on both sides thereof along the second direction, such as the oy direction, are used to form a fourth MOS tube, the second gate bar pattern 42 and the fourth active region pattern 14 located on both sides thereof along the second direction are used to form a sixth MOS tube, the first gate bar pattern 41 and the third active region pattern 13 located on both sides thereof along the second direction are used to form a second MOS tube, the fourth gate bar pattern 44 and the second active region pattern 12 located on both sides thereof along the second direction are used to form a third MOS tube, the third gate bar pattern 43 and the first active region pattern 11 located on both sides thereof along the second direction are used to form a fifth MOS tube, and the fourth gate bar pattern 44 and the first active region pattern 11 located on both sides thereof along the second direction are used to form a first MOS tube.

[0055] For example, please continue to refer to Figure 2In an embodiment of the present application, the connection hole pattern layer includes a first connection hole pattern 511, a second connection hole pattern 512, a third connection hole pattern 513, a fourth connection hole pattern 514, a fifth connection hole pattern 515, a sixth connection hole pattern 516, a seventh connection hole pattern 517, an eighth connection hole pattern 518, a ninth connection hole pattern 519, and a tenth connection hole pattern 510; the first connection hole pattern 511 is located in the first active area pattern 11 on the side of the third gate strip pattern 43 away from the fourth gate strip pattern 44, the second connection hole pattern 512 is located in the first active area pattern 11 between the third gate strip pattern 43 and the fourth gate strip pattern 44; the second active area pattern 12 overlaps the first gate strip pattern 41 and forms a first overlapping area, the third connection hole pattern 513 covers the first overlapping area; the fourth connection hole pattern 514 is located in the second active area pattern 12 on the side of the fourth gate strip pattern 44 away from the first gate strip pattern 41; the fifth connection hole pattern 515 is located in the third active area pattern 13 on the side of the first gate strip pattern 41 away from the fourth gate strip pattern 44; the third active area pattern 13 overlaps the fourth gate strip pattern 44 and forms a second overlapping area, the sixth connection hole pattern 516 covers the second overlapping area; the seventh connection hole pattern 517 is located in the fourth active area pattern 14 on the side of the first gate strip pattern 41 away from the second gate strip pattern 42; the eighth connection hole pattern 518 is located in the fourth active area pattern 14 between the first gate strip pattern 41 and the second gate strip pattern 42; the ninth connection hole pattern 519 is located in the fourth active area pattern 14 on the side of the second gate strip pattern 42 away from the first gate strip pattern 41; and the tenth connection hole pattern 510 is located in the third gate strip pattern 43 between the first active area pattern 11 and the first symmetric active area pattern 21.

[0056] For example, please continue to refer to Figure 2 In an embodiment of the present application, the second active area pattern region 20 includes a fifth gate strip pattern 45, a sixth gate strip pattern 46, a seventh gate strip pattern 47, and an eighth gate strip pattern 48; the fifth gate strip pattern 45 is symmetrically arranged with the first gate strip pattern 41 along the first direction, and the symmetry axis is the symmetry axis of the first active area pattern region 10 and the second active area pattern region 20 along the first direction; the sixth gate strip pattern 46 is symmetrically arranged with the second gate strip pattern 42 along the first direction; the seventh gate strip pattern 47 is symmetrically arranged with the third gate strip pattern 43 along the first direction; and the eighth gate strip pattern 48 is symmetrically arranged with the fourth gate strip pattern 44 along the first direction.

[0057] For example, please continue to refer to Figure 2In an embodiment of the present application, the grid pattern layer further comprises a fifth grid pattern 45, a sixth grid pattern 46, a seventh grid pattern 47 and an eighth grid pattern 48; the connecting hole pattern layer further comprises a first symmetric connecting hole pattern 521, a second symmetric connecting hole pattern 522, a third symmetric connecting hole pattern 523, a fourth symmetric connecting hole pattern 524, a fifth symmetric connecting hole pattern 525, a sixth symmetric connecting hole pattern 526, a seventh symmetric connecting hole pattern 527, an eighth symmetric connecting hole pattern 528, a ninth symmetric connecting hole pattern 529 and a tenth symmetric connecting hole pattern 520. The first symmetric active area pattern 21 can be arranged to be left-right symmetric with the first active area pattern 11, the second symmetric active area pattern 22 can be arranged to be left-right symmetric with the second active area pattern 12, the third symmetric active area pattern 23 can be arranged to be left-right symmetric with the third active area pattern 13, and the fourth symmetric active area pattern 24 can be arranged to be left-right symmetric with the fourth active area pattern 14. The first symmetric connecting hole pattern 521 can be arranged to be left-right symmetric with the first connecting hole pattern 511, the second symmetric connecting hole pattern 522 can be arranged to be left-right symmetric with the second connecting hole pattern 512, the third symmetric connecting hole pattern 523 can be arranged to be left-right symmetric with the third connecting hole pattern 513, the fourth symmetric connecting hole pattern 524 can be arranged to be left-right symmetric with the fourth connecting hole pattern 514, the fifth symmetric connecting hole pattern 525 can be arranged to be left-right symmetric with the fifth connecting hole pattern 515, the sixth symmetric connecting hole pattern 526 can be arranged to be left-right symmetric with the sixth connecting hole pattern 516, the seventh symmetric connecting hole pattern 527 can be arranged to be left-right symmetric with the seventh connecting hole pattern 517, the eighth symmetric connecting hole pattern 528 can be arranged to be left-right symmetric with the eighth connecting hole pattern 518, the ninth symmetric connecting hole pattern 529 can be arranged to be left-right symmetric with the ninth connecting hole pattern 519, and the tenth symmetric connecting hole pattern 520 can be arranged to be left-right symmetric with the tenth connecting hole pattern 510.

[0058] Further, please refer to Figure 3In one embodiment of the present application, the layout formation method of the sense amplifier further includes: forming a metal pattern layer on a surface of the gate pattern layer away from the first active area pattern layer 100; the metal pattern layer includes a first metal pattern 611, a second metal pattern 612, a third metal pattern 613, a fourth metal pattern 614, a fifth metal pattern 615, a sixth metal pattern 616, a seventh metal pattern 617, and an eighth metal pattern 618; the first metal pattern 611 covers the first connection hole pattern 511; the second metal pattern 612 covers the second connection hole pattern 512 and a portion of the third connection hole pattern 513; the third metal pattern 613 covers the fourth connection hole pattern 514; the fourth metal pattern 614 covers the fifth connection hole pattern 515; the fifth metal pattern 615 covers a portion of the sixth connection hole pattern 516 and the eighth connection hole pattern 518; the sixth metal pattern 616 covers the seventh connection hole pattern 517; the seventh metal pattern 617 covers the ninth connection hole pattern 519; and the eighth metal pattern 618 covers the tenth connection hole pattern 510.

[0059] As an example, see Figure 3 In one embodiment of the present application, the metal pattern layer includes a first symmetrical metal pattern 621, a second symmetrical metal pattern 622, a third symmetrical metal pattern 623, a fourth symmetrical metal pattern 624, a fifth symmetrical metal pattern 625, a sixth symmetrical metal pattern 626, a seventh symmetrical metal pattern 627 and an eighth symmetrical metal pattern 628. The first symmetrical metal pattern 621 can be set to be left-right symmetrical with the first metal pattern 611, the second symmetrical metal pattern 622 can be set to be left-right symmetrical with the second metal pattern 612, the third symmetrical metal pattern 623 can be set to be left-right symmetrical with the third metal pattern 613, the fourth symmetrical metal pattern 624 can be set to be left-right symmetrical with the fourth metal pattern 614, the fifth symmetrical metal pattern 625 can be set to be left-right symmetrical with the fifth metal pattern 615, the sixth symmetrical metal pattern 626 can be set to be left-right symmetrical with the sixth metal pattern 616, the seventh symmetrical metal pattern 627 can be set to be left-right symmetrical with the seventh metal pattern 617, and the eighth symmetrical metal pattern 628 can be set to be left-right symmetrical with the eighth metal pattern 618. Then, the following is designed: Figure 4 The layout of the sense amplifier circuit is shown in Figure 1. Figure 3 The source of the first pull-down transistor M1 and the source of the second pull-down transistor M2 are electrically connected and grounded via a bridge pattern, effectively reducing the area of ​​the active region used to set the pull-down transistors, thereby reducing the area of ​​the single cell and the area of ​​the array area; since the area of ​​the isolation space between adjacent pull-down transistors is reduced, the introduction of large interference factors can be avoided; since the first active area pattern area and the second active area pattern area are symmetrically arranged along the central axis of the bridge pattern, the uniformity of the pattern shape on the layout can be improved, the design rule requirements for each layer of the layout can be reduced, and the complexity of the photolithography process can be reduced.

[0060] As an example, please continue to refer to Figure 3 In an embodiment of the present application, the shape of the bridge pattern 30 can be set as a rectangle to facilitate the uniformity of the pattern shape on the layout, reduce the design rule requirement for each layer of the layout, and reduce the complexity of the photolithography process. The bridge pattern 30 can be set to extend along a first direction, for example, the ox direction, and the length of the bridge pattern 30 along a second direction, for example, the oy direction, is greater than or equal to a preset width threshold to reduce the parasitic capacitance introduced by the bridge pattern 30.

[0061] As an example, in an embodiment of the present application, the layout forming method of the sense amplifier further comprises: providing a first symmetric active region pattern layer, the first symmetric active region pattern layer (not shown) is spaced apart and symmetrically arranged with the first active region pattern layer along a second direction, for example, the oy direction, which is perpendicular to the first direction, to facilitate the formation of a layout including a plurality of memory cell structures, reduce the complexity of the layout design, and improve the yield and reliability of the manufactured memory cell structure products.

[0062] As an example, in an embodiment of the present application, the first memory cell structure is a 6T SRAM; and / or the second memory cell structure is a 6T SRAM.

[0063] As an example, please continue to refer to Figure 1 In an embodiment of the present application, a layout of a sense amplifier is provided, which comprises a first active region pattern layer 100; the first active region pattern layer 100 comprises a bridge pattern 30, and a first active region pattern area 10 and a second active region pattern area 20 spaced apart along a first direction and symmetrically arranged along the central axis of the bridge pattern 30; the first active region pattern area 10 is used to define a first memory cell structure, and the first active region pattern area 10 comprises a first active region pattern 11 used to define a first pull-down transistor of the first memory cell structure; the second active region pattern area 20 is used to define a second memory cell structure, and the second active region pattern area 20 comprises a first symmetric active region pattern 21 used to define a second pull-down transistor of the second memory cell structure; wherein the first active region pattern 11 is adjacent to the first symmetric active region pattern 21 and is connected via the bridge pattern 30, so that the source of the first pull-down transistor and the source of the second pull-down transistor are electrically connected via the bridge pattern 30.

[0064] As an example, please continue to refer to Figure 2 In an embodiment of the present application, the layout of the sense amplifier further comprises a connection hole pattern layer and a gate strip pattern layer, the connection hole pattern layer is located on the first active region pattern layer 100, and the gate strip pattern layer is located on the surface of the connection hole pattern layer away from the first active region pattern layer 100, wherein the gate strip pattern layer partially overlaps the first active region pattern layer 100 and is used to form the first pull-down transistor and the second pull-down transistor.

[0065] As an example, please continue to refer to Figure 2 and Figure 4 In an embodiment of the present application, the first active region pattern area 10 further comprises a second active region pattern 12, a third active region pattern 13 and a fourth active region pattern 14 arranged along the first direction in sequence and at intervals, wherein the second active region pattern 12 is adjacent to the first active region pattern 11; the gate bar pattern layer comprises a first gate bar pattern 41, a second gate bar pattern 42, a third gate bar pattern 43 and a fourth gate bar pattern 44; wherein the first gate bar pattern 41 and the third gate bar pattern 43 are arranged along the first direction in sequence and at intervals, and the second gate bar pattern 42 and the fourth gate bar pattern 44 are arranged along the first direction in sequence and at intervals; the first gate bar pattern 41 and the second gate bar pattern 42 are arranged along the second direction in sequence and at intervals, and the third gate bar pattern 43 and the fourth gate bar pattern 44 are arranged along the second direction in sequence and at intervals; the first active region pattern 11 overlaps with the third gate bar pattern 43 and the fourth gate bar pattern 44 respectively, the second active region pattern 12 overlaps with the first gate bar pattern 41 and the fourth gate bar pattern 44 respectively, the third active region pattern 13 overlaps with the first gate bar pattern 41 and the fourth gate bar pattern 44 respectively, and the fourth active region pattern 14 overlaps with the first gate bar pattern 41 and the second gate bar pattern 42 respectively; the first gate bar pattern 41 and the fourth active region pattern 14 located on both sides of the first gate bar pattern 41 along the second direction are used to form a fourth MOS tube, the second gate bar pattern 42 and the fourth active region pattern 14 located on both sides of the second gate bar pattern 42 along the second direction are used to form a sixth MOS tube, the first gate bar pattern 41 and the third active region pattern 13 located on both sides of the first gate bar pattern 41 along the second direction are used to form a second MOS tube, the fourth gate bar pattern 44 and the second active region pattern 12 located on both sides of the fourth gate bar pattern 44 along the second direction are used to form a third MOS tube, the third gate bar pattern 43 and the first active region pattern 11 located on both sides of the third gate bar pattern 43 along the second direction are used to form a fifth MOS tube, and the fourth gate bar pattern 44 and the first active region pattern 11 located on both sides of the fourth gate bar pattern 44 along the second direction are used to form a first MOS tube.

[0066] As an example, please continue to refer to Figure 2 In an embodiment of the present application, the second active region pattern area 20 comprises a fifth gate bar pattern 45, a sixth gate bar pattern 46, a seventh gate bar pattern 47 and an eighth gate bar pattern 48; the fifth gate bar pattern 45 is symmetrically arranged with the first gate bar pattern 41 along the first direction, and the symmetry axis is the symmetry axis of the first active region pattern area 10 and the second active region pattern area 20 along the first direction; the sixth gate bar pattern 46 is symmetrically arranged with the second gate bar pattern 42 along the first direction; the seventh gate bar pattern 47 is symmetrically arranged with the third gate bar pattern 43 along the first direction; and the eighth gate bar pattern 48 is symmetrically arranged with the fourth gate bar pattern 44 along the first direction.

[0067] As an example, please continue to refer to Figure 2In an embodiment of the present application, the connection hole pattern layer includes a first connection hole pattern 511, a second connection hole pattern 512, a third connection hole pattern 513, a fourth connection hole pattern 514, a fifth connection hole pattern 515, a sixth connection hole pattern 516, a seventh connection hole pattern 517, an eighth connection hole pattern 518, a ninth connection hole pattern 519, and a tenth connection hole pattern 510; the first connection hole pattern 511 is located in the first active area pattern 11 on the side of the third gate strip pattern 43 away from the fourth gate strip pattern 44, the second connection hole pattern 512 is located in the first active area pattern 11 between the third gate strip pattern 43 and the fourth gate strip pattern 44; the second active area pattern 12 overlaps the first gate strip pattern 41 and forms a first overlapping area, the third connection hole pattern 513 covers the first overlapping area; the fourth connection hole pattern 514 is located in the second active area pattern 12 on the side of the fourth gate strip pattern 44 away from the first gate strip pattern 41; the fifth connection hole pattern 515 is located in the third active area pattern 13 on the side of the first gate strip pattern 41 away from the fourth gate strip pattern 44; the third active area pattern 13 overlaps the fourth gate strip pattern 44 and forms a second overlapping area, the sixth connection hole pattern 516 covers the second overlapping area; the seventh connection hole pattern 517 is located in the fourth active area pattern 14 on the side of the first gate strip pattern 41 away from the second gate strip pattern 42; the eighth connection hole pattern 518 is located in the fourth active area pattern 14 between the first gate strip pattern 41 and the second gate strip pattern 42; the ninth connection hole pattern 519 is located in the fourth active area pattern 14 on the side of the second gate strip pattern 42 away from the first gate strip pattern 41; and the tenth connection hole pattern 510 is located in the third gate strip pattern 43 between the first active area pattern 11 and the first symmetric active area pattern 21.

[0068] For example, see Figure 3 In an embodiment of the present application, the layout of the sensitive amplifier further includes a metal pattern layer located on the surface of the gate strip pattern layer away from the first active area pattern layer 100; the metal pattern layer includes a first metal pattern 611, a second metal pattern 612, a third metal pattern 613, a fourth metal pattern 614, a fifth metal pattern 615, a sixth metal pattern 616, a seventh metal pattern 617, and an eighth metal pattern 618; the first metal pattern 611 covers the first connection hole pattern 511; the second metal pattern 612 covers the second connection hole pattern 512 and part of the third connection hole pattern 513; the third metal pattern 613 covers the fourth connection hole pattern 514; the fourth metal pattern 614 covers the fifth connection hole pattern 515; the fifth metal pattern 615 covers part of the sixth connection hole pattern 516 and the eighth connection hole pattern 518; the sixth metal pattern 616 covers the seventh connection hole pattern 517; the seventh metal pattern 617 covers the ninth connection hole pattern 519; and the eighth metal pattern 618 covers the tenth connection hole pattern 510.

[0069] As an example, please continue to refer to Figure 4 In one embodiment of the present application, a storage unit circuit is provided, comprising a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5 and a sixth MOS transistor M6. The source of the third MOS transistor M3 and the source of the fourth MOS transistor M4 are both connected to a power supply line VDD. The source of the first MOS transistor M1 and the source of the second MOS transistor M2 are both connected to a ground line VSS. The drain of the third MOS transistor M3 is connected to the source of the fifth MOS transistor M5, the drain of the first MOS transistor M1, the gate of the fourth MOS transistor M4 and the gate of the second MOS transistor M2. The drain of the fourth MOS transistor M4 is connected to the source of the sixth MOS transistor M6, the drain of the second MOS transistor M2, the gate of the third MOS transistor M3 and the gate of the first MOS transistor M1. The gates of the fifth MOS transistor M5 and the sixth MOS transistor M6 are both connected to a word line WL. The drain of the fifth MOS transistor M5 is connected to a bit line BL, and the drain of the sixth MOS transistor M6 is connected to a complementary bit line BL_.

[0070] As an example, please refer to Figure 5 In a top view schematic diagram of a conventional sensitive amplifier layout, as shown in Figure 3 different from the top view schematic diagram of the sensitive amplifier layout shown in Figure 5 at least further comprising an eleventh connection hole pattern 5101, a twelfth connection hole pattern 5201 and a conductive metal line 619, wherein the active region of the pull-down transistor G3 is provided with the eleventh connection hole pattern 5101, the active region of the pull-down transistor G4 is provided with the twelfth connection hole pattern 5201, and the eleventh connection hole pattern 5101 is electrically connected to the twelfth connection hole pattern 5201 via the conductive metal line 619.

[0071] with respect to as Figure 5 and Figure 6aThe conventional semiconductor structure shown in the figure, the eleventh connection hole pattern 5101 is arranged in the active region of the pull-down transistor G3, and the twelfth connection hole pattern 5201 is arranged in the active region of the pull-down transistor G4, so as to electrically connect the eleventh connection hole pattern 5101 and the twelfth connection hole pattern 5201 by the conductive metal line 619, and realize the electrical connection between the active region of the pull-down transistor G3 and the active region of the pull-down transistor G4. The active region of the first pull-down transistor M1 and the active region of the second pull-down transistor M2 are electrically connected through the bridge pattern 30, at least the eleventh connection hole pattern 5101, the twelfth connection hole pattern 5201 and the conductive metal line 619 are saved, which can effectively reduce the area of the active region for arranging the pull-down transistor, thereby reducing the area of the single cell and the area of the array region; since the area of the isolation space between adjacent pull-down transistors is reduced, the introduction of a larger interference factor can be avoided; since the first active region pattern area 10 and the second active region pattern area 20 are symmetrically arranged along the central axis of the bridge pattern 30, the uniformity of the pattern shape on the layout can be improved, the design rule requirement of each layer layout is reduced, and the complexity of the photolithography process is reduced, which is convenient for optical proximity correction. The present application can use the pattern on the adjacent previous layer for alignment, which improves the accuracy of alignment.

[0072] In an embodiment of the present application, the bridge pattern 30 extends along a first direction; the length of the bridge pattern 30 along a second direction is greater than or equal to a preset width threshold, so as to reduce the parasitic capacitance introduced by the bridge pattern 30.

[0073] In an embodiment of the present application, the layout of the sense amplifier further comprises a first symmetrical active region pattern layer, the first symmetrical active region pattern layer is arranged symmetrically with the first active region pattern layer along a second direction, and the second direction can be perpendicular to the first direction, so as to form a layout comprising a plurality of memory cell structures, reduce the complexity of layout design, and improve the yield and reliability of the manufactured memory cell structure product.

[0074] Please note that the above embodiments are only for illustrative purposes and do not mean to limit the present application.

[0075] It should be understood that, unless otherwise explicitly stated herein, the execution of the steps described is not strictly limited in sequence, and the steps can be executed in other sequences. Moreover, at least a part of the steps described can include a plurality of sub-steps or stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of the sub-steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least a part of other steps or sub-steps or stages of other steps.

[0076] Various embodiments are described herein with reference to the following items, but the embodiments are not limited to the items and can include any appropriate items. 1. A method for manufacturing a semiconductor device, comprising: forming a first insulating layer over a substrate; forming a first conductive layer over the first insulating layer; forming a second insulating layer over the first conductive layer; forming a second conductive layer over the second insulating layer; and forming a third insulating layer over the second conductive layer.

[0077] The technical features of the above-described embodiments can be combined in any manner, and for brevity, not all possible combinations of the technical features are described herein, but it is to be understood that any combination of the technical features is within the scope of the present specification.

[0078] The above-described embodiments are merely some embodiments of the present application, and the description is specific and detailed, but should not be construed as limiting the scope of the patent application. It should be noted that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of the present application. Therefore, the scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method for forming a layout of a sense amplifier, characterized in that: include: Providing a first active area pattern layer, the first active area pattern layer including a bridge pattern, and a first active area pattern region and a second active area pattern region spaced apart along a first direction and symmetrically arranged along a central axis of the bridge pattern; The first active area pattern region is used to define a first memory cell structure, and the first active area pattern region includes a first active area pattern for defining a first pull-down transistor of the first memory cell structure; The second active area pattern region is used to define a second memory cell structure, and the second active area pattern region includes a first symmetrical active area pattern for defining a second pull-down transistor of the second memory cell structure; The first active area pattern is adjacent to the first symmetrical active area pattern and is connected via the bridge pattern, so that the source of the first pull-down transistor and the source of the second pull-down transistor are electrically connected via the bridge pattern; forming a connection hole pattern layer on the first active area pattern layer; forming a gate pattern layer on a surface of the contact hole pattern layer away from the first active area pattern layer, wherein the gate pattern layer partially overlaps with the first active area pattern layer and is used to form the first pull-down transistor and the second pull-down transistor; The first active area pattern region further includes a second active area pattern, a third active area pattern, and a fourth active area pattern sequentially spaced apart along the first direction, wherein the second active area pattern is adjacent to the first active area pattern; The grid pattern layer includes a first grid pattern, a second grid pattern, a third grid pattern and a fourth grid pattern; wherein the first grid pattern and the third grid pattern are sequentially spaced along the first direction, and the second grid pattern and the fourth grid pattern are sequentially spaced along the first direction; the first grid pattern and the second grid pattern are sequentially spaced along the second direction, and the third grid pattern and the fourth grid pattern are sequentially spaced along the second direction; The first active area pattern overlaps with the third grid bar pattern and the fourth grid bar pattern respectively, the second active area pattern overlaps with the first grid bar pattern and the fourth grid bar pattern respectively, the third active area pattern overlaps with the first grid bar pattern and the fourth grid bar pattern respectively, and the fourth active area pattern overlaps with the first grid bar pattern and the second grid bar pattern respectively; The first gate bar pattern and the fourth active area pattern located on both sides thereof along the second direction are used to form a fourth MOS transistor, the second gate bar pattern and the fourth active area pattern located on both sides thereof along the second direction are used to form a sixth MOS transistor, the first gate bar pattern and the third active area pattern located on both sides thereof along the second direction are used to form a second MOS transistor, the fourth gate bar pattern and the second active area pattern located on both sides thereof along the second direction are used to form a third MOS transistor, the third gate bar pattern and the first active area pattern located on both sides thereof along the second direction are used to form a fifth MOS transistor, and the fourth gate bar pattern and the first active area pattern located on both sides thereof along the second direction are used to form a first MOS transistor.

2. The method for forming a layout of a sense amplifier according to claim 1, wherein: The connection hole pattern layer includes a first connection hole pattern, a second connection hole pattern, a third connection hole pattern, a fourth connection hole pattern, a fifth connection hole pattern, a sixth connection hole pattern, a seventh connection hole pattern, an eighth connection hole pattern, a ninth connection hole pattern, and a tenth connection hole pattern; The first connection hole pattern is located in the first active area pattern on a side of the third gate pattern away from the fourth gate pattern; The second connection hole pattern is located in the first active area pattern between the third grid bar pattern and the fourth grid bar pattern; The second active area pattern overlaps with the first gate pattern to form a first overlapping area, and the third connection hole pattern covers the first overlapping area; The fourth connection hole pattern is located in the second active area pattern on a side of the fourth gate pattern away from the first gate pattern; The fifth connection hole pattern is located in the third active area pattern on a side of the first gate pattern away from the fourth gate pattern; The third active area pattern overlaps with the fourth gate pattern to form a second overlapping area, and the sixth connection hole pattern covers the second overlapping area; The seventh connection hole pattern is located in the fourth active area pattern on a side of the first gate pattern away from the second gate pattern; The eighth connection hole pattern is located in the fourth active area pattern between the first gate pattern and the second gate pattern; The ninth connection hole pattern is located in the fourth active area pattern on a side of the second gate pattern away from the first gate pattern; The tenth connection hole pattern is located in the third gate bar pattern between the first active area pattern and the first symmetrical active area pattern.

3. The method for forming a layout of a sense amplifier according to claim 2, wherein: Also includes: forming a metal pattern layer on a surface of the gate pattern layer away from the first active area pattern layer; the metal pattern layer includes a first metal pattern, a second metal pattern, a third metal pattern, a fourth metal pattern, a fifth metal pattern, a sixth metal pattern, a seventh metal pattern, and an eighth metal pattern; The first metal pattern covers the first connection hole pattern; The second metal pattern covers the second connection hole pattern and a portion of the third connection hole pattern; The third metal pattern covers the fourth connection hole pattern; The fourth metal pattern covers the fifth connection hole pattern; The fifth metal pattern partially covers the sixth connection hole pattern and the eighth connection hole pattern; The sixth metal pattern covers the seventh connection hole pattern; The seventh metal pattern covers the ninth connection hole pattern; The eighth metal pattern covers the tenth connection hole pattern.

4. The method for forming a layout of a sense amplifier according to claim 3, wherein: The second active region pattern area includes a fifth grid bar pattern, a sixth grid bar pattern, a seventh grid bar pattern and an eighth grid bar pattern; The fifth grid pattern is symmetrical to the first grid pattern along the first direction, and the axis of symmetry is the axis of symmetry of the first active area pattern region and the second active area pattern region along the first direction; The sixth grid bar pattern and the second grid bar pattern are symmetrically arranged along the first direction; The seventh grid bar pattern and the third grid bar pattern are symmetrically arranged along the first direction; The eighth grid bar pattern and the fourth grid bar pattern are symmetrically arranged along the first direction.

5. The method for forming a layout of a sense amplifier according to any one of claims 1 to 4, wherein: The shape of the bridge figure is a rectangle.

6. The method for forming a layout of a sense amplifier according to claim 5, wherein: The bridge pattern extends along the first direction.

7. The method for forming a layout of a sense amplifier according to claim 5, wherein: The length of the bridge pattern along the second direction is greater than or equal to a preset width threshold.

8. The method for forming a layout of a sense amplifier according to any one of claims 1 to 4, wherein: Also includes: A first symmetrical active area pattern layer is provided. The first symmetrical active area pattern layer is spaced apart from and symmetrically arranged with the first active area pattern layer along a second direction. The second direction is perpendicular to the first direction.

9. The method for forming a layout of a sense amplifier according to any one of claims 1 to 4, wherein: The first storage unit structure is a 6T SRAM; and / or The second storage unit structure is a 6T SRAM.

10. A layout of a sense amplifier, characterized in that: The present invention comprises a first active area pattern layer; the first active area pattern layer comprises a bridge pattern, and a first active area pattern region and a second active area pattern region spaced along a first direction and symmetrically arranged along a central axis of the bridge pattern; The first active area pattern region is used to define a first memory cell structure, and the first active area pattern region includes a first active area pattern for defining a first pull-down transistor of the first memory cell structure; The second active area pattern region is used to define a second memory cell structure, and the second active area pattern region includes a first symmetrical active area pattern for defining a second pull-down transistor of the second memory cell structure; The first active area pattern is adjacent to the first symmetrical active area pattern and is connected via the bridge pattern, so that the source of the first pull-down transistor and the source of the second pull-down transistor are electrically connected via the bridge pattern; The layout of the sense amplifier further includes a connection hole pattern layer and a gate bar pattern layer, wherein the connection hole pattern layer is located on the first active area pattern layer, and the gate bar pattern layer is located on a surface of the connection hole pattern layer away from the first active area pattern layer, wherein the gate bar pattern layer partially overlaps with the first active area pattern layer and is used to form the first pull-down transistor and the second pull-down transistor; The first active area pattern region further includes a second active area pattern, a third active area pattern, and a fourth active area pattern sequentially spaced apart along the first direction, wherein the second active area pattern is adjacent to the first active area pattern; The grid pattern layer includes a first grid pattern, a second grid pattern, a third grid pattern and a fourth grid pattern; wherein the first grid pattern and the third grid pattern are sequentially spaced along the first direction, and the second grid pattern and the fourth grid pattern are sequentially spaced along the first direction; the first grid pattern and the second grid pattern are sequentially spaced along the second direction, and the third grid pattern and the fourth grid pattern are sequentially spaced along the second direction; The first active area pattern overlaps with the third grid bar pattern and the fourth grid bar pattern respectively, the second active area pattern overlaps with the first grid bar pattern and the fourth grid bar pattern respectively, the third active area pattern overlaps with the first grid bar pattern and the fourth grid bar pattern respectively, and the fourth active area pattern overlaps with the first grid bar pattern and the second grid bar pattern respectively; The first gate bar pattern and the fourth active area pattern located on both sides thereof along the second direction are used to form a fourth MOS transistor, the second gate bar pattern and the fourth active area pattern located on both sides thereof along the second direction are used to form a sixth MOS transistor, the first gate bar pattern and the third active area pattern located on both sides thereof along the second direction are used to form a second MOS transistor, the fourth gate bar pattern and the second active area pattern located on both sides thereof along the second direction are used to form a third MOS transistor, the third gate bar pattern and the first active area pattern located on both sides thereof along the second direction are used to form a fifth MOS transistor, and the fourth gate bar pattern and the first active area pattern located on both sides thereof along the second direction are used to form a first MOS transistor.

11. The layout of the sense amplifier according to claim 10, wherein: The connection hole pattern layer includes a first connection hole pattern, a second connection hole pattern, a third connection hole pattern, a fourth connection hole pattern, a fifth connection hole pattern, a sixth connection hole pattern, a seventh connection hole pattern, an eighth connection hole pattern, a ninth connection hole pattern, and a tenth connection hole pattern; The first connection hole pattern is located in the first active area pattern on a side of the third gate pattern away from the fourth gate pattern; The second connection hole pattern is located in the first active area pattern between the third grid bar pattern and the fourth grid bar pattern; The second active area pattern overlaps with the first gate pattern to form a first overlapping area, and the third connection hole pattern covers the first overlapping area; The fourth connection hole pattern is located in the second active area pattern on a side of the fourth gate pattern away from the first gate pattern; The fifth connection hole pattern is located in the third active area pattern on a side of the first gate pattern away from the fourth gate pattern; The third active area pattern overlaps with the fourth gate pattern to form a second overlapping area, and the sixth connection hole pattern covers the second overlapping area; The seventh connection hole pattern is located in the fourth active area pattern on a side of the first gate pattern away from the second gate pattern; The eighth connection hole pattern is located in the fourth active area pattern between the first gate pattern and the second gate pattern; The ninth connection hole pattern is located in the fourth active area pattern on a side of the second gate pattern away from the first gate pattern; The tenth connection hole pattern is located in the third gate bar pattern between the first active area pattern and the first symmetrical active area pattern.

12. The layout of the sense amplifier according to claim 11, wherein: It also includes a metal pattern layer, the metal pattern layer is located on a surface of the gate pattern layer away from the first active area pattern layer; The metal pattern layer includes a first metal pattern, a second metal pattern, a third metal pattern, a fourth metal pattern, a fifth metal pattern, a sixth metal pattern, a seventh metal pattern and an eighth metal pattern; The first metal pattern covers the first connection hole pattern; The second metal pattern covers the second connection hole pattern and a portion of the third connection hole pattern; The third metal pattern covers the fourth connection hole pattern; The fourth metal pattern covers the fifth connection hole pattern; The fifth metal pattern partially covers the sixth connection hole pattern and the eighth connection hole pattern; The sixth metal pattern covers the seventh connection hole pattern; The seventh metal pattern covers the ninth connection hole pattern; The eighth metal pattern covers the tenth connection hole pattern.

13. The layout of the sense amplifier according to claim 12, wherein: The second active region pattern area includes a fifth grid bar pattern, a sixth grid bar pattern, a seventh grid bar pattern and an eighth grid bar pattern; The fifth grid pattern is symmetrical to the first grid pattern along the first direction, and the axis of symmetry is the axis of symmetry of the first active area pattern region and the second active area pattern region along the first direction; The sixth grid bar pattern and the second grid bar pattern are symmetrically arranged along the first direction; The seventh grid bar pattern and the third grid bar pattern are symmetrically arranged along the first direction; The eighth grid bar pattern and the fourth grid bar pattern are symmetrically arranged along the first direction.

14. The layout of the sense amplifier according to any one of claims 10 to 13, wherein: The bridge pattern extends along the first direction; The length of the bridge pattern along the second direction is greater than or equal to a preset width threshold.

15. The layout of the sense amplifier according to claim 14, wherein: The invention also includes a first symmetrical active area pattern layer, wherein the first symmetrical active area pattern layer is spaced apart and symmetrically arranged with the first active area pattern layer along a second direction, and the second direction is perpendicular to the first direction.

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