Semiconductor device and method for manufacturing semiconductor device

Abstract

The present disclosure relates to a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: an n-type gallium oxide semiconductor layer having a central region and a peripheral region having a lower donor density than the central region; an electrode layer stacked on the n-type gallium oxide semiconductor layer and forming a Schottky junction with the n-type gallium oxide semiconductor layer in the central region when viewed in the stacking direction; and a first p-type nickel oxide semiconductor layer stacked on the n-type gallium oxide semiconductor layer so as to be partially positioned between the n-type gallium oxide semiconductor layer and the electrode layer, with an outer peripheral end portion on the peripheral region side being located in the peripheral region when viewed in the stacking direction.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] Japanese Patent Application Laid-Open No. 2016-81981 discloses a semiconductor device made of semiconductor SiC, having a termination region surrounding an active region. The surface of the termination region is covered with a passivation film. The passivation film is characterized in that it comprises: a first silicon oxide film in contact with the surface of the termination region; a second silicon oxide film laminated on and in contact with the first silicon oxide film; and a third silicon oxide film laminated on and in contact with the second silicon oxide film. The document discloses that, in the semiconductor device, the termination region may have an FLR (field limiting ring) structure. Summary of the Invention

[0003] In semiconductor devices where an n-type gallium oxide semiconductor layer forms a Schottky junction with an electrode layer, a p-type nickel oxide semiconductor layer can be used in the peripheral voltage-withstand structure. However, it is difficult to reduce the acceptor density in a p-type nickel oxide semiconductor layer. Consequently, the electric field concentrates at the outer edge of the p-type nickel oxide semiconductor layer in contact with the electrode layer, easily causing dielectric breakdown.

[0004] Therefore, in a semiconductor device in which a Schottky junction is formed between an n-type gallium oxide semiconductor layer and an electrode layer, suppression of dielectric breakdown, that is, improvement of withstand voltage, is required.

[0005] An object of the present disclosure is to provide a semiconductor device having high withstand voltage and in which an n-type gallium oxide semiconductor layer and an electrode layer form a Schottky junction.

[0006] The present inventors have discovered that the above-mentioned problems can be achieved by the following means:

[0007] Plan 1

[0008] A semiconductor device comprising:

[0009] An n-type gallium oxide semiconductor layer having a central region and a peripheral region having a lower donor density than the central region;

[0010] an electrode layer stacked on the n-type gallium oxide semiconductor layer and forming a Schottky junction with the n-type gallium oxide semiconductor layer in the central region when viewed from the stacking direction; and

[0011] The first p-type nickel oxide semiconductor layer is stacked on the n-type gallium oxide semiconductor layer so as to be partially arranged between the n-type gallium oxide semiconductor layer and the electrode layer, and when viewed from the stacking direction, the outer peripheral end portion on the peripheral region side is located in the peripheral region.

[0012] Plan 2

[0013] In the semiconductor device described in claim 1, the donor density in the peripheral region is 5.0×10 15 cm -3 the following.

[0014] Plan 3

[0015] In the semiconductor device according to claim 1 or 2, the donor density in the central region is 1.0×10 16 cm -3 above.

[0016] Plan 4

[0017] In the semiconductor device according to any one of claims 1 to 3, the first p-type nickel oxide semiconductor layer is arranged so as to span the central region and the peripheral region when viewed in the stacking direction.

[0018] Plan 5

[0019] In the semiconductor device described in claim 4, when the thickness of the central region of the n-type gallium oxide semiconductor layer is t and the width of the portion of the first p-type nickel oxide semiconductor layer located in the central region is x, x / t>0.50.

[0020] Plan 6

[0021] In the semiconductor device according to any one of aspects 1 to 5, the donor is Sn or Si.

[0022] Plan 7

[0023] In the semiconductor device according to any one of claims 1 to 6, the peripheral region is doped with acceptors so that the donor density is lower than that of the central region.

[0024] Plan 8

[0025] In the semiconductor device described in claim 7, the acceptor is N or Mg.

[0026] Plan 9

[0027] In the semiconductor device described in any one of Schemes 1 to 8, a plurality of second p-type nickel oxide semiconductor layers are provided at intervals from the central region toward the peripheral region in the peripheral region on the side of the n-type gallium oxide semiconductor layer on which the first p-type nickel oxide semiconductor layer is stacked.

[0028] Plan 10

[0029] In the semiconductor device according to claim 9, the n-type gallium oxide semiconductor layer has a plurality of trench structures on a side where the first p-type nickel oxide semiconductor layer and the plurality of second p-type nickel oxide semiconductor layers are stacked.

[0030] The first p-type nickel oxide semiconductor layer and the plurality of second p-type nickel oxide semiconductor layers are respectively stacked in the concave portions of the trench structure.

[0031] Plan 11

[0032] In the semiconductor device according to any one of aspects 1 to 10, the semiconductor device is a pn diode, a JBS diode, a metal oxide semiconductor field effect transistor, or a junction field effect transistor.

[0033] Plan 12

[0034] A method for manufacturing a semiconductor device according to any one of claims 1 to 11, wherein:

[0035] The method includes reducing the donor density by ion irradiation or heating in an oxygen atmosphere, thereby forming the peripheral region of the n-type gallium oxide semiconductor layer.

[0036] Plan 13

[0037] In the method described in claim 12, in the ion irradiation, ions of an acceptor element, hydrogen, or helium are irradiated.

[0038] Plan 14

[0039] In the method described in claim 12 or 13, after the ion irradiation, an annealing treatment is performed on the n-type gallium oxide semiconductor layer.

[0040] Plan 15

[0041] In the method described in claim 12 or 13, the n-type gallium oxide semiconductor layer is not annealed after the ion irradiation.

[0042] According to the present disclosure, a semiconductor device having high withstand voltage and in which an n-type gallium oxide semiconductor layer and an electrode layer form a Schottky junction can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Features, advantages, and technical and industrial significance of exemplary embodiments of the present invention will be described below with reference to the accompanying drawings, in which like reference numerals represent like elements, and in which:

[0044] Figure 1 It is a schematic diagram of the semiconductor device 1 according to the first embodiment of the present disclosure.

[0045] Figure 2 It is a schematic diagram of a semiconductor device 2 which is different from the embodiment of the present disclosure.

[0046] Figure 3 It is a schematic diagram of the semiconductor device 1 according to the first embodiment of the present disclosure.

[0047] Figure 4 It is a schematic diagram of a semiconductor device 3 of Comparative Example 2.

[0048] Figure 5 It is a schematic diagram of a semiconductor device 4 of Comparative Example 3.

[0049] Figure 6 Schematic diagram of the semiconductor device 5 according to the first embodiment.

[0050] Figure 7 This is a graph showing the relationship between the depth of the n-type gallium oxide semiconductor layer after ion implantation and the Mg density in Example 7.

[0051] Figure 8 This is a graph showing the relationship between the depth and Mg density of the n-type gallium oxide semiconductor layer after heat treatment in an air atmosphere in Example 8. DETAILED DESCRIPTION

[0052] Hereinafter, embodiments of the present disclosure will be described in detail. However, the present disclosure is not limited to the following embodiments, and can be implemented with various modifications within the scope of the disclosed gist.

[0053] The present disclosure provides a semiconductor device comprising: an n-type gallium oxide semiconductor layer having a central region and a peripheral region having a lower donor density than the central region; an electrode layer stacked on the n-type gallium oxide semiconductor layer and forming a Schottky junction with the n-type gallium oxide semiconductor layer in the central region when viewed in the stacking direction; and a first p-type nickel oxide semiconductor layer stacked on the n-type gallium oxide semiconductor layer in a manner partially arranged between the n-type gallium oxide semiconductor layer and the electrode layer, and having an outer peripheral end portion on the peripheral region side located in the peripheral region when viewed in the stacking direction.

[0054] In semiconductor devices where an n-type gallium oxide semiconductor layer forms a Schottky junction with an electrode layer, dielectric breakdown is more likely to occur when a p-type nickel oxide semiconductor layer is used in the peripheral voltage-withstand structure. This is because it is difficult to reduce the acceptor density in the p-type nickel oxide semiconductor layer, so the electric field tends to concentrate at the outer edge of the p-type nickel oxide semiconductor layer in contact with the electrode layer.

[0055] When viewed in the stacking direction, the semiconductor device disclosed herein has an outer peripheral edge of the first p-type nickel oxide semiconductor layer located in the peripheral region of the n-type gallium oxide semiconductor layer. This peripheral region has a lower donor density than the central region. This suppresses electric field concentration in the outer peripheral edge of the first p-type nickel oxide semiconductor layer, which is in contact with the electrode layer. Consequently, dielectric breakdown in the semiconductor device disclosed herein is suppressed.

[0056] Figure 1 It is a schematic diagram of the semiconductor device 1 according to the first embodiment of the present disclosure.

[0057] like Figure 1 As shown, the semiconductor device 1 involved in the first embodiment of the present disclosure includes: an n-type gallium oxide semiconductor layer 10, having a central region 11 and a peripheral region 13 with a lower donor density than the central region 11; a first electrode layer 20, stacked on the n-type gallium oxide semiconductor layer 10, and forming a Schottky junction with the n-type gallium oxide semiconductor layer 10 in the central region 11 when viewed from the stacking direction; and a first p-type nickel oxide semiconductor layer 40, stacked on the n-type gallium oxide semiconductor layer 10 in a manner partially arranged between the n-type gallium oxide semiconductor layer 10 and the first electrode layer 20, and having an outer peripheral end portion on the peripheral region 13 side located in the peripheral region 13 when viewed from the stacking direction.

[0058] The semiconductor device 1 according to the first embodiment of the present disclosure has a second electrode layer 30 stacked on the surface of the n-type gallium oxide semiconductor layer 10 on the side not stacked with the first electrode layer 20. The second electrode layer 30 forms an ohmic junction with the n-type gallium oxide semiconductor layer 10.

[0059] also, Figure 1 In the figure, "C" indicates the central region side, and "O" indicates the peripheral region side. The terms "central region side C" and "peripheral region side O" simply indicate directions. The "central region side C" of a component does not necessarily overlap with the central region of the n-type gallium oxide semiconductor layer 10 when viewed in the stacking direction. The same applies to the "peripheral region side O."

[0060] In the semiconductor device 1 according to the first embodiment of the present disclosure, when viewed in the stacking direction, the outer peripheral end portion of the first p-type nickel oxide semiconductor layer 40 on the peripheral region side O is located in the peripheral region 13 of the n-type gallium oxide semiconductor layer 10. The donor density in the peripheral region 13 is lower than that in the central region 11. This suppresses electric field concentration at the outer peripheral end portion of the first p-type nickel oxide semiconductor layer 40 in contact with the first electrode layer 20. Consequently, dielectric breakdown in the semiconductor device 1 according to the first embodiment of the present disclosure is suppressed.

[0061] also, Figure 1 This does not limit the gist of the semiconductor device disclosed herein.

[0062] Figure 2 It is a schematic diagram of a semiconductor device 2 which is different from the embodiment of the present disclosure.

[0063] like Figure 2 As shown, semiconductor device 2, which differs from the embodiment of the present disclosure, has no difference in donor density between central region 11 and peripheral region 13. Generally, p-type nickel oxide semiconductor layers have a high acceptor density. Therefore, in such semiconductor device 2, the electric field concentrates at the outer peripheral edge of first p-type nickel oxide semiconductor layer 40 in contact with first electrode layer 20, easily causing dielectric breakdown.

[0064] Furthermore, the semiconductor device disclosed herein may be, for example, a diode, more specifically a pn diode or a JBS diode, or a transistor, more specifically a metal oxide semiconductor field effect transistor (MOSFET) or a junction field effect transistor (JFET).

[0065] 《n-type gallium oxide semiconductor layer》

[0066] The n-type gallium oxide semiconductor layer includes a central region and a peripheral region. The donor density in the peripheral region is lower than that in the central region.

[0067] The n-type gallium oxide semiconductor layer may be, for example, a layer formed on a gallium oxide single crystal layer. More specifically, the n-type gallium oxide semiconductor layer may be, for example, an epitaxial layer.

[0068] The gallium oxide single crystal layer may be, for example, an α-Ga 2 O 3 single crystal, a β-Ga 2 O 3 single crystal, or a Ga 2 O 3 single crystal layer having another crystal structure, and is preferably a β-Ga 2 O 3 single crystal layer.

[0069] The n-type gallium oxide semiconductor layer contains a donor, which may be, for example, Sn or Si.

[0070] <Central Area>

[0071] The central region may include at least an active region of a Schottky diode in which an electrode layer is arranged. The active region refers to a portion where a semiconductor element is formed.

[0072] The central area has a higher donor density than the peripheral area.

[0073] The donor density in the central region can be 1.0×10 16 cm -3 above.

[0074] The donor density in the central region can be 1.0×10 16 cm -3 Above and 1.0×10 18 cm -3 the following.

[0075] The donor density in the central region can be 1.0×10 16 cm -3 Above, 2.0×10 16 cm -3 Above, 5.0×10 16 cm -3 Above, or 1.0×10 17 cm -3 Above, it can be 1.0×10 18 cm -3 Below, 5.0×10 17 cm -3 Below, 2.0×10 17 cm -3 Below, or 1.0×10 17 cm -3 the following.

[0076] <Surrounding Area>

[0077] The peripheral region is the region surrounding the central region and has a lower donor density than the central region.

[0078] The donor density in the peripheral region can be 5.0×10 15 cm -3 the following.

[0079] The donor density in the peripheral area can be 0.0 cm -3 Above and 5.0×10 15 cm -3 the following.

[0080] The donor density in the peripheral area can be 0.0 cm-3 Above, 5.0×10 10 cm -3 Above, 2.0×10 14 cm -3 Above, or 1.0×10 15 cm -3 Above, it can also be 5.0×10 15 cm -3 Below, or 1.0×10 15 cm -3 the following.

[0081] In order to make the donor density in the peripheral region lower than that in the central region, the peripheral region may be doped with acceptors. In this case, for example, after forming an n-type gallium oxide semiconductor layer uniformly doped with donors, the portion of the n-type gallium oxide semiconductor layer that is to serve as the peripheral region is subsequently doped with acceptors, thereby making it possible to easily form the central and peripheral regions.

[0082] For example, before stacking the first p-type nickel oxide semiconductor layer or the first and second p-type nickel oxide semiconductor layers on the n-type gallium oxide semiconductor layer, acceptors may be doped into the n-type gallium oxide semiconductor layer by ion implantation.

[0083] The acceptor may be, for example, N or Mg.

[0084] Electrode Layer

[0085] The electrode layer is stacked on the n-type gallium oxide semiconductor layer. When the semiconductor device is viewed from the stacking direction, the electrode layer forms a Schottky junction with the n-type gallium oxide semiconductor layer in a central region.

[0086] The electrode layer may be formed of any material capable of forming a Schottky junction with the n-type gallium oxide semiconductor layer at least in a portion in contact with the n-type gallium oxide semiconductor layer.

[0087] Examples of materials capable of forming a Schottky junction with the n-type gallium oxide semiconductor layer include, but are not limited to, Ti, Ni, Fe, Cu, Mo, W, or Pt.

[0088] The electrode layer can be formed on the n-type gallium oxide semiconductor layer by any film-forming method. The film-forming method used to form the electrode layer can be, for example, physical vapor deposition, more specifically, vacuum evaporation, molecular beam evaporation, ion plating, ion beam evaporation, conventional sputtering, magnetron sputtering, or ion beam sputtering.

[0089] Furthermore, the semiconductor device of the present disclosure may have an n-type gallium oxide semiconductor layer on the side opposite to the side on which the electrode layer is stacked. +Type gallium oxide substrate and other electrode layers. + type gallium oxide substrate.

[0090] The other electrode layer may form an ohmic junction with the n-type gallium oxide semiconductor layer at least in a portion in contact with the n-type gallium oxide semiconductor layer.

[0091] The other electrode layer may be formed of any material capable of forming an ohmic junction with the n-type gallium oxide semiconductor layer at least in a portion in contact with the n-type gallium oxide semiconductor layer.

[0092] Examples of the material capable of forming an ohmic junction with the n-type gallium oxide semiconductor layer include Ti, but are not limited thereto.

[0093] In addition, the other electrode layer can also be formed by the same method as the electrode layer.

[0094] 《First p-type nickel oxide semiconductor layer》

[0095] The semiconductor device disclosed herein includes a first p-type nickel oxide semiconductor layer stacked on an n-type gallium oxide semiconductor layer so as to be partially positioned between the n-type gallium oxide semiconductor layer and an electrode layer. When the semiconductor device is viewed from the stacking direction, the outer peripheral end of the first p-type nickel oxide semiconductor layer is located in the peripheral region.

[0096] The first p-type nickel oxide semiconductor layer may be doped with an acceptor.

[0097] The acceptor may be, for example, Li, Cu or Ag.

[0098] The acceptor density in the first p-type nickel oxide semiconductor layer may be 1.0×10 18 cm -3 above.

[0099] The acceptor density in the first p-type nickel oxide semiconductor layer may be 1.0×10 18 cm -3 Above and 1.0×10 20 cm -3 the following.

[0100] The acceptor density in the first p-type nickel oxide semiconductor layer may be 1.0×10 18 cm -3 Above, 2.0×10 18 cm -3 Above, 5.0×10 18 cm -3 Above, or 1.0×10 19 cm -3 Above, it can be 1.0×10 20 cm-3 Below, 5.0×10 19 cm -3 Below, 2.0×10 19 cm -3 Below, or 1.0×10 19 cm -3 the following.

[0101] Furthermore, the first p-type nickel oxide semiconductor layer can be doped with acceptors by, for example, doping during film formation.

[0102] The first p-type nickel oxide semiconductor layer can be arranged across the central region and the peripheral region when viewed in the stacking direction. Thus, when viewing the semiconductor device in the stacking direction, the first p-type nickel oxide semiconductor layer has a central region portion and a peripheral region portion.

[0103] Here, if Figure 3 As shown, in the semiconductor device 1 of the present disclosure, the drift layer thickness of the central region 11 of the n-type gallium oxide semiconductor layer 10 is set to t (excluding the above n + (a p-type gallium oxide semiconductor substrate), and where the width of the portion of the first p-type nickel oxide semiconductor layer 40 in the central region 11 is x, preferably x / t>0.50. Furthermore, "thickness" refers to the maximum thickness of the drift layer. Furthermore, "width" refers to the maximum width.

[0104] also, Figure 3 This does not limit the gist of the semiconductor device disclosed herein.

[0105] When the portion in the central region of the first p-type nickel oxide semiconductor layer is small, that is, when x / t is small, the withstand voltage of the semiconductor device can be improved, but the resistivity of the semiconductor device increases.

[0106] In the case of x / t>0.50, the withstand voltage can be improved while maintaining the resistivity of the semiconductor device.

[0107] Alternatively, x / t≤2.00 may be satisfied.

[0108] x / t may be greater than 0.50, 0.80 or greater, 1.00 or greater, or 1.50 or greater, and may be less than 2.00, less than 1.80, less than 1.60, or less than 1.50.

[0109] The width of the first p-type nickel oxide semiconductor layer can be, for example, 1.0 μm to 10.0 μm. In addition, the “width” refers to the maximum width.

[0110] The width of the first p-type nickel oxide semiconductor layer may be greater than 1.0 μm, greater than 2.0 μm, greater than 3.0 μm, or greater than 5.0 μm, and may be less than 10.0 μm, less than 8.0 μm, less than 60.0 μm, or less than 5.0 μm.

[0111] Furthermore, the first p-type nickel oxide semiconductor layer may be stacked in a recessed portion of a trench structure formed on the surface of the n-type gallium oxide semiconductor layer on the side where the electrode layer is stacked, for example.

[0112] Second p-type nickel oxide semiconductor layer

[0113] The semiconductor device disclosed herein may include a plurality of second p-type nickel oxide semiconductor layers spaced apart from one another in a direction extending from a central region toward the peripheral region in a peripheral region on the side of the n-type gallium oxide semiconductor layer on which the first p-type nickel oxide semiconductor layer is stacked. These plurality of second p-type nickel oxide semiconductor layers can function together with the first p-type nickel oxide semiconductor layer as a peripheral voltage-resistant structure.

[0114] The acceptor density in the second p-type nickel oxide semiconductor layer may be the same as the acceptor density in the first p-type nickel oxide semiconductor layer.

[0115] The width of the second p-type nickel oxide semiconductor layer can be, for example, 1.0 μm to 10.0 μm. In addition, the “width” refers to the maximum width.

[0116] The width of the second p-type nickel oxide semiconductor layer may be greater than 1.0 μm, greater than 2.0 μm, greater than 3.0 μm, or greater than 4.0 μm, and may be less than 10.0 μm, less than 9.0 μm, less than 80.0 μm, or less than 7.0 μm.

[0117] The spacing between adjacent second p-type nickel oxide semiconductor layers and / or between adjacent first and second p-type nickel oxide semiconductor layers can be, for example, 0.5 μm to 5.0 μm. Furthermore, "spacing" refers to the shortest distance between adjacent p-type nickel oxide semiconductor layers.

[0118] The interval may be 0.5 μm or more, 1.0 μm or more, 1.5 μm or more, or 2.0 μm or more, and may be 5.0 μm or less, 4.5 μm or less, 4.0 μm or less, or 3.5 μm or less.

[0119] Furthermore, the second p-type nickel oxide semiconductor layer may be stacked in a recessed portion of a trench structure formed on the surface of the n-type gallium oxide semiconductor layer on the side where the electrode layer is stacked, for example.

[0120] Trench Structure

[0121] The n-type gallium oxide semiconductor layer may have multiple trench structures on the side where the first p-type nickel oxide semiconductor layer and the plurality of second p-type nickel oxide semiconductor layers are stacked. The first p-type nickel oxide semiconductor layer and the plurality of second p-type nickel oxide semiconductor layers may be stacked in recessed portions of the trench structures.

[0122] The trench structure can be formed, for example, by etching an n-type gallium oxide semiconductor layer. During etching, a mask can be applied to the portions of the n-type gallium oxide semiconductor layer's surface that will become the convex portions of the trench structure. After etching, the mask is removed. A p-type nickel oxide semiconductor layer is then deposited on the surface of the n-type gallium oxide semiconductor layer, for example, using physical vapor deposition. Finally, the p-type nickel oxide semiconductor layer stacked within the concave portions of the trench structure remains, while the p-type nickel oxide semiconductor layer stacked on the convex portions of the trench structure is removed. This allows a structure in which the first and second p-type nickel oxide semiconductor layers are stacked within the concave portions of the trench structure.

[0123] Semiconductor device manufacturing method

[0124] The method for manufacturing a semiconductor device disclosed herein includes reducing the donor density by ion irradiation or heating in an oxygen atmosphere, thereby forming a peripheral region of an n-type gallium oxide semiconductor layer.

[0125] <Ion irradiation>

[0126] The method for manufacturing a semiconductor device disclosed herein includes reducing donor density by ion irradiation, thereby forming a peripheral region of an n-type gallium oxide semiconductor layer.

[0127] In the method for manufacturing a semiconductor device of the present disclosure, the donor density in a portion of a precursor of an n-type gallium oxide semiconductor layer, for example, a gallium oxide layer having a predetermined donor density, is reduced by ion irradiation.

[0128] In ion irradiation, ions of an acceptor element, hydrogen, or helium can be irradiated. Examples of the acceptor element include Mg, N, and Ga.

[0129] When hydrogen or helium is irradiated during ion irradiation, the donor can be reduced to a deeper region of the n-type gallium oxide semiconductor layer.

[0130] Although annealing of the n-type gallium oxide semiconductor layer can be performed after ion irradiation, it is preferably not performed to improve productivity. Furthermore, "annealing" refers to, for example, a heat treatment in an inert gas atmosphere. The heat treatment temperature of "annealing" is, for example, 800°C or higher.

[0131] <Heating in Oxygen Atmosphere>

[0132] The method for manufacturing a semiconductor device disclosed herein includes forming a peripheral region of an n-type gallium oxide semiconductor layer by heating in an oxygen atmosphere.

[0133] In the method for manufacturing a semiconductor device disclosed herein, the donor density can be reduced by heating in an oxygen atmosphere. The principle is believed to be that defects that compensate for the donors are generated on the surface of the gallium oxide layer, thereby reducing the donor density. However, the present invention is not limited to this.

[0134] In the semiconductor device manufacturing method disclosed herein, a peripheral region of an n-type gallium oxide semiconductor layer is formed by heating a precursor of the n-type gallium oxide semiconductor layer, for example, a gallium oxide layer having a predetermined donor density, in an oxygen atmosphere. The central region of the n-type gallium oxide semiconductor layer has a higher donor density than the peripheral region. However, the donor density can be reduced only in the peripheral region by, for example, masking the surface of the portion of the n-type gallium oxide semiconductor layer precursor that should be the central region.

[0135] "Under an oxygen atmosphere" refers to an atmosphere containing oxygen, and may be, for example, an air atmosphere. The oxygen concentration in the oxygen atmosphere is not particularly limited; for example, the volume ratio of oxygen to the total atmosphere may be 5.0% to 40.0%. The volume ratio of oxygen may be 5.0% or greater, 10.0% or greater, 15.0% or greater, or 20.0% or greater, and may be 40.0% or less, 35.0% or less, 30.0% or less, or 25.0% or less.

[0136] The heating temperature is not particularly limited as long as it is a temperature high enough to reduce the donor density of the gallium oxide layer.

[0137] The heating temperature may be, for example, 600° C. to 900° C. The heating temperature may be 600° C. or higher, 650° C. or higher, 675° C. or higher, or 700° C. or higher, and may be 900° C. or lower, 850° C. or lower, 800° C. or lower, or 750° C. or lower.

[0138] The heating may be performed before or after forming the first or second p-type nickel oxide semiconductor layer on the n-type gallium oxide semiconductor layer. When the temperature is high enough for nickel oxide to decompose, heating is preferably performed before forming nickel oxide.

[0139] Examples 1 to 6 and Comparative Examples 1 to 3

[0140] <Comparative Example 1>

[0141] When the donor density Nd is 1.2×10 16 cm -3 A Pt electrode layer is formed on the n-type gallium oxide semiconductor layer to serve as a Schottky diode. +An n-type gallium oxide semiconductor substrate (thickness 650 μm) was used, but this is omitted in the figure. This is used as the semiconductor device of Comparative Example 1. The thickness of the n-type gallium oxide semiconductor layer is 10 μm.

[0142] <Comparative Example 2>

[0143] In the end of the Schottky diode, in addition to the guard ring (GR), an effective acceptor density Na of 1.0×10 19 cm -3 A semiconductor device of Comparative Example 2 was produced in the same manner as Comparative Example 1 except for the p-type nickel oxide semiconductor layer.

[0144] Specifically, the semiconductor device 3 of Comparative Example 2 has the following Figure 4 The structure shown.

[0145] like Figure 4 As shown, the semiconductor device 3 of Comparative Example 2 includes a first electrode layer 20 stacked on one surface of an n-type gallium oxide semiconductor layer 10. The first electrode layer 20 forms a Schottky junction with the n-type gallium oxide semiconductor layer 10. Furthermore, the semiconductor device 3 of Comparative Example 2 includes a second electrode layer 30 stacked on the other surface of the n-type gallium oxide semiconductor layer 10. The second electrode layer 30 forms an ohmic junction with the n-type gallium oxide semiconductor layer 10.

[0146] exist Figure 4 In the embodiment of the present invention, the semiconductor device 3 of Comparative Example 2 includes a guard ring 60 partially disposed between the n-type gallium oxide semiconductor layer 10 and the first electrode layer 20. The guard ring layer is a p-type nickel oxide semiconductor layer.

[0147] <Comparative Example 3>

[0148] In the end of the Schottky diode, in addition to forming a plurality of effective acceptor density Na of 1.0×10 19 cm -3 A semiconductor device according to Comparative Example 3 was fabricated in the same manner as Comparative Example 1, except that a field limiting ring (FLR) was formed by adding a p-type nickel oxide semiconductor layer. Here, the width of the p-type nickel oxide semiconductor layer was 2.5 μm, and the distance between adjacent p-type nickel oxide semiconductor layers was 5.0 μm.

[0149] Specifically, the semiconductor device 4 of Comparative Example 3 has the following Figure 5 The structure shown.

[0150] <Example 1>

[0151] The semiconductor device of Example 1 was fabricated in the same manner as in Comparative Example 3, except that the donor density Nd in the peripheral region of the n-type gallium oxide semiconductor layer was reduced. Consequently, the donor density Nd of the portion of the n-type gallium oxide semiconductor layer surrounding the outer peripheral edge portion of the p-type nickel oxide semiconductor layer sandwiched between the electrode layer and the n-type gallium oxide semiconductor layer on the peripheral region side was lower than the donor density Nd of the portion of the n-type gallium oxide semiconductor layer surrounding the other portions of the p-type nickel oxide semiconductor layer.

[0152] In addition, in the semiconductor device of Example 1, the donor density in the central region is 1.2×10 16 cm -3 , the effective donor density in the surrounding area is 0.0cm -3 .

[0153] The semiconductor device 5 of the first embodiment has the following features: Figure 6 Here, in the semiconductor device 5 of Example 1, the ratio x / t of the width x of the central portion of the p-type nickel oxide semiconductor layer sandwiched between the electrode layer and the n-type gallium oxide semiconductor layer to the thickness t of the n-type gallium oxide semiconductor layer 10 is 1.50.

[0154] <Example 2>

[0155] In addition to making the donor density in the peripheral area 1.0×10 15 cm -3 The semiconductor device of Example 2 was manufactured in the same manner as in Example 1 except for the above.

[0156] <Example 3>

[0157] In addition to making the donor density in the peripheral area 5.0×10 15 cm -3 The semiconductor device of Example 3 was manufactured in the same manner as in Example 1 except for the above.

[0158] <Example 4>

[0159] A semiconductor device of Example 4 was manufactured in the same manner as in Example 1 except that x / t was changed to 0.8.

[0160] <Example 5>

[0161] A semiconductor device of Example 5 was manufactured in the same manner as in Example 1 except that x / t was changed to 0.53.

[0162] <Example 6>

[0163] A semiconductor device of Example 5 was manufactured in the same manner as in Example 1 except that x / t was set to 0.50.

[0164] <Withstand voltage test>

[0165] A voltage was applied in the forward direction to the semiconductor device of each example, and the voltage at which dielectric breakdown occurred was measured.

[0166] <Resistivity Measurement Test>

[0167] The resistivity of the semiconductor device of each example was measured.

[0168] <Results>

[0169] Table 1 shows the structure of the semiconductor device of each example, and the results of the withstand voltage test and the resistivity measurement test.

[0170]

Table 1

[0171]

[0172] As shown in Table 1, in Comparative Example 1 which does not have a peripheral withstand voltage structure, dielectric breakdown occurs at the end of the electrode layer at approximately 78 V.

[0173] Furthermore, in Comparative Examples 2 and 3, which have a peripheral voltage-resistant structure but have no difference in donor density between the central region and the peripheral region, the voltage resistance is higher than that of Comparative Example 1 (694 V and 844 V, respectively).

[0174] In Examples 1 to 6 having a peripheral voltage-resistant structure and a peripheral region with a lower donor density than a central region, the voltage resistance is above 1200 V, and in particular, above 1500 V in Examples 1, 2, and 4 to 6, which is much higher than that in Comparative Examples 1 to 3.

[0175] In Examples 1 to 5 where x / t is greater than 0.5, the resistivity is 16.0 mΩcm. 2 , maintaining the same level as Comparative Example 1. On the other hand, in Example 6 where x / t is 0.5, the resistivity is 16.1 mΩcm 2 , which is regarded as an increase in resistivity.

[0176] Although not described as an example, when x / t was further reduced, a withstand voltage far higher than that of Comparative Examples 1 to 3 was obtained, but it was considered that the resistivity further increased.

[0177] Examples 7 and 8, and Comparative Example 4

[0178] <Example 7>

[0179] The semiconductor device of Example 7 was produced as follows.

[0180] At a donor density of 1.2×10 16 cm -3A metal mask was formed in the center of the gallium oxide layer, and ion implantation using Mg ions was performed only in the peripheral portion without performing the subsequent annealing process.

[0181] Here, at 140 keV and a dose of 5 × 10 14 cm -2 By this ion implantation, ion implantation defects are formed at a depth of 500 nm from the surface. As a result, Figure 7 As shown in the figure, the donor density is reduced and the material becomes semi-insulating. Figure 7 As shown, the depth of the region where the donor density is reduced is 0.5 μm from the surface of the gallium oxide layer.

[0182] Furthermore, the semiconductor device of Example 7 has Figure 6 The structure shown is the same structure.

[0183] When the semiconductor device of Example 7 was subjected to a withstand voltage test, the dielectric breakdown voltage was increased to 970V.

[0184] <Example 8>

[0185] The semiconductor device of Example 8 was produced as follows.

[0186] At a donor density of 1.2×10 16 cm -3 A metal mask was formed in the center of the gallium oxide layer, and heat treatment was performed at 700°C in an air atmosphere for 10 minutes. Figure 8 As shown in Figure 2, a decrease in the donor density is observed on the surface of the gallium oxide layer. Figure 8 As shown, the depth of the region where the donor density is reduced is 1.5 μm to 2.0 μm.

[0187] The gallium oxide layer thus obtained is formed into Figure 6 When the semiconductor device shown is subjected to a withstand voltage test, the insulation breakdown voltage increases to 1070V.

[0188] <Comparative Example 4>

[0189] A semiconductor device of Comparative Example 4 was produced as follows.

[0190] At a donor density of 1.2×10 16 cm -3 The gallium oxide layer is formed with a thickness of 100 nm and an acceptor density of 1-2×10 20 cm -3 The NiO layer acts as a pn diode.

[0191] and Figure 5Similarly to the example shown, in the peripheral region 13 of the semiconductor device 2 of Comparative Example 4, NiO layers (second p-type nickel oxide semiconductor layers) with a width of 2.5 μm were arranged at intervals of 5.0 μm to form a peripheral withstand voltage structure. Ni was formed on the NiO layer as an ohmic electrode.

[0192] In this semiconductor device 2 , the donor density of the peripheral voltage-resistant structure formed in the peripheral region 13 was not reduced, and therefore, dielectric breakdown occurred at 800 V as a result of the voltage resistance test.

Claims

1. A semiconductor device comprising: An n-type gallium oxide semiconductor layer having a central region and a peripheral region having a lower donor density than the central region; an electrode layer stacked on the n-type gallium oxide semiconductor layer and forming a Schottky junction with the n-type gallium oxide semiconductor layer in the central region when viewed from the stacking direction; as well as The first p-type nickel oxide semiconductor layer is stacked on the n-type gallium oxide semiconductor layer in a manner of being partially arranged between the n-type gallium oxide semiconductor layer and the electrode layer, and when viewed from the stacking direction, the outer peripheral end portion on the peripheral region side is located in the peripheral region, Here, when viewed from the stacking direction, the first p-type nickel oxide semiconductor layer is arranged across the central region and the peripheral region.

2. The semiconductor device according to claim 1, wherein The donor density in the peripheral region is 5.0×10 15 cm -3 the following.

3. The semiconductor device according to claim 1 or 2, wherein: The donor density in the central region is 1.0×10 16 cm -3 above.

4. The semiconductor device according to claim 1, wherein When the thickness of the central region of the n-type gallium oxide semiconductor layer is t and the width of the portion of the first p-type nickel oxide semiconductor layer located in the central region is x, x / t>0.

50.

5. The semiconductor device according to claim 1 or 2, wherein The donor is Sn or Si.

6. The semiconductor device according to claim 1 or 2, wherein The peripheral region is doped with acceptors, so that the donor density is lower than that of the central region.

7. The semiconductor device according to claim 6, wherein The acceptor is N or Mg.

8. The semiconductor device according to claim 1 or 2, wherein In the peripheral region on the side of the n-type gallium oxide semiconductor layer on which the first p-type nickel oxide semiconductor layer is stacked, a plurality of second p-type nickel oxide semiconductor layers are provided spaced apart from each other in a direction from the central region toward the peripheral region.

9. The semiconductor device according to claim 8, wherein The n-type gallium oxide semiconductor layer has a plurality of trench structures on a side where the first p-type nickel oxide semiconductor layer and the plurality of second p-type nickel oxide semiconductor layers are stacked. The first p-type nickel oxide semiconductor layer and the plurality of second p-type nickel oxide semiconductor layers are respectively stacked in the concave portions of the trench structure.

10. The semiconductor device according to claim 1 or 2, wherein The semiconductor device is a pn diode, a JBS diode, a metal oxide semiconductor field effect transistor, or a junction field effect transistor.

11. A method for manufacturing a semiconductor device according to any one of claims 1 to 10, wherein: The method includes reducing the donor density by ion irradiation or heating in an oxygen atmosphere, thereby forming the peripheral region of the n-type gallium oxide semiconductor layer.

12. The method according to claim 11, wherein In the ion irradiation, ions of an acceptor element, hydrogen, or helium are irradiated.

13. The method according to claim 11 or 12, wherein: After the ion irradiation, an annealing process is performed on the n-type gallium oxide semiconductor layer.

14. The method according to claim 11 or 12, wherein: After the ion irradiation, the n-type gallium oxide semiconductor layer is not annealed.

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