A control method for a bridge circuit and a dc / ac conversion circuit in which switches are connected in series

Abstract

The present application relates to the field of power electronics, and aims to provide a switching series bridge circuit and a control method of DC / AC conversion circuit. In the switching series bridge circuit, an active clamp circuit is connected in parallel with each main switch, and the common end of the bridge arm outputs an output current. When the amplitude of the output current is greater than a preset threshold, the control method controls all auxiliary switches of the first bridge arm to be turned on when the main switch of the second bridge arm is turned on, and the clamp capacitor discharges when the sum of the clamp capacitor voltages exceeds the input voltage, thereby reducing the fluctuation of the clamp capacitor voltage in the first bridge arm. The control method can greatly reduce the requirement for the capacitance value of the clamp capacitor under heavy load conditions, effectively improve the power density of the overall system, and combine the heavy load control method with the dead zone discharge voltage balancing control method to reduce the fluctuation of the clamp capacitor voltage and balance the voltage between the clamp capacitors.

Description

Technical Field

[0001] This invention belongs to the field of power electronics technology, specifically relating to a control method for a bridge circuit with switches connected in series and a DC / AC conversion circuit. Background Technology

[0002] Because the withstand voltage of a single power switch is limited, multiple power switches are usually connected in series in medium and high voltage applications. To ensure reliable operation of series-connected devices, voltage balance among them is crucial. The main causes of voltage imbalance in series-connected devices include differences in dynamic and static parameters and differences in external circuit conditions. Existing solutions to this problem mainly fall into three categories: passive buffer circuits, gate drive compensation circuits, and active voltage clamping circuits. Active voltage clamping circuits absorb voltage spikes generated when the switching of series-connected power devices is asynchronous by connecting a circuit consisting of a capacitor, resistor, semiconductor diode, semiconductor switch, or a combination thereof in parallel across each power device. This clamps the voltage across the power device to the capacitor voltage, achieving voltage balance through equalization control of the capacitor voltage. Compared to gate drive compensation circuits and active voltage clamping circuits, active voltage clamping circuits offer advantages such as simple structure, high reliability, and low losses.

[0003] Adding an auxiliary switch to the clamping circuit allows for selective control of the auxiliary switch's conduction time for a preset duration within the dead time, based on the voltage ranking of the clamping capacitors. This utilizes the negative bridge arm current to discharge the clamping capacitors, achieving voltage equalization. This method enables energy feedback and further reduces overall system losses. However, when the output cycle is much longer than the switching cycle, the clamping capacitors will remain charged for a period without discharging. In a power frequency inverter, the clamping capacitors experience charging, discharging, and voltage stabilization phases. During the charging phase, the clamping capacitor voltage continuously rises, and the voltage fluctuation increases with the output current. Therefore, to ensure the voltage fluctuation remains within a certain range, the required clamping capacitor capacitance will significantly increase under heavy load conditions, drastically reducing the overall system power density. Furthermore, increased voltage fluctuations in the clamping capacitors also increase the voltage imbalance between power devices. Summary of the Invention

[0004] To overcome the shortcomings of the prior art, the present invention provides a control method for a bridge circuit with switches connected in series and a DC / AC conversion circuit.

[0005] According to an embodiment of the present invention, a control method for a bridge circuit with series-connected switches is provided. The bridge circuit includes a first bridge arm and a second bridge arm coupled to a common terminal. The first bridge arm includes a plurality of first main switches coupled in series, wherein each first main switch is connected in parallel with a first auxiliary module. Each first auxiliary module includes a first clamping capacitor and a first auxiliary switch transistor. The second bridge arm includes at least one second main switch. The first bridge arm receives a first main switch signal to control the plurality of first main switches, and the second bridge arm receives a second main switch signal for the at least one second main switch. Each switching cycle includes a first time period, a second time period, a first dead time, and a second dead time. The first time period is when the second main switch is turned on and the first dead time is... The control method includes: a first time period during which a main switch is off, and a second time period during which a first main switch is on and a second main switch is off, wherein the first main switch signal and the second main switch signal include a first dead time and a second dead time. The control method includes: during the first time period, controlling the plurality of first main switches to be off, the at least one second main switch to be on, and all of the plurality of first auxiliary switches to be on for a first preset time, wherein during the first preset time, when the sum of the voltages of the first clamping capacitors in all the first auxiliary modules exceeds the bus voltage, the voltages of the first clamping capacitors in all the first auxiliary modules are discharged; and during the second time period, controlling the plurality of first main switches to be on, the at least one second main switch to be off, and all of the plurality of first auxiliary switches to be off.

[0006] Furthermore, the bridge circuit outputs an output current and an output voltage at the common terminal. When the amplitude of the output current is greater than a preset threshold, the bridge circuit is in a heavy-load operating state, and the control method is used in the heavy-load operating state.

[0007] Furthermore, the first preset duration is less than the oscillation period between the parasitic inductance in the first bridge arm and the second bridge arm circuit and the equivalent capacitance of all the first clamping capacitors in the first bridge arm connected in series.

[0008] Furthermore, the second bridge arm includes a plurality of second main switches connected in series between its first and second ends. Each second main switch is connected in parallel with a second auxiliary module. Each second auxiliary module includes a second clamping capacitor and a second auxiliary switch transistor. The control method further includes: controlling the plurality of second main switches to be turned on during a first time period; controlling all second auxiliary switch transistors to be turned off during a first preset time period; and controlling the plurality of second main switches to be turned off during a second time period, and controlling all second auxiliary switch transistors to be turned on for a second preset time period. During the second preset time period, when the sum of the voltages of the second clamping capacitors in all the second auxiliary modules exceeds the bus voltage, all the second clamping capacitors in the second auxiliary modules discharge.

[0009] Furthermore, the second preset duration is less than the oscillation period between the parasitic inductance in the first and second bridge arm circuits and the equivalent capacitance of all the second clamping capacitors in the second bridge arm connected in series.

[0010] According to another embodiment of the present invention, a control method for a bridge circuit with series-connected switches is provided. The bridge circuit includes a first bridge arm and a second bridge arm coupled to a common terminal. The first bridge arm includes a plurality of first main switches coupled in series, wherein each first main switch is connected in parallel with a first auxiliary module. Each first auxiliary module includes a first clamping capacitor and a first auxiliary switch transistor. The second bridge arm includes at least one second main switch. The first bridge arm receives a first main switch signal to control the plurality of first main switches, and the second bridge arm receives a second main switch signal for the at least one second main switch. Each switching cycle includes a first time period, a second time period, a first dead time, and a second dead time. The first time period is the time period during which the second main switch is on and the first main switch is off. The second time period is the time period during which the first main switch is on and the second main switch is off. The main switch signal and the second main switch signal include a first dead time and a second dead time. The common terminal outputs an output current. The control method includes a heavy load control method and a voltage equalization control method. The heavy load control method includes: controlling all first auxiliary switches in the first bridge arm to be turned on for a first preset duration within a first time period; when the sum of the voltages of the first clamping capacitors in all the first auxiliary modules exceeds the bus voltage, the first clamping capacitors discharge; the first preset duration is less than or equal to the first time period. The voltage equalization control method includes: controlling the first auxiliary switch corresponding to the first clamping capacitor with the largest voltage or the first k clamping capacitors in the first bridge arm to be turned on for a first auxiliary turn-on duration within the first dead time period; the first k clamping capacitors discharge through freewheeling current; the first auxiliary turn-on duration is less than or equal to the first dead time; where k is a natural number greater than or equal to 2.

[0011] Furthermore, the bridge circuit outputs an output current and an output voltage at the common terminal. When the output current is greater than a first preset threshold, the bridge circuit adopts a heavy load control method. When the output current is less than a second preset threshold, the bridge circuit adopts a voltage equalization control method.

[0012] Furthermore, the second bridge arm includes multiple second main switches connected in series between its first and second ends. Each second main switch is connected in parallel with a second auxiliary module. Each second auxiliary module includes a second clamping capacitor and a second auxiliary switch. The control method further includes: the overload control method further includes: during a second time period, controlling all second auxiliary switches in the second bridge arm to be turned on for a second preset duration. When the sum of the voltages of the second clamping capacitors in all the second auxiliary modules exceeds the bus voltage, the second clamping capacitors discharge. The second preset duration is less than or equal to the second time period. The voltage equalization control method further includes: during a second dead time period, controlling the second auxiliary switch corresponding to the second clamping capacitor with the largest voltage or the first q in the second bridge arm to be turned on for a second auxiliary turn-on duration. The second clamping capacitors in the first q in the second bridge arm discharge through freewheeling current to compensate for the imbalance between the voltages of the second clamping capacitors. The second auxiliary turn-on duration is less than or equal to the second dead time, where q is a natural number greater than or equal to 2.

[0013] Furthermore, the bridge circuit outputs an output current and an output voltage at the common terminal. When the output current is less than a third preset threshold, the bridge circuit adopts a heavy load control method. When the output current is greater than a fourth preset threshold, the bridge circuit adopts a voltage equalization control method.

[0014] According to another embodiment of the present invention, a control method for a DC / AC converter circuit with series-connected switches is provided. The DC / AC converter circuit includes: a bridge circuit with series-connected switches, a filter device, and an output load. The bridge circuit with series-connected switches includes a first bridge arm and a second bridge arm coupled to a common terminal. The first bridge arm includes a plurality of first main switches coupled in series, wherein each first main switch is connected in parallel with a first auxiliary module. Each first auxiliary module includes a first clamping capacitor and a first auxiliary switching transistor. The second bridge arm includes at least one second main switch. The first bridge arm receives a first main switch signal for the plurality of first main switches, and the second bridge arm receives a second main switch signal for the at least one second main switch. The common terminal outputs an output current and an output voltage. A switching cycle of the DC / AC converter circuit includes a first time period, a second time period, a first dead time, and a second dead time. The first time period is the time period during which the second main switch is on and the first main switch is off, and the second time period is the time period during which the first main switch is on and the second main switch is off. The control method includes: within a time period, controlling the plurality of first main switches to turn off, the at least one second main switch to turn on, controlling all first auxiliary switches in the first bridge arm to turn on for a first preset duration, discharging the first clamping capacitor in the first bridge arm, and controlling the DC / AC conversion circuit to enter normal inverter / rectification operation; within the first dead time, controlling the plurality of first main switches to turn off, the at least one second main switch to turn off, and controlling the first auxiliary switch in at least one first auxiliary module in the first bridge arm to turn on for a first auxiliary turn-on duration; within a second time period, controlling the plurality of first main switches to turn on, the at least one second main switch to turn off, and controlling all first auxiliary switches to turn off, and controlling the DC / AC conversion circuit to enter normal inverter / rectification operation; and within the second dead time, controlling the plurality of first main switches to turn off, the at least one second main switch to turn off, and controlling all first auxiliary switches to turn off.

[0015] Furthermore, wherein the bridge circuit outputs an output current and an output voltage at the common terminal, the control method further includes: detecting the output current; within a first time period, if the output current is greater than a first preset threshold, controlling all first auxiliary switches in the first bridge arm to be turned on for a first preset duration, and discharging the first clamping capacitor in the first bridge arm; if the output current is less than the first preset threshold, controlling all first auxiliary switches to be turned off, and controlling the DC / AC conversion circuit to enter normal inverter / rectification operation state; within a first dead time period, if the output current is greater than a second preset threshold, controlling all first auxiliary switches to be turned off; if the output current is less than the second preset threshold, controlling at least one first auxiliary switch in the first bridge arm to be turned on for a first auxiliary turn-on duration, and discharging the first clamping capacitor in the at least one first auxiliary module by the freewheeling current.

[0016] Furthermore, the first dead time is the dead time before the rising edge of the first main switch signal, and the second dead time is the dead time before the rising edge of the second main switch signal.

[0017] Furthermore, the second bridge arm includes multiple second main switches connected in series between its first and second ends. Each second main switch is connected in parallel with a second auxiliary module. Each second auxiliary module includes a second clamping capacitor and a second auxiliary switch transistor. The control method further includes: during the second time period, controlling all second auxiliary switch transistors in the second bridge arm to turn on for a second preset duration, discharging the clamping capacitors in the second bridge arm, and controlling the DC / AC conversion circuit to enter normal inverter / rectifier operation; during the second dead time, controlling at least one second auxiliary switch transistor in a second auxiliary module in the second bridge arm to turn on for a second auxiliary turn-on duration.

[0018] Furthermore, the control method further includes: detecting the output current; during the second time period, if the output current is less than a third preset threshold, controlling all second auxiliary switches in the second bridge arm to be turned on for a second preset duration, and discharging the clamping capacitors in the second bridge arm; if the output current is greater than the third preset threshold, controlling all second auxiliary switches to be turned off, and controlling the DC / AC conversion circuit to enter normal inverter / rectification operation state; during the second dead time, if the output current is greater than the fourth preset threshold, controlling at least one second auxiliary switch in the second bridge arm to be turned on for a second auxiliary turn-on duration, and discharging the second clamping capacitors in the at least one second auxiliary module by the freewheeling current; if the output current is less than the fourth preset threshold, controlling the plurality of first main switches to be turned off and the plurality of second main switches to be turned off, and controlling all first auxiliary switches and second auxiliary switches to be turned off.

[0019] Furthermore, the first preset duration is less than the oscillation period between the parasitic inductance in the first bridge arm and the second bridge arm circuit and the equivalent capacitance of all the first clamping capacitors in the first bridge arm connected in series; the second preset duration is less than the oscillation period between the parasitic inductance in the first bridge arm and the second bridge arm circuit and the equivalent capacitance of all the second clamping capacitors in the second bridge arm connected in series.

[0020] Furthermore, the control method further includes: sampling the voltage across all the first clamping capacitors, sorting the voltages across the first clamping capacitors using a control circuit, and when a certain voltage sampling signal is the largest or ranks among the top k of all the first voltage sampling signals, controlling the first auxiliary switch corresponding to the first voltage sampling signal to turn on for the first auxiliary turn-on duration during a first dead time, and controlling the first auxiliary switch corresponding to the remaining first voltage sampling signals to turn off, where k is a natural number greater than or equal to 2; sampling the voltage across all the second clamping capacitors, sorting the voltages across the second clamping capacitors using a control circuit, and when a certain voltage sampling signal is the largest or ranks among the top j of all the second voltage sampling signals, controlling the second auxiliary switch corresponding to the second voltage sampling signal to turn on for the second auxiliary turn-on duration during a second dead time, and controlling the second auxiliary switch corresponding to the remaining second voltage sampling signals to turn off, where j is a natural number greater than or equal to 2, and k and j may be equal or unequal.

[0021] Furthermore, the DC / AC conversion circuit further includes a third bridge arm and a fourth bridge arm. The main switching signals of the third bridge arm and the fourth bridge arm are 180 degrees out of phase with the main switching signals of the first bridge arm and the second bridge arm. The ordering of the clamping capacitors of the third bridge arm and the control of the auxiliary switching transistors are independent of the first bridge arm and the second bridge arm.

[0022] Furthermore, the DC / AC conversion circuit further includes a third bridge arm and a fourth bridge arm, a fifth bridge arm and a sixth bridge arm, wherein the main switching signals of the third bridge arm and the fourth bridge arm, the fifth bridge arm and the sixth bridge arm, the first bridge arm and the second bridge arm are 120 degrees out of phase, and the ordering of the clamping capacitors of the third bridge arm and the fourth bridge arm, the fifth bridge arm and the sixth bridge arm and the control of the auxiliary switching transistors are independent of the first bridge arm and the second bridge arm.

[0023] Compared with existing technical solutions, the beneficial effects of the present invention are:

[0024] The heavy-load control method of this invention utilizes the principle of turning on all auxiliary switches of the bridge arm when it is turned on, feeding the energy of the clamping capacitor back to the DC side without affecting the working state of the bridge circuit itself. This method significantly reduces the capacitance requirement of the clamping capacitor under heavy-load conditions, thus effectively improving the overall system power density. Furthermore, the auxiliary switches in the clamping circuit can achieve near-zero voltage turn-on, resulting in extremely low power loss due to voltage fluctuations in the clamping capacitor. Simultaneously, combining the heavy-load control method with a dead-time discharge voltage equalization control method reduces voltage fluctuations in the clamping capacitor and achieves voltage balance between the clamping capacitors. Attached Figure Description

[0025] Figure 1 This is a block diagram of a half-bridge circuit 1000 with switches connected in series according to an embodiment of the present invention;

[0026] Figure 2 According to embodiments of the present invention, Figure 1 The circuit schematic of the first bridge arm 10 and the second bridge arm 20 is shown.

[0027] Figure 3 A flowchart 2000 shows a method for controlling the overload of the first bridge arm 10 when the second bridge arm 20 includes at least one second main switch, which is a bridge circuit with switches connected in series according to an embodiment of the present invention.

[0028] Figure 4 A flowchart 3000 shows a heavy-load control method for the first bridge arm 10 and the second bridge arm 20 in a bridge circuit with series switches according to an embodiment of the present invention, where both the first bridge arm 10 and the second bridge arm 20 contain multiple main switching transistors.

[0029] Figure 5 A flowchart 4000 shows a control method for a bridge circuit with switches connected in series according to an embodiment of the present invention.

[0030] Figure 6For a bridge circuit with switches connected in series according to an embodiment of the present invention, when the second bridge arm includes only a second main switch, the gate drive waveform diagram and its circuit mode diagram of the first bridge arm 10 under heavy load control are shown.

[0031] Figure 7 For a bridge circuit with switches connected in series according to an embodiment of the present invention, when both the first bridge arm and the second bridge arm include multiple main switches, the gate drive waveform diagram of the heavy-load control of the first bridge arm 10 and the second bridge arm 20 is shown.

[0032] Figure 8 According to embodiments of the present invention, Figure 7 The waveform diagrams shown are circuit mode diagrams of the first bridge arm 10 and the second bridge arm 20 during time periods t2~t3 and t6~t7.

[0033] Figure 9 The schematic diagrams are for implementing half-bridge, full-bridge, and three-phase DC / AC conversion circuits with multiple switches connected in series according to embodiments of the present invention.

[0034] Figure 10 According to embodiments of the present invention, Figure 9 Flowchart 5000 shows the overload control and voltage equalization control methods for the DC / AC converter circuit.

[0035] Figure 11 According to embodiments of the present invention, Figure 9 The diagram shows the gate drive waveforms for heavy-load control and voltage equalization control of the half-bridge DC / AC converter circuit.

[0036] Figure 12 According to embodiments of the present invention, Figure 11 The waveform diagram shown shows t 10 ~t 11 Circuit mode diagrams of voltage equalization control of the first bridge arm 10 and the second bridge arm 20 within time t4 and time t5;

[0037] Figure 13 According to embodiments of the present invention, Figure 9 The diagram shows the steady-state waveforms of the clamping capacitor voltages of the first bridge arm 10 and the second bridge arm 20 in the half-bridge DC / AC converter circuit under heavy load control and voltage equalization control.

[0038] Figure 14 A block diagram 7000 illustrates a method for heavy-load control and voltage equalization control of a DC / AC converter circuit with switches connected in series according to an embodiment of the present invention. Detailed Implementation

[0039] To describe the present invention in more detail, the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0040] Figure 1This is a block diagram of a half-bridge circuit 1000 with series-connected switches according to an embodiment of the present invention. The half-bridge circuit 1000 includes a first bridge arm 10, a second bridge arm 20, a voltage sampling circuit 70, and a control circuit 80. The first bridge arm 10 includes a first terminal 101, a second terminal 102, and a control terminal 103. The control terminal 103 is used to receive a first main switch signal g. The second bridge arm 20 includes a first terminal 201, a second terminal 202, and a control terminal 203. The first terminal 201 of the second bridge arm 20 and the second terminal 102 of the first bridge arm 10 are coupled to a common terminal M1. The control terminal 203 of the second bridge arm 20 is used to receive a second main switch signal g'. The half-bridge circuit 1000 outputs an output current i at the common terminal M1. a and an output voltage v r In one embodiment, the output current i a When the load exceeds a certain threshold, the bridge circuit is in a heavy-load operating state.

[0041] In one embodiment, each switching cycle includes a first time period, a second time period, a first dead time, and a second dead time. The first time period is the time when the second main switch is on and the first main switch is off (i.e., the time when the first main switch signal g is low and the second main switch signal g' is high). The second time period is the time when the first main switch is on and the second main switch is off (i.e., the time when the first main switch signal g is high and the second main switch signal g' is low). The first dead time and the second main switch signal g' are separated by a first dead time and a second dead time. The first dead time is the dead time before the rising edge of the first main switch signal g, and the second dead time is the dead time before the rising edge of the second main switch signal g'. In one embodiment, the first main switch signal g and the second main switch signal g' are complementary. The first dead time or the second dead time is not limited to the duration of the dead time, but also includes the moment of the dead time.

[0042] In one embodiment, the structure of the first bridge arm 10 can be as follows: Figure 2 As shown in (a), the first bridge arm 10 includes N main switches S connected in series. 11 ~S 1N N is a natural number greater than or equal to 1, and the first main switch signal g is used to control the N main switches S. 11 ~S 1N Each main switch S 1N Each is connected in parallel with an auxiliary module ARM1N (e.g., main switch S). 11 Parallel auxiliary module ARM11, main switch S 12 Parallel auxiliary modules ARM12), each auxiliary module ARM1N includes a clamping capacitor C.1N and an auxiliary switching transistor S a1N (For example, the auxiliary module ARM11 includes clamping capacitor C) 11 and auxiliary switching transistor S a11 In one embodiment, each auxiliary switch S a1N Includes an anti-parallel diode, and each clamping capacitor C 1N The voltage across the terminals is v c1N (e.g., clamping capacitor C) 11 The voltage across the terminals is v c11 Each auxiliary switch S a1N Receive an auxiliary switch signal g a1N (e.g. auxiliary switch signal g) a11 Used to control auxiliary switching transistor S a11 (Opening and closing). For example... Figure 1 The illustrated embodiment, and in conjunction with Figure 2 In the embodiment shown in (a), the voltage sampling circuit 70 is used to sample the clamping capacitor C. 11 ~C 1N Voltage v across the terminals c11 ~v c1N And output the corresponding voltage sampling signal v c11 '~v cIN The control circuit 80 receives the voltage sampling signal v. c11 '~v cIN ', and according to the voltage sampling signal v c11 '~v c1N 'and the first dead time generates the auxiliary switching signal g' a11 ~g a1N To control the auxiliary switching transistor S respectively a11 ~S a1N .

[0043] In one embodiment, the structure of the second bridge arm 20 can be as follows: Figure 2 As shown in (b), the second bridge arm 20 includes N series-coupled main switches S 21 ~S 2N The second main switch signal g' is used to control the N main switches S 21 ~S 2N Each main switch S 2N Each is connected in parallel with an auxiliary module ARM2N (e.g., main switch S). 21 Parallel auxiliary module ARM21, main switch S 22 Parallel auxiliary modules ARM22), each auxiliary module ARM2N includes a clamping capacitor C. 2N and an auxiliary switching transistor S a2N(For example, the auxiliary module ARM21 includes clamping capacitor C) 21 and auxiliary switching transistor S a21 Each auxiliary switch S a2N Includes an anti-parallel diode, and in one embodiment, each clamping capacitor C 2N The voltage across the terminals is v c2N (e.g., clamping capacitor C) 21 The voltage across the terminals is v c21 Each auxiliary switch S a2N Receive an auxiliary switch signal g a2N (e.g. auxiliary switch signal g) a21 Used to control auxiliary switching transistor S a21 (The on / off state). The voltage sampling circuit 70 samples the clamping capacitor C. 21 ~C 2N Voltage v across the terminals c21 ~v c2N And output the corresponding voltage sampling signal v c21 '~v c2N The control circuit 80 receives the voltage sampling signal v. c21 '~v c2N ', and according to the voltage sampling signal v c21 '~v c2N Generate the auxiliary switching signal g a21 ~g a2N To control the auxiliary switching transistor S respectively a21 ~S a2N .

[0044] Figure 3A flowchart 2000 illustrates a method for controlling the overload of the first bridge arm 10 when the second bridge arm 20 includes at least one second main switch, in a bridge circuit with switches connected in series according to an embodiment of the present invention. The bridge circuit includes a first bridge arm and a second bridge arm coupled to a common terminal. The bridge circuit outputs an output current and an output voltage at the common terminal. When the output current amplitude is greater than a preset threshold, the bridge circuit is in a heavy-load operating state. In the heavy-load operating state, the control method is adopted. The first bridge arm includes multiple first main switches coupled in series, wherein each first main switch is connected in parallel with a first auxiliary module. Each first auxiliary module includes a first clamping capacitor and a first auxiliary switch transistor. The second bridge arm includes at least one second main switch. The first bridge arm receives a first main switch signal to control the multiple first main switches. The second bridge arm receives a second main switch signal for the at least one second main switch. Each switching cycle includes a first time period, a second time period, a first dead time, and a second dead time. The first time period is the time period during which the second main switch is turned on and the first main switch is turned off. The second time period is the time period during which the first main switch is turned on and the second main switch is turned off. The first dead time and the second dead time are between the first main switch signal and the second main switch signal. The control method includes steps S22 to S23.

[0045] Step S22: During a first time period, the plurality of first main switches are turned off, at least one second main switch is turned on, and all of the plurality of first auxiliary switches are turned on for a first preset time. During the first preset time, when the sum of the voltages of the first clamping capacitors in all the first auxiliary modules exceeds the bus voltage, the voltages of the first clamping capacitors in all the first auxiliary modules are discharged, and the energy is fed back to the DC bus. If the first preset time is less than the first time period, the overload control method can feed the energy of the clamping capacitors back to the DC bus under any output current condition. In one embodiment, the first preset time can be further controlled to be less than the oscillation period between the parasitic inductance in the first bridge arm and the second bridge arm circuit and the equivalent capacitance of all the first clamping capacitors in series in the first bridge arm, so as to avoid voltage oscillation on the first clamping capacitors.

[0046] Step S23: During the second time period, control the plurality of first main switches to be turned on, the at least one second main switch to be turned off, and all of the plurality of first auxiliary switches to be turned off.

[0047] In one embodiment of the present invention, the bridge circuit outputs an output current and an output voltage at the common terminal. When the amplitude of the output current exceeds a preset threshold, the bridge circuit is in a heavy-load operating state, and the above-described control method is applied in the heavy-load operating state. In another embodiment of the present invention, the output current can be ignored, the threshold can be ignored, and the above-described control method can be applied directly to the first bridge arm in each switching cycle.

[0048] Figure 4 A flowchart 3000 illustrates a heavy-load control method for a bridge circuit with series-connected switches according to an embodiment of the present invention, where both the first bridge arm 10 and the second bridge arm 20 include multiple main switches. The bridge circuit includes a first bridge arm and a second bridge arm coupled to a common terminal. The first bridge arm includes multiple series-coupled first main switches, each of which is connected in parallel with a first auxiliary module. Each first auxiliary module includes a first clamping capacitor and a first auxiliary switch. The second bridge arm includes multiple second main switches, each of which is connected in parallel with a second auxiliary module. Each second auxiliary module includes a second clamping capacitor and a second auxiliary switch. The first bridge arm receives a first main switch signal to control the multiple first main switches, and the second bridge arm receives a second main switch signal to control the multiple second main switches. Each switching cycle includes a first time period and a second time period. The control method includes steps S31 to S32.

[0049] Step S31: During the first time period, control the plurality of first main switches to turn off, the plurality of second main switches to turn on, and all the plurality of first auxiliary switches to turn on for a first preset time. During the first preset time, control the second auxiliary switches to turn off. When the sum of the voltages of the first clamping capacitors in all the first auxiliary modules exceeds the bus voltage, the voltages of the first clamping capacitors in all the first auxiliary modules discharge and feed energy back to the DC bus.

[0050] Step S32: During the second time period, the plurality of first main switches are turned on, the plurality of second main switches are turned off, and all the plurality of second auxiliary switches are turned on for a second preset duration. During the second preset duration, all the first auxiliary switches are turned off. When the sum of the voltages of the second clamping capacitors in all the second auxiliary modules exceeds the bus voltage, all the second clamping capacitors in the second auxiliary modules discharge and feed energy back to the DC bus. The first preset duration is shorter than the first time period, and the second preset duration is shorter than the second time period. The first preset duration and the second preset duration can be equal or unequal. The overload control method can feed energy from the clamping capacitors back to the DC bus under any output current condition. In one embodiment, the first preset duration (second preset duration) can be further controlled to be less than the oscillation period between the parasitic inductance in the first bridge arm and the second bridge arm circuit and the equivalent capacitance of all the first clamping capacitors in series in the first bridge arm (all the second clamping capacitors in series in the second bridge arm), so as to avoid voltage oscillation on the first clamping capacitors (second clamping capacitors).

[0051] Figure 5 This is a flowchart 4000 of a control method for a bridge circuit with series-connected switches according to an embodiment of the present invention. The bridge circuit includes a first bridge arm and a second bridge arm coupled to a common terminal. The first bridge arm includes a plurality of first main switches coupled in series, wherein each first main switch is connected in parallel with a first auxiliary module. Each first auxiliary module includes a first clamping capacitor and a first auxiliary switch transistor. The second bridge arm includes at least one second main switch. The first bridge arm receives a first main switch signal to control the plurality of first main switches, and the second bridge arm receives a second main switch signal for the at least one second main switch. Each switching cycle includes a first time period, a second time period, a first dead time, and a second dead time. The first time period is the time period during which the second main switch is on and off, and the second time period is the time period during which the first main switch is on and off. A first dead time and a second dead time are included between the first main switch signal and the second main switch signal. The common terminal outputs an output current. The control method includes a heavy-load control method and a voltage equalization control method.

[0052] The heavy load control method includes: controlling all first auxiliary switches in the first bridge arm to be turned on for a first preset duration within a first time period; when the sum of the voltages of the first clamping capacitors in all the first auxiliary modules exceeds the bus voltage, the first clamping capacitors are discharged; the first preset duration is less than or equal to the first time period.

[0053] The voltage equalization control method includes: during the first dead time, controlling the voltage of the first clamping capacitor in the first bridge arm to be the maximum or the first auxiliary switch corresponding to the first clamping capacitor ranked in the top k for a first auxiliary turn-on time, the first clamping capacitor ranked in the top k is discharged through freewheeling current, the first auxiliary turn-on time is less than or equal to the first dead time, and k is a natural number greater than or equal to 2.

[0054] In one embodiment of the present invention, wherein the bridge circuit outputs an output current and an output voltage at the common terminal, it can be configured such that: when the output current is greater than a first preset threshold, the bridge circuit adopts a heavy-load control method; and when the output current is less than a second preset threshold, the bridge circuit adopts a voltage equalization control method. Alternatively, it can be configured such that: the output current is not detected, and the above-mentioned heavy-load control method and voltage equalization control method are used in each switching cycle.

[0055] In other embodiments, a plurality of second main switches are connected in series between the first and second ends of the second bridge arm, each second main switch is connected in parallel with a second auxiliary module, and each second auxiliary module includes a second clamping capacitor and a second auxiliary switching transistor. The control method further includes:

[0056] The heavy-load control method further includes: during the second time period, controlling all second auxiliary switches in the second bridge arm to be turned on for a second preset duration; when the sum of the voltages of the second clamping capacitors in all the second auxiliary modules exceeds the bus voltage, the second clamping capacitors are discharged; the second preset duration is less than or equal to the second time period.

[0057] The voltage equalization control method further includes: during the second dead time, controlling the second auxiliary switch corresponding to the second clamping capacitor with the largest voltage or the first q in the second bridge arm to be turned on for a second auxiliary turn-on duration, the second clamping capacitors with the first q in the second bridge arm are discharged through freewheeling current to compensate for the imbalance between the voltages of the second clamping capacitors, the second auxiliary turn-on duration is less than or equal to the second dead time, and q is a natural number greater than or equal to 2.

[0058] In one embodiment of the present invention, wherein the bridge circuit outputs an output current and an output voltage at the common terminal, and can be configured such that: when the output current is less than a third preset threshold, the bridge circuit adopts a heavy load control method, and when the output current is greater than a fourth preset threshold, the bridge circuit adopts a voltage equalization control method.

[0059] Figure 6 For a bridge circuit with switches connected in series according to an embodiment of the present invention, when the second bridge arm includes only one second main switch, the gate drive waveform diagram and its circuit mode diagram for heavy-load control of the first bridge arm 10 are shown. Figure 6As shown in (a), V dc V is the input voltage of the DC / AC converter circuit. 10 V is the bridge arm voltage of the first bridge arm 10. 20 i is the bridge arm voltage of the second bridge arm, i1 is the bridge arm current of the first bridge arm 10, i a The output current is shown in the figure as i. a The positive direction, i a If the amplitude exceeds a certain threshold, the circuit is in a heavy-load operating state, and the control method described above is used in the heavy-load operating state. s For the switching cycle of each main switch, in such a case Figure 6 In the described embodiment, the first time period is the time during which the second main switch signal g' remains at a high level (t3~t6), and the second time period is the time during which the first main switch signal g remains at a high level (t1~t2). The first time period and the second time period may be equal or unequal. The first main switch signal and the second main switch signal have a first dead time and a second dead time. The first dead time is the dead time before the first main switch signal g changes from a low level to a high level, and the second dead time is the dead time before the second main switch signal g' changes from a low level to a high level. a The pulse turn-on drive signal ga is the auxiliary switch transistor within the first bridge arm 10. The pulse turn-on drive signal ga is high for a period of time within the first time interval, and low for the rest of the time. In... Figure 6 In one embodiment, the pulse turn-on drive signal g a All auxiliary switching transistors within the first bridge arm 10 are allocated. Pulse turn-on drive signal g a The duration of maintaining a high level during the first time period is t. p1 The t p1 Less than the first time period, it can also include the start and end times of the first time period. Figure 6 In the described embodiment, t3 < t4, t5 < t6, and the first dead time equals the second dead time. In other embodiments, t3 = t4, t5 = t6, and t... p1 The value can be adjusted according to the circuit parameters, and the dead time can be set according to the actual needs such as the switching frequency of the circuit.

[0060] Figure 6 (b) is as described in the embodiments of the present invention. Figure 6 (a) shows the circuit mode diagram of the discharge of the first clamping capacitor in the first bridge arm 10 during the first time period in the waveform diagram. Corresponding to... Figure 6(a) During the first time period (t3~t6), in the t4~t5 stage: when t4<t<t5, all the first main switches in the first bridge arm 10 are turned off, and all the main switches S in the second bridge arm 20 are turned on. Since the auxiliary switch tubes S in all the sub-modules SM11~SM1N in the first bridge arm 10 are turned on, a When the circuit is activated, the clamping capacitor C in these sub-modules is connected in parallel with the parasitic capacitance of the corresponding main switch S. When the sum of the voltages across the clamping capacitors exceeds the input voltage V... dc At that time, that is

[0061] v c11 ++v c12 ...+v c1N ≥V dc

[0062] The clamping capacitor in the first bridge arm will naturally discharge to the input side, with a bridge arm discharge current of i1, and will feed energy back to the input side until time t5, when the auxiliary switching transistors S in submodules SM11 to SM1N discharge to the input side. a Turn off. Since the capacitance of the clamping capacitor C is much larger than the parasitic capacitance of the main switch S, the bridge arm discharge current i1 mainly flows through the clamping capacitor C. During this process, the equivalent capacitance of all the first clamping capacitors connected in series in the first bridge arm will interact with the parasitic inductance L in the first and second bridge arm circuits. s An oscillation occurred, with the oscillation period being:

[0063]

[0064] Therefore, preferably, the pulse turn-on drive signal g a The duration t of maintaining a high level during the first time period p1 The value should be less than the oscillation period to avoid oscillation of the first clamping capacitor in the first bridge arm when the first auxiliary switch is turned on. Furthermore, when the auxiliary switch S in the first bridge arm 10... a When the circuit is turned on, the second bridge arm is already turned on, therefore the voltage across each first main switch transistor in the first bridge arm is approximately V. dc / N, therefore the voltage difference between the first clamping capacitor and the first main switch is very small, so the first auxiliary switch can achieve near-zero voltage turn-on, reducing switching losses.

[0065] Figure 7 This is a diagram illustrating the gate drive waveforms for heavy-load control of a bridge circuit with series-connected switches according to an embodiment of the present invention, where both the first and second bridge arms contain multiple main switches. For example... Figure 7 As shown, V dc V is the input voltage of the DC / AC converter circuit. 10 V is the bridge arm voltage of the first bridge arm 10. 20The bridge arm voltage of the second bridge arm 20 is shown in the figure as i. a The positive direction, i a If the amplitude exceeds a certain threshold, the circuit is in a heavy-load operating state. s For the switching cycle of each main switch, in such a case Figure 7 In the described embodiment, the first time period is the time during which the second main switch signal g' remains at a high level (t5~t8), and the second time period is the time during which the first main switch signal g remains at a high level (t1~t4). The first time period and the second time period may be equal or unequal. The first main switch signal and the second main switch signal have a first dead time and a second dead time. The first dead time is the dead time before the first main switch signal g changes from a low level to a high level, and the second dead time is the dead time before the second main switch signal g' changes from a low level to a high level. a The pulse turn-on drive signal g is the auxiliary switch transistor within the first bridge arm 10. a The signal is high for a period of time within the first time interval, and low for the rest of the time; g' a The pulse turn-on drive signal g' is the auxiliary switch transistor within the second bridge arm 20. a During the second time period, the voltage level is high for a short period, and low for the rest of the time. (In the example...) Figure 7 In one embodiment, the pulse turn-on drive signal g a The pulse turn-on drive signal g' is allocated to all auxiliary switching transistors within the first bridge arm 10. a All auxiliary switching transistors within the second bridge arm 20 are allocated. Pulse turn-on drive signal g a (g' a The duration of maintaining a high level during the first time period (second time period) is t. p1 (t p2 ), the t p1 (t p2 The second time period (or the first time period) may be shorter than the first time period (or the second time period), but may also include the start and end times of the first time period (or the second time period). Figure 7 In the described embodiment, t1 < t2, t3 < t4, t5 < t6, t7 < t8, and the first dead time is equal to the second dead time. In other embodiments, t1 = t2, t3 = t4, t5 = t6, t7 = t8, and t... p1 and t p2 The value can be adjusted according to the circuit parameters, and the dead time can be set according to the actual needs such as the switching frequency of the circuit.

[0066] Figure 8 According to embodiments of the present invention, Figure 7The waveform diagrams shown depict the circuit modes of the first bridge arm 10 and the second bridge arm 20 during time periods t2 to t3 and t6 to t7. Figure 8 (a) as described in the embodiments of the present invention Figure 7 The waveform diagram shown represents the circuit mode diagram of the discharge of the first clamping capacitor in the first bridge arm 10 during the first time period, corresponding to... Figure 7 During the first time period (t5~t8), specifically the t6~t7 stage: when t6<t<t7, all the first main switches in the first bridge arm 10 are turned off, and all the second main switches in the second bridge arm 20 are turned on. This is because the auxiliary switching transistors S in all sub-modules SM11~SM1N within the first bridge arm 10... a When the circuit is activated, the clamping capacitor C in these sub-modules is connected in parallel with the parasitic capacitance of the corresponding main switch S. When the sum of the voltages across the clamping capacitors exceeds the input voltage V... dc That is, v c11 ++v c12 ...+v c1N ≥V dc At that time, the clamping capacitor in the first bridge arm will naturally discharge to the input side, with a bridge arm discharge current of i1, and feed energy back to the input side until time t7, when the auxiliary switching transistors S in submodules SM11 to SM1N discharge to the input side. a Turn off. Since the capacitance of the clamping capacitor C is much larger than the parasitic capacitance of the main switch S, the bridge arm discharge current i1 mainly flows through the clamping capacitor C. During this process, the equivalent capacitance of all the first clamping capacitors connected in series in the first bridge arm will interact with the parasitic inductance L in the first and second bridge arm circuits. s An oscillation occurred, with the oscillation period being:

[0067]

[0068] Therefore, preferably, the pulse turn-on drive signal g a The duration t of maintaining a high level during the first time period p1 The value should be less than the oscillation period to avoid oscillation of the clamping capacitor in the first bridge arm when the first auxiliary switch is turned on. Figure 8 (b) is as described in the embodiments of the present invention. Figure 7 The waveform diagram shown represents the circuit mode diagram of the discharge of the second clamping capacitor within the second bridge arm 20 during the second time period, corresponding to... Figure 7 During the second time period (t1~t4), in the stage t2~t3: when t2<t<t3, all the first main switches in the first bridge arm 10 are turned on, and all the second main switches in the second bridge arm 20 are turned off. This is because the auxiliary switching transistors S in all sub-modules SM21~SM2N within the second bridge arm 20... aWhen the circuit is activated, the clamping capacitor C in these sub-modules is connected in parallel with the parasitic capacitance of the corresponding second main switch S. When the sum of the voltages across the clamping capacitors exceeds the input voltage V... dc That is, v c21 ++v c22 ...+v c2N ≥V dc At that time, the clamping capacitor in the second bridge arm will naturally discharge to the input side, with a bridge arm discharge current of i2, and feed energy back to the input side until time t3, when the auxiliary switching transistors S in submodules SM21 to SM2N discharge to the input side. a Turn off. Since the capacitance of the clamping capacitor C is much larger than the parasitic capacitance of the main switch S, the bridge arm discharge current i2 mainly flows through the clamping capacitor C. During this process, the equivalent capacitance of all the second clamping capacitors connected in series in the second bridge arm will interact with the parasitic inductance L in the first and second bridge arm circuits. s An oscillation occurred, with the oscillation period being:

[0069]

[0070] Therefore, preferably, the pulse turn-on drive signal g' a The duration t of maintaining a high level during the second time period p2 The value should be less than the oscillation period to avoid oscillation of the clamping capacitor in the second bridge arm when the second auxiliary switch is turned on.

[0071] Figure 9 This is a schematic diagram of a half-bridge, full-bridge, and three-phase DC / AC converter circuit implementing multiple switches connected in series according to an embodiment of the present invention. The half-bridge DC / AC converter circuit (e.g.) Figure 9 (a) shows that the circuit includes a half-bridge circuit 110 and a filter device 120. The half-bridge circuit 110 includes two bridge arm capacitors C. i He Ru Figure 1 The half-bridge circuit shown is a series-connected switch circuit, comprising a first bridge arm 10 and a second bridge arm 20. The midpoints M1 and M2 of the two bridge arms of the half-bridge circuit 110 are connected to the load via a filter device 120. The full-bridge DC / AC converter circuit (such as...) Figure 9 (b) shows a three-phase DC / AC converter circuit, including a full-bridge circuit 130 and a filter device 140. The full-bridge circuit 130 includes a first bridge arm 10, a second bridge arm 20, a third bridge arm 30, and a fourth bridge arm 40. The midpoints M1 and M2 of the two bridge arms of the full-bridge circuit 130 are connected to the load via the filter device 140. The structure and control method of the third bridge arm 30 and the fourth bridge arm 40 are similar to those of the first bridge arm 10 and the second bridge arm 20. Figure 9(c) shows the circuit, which includes a three-phase bridge circuit 150 and a filter device 160. The three-phase bridge circuit 150 includes a first bridge arm 10, a second bridge arm 20, a third bridge arm 30, a fourth bridge arm 40, a fifth bridge arm 50, and a sixth bridge arm 60. The midpoints M1, M2, and M3 of the three bridge arms of the three-phase bridge circuit 150 are connected to the load via the filter device 160. The structure and control method of the fifth bridge arm 50 and the sixth bridge arm 60 are similar to those of the first bridge arm 10 and the second bridge arm 20. The load can be an AC source such as a power grid, a motor, or a heating device. This study focuses on the control method under heavy load conditions, specifically the output current i. a i b and i c The amplitude exceeds a certain threshold. The filtering devices 120, 140, and 160 include a filter inductor L. f and filter capacitor C f It may also include a damping resistor; V dc and V ac These are the DC-side voltage and AC-side voltage of the DC / AC conversion circuit, respectively. Figure 9 In the embodiment shown in (a), for ease of description, each main switch and its parallel auxiliary module are defined as a sub-module. That is, the first bridge arm 10 includes sub-modules SM11 to SM1N connected in series, and the second bridge arm 20 includes sub-modules SM21 to SM2N connected in series. Each sub-module SM1i and SM2i includes a main switch S and an auxiliary diode D. a An auxiliary switching transistor S a And a clamping capacitor C, the auxiliary switching transistor S a The clamping capacitor C is connected in series with the main switch S. The two output ports of each submodule are located at the two ends of the main switch S. The auxiliary diode D a With auxiliary switch S a Anti-parallel connection, i arm For the bridge arm current, Figure 9 The direction shown in (a) is the positive direction. For ease of description, the components in each submodule are not labeled separately, but in an actual embodiment, Figure 9 (a) The structure and component markings of the first bridge arm 10 shown in the figure are consistent with those of the first bridge arm 10 shown in the figure. Figure 2 The first bridge arm 10 shown in (a) is the same. Figure 9 (a) The structure and component markings of the second bridge arm 20 shown in the figure are consistent with those of the second bridge arm 20 shown in the figure. Figure 2 The second bridge arm 20 shown in (b) is the same. Similarly, Figure 9 (b) The structure of the third bridge arm 30 and the fourth bridge arm 40 shown is similar to that of the first bridge arm 10 and the second bridge arm 20, except that the drive signals of the main switch S are 180 degrees out of phase. Figure 9(c) The structures of the fifth bridge arm 50 and the sixth bridge arm 60 shown are similar to those of the first bridge arm 10 and the second bridge arm 20, except that the drive signals of the main switches S of the first bridge arm 10 and the second bridge arm 20, the third bridge arm 30 and the fourth bridge arm 40, and the fifth bridge arm 50 and the sixth bridge arm 60 are 120 degrees out of phase. It should be noted that... Figure 9 This is the most common topology for two-level DC / AC converter circuits. In practical applications, in midpoint clamping (NPC), cascaded H-bridge (CHB), and modular multilevel (MMC) DC / AC converter circuits, replacing a single power device with a bridge arm (first or second bridge arm) connected in series with a switch can also be achieved by using the aforementioned heavy-load control method to discharge the clamping capacitor in the bridge arm.

[0072] Figure 10 According to embodiments of the present invention, Figure 9 The flowchart 5000 shows the overload control and voltage equalization control method for the DC / AC converter circuit. The bridge circuit includes a first bridge arm and a second bridge arm coupled to a common terminal. The first bridge arm includes a plurality of first main switches coupled in series, wherein each first main switch is connected in parallel with a first auxiliary module. Each first auxiliary module includes a first clamping capacitor and a first auxiliary switch. The second bridge arm includes at least one second main switch. The first bridge arm receives a first main switch signal to control the plurality of first main switches. The second bridge arm receives a second main switch signal for the at least one second main switch. Each switching cycle includes a first time period, a second time period, a first dead time, and a second dead time. The first time period is the time period during which the second main switch is turned on and the first main switch is turned off. The second time period is the time period during which the first main switch is turned on and the second main switch is turned off. The first dead time and the second dead time are between the first main switch signal and the second main switch signal. The common terminal outputs an output current. The control method includes steps S51 to S53.

[0073] Step S51: Detect the output current. When the output current is greater than a first preset threshold, proceed to step S52 where the bridge circuit adopts a heavy load control method. When the output current is less than a second preset threshold, proceed to step S53 where the bridge circuit adopts a voltage equalization control method.

[0074] Step S52: In this switching cycle, the first bridge arm adopts a heavy load control method: During the first time period, all first auxiliary switches in the first bridge arm are turned on for a first preset duration. When the sum of the voltages of the first clamping capacitors in all the first auxiliary modules exceeds the bus voltage, the first clamping capacitors discharge and feed energy back to the DC side to reduce the fluctuation of the voltage of the first clamping capacitors. The first preset duration is less than or equal to the first time period, and the process returns to step S51.

[0075] Step S53: In this switching cycle, the first bridge arm adopts a voltage equalization control method: During the first dead time, the voltage of the first clamping capacitor in the first bridge arm is controlled to be the largest or the first auxiliary switch corresponding to the first clamping capacitor in the top k is turned on for a first auxiliary turn-on time. The first clamping capacitor in the top k is discharged through freewheeling current to compensate for the imbalance between the voltages of the first clamping capacitors. The first auxiliary turn-on time is less than or equal to the first dead time, where k is a natural number greater than or equal to 2. Return to step S51.

[0076] It should be noted that, in one embodiment of the present invention, it is possible to directly apply heavy-load control and voltage equalization control methods to the first bridge arm in each switching cycle without detecting the output current or determining the threshold, thus simplifying the complexity of the control program. Furthermore, Figure 10 The control method shown in the embodiment is not limited to DC / AC conversion circuits, but is also applicable to other bridge circuits.

[0077] In other embodiments, the second bridge arm includes a plurality of second main switches connected in series between the first end and the second end. Each second main switch is connected in parallel with a second auxiliary module. Each second auxiliary module includes a second clamping capacitor and a second auxiliary switch. In this case, similar to the overload control and voltage equalization control method of the first bridge arm, the control method of the second bridge arm includes steps S61 to S63.

[0078] Step S61: Detect the output current. When the output current is less than a third preset threshold, proceed to step S62 where the bridge circuit adopts a heavy load control method. When the output current is greater than a fourth preset threshold, proceed to step S63 where the bridge circuit adopts a voltage equalization control method.

[0079] Step S62: In this switching cycle, the second bridge arm adopts a heavy load control method: During the second time period, all second auxiliary switches in the second bridge arm are turned on for a second preset duration. When the sum of the voltages of the second clamping capacitors in all the second auxiliary modules exceeds the bus voltage, the second clamping capacitors discharge and feed energy back to the DC side to reduce the fluctuation of the voltage of the second clamping capacitors. The second preset duration is less than or equal to the second time period, and the process returns to step S61.

[0080] Step S63: In this switching cycle, the second bridge arm adopts a voltage equalization control method: During the second dead time, the second auxiliary switch corresponding to the second clamping capacitor with the largest voltage or the first q clamping capacitor is turned on for a second auxiliary turn-on duration. The second clamping capacitors with the first q clamping capacitors are discharged through freewheeling current to compensate for the imbalance between the voltages of the second clamping capacitors. The second auxiliary turn-on duration is less than or equal to the second dead time, where q is a natural number greater than or equal to 2. Return to step S61.

[0081] It should be noted that, in one embodiment of the present invention, the output current can be not detected and the threshold can be not determined. The heavy load control and voltage equalization control methods can be directly applied to the second bridge arm in each switching cycle, which can simplify the complexity of the control program. Figure 11 According to embodiments of the present invention, Figure 9 The diagram shows the gate drive waveforms for heavy-load control and voltage equalization control of the half-bridge DC / AC converter circuit. Figure 11 As shown, v 10 V is the bridge arm voltage of the first bridge arm 10. 20 For the bridge arm voltage of the second bridge arm 20, i a The output sinusoidal current is shown as i in the figure. a The positive direction, i a If the amplitude exceeds a certain threshold, the circuit enters a heavy-load operating state, and the aforementioned control method is employed during this state. Figure 11 In the illustrated embodiment, the first preset threshold, the second preset threshold, the third preset threshold, and the fourth preset threshold are all set to 0, i.e., i th1 =i th2 =i th3 =i th4 =0. In other embodiments, the first to fourth preset thresholds can be selected according to actual needs, for example, i th1 It can also take a value greater than zero, i th2 It can also take a value less than zero. s For the switching cycle of each main switch, in such a case Figure 11 In the described embodiment, the first time period is the time during which the second main switch signal g' remains at a high level (t6~t7). 10 The second time period is the time (0~t4) during which the first main switch signal g remains at a high level. The first and second time periods may be equal or unequal. There is a first dead time and a second dead time for the first and second main switch signals. The first dead time is the dead time before the first main switch signal g changes from low to high, and the second dead time is the dead time before the second main switch signal g' changes from low to high. d1 (t d2) represents the duration of the first dead time (second dead time), where t is... d1 With t d2 They can be equal or unequal.

[0082] like Figure 11 In the illustrated embodiment, g a3 (g' a1 In the heavy-load control method, g is the pulse turn-on drive signal for the auxiliary switching transistor in the first bridge arm 10 (second bridge arm 20). a3 (g' a1 The signal maintains a high level for a period during the first time period (second time period), and a low level for the rest of the time. In such a case... Figure 11 In one embodiment, the pulse turn-on drive signal g a3 (g' a1 All auxiliary switching transistors within the first bridge arm 10 (second bridge arm 20) are allocated. The heavy-load control pulse turn-on drive signal g... a3 (g' a1 The duration of maintaining a high level during the first time period (second time period) is t. p4 (t p2 ), the t p4 (t p2 The second time period (or the first time period) may be shorter than the first time period (or the second time period), but may also include the start and end times of the first time period (or the second time period). Figure 11 In the described embodiment, 0 < t1, t2 < t6, t5 < t7, t8 < t6. 10 In other embodiments, 0 = t1, t2 = t6, t5 = t7, t8 = t 10 , t p4 and t p2 The value of g can be adjusted according to the circuit parameters. a1 (g' a2 In the voltage equalization control method, g is the pulse turn-on drive signal for the auxiliary switching transistor in the first bridge arm 10 (second bridge arm 20). a1 (g' a2 The high level is maintained for a period of time during the first dead time (second dead time), g a1 (g' a2 The auxiliary switch is turned on a short time before the first dead time (second dead time) to ensure near-zero voltage turn-on of the auxiliary switch; the remaining time is spent at a low level. Figure 11 In one embodiment, the pulse turn-on drive signal g a1 The first auxiliary switch is assigned to the first clamping capacitor with the largest voltage or the first k clamping capacitors in the first bridge arm 10. The drive signal for the remaining first auxiliary switches is the turn-off signal g. a2That is, low level; pulse turn-on drive signal g' a2 The second auxiliary switch corresponding to the second clamping capacitor with the largest voltage or the first j-th voltage in the second bridge arm 20 is assigned to the second auxiliary switch. The drive signal for the remaining second auxiliary switches is the turn-off signal g'. a3 That is, a low level, where k and j are natural numbers greater than or equal to 2. The voltage equalization control pulse turn-on drive signal g a1 (g' a2 The duration of maintaining a high level within the first dead time (second dead time) is t. p1 (t p3 ), the t p1 (t p3 The time t is less than the first dead time (second dead time), and may also include the start and end times of the first dead time (second dead time). p1 and t p3 They can be equal or unequal, t p1 and t p3 The value can be adjusted according to the circuit parameters.

[0083] like Figure 11 In the illustrated embodiment, the heavy-load control mode diagrams of the first bridge arm 10 and the second bridge arm 20 are similar to those of... Figure 8 Same. Corresponding as Figure 11 The first time period (t6~t) 10 The circuit mode diagram of the discharge of the first clamping capacitor in the first bridge arm 10 during the t7-t8 stage is as follows: Figure 8 (a) Same; Corresponding as Figure 11 The circuit mode diagram of the discharge of the second clamping capacitor in the second bridge arm 20 during the t1 to t2 stage within the second time period (0 to t4) is as follows: Figure 8 (b) Same.

[0084] Figure 12 According to embodiments of the present invention, Figure 11 The waveform diagram shown shows t 10 ~t H Circuit mode diagrams for voltage equalization control of the first bridge arm 10 and the second bridge arm 20 within time t4 and time t5. Figure 12 (a) is the pulse turn-on drive signal number g during the first dead time. a1 The circuit mode diagrams of the first bridge arm 10 and the second bridge arm 20 during the high-level maintenance are as follows: Figure 11 The first dead time (t) 10 ~t 12 )in t 10 ~t 11 Stage; where t 10 <t<t 11At that time, the main switch S in the second bridge arm 20 is turned off, and the parasitic capacitance of the main switch S in the first bridge arm 10 is discharged. Assuming that the clamping capacitor voltages in the submodules SM11 to SM1k in the first bridge arm 10 are in the first k order, their corresponding auxiliary switch S a When activated, the clamping capacitor C in submodules SM11 to SM1k is connected in parallel with the parasitic capacitance of the corresponding main switch S. Both are discharged simultaneously until the auxiliary switch S in submodules SM11 to SM1k is activated. a Turn off. Since the capacitance of the clamping capacitor C is much larger than the parasitic capacitance of the main switch S, the freewheeling current of the bridge arm mainly flows through the clamping capacitor C, while the parasitic capacitance in the other sub-modules is quickly discharged to 0. The freewheeling current of the bridge arm is transferred to the anti-parallel diode of the corresponding main switch S, ensuring that the corresponding main switch S is turned on at zero voltage.

[0085] Figure 12 (b) is the pulse drive signal g' during the second dead time. a2 The circuit mode diagrams of the first bridge arm 10 and the second bridge arm 20 during the high-level maintenance are as follows: Figure 11 During the second dead time (t4~t6), in the t4~t5 stage; where t4<t<t5, the main switch S in the first bridge arm 10 is turned off, and the parasitic capacitance of the main switch S in the second bridge arm 20 is discharged. Assuming that the clamping capacitor voltages in the submodules SM21~SM2j in the second bridge arm 20 are among the first j, their corresponding auxiliary switch S... a When activated, the clamping capacitor C in submodules SM21 to SM2j is connected in parallel with the parasitic capacitance of the corresponding main switch S, and both are discharged simultaneously until the auxiliary switch S in submodules SM21 to SM2i is activated. a Turn off. Since the capacitance of the clamping capacitor C is much larger than the parasitic capacitance of the main switch S, the freewheeling current of the bridge arm mainly flows through the clamping capacitor C, while the parasitic capacitance in the other sub-modules is quickly discharged to 0. The freewheeling current of the bridge arm is transferred to the anti-parallel diode of the corresponding main switch S, ensuring that the corresponding main switch S is turned on at zero voltage.

[0086] Figure 13 According to embodiments of the present invention, Figure 9 The diagram shows the steady-state voltage waveforms of the clamping capacitors in the first bridge arm 10 and the second bridge arm 20 of the half-bridge DC / AC converter circuit under heavy load control and voltage equalization control. Figure 13 In the aforementioned steady-state waveform diagram, i a For the output current, i a Including the fundamental sinusoidal wave and high-frequency ripple, v c1 and v c2 These are schematic diagrams of the clamping capacitor voltage waveforms in the first bridge arm 10 and the second bridge arm 20, respectively. ac T is the output period at the power frequency. acMuch longer than the switching period T of the main switch transistor s .exist Figure 13 In the illustrated embodiment, i th1 =i th2 =i th3 =i th4 =0. Figure 13 In the aforementioned steady-state waveform diagram, 0 < t < 0.5T ac At that time, i a >0, the first bridge arm 10 is in the charging phase. During the dead time after the main switch in the first bridge arm 10 is turned off, the clamping capacitors of submodules SM11~SM1N are charged due to the freewheeling current of the parasitic inductance of the first bridge arm 10. Under the original dead-time discharge control method, there is no negative output current to discharge the clamping capacitors of the first bridge arm. Therefore, after several switching cycles, at the end of charging, the voltage of the clamping capacitors of the first bridge arm 10 reaches its peak value, as shown by the dotted line in the figure. Since the circuit is under heavy load at this time, the output current i a The amplitude is relatively large, the charging amount of the first clamping capacitor is large, and the peak voltage of the capacitor is also very high at the end of the charging phase. When the above-mentioned heavy-load control method is adopted, during the charging phase, the first bridge arm 10 can still turn on all the first auxiliary switches of the first bridge arm 10 when the main switch of the second bridge arm 20 is turned on, to discharge the first clamping capacitor in the first bridge arm 10 and feed the energy back to the DC side. Under the condition that the clamping capacitor capacitance is the same, the heavy-load control method can significantly reduce the fluctuation of the clamping capacitor voltage compared with the original dead-time discharge control method. 0.5T ac <t<T ac At that time, i a <0, the auxiliary switching transistor S in the auxiliary modules SM11~SM1N of the first bridge arm 10 a The first auxiliary activation duration t is activated in turn. a Since i a When the value is less than 0, the corresponding clamping capacitor C is discharged in turn. The duration of the discharge phase is determined by the number of dead-time insertion submodules k in each bridge arm and the auxiliary switching transistor S. a Pulse turn-on time t a Impact. When i a With proper settings, after multiple switching cycles, at the end of the discharge phase, the following condition is met: v c11 +v c12 +…+v c1N <V dc The first bridge arm 10 naturally transitions to the voltage stabilization stage, and the voltage v of the clamping capacitor in the first bridge arm 10... c11 ~v c1N In V dcDynamic balance is achieved at / N. By alternately discharging the clamping capacitor in each switching cycle, voltage equalization control of the clamping capacitor is realized during the discharge and voltage stabilization phases. Similarly, 0 < t < 0.5T ac At that time, the second bridge arm 20 was in the discharge stage and voltage stabilization stage; 0.5T ac <t<T ac At this time, the second bridge arm 20 is in the charging phase. By adopting a heavy-load control method, the voltage fluctuation of the second clamping capacitor in the second bridge arm 20 can be significantly reduced. Therefore, in one output cycle T... ac In this process, on the one hand, the heavy-load control method can significantly reduce the voltage fluctuation of the clamped capacitor during the charging stage; on the other hand, the voltage equalization control method can achieve voltage balance of the clamped capacitor during the discharging stage and the voltage stabilization stage, ultimately achieving periodic dynamic balance of the clamped capacitor voltage in each bridge arm.

[0087] Figure 14 A block diagram 7000 illustrates a method for heavy-load control and voltage equalization control of a DC / AC converter circuit with switches connected in series according to an embodiment of the present invention. The DC / AC conversion circuit includes: a bridge circuit with switches connected in series, a filter device, and an output load. The bridge circuit with switches connected in series includes a first bridge arm and a second bridge arm coupled to a common terminal. The first bridge arm includes multiple first main switches connected in series, wherein each first main switch is connected in parallel with a first auxiliary module. Each first auxiliary module includes a first clamping capacitor and a first auxiliary switch transistor. The second bridge arm includes at least one second main switch. The first bridge arm receives a first main switch signal for the multiple first main switches, and the second bridge arm receives a second main switch signal for the at least one second main switch. The common terminal outputs an output current and an output voltage. One switching cycle of the DC / AC conversion circuit includes a first time period, a second time period, a first dead time, and a second dead time. The first time period is the time period during which the second main switch is turned on and the first main switch is turned off. The second time period is the time period during which the first main switch is turned on and the second main switch is turned off. The first dead time and the second dead time are between the first main switch signal and the second main switch signal. The control method includes steps S71 to S74.

[0088] Step S71: During the first time period, control the plurality of first main switches to turn off, control at least one second main switch to turn on, control all first auxiliary switches in the first bridge arm to turn on for a first preset time, discharge the first clamping capacitor in the first bridge arm, and control the DC / AC conversion circuit to enter the normal inverter / rectifier working state.

[0089] Step S72: During the first dead time, control the plurality of first main switches to turn off, control the at least one second main switch to turn off, and control the first auxiliary switch tube in at least one first auxiliary module in the first bridge arm to turn on for a first auxiliary turn-on duration.

[0090] In step S73, during the second time period, the plurality of first main switches are turned on, at least one second main switch is turned off, and all first auxiliary switches are turned off, thereby controlling the DC / AC conversion circuit to enter normal inverter / rectification operation.

[0091] Step S74: During the second dead time, control the plurality of first main switches to turn off, control at least one second main switch to turn off, and control all first auxiliary switches to turn off.

[0092] In one embodiment, the bridge circuit outputs an output current and an output voltage at the common terminal, and the control method further includes:

[0093] Detect the output current;

[0094] During the first time period, if the output current is greater than a first preset threshold, then all the first auxiliary switches in the first bridge arm are turned on for a first preset duration, and the first clamping capacitor in the first bridge arm is discharged; if the output current is less than the first preset threshold, then all the first auxiliary switches are turned off, and the DC / AC conversion circuit is controlled to enter the normal inverter / rectifier working state.

[0095] During the first dead time, if the output current is greater than the second preset threshold, all first auxiliary switches are turned off; if the output current is less than the second preset threshold, the first auxiliary switches in at least one first auxiliary module in the first bridge arm are turned on for a first auxiliary turn-on duration, and the first clamping capacitor in the at least one first auxiliary module is discharged by the freewheeling current.

[0096] In one embodiment, the common terminal outputs an output current and an output voltage, the first dead time is the dead time before the rising edge of the first main switch signal, and the second dead time is the dead time before the rising edge of the second main switch signal. In one embodiment, the first time period is the period during which the first main switch signal remains at a low level and the second main switch signal remains at a high level, corresponding to... Figure 11 The waveform diagram of the DC / AC converter circuit embodiment shown includes t6 to t7. 10 The first dead time is the period after the first main switch signal remains low while the second main switch signal changes from high to low. The corresponding time interval is as follows: Figure 11 The waveform diagram of the DC / AC converter circuit embodiment shown below shows t.10 ~t 12 The second time period is the period during which the first main switch signal changes from low to high while the second main switch signal remains low, as shown below. Figure 10 In the waveform diagram of the DC / AC converter circuit embodiment shown, the time period from 0 to t4 represents the second dead time, which is the period during which the first main switch signal changes from high to low while the second main switch signal remains low. This corresponds to the time period shown in the diagram. Figure 10 The waveform diagram of the DC / AC conversion circuit embodiment shown includes the time period t4 to t6.

[0097] In other embodiments, a plurality of second main switches are connected in series between the first and second ends of the second bridge arm, each second main switch is connected in parallel with a second auxiliary module, and each second auxiliary module includes a second clamping capacitor and a second auxiliary switching transistor. The control method further includes:

[0098] During the second time period, all second auxiliary switches in the second bridge arm are turned on for a second preset duration, the clamping capacitors in the second bridge arm are discharged, and the DC / AC conversion circuit is controlled to enter the normal inverter / rectifier working state.

[0099] During the second dead time, control the second auxiliary switch tube in at least one second auxiliary module in the second bridge arm to turn on for a second auxiliary turn-on duration.

[0100] In one embodiment, the control method further includes:

[0101] Detect the output current;

[0102] During the second time period, if the output current is less than a third preset threshold, then all second auxiliary switches in the second bridge arm are turned on for a second preset duration, and the clamping capacitors in the second bridge arm are discharged; if the output current is greater than the third preset threshold, then all second auxiliary switches are turned off, and the DC / AC conversion circuit enters the normal inverter / rectifier working state.

[0103] During the second dead time, if the output current is greater than the fourth preset threshold, then the second auxiliary switch in at least one second auxiliary module within the second bridge arm is turned on for a second auxiliary turn-on duration, and the second clamping capacitor in the at least one second auxiliary module is discharged by the freewheeling current; if the output current is less than the fourth preset threshold, then the plurality of first main switches and the plurality of second main switches are turned off, and all auxiliary switches are turned off. The first preset duration is less than the oscillation period between the parasitic inductance in the first bridge arm and the second bridge arm circuit and the equivalent capacitance of all first clamping capacitors in series in the first bridge arm; the second preset duration is less than the oscillation period between the parasitic inductance in the first bridge arm and the second bridge arm circuit and the equivalent capacitance of all second clamping capacitors in series in the second bridge arm.

[0104] It's important to understand that by detecting the output current and selectively controlling the conduction of the first and second auxiliary switches in each switching cycle, the switching losses of the auxiliary switches can be reduced, thereby lowering the overall system losses. For example... Figure 14 The control method for the DC / AC converter circuit shown further includes:

[0105] The voltages across all the first clamping capacitors are sampled, and a control circuit is used to sort the voltages across the first clamping capacitors. When a certain voltage sampling signal is the largest or ranks in the top k among all the first voltage sampling signals, the first auxiliary switch corresponding to the first voltage sampling signal is controlled to turn on for the first auxiliary turn-on duration during the first dead time, and the first auxiliary switch corresponding to the other first voltage sampling signals is controlled to turn off, where k is a natural number greater than or equal to 2.

[0106] The voltages across all the second clamping capacitors are sampled, and a control circuit is used to sort the voltages across the second clamping capacitors. When a certain voltage sampling signal is the largest or ranks first j among all the second voltage sampling signals, the second auxiliary switch corresponding to the second voltage sampling signal is turned on during the second dead time, and the second auxiliary switch corresponding to the other second voltage sampling signals is turned off. Here, j is a natural number greater than or equal to 2, and k is equal to or not equal to j.

[0107] The specific examples described above are merely illustrative of the technical concept and application features of this invention, intended to enable engineers skilled in the art to understand and apply the invention, but they do not limit the scope of protection of this invention. The details of the circuit structure and its control method described above can undergo considerable variation during implementation; however, they are still included within the scope of this invention disclosed herein. All equivalent transformations or modifications made according to the spirit and essence of this invention should be covered within the scope of protection of this invention.

Claims

1. A control method for a bridge circuit with series-connected switches, the bridge circuit including a first bridge arm and a second bridge arm coupled to a common terminal, the first bridge arm including a plurality of first main switches coupled in series, wherein each first main switch is connected in parallel with a first auxiliary module, each first auxiliary module including a first clamping capacitor and a first auxiliary switch transistor, the second bridge arm including at least one second main switch, the first bridge arm receiving a first main switch signal for controlling the plurality of first main switches, the second bridge arm receiving a second main switch signal for the at least one second main switch, wherein each switching cycle includes a first time period, a second time period, a first dead time, and a second dead time, the first time period being the time period during which the second main switch is turned on and the first main switch is turned off, the second time period being the time period during which the first main switch is turned on and the second main switch is turned off, and the first dead time and the second dead time are between the first main switch signal and the second main switch signal, the control method comprising: During the first time period, the plurality of first main switches are turned off, at least one second main switch is turned on, and all of the plurality of first auxiliary switches are turned on for a first preset time. During the first preset time, when the sum of the voltages of the first clamping capacitors in all the first auxiliary modules exceeds the bus voltage, the voltages of the first clamping capacitors in all the first auxiliary modules are discharged. as well as During the second time period, the plurality of first main switches are turned on, the at least one second main switch is turned off, and all of the plurality of first auxiliary switches are turned off. The bridge circuit outputs an output current and an output voltage at its common terminal. When the amplitude of the output current is greater than a preset threshold, the bridge circuit is in a heavy-load operating state, and the control method is used in the heavy-load operating state.

2. The control method as described in claim 1, wherein the first preset duration is less than the oscillation period between the parasitic inductance in the first bridge arm and the second bridge arm circuit and the equivalent capacitance of all the first clamping capacitors in the first bridge arm connected in series.

3. The control method as described in claim 1, wherein the first end and the second end of the second bridge arm include a plurality of second main switches connected in series, each second main switch is connected in parallel with a second auxiliary module, each second auxiliary module includes a second clamping capacitor and a second auxiliary switching transistor, and the control method further includes: During the first time period, multiple second main switches are turned on; during the first preset time period, all second auxiliary switches are turned off. as well as During the second time period, the plurality of second main switches are controlled to turn off, and the plurality of second auxiliary switches are all turned on for a second preset time. During the second preset time, the first auxiliary switches are controlled to turn off. When the sum of the voltages of the second clamping capacitors in all the second auxiliary modules exceeds the bus voltage, the second clamping capacitors in all the second auxiliary modules are discharged.

4. The control method as described in claim 3, wherein the second preset duration is less than the oscillation period between the equivalent capacitance of the parasitic inductance in the first bridge arm and the second bridge arm circuit and all the second clamping capacitors of the second bridge arm connected in series.

5. A control method for a bridge circuit with series-connected switches, the bridge circuit including a first bridge arm and a second bridge arm coupled to a common terminal, the first bridge arm including a plurality of first main switches coupled in series, wherein each first main switch is connected in parallel with a first auxiliary module, each first auxiliary module including a first clamping capacitor and a first auxiliary switch transistor, the second bridge arm including at least one second main switch, the first bridge arm receiving a first main switch signal for controlling the plurality of first main switches, the second bridge arm receiving a second main switch signal for the at least one second main switch, wherein each switching cycle includes a first time period, a second time period, a first dead time, and a second dead time, the first time period being the time period during which the second main switch is turned on and the first main switch is turned off, the second time period being the time period during which the first main switch is turned on and the second main switch is turned off, the first dead time and the second dead time are between the first main switch signal and the second main switch signal, the common terminal outputting an output current, the control method including a heavy-load control method and a voltage equalization control method: The heavy-load control method includes: During the first time period, all first auxiliary switches in the first bridge arm are turned on for a first preset duration. When the sum of the voltages of the first clamping capacitors in all the first auxiliary modules exceeds the bus voltage, the first clamping capacitors are discharged. The first preset duration is less than or equal to the first time period. The voltage equalization control method includes: during the first dead time, controlling the voltage of the first clamping capacitor in the first bridge arm to be the largest or the first auxiliary switch corresponding to the first clamping capacitor ranked in the top k for a first auxiliary turn-on time, the first clamping capacitor ranked in the top k is discharged through freewheeling current, the first auxiliary turn-on time is less than or equal to the first dead time, and k is a natural number greater than or equal to 2; The bridge circuit outputs an output current and an output voltage at its common terminal. When the output current is greater than a first preset threshold, the bridge circuit adopts a heavy load control method. When the output current is less than a second preset threshold, the bridge circuit adopts a voltage equalization control method.

6. The control method as described in claim 5, wherein a plurality of second main switches are connected in series between the first end and the second end of the second bridge arm, each second main switch is connected in parallel with a second auxiliary module, each second auxiliary module includes a second clamping capacitor and a second auxiliary switching transistor, and the control method further includes: The heavy-load control method further includes: during the second time period, controlling all second auxiliary switches in the second bridge arm to be turned on for a second preset duration; when the sum of the voltages of the second clamping capacitors in all the second auxiliary modules exceeds the bus voltage, the second clamping capacitors are discharged; the second preset duration is less than or equal to the second time period. The voltage equalization control method further includes: during the second dead time, controlling the second auxiliary switch corresponding to the second clamping capacitor with the largest voltage or the first q in the second bridge arm to be turned on for a second auxiliary turn-on duration, the second clamping capacitors with the first q in the second bridge arm are discharged through freewheeling current to compensate for the imbalance between the voltages of the second clamping capacitors, the second auxiliary turn-on duration is less than or equal to the second dead time, and q is a natural number greater than or equal to 2.

7. The control method as described in claim 6, wherein the bridge circuit outputs an output current and an output voltage at the common terminal, and when the output current is less than a third preset threshold, the bridge circuit adopts a heavy load control method, and when the output current is greater than a fourth preset threshold, the bridge circuit adopts a voltage equalization control method.

8. A control method for a DC / AC converter circuit with switches connected in series, the DC / AC converter circuit comprising: The circuit comprises a bridge circuit with switches connected in series, a filter device, and an output load. The bridge circuit includes a first bridge arm and a second bridge arm coupled to a common terminal. The first bridge arm includes multiple first main switches connected in series, each first main switch having a first auxiliary module connected in parallel. Each first auxiliary module includes a first clamping capacitor and a first auxiliary switching transistor. The second bridge arm includes at least one second main switch. The first bridge arm receives a first main switch signal for the multiple first main switches, and the second bridge arm receives a second main switch signal for the at least one second main switch. The common terminal outputs an output current and an output voltage. A switching cycle of the DC / AC conversion circuit includes a first time period, a second time period, a first dead time, and a second dead time. The first time period is the time when the second main switch is on and the first main switch is off. The second time period is the time when the first main switch is on and the second main switch is off. A first dead time and a second dead time are included between the first main switch signal and the second main switch signal. The control method includes: During the first time period, the plurality of first main switches are controlled to turn off, the at least one second main switch is turned on, all first auxiliary switches in the first bridge arm are controlled to be turned on for a first preset time, the first clamping capacitor in the first bridge arm is discharged, and the DC / AC conversion circuit is controlled to enter the normal inverter / rectification working state. During the first dead time, control the multiple first main switches to turn off, control the at least one second main switch to turn off, and control the first auxiliary switch tube in at least one first auxiliary module in the first bridge arm to turn on for a first auxiliary turn-on duration. During the second time period, the plurality of first main switches are turned on, at least one second main switch is turned off, and all first auxiliary switches are turned off, thereby controlling the DC / AC conversion circuit to enter normal inverter / rectification operation; and During the second dead time, control the plurality of first main switches to turn off, control at least one second main switch to turn off, and control all first auxiliary switches to turn off. The bridge circuit outputs an output current and an output voltage at its common terminal, and the control method further includes: Detect the output current; During the first time period, if the output current is greater than a first preset threshold, then all the first auxiliary switches in the first bridge arm are turned on for a first preset duration, and the first clamping capacitor in the first bridge arm is discharged; if the output current is less than the first preset threshold, then all the first auxiliary switches are turned off, and the DC / AC conversion circuit is controlled to enter the normal inverter / rectifier working state. During the first dead time, if the output current is greater than a second preset threshold, all first auxiliary switches are turned off; if the output current is less than the second preset threshold, at least one first auxiliary switch in the first bridge arm is turned on for a first auxiliary turn-on duration, and the first clamping capacitor in the at least one first auxiliary module is discharged by the freewheeling current.

9. The control method as described in claim 8, wherein the first dead time is the dead time before the rising edge of the first main switch signal, and the second dead time is the dead time before the rising edge of the second main switch signal.

10. The control method of claim 8, wherein the first end and the second end of the second bridge arm include a plurality of second main switches connected in series, each second main switch is connected in parallel with a second auxiliary module, each second auxiliary module includes a second clamping capacitor and a second auxiliary switching transistor, the control method further comprising: During the second time period, all second auxiliary switches in the second bridge arm are turned on for a second preset duration, the clamping capacitors in the second bridge arm are discharged, and the DC / AC conversion circuit is controlled to enter the normal inverter / rectifier working state. During the second dead time, control the second auxiliary switch tube in at least one second auxiliary module in the second bridge arm to turn on for a second auxiliary turn-on duration.

11. The control method of claim 10, further comprising: Detect the output current; During the second time period, if the output current is less than a third preset threshold, then all second auxiliary switches in the second bridge arm are turned on for a second preset duration, and the clamping capacitors in the second bridge arm are discharged; if the output current is greater than the third preset threshold, then all second auxiliary switches are turned off, and the DC / AC conversion circuit enters the normal inverter / rectifier working state. During the second dead time, if the output current is greater than the fourth preset threshold, the second auxiliary switch in at least one second auxiliary module in the second bridge arm is turned on for a second auxiliary turn-on duration, and the second clamping capacitor in the at least one second auxiliary module is discharged by the freewheeling current; if the output current is less than the fourth preset threshold, the plurality of first main switches and the plurality of second main switches are turned off, and all first auxiliary switches and second auxiliary switches are turned off.

12. The control method as described in claim 11, wherein the first preset duration is less than the oscillation period between the parasitic inductance in the first bridge arm and the second bridge arm circuit and the equivalent capacitance of all the first clamping capacitors in the first bridge arm connected in series; and the second preset duration is less than the oscillation period between the parasitic inductance in the first bridge arm and the second bridge arm circuit and the equivalent capacitance of all the second clamping capacitors in the second bridge arm connected in series.

13. The control method as described in claim 11, further comprising: The voltages across all the first clamping capacitors are sampled as first voltage sampling signals. A control circuit is used to sort the voltages across the first clamping capacitors. When a certain voltage sampling signal is the largest or ranks in the top k among all the first voltage sampling signals, the first auxiliary switch corresponding to the first voltage sampling signal is controlled to turn on for the first auxiliary turn-on duration during the first dead time, and the first auxiliary switch corresponding to the other first voltage sampling signals is controlled to turn off. Here, k is a natural number greater than or equal to 2. The voltages across all the second clamping capacitors are sampled as second voltage sampling signals. A control circuit sorts the voltages across the second clamping capacitors. When a certain voltage sampling signal is the largest or ranks first j among all the second voltage sampling signals, the second auxiliary switch corresponding to the second voltage sampling signal is turned on during the second dead time. The second auxiliary switch corresponding to the other second voltage sampling signals is turned off. Here, j is a natural number greater than or equal to 2, and k is equal to or not equal to j.

14. The control method as described in claim 8, wherein the DC / AC conversion circuit further includes a third bridge arm and a fourth bridge arm, the main switching signals of the third bridge arm and the fourth bridge arm are 180 degrees out of phase with the main switching signals of the first bridge arm and the second bridge arm, and the ordering of the clamping capacitors of the third bridge arm and the fourth bridge arm and the control of the auxiliary switching transistors are independent of the first bridge arm and the second bridge arm.

15. The control method as described in claim 8, wherein the DC / AC conversion circuit further includes a third bridge arm and a fourth bridge arm, a fifth bridge arm and a sixth bridge arm, wherein the main switching signals of the third bridge arm and the fourth bridge arm, the fifth bridge arm and the sixth bridge arm, the first bridge arm and the second bridge arm are 120 degrees out of phase, and the ordering of the clamping capacitors of the third bridge arm and the fourth bridge arm, the fifth bridge arm and the sixth bridge arm and the control of the auxiliary switching transistors are independent of the first bridge arm and the second bridge arm.

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