Comparator circuit, image sensor

Abstract

A comparator circuit and an image sensor, the comparator circuit comprises a current mirror unit, a first NMOS tube, a second NMOS tube, a first capacitor, a second capacitor, a first switch, a second switch and a current source; the input end of the current mirror unit is connected to the source of the first NMOS tube, and the output end is connected to the source of the second NMOS tube; the drain of the first NMOS tube and the drain of the second NMOS tube are connected to the output end of the current source; the gate of the first NMOS tube is connected to the first capacitor to receive a ramp voltage signal; the gate of the second NMOS tube receives an external input voltage through the second capacitor; one end of the first switch is connected to the source of the first NMOS tube, and the other end is connected to the gate of the first NMOS tube; one end of the second switch is connected to the source of the second NMOS tube, and the other end of the second switch is connected to the gate of the second NMOS tube. This solution can effectively improve the dynamic range of the image sensor.

Description

Technical Field

[0001] The present invention relates to the field of image processing, and in particular to a comparator circuit and an image sensor. Background Art

[0002] In an image sensor circuit, when the amplitude of the voltage signal output by the pixel circuit is large, it will exceed the working range of the comparator in the column analog-to-digital converter, thereby limiting the dynamic range of the image sensor.

[0003] Or when the pixel circuit output voltage amplitude is small, but in order to obtain a higher dynamic range in low-light scenes, the output voltage of the pixel circuit is usually amplified by a programmable gain amplifier (PGA) circuit, and then sent to the column analog-to-digital converter to obtain a digital value that is linearly related to the light intensity. After the output voltage of the pixel circuit is sent to the PGA circuit for signal amplification, the initialization voltage of the comparator in the column conversion analog-to-digital converter is relatively high, about VDD-Vth (Vth is the threshold voltage of the MOS tube), which exceeds the quantization range of the traditional column analog-to-digital converter and limits the dynamic range of the image sensor. Summary of the invention

[0004] The technical problem solved by the present invention is how to improve the dynamic range of an image sensor.

[0005] To solve the above technical problems, an embodiment of the present invention provides a comparator circuit, which includes a current mirror unit, a first NMOS tube, a second NMOS tube, a first capacitor, a second capacitor, a first switch, a second switch and a current source; wherein, the input end of the current mirror unit is connected to the source of the first NMOS tube, and the output end of the current mirror unit is connected to the source of the second NMOS tube; the drain of the first NMOS tube and the drain of the second NMOS tube are connected to the output end of the current source; the gate of the first NMOS tube is connected to the first capacitor to receive a ramp voltage signal; the gate of the second NMOS tube receives an external input voltage through the second capacitor; one end of the first switch is connected to the source of the first NMOS tube, and the other end of the first switch is connected to the gate of the first NMOS tube; one end of the second switch is connected to the source of the second NMOS tube, and the other end of the second switch is connected to the gate of the second NMOS tube.

[0006] Optionally, the current mirror unit includes a first load tube and a second load tube, and the first load tube and the second load tube adopt an N-type silicon gate structure.

[0007] Optionally, the comparator circuit also includes a third capacitor and a fourth capacitor, one end of the third capacitor is connected to the gate of the first NMOS tube, and the other end of the third capacitor receives the first regulation voltage; one end of the fourth capacitor is connected to the gate of the second NMOS tube, and the other end of the fourth capacitor receives the first regulation voltage.

[0008] Optionally, when initializing the comparator circuit, the first switch and the second switch are controlled to be closed, and the offset voltage of the ramp voltage signal is stored in the first capacitor and the third capacitor.

[0009] Optionally, after initializing the comparator circuit, the first regulation voltage is reduced, and the reduction amount of the first regulation voltage is It indicates that the reduction amount of the initialization common mode voltage of the comparator circuit is expressed by the following formula: ;in, is the change in the initialization common-mode voltage of the comparator circuit, is the capacitance of the first capacitor, is the capacitance of the third capacitor.

[0010] An embodiment of the present invention also provides a comparator circuit, which includes a current mirror unit, a first NMOS tube, a second NMOS tube, a first capacitor, a second capacitor, a first switch, a second switch and a current source; wherein, the input end of the current mirror unit is connected to the source of the first NMOS tube, and the output end of the current mirror unit is connected to the source of the second NMOS tube; the drain of the first NMOS tube and the drain of the second NMOS tube are connected to the output end of the current source; the gate of the first NMOS tube is connected to the first capacitor to receive a ramp voltage signal; the gate of the second NMOS tube receives an external input voltage through the second capacitor; one end of the first switch is connected to the gate of the first NMOS tube, and the other end of the first switch is connected to the second adjustment voltage; one end of the second switch is connected to the gate of the second NMOS tube, and the other end of the second switch is connected to the source of the second NMOS tube.

[0011] Optionally, the current mirror unit includes a first load tube and a second load tube, and the first load tube and the second load tube adopt an N-type silicon gate structure.

[0012] Optionally, a power supply terminal of the current mirror unit of the comparator circuit receives a first power supply voltage, and the second regulation voltage receives the first power supply voltage via one or more diodes connected in series.

[0013] Optionally, a bias tube is also included, the second regulating voltage is connected to the drain of the bias tube, the gate of the bias tube is connected to the third regulating voltage, and the source of the bias tube receives the second power supply voltage.

[0014] Optionally, the size of the bias tube is equal to the size of the first NMOS tube and equal to the size of the second NMOS tube.

[0015] Optionally, there are two diodes, and the size of a diode close to the second regulating voltage is equal to the size of the first load tube and equal to the size of the second load tube.

[0016] An embodiment of the present invention also provides an image sensor, which includes a pixel circuit, a programmable gain amplifier, and a column analog-to-digital converter, one end of the programmable gain amplifier is connected to the pixel circuit, the other end of the programmable gain amplifier is connected to the column analog-to-digital converter, and the column analog-to-digital converter includes any of the comparator circuits described above.

[0017] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0018] The comparator circuit of the embodiment of the present invention replaces the PMOS tube used in the input pair tube of the comparator circuit with an NMOS tube in a traditional image sensor with a PGA circuit, which can effectively reduce the initialization voltage of the comparator circuit and improve the dynamic range of the image sensor.

[0019] Furthermore, by adopting an N-type silicon gate structure for the load tube in the current mirror unit of the comparator circuit, the threshold voltage of the load tube can be increased, so that the initialization voltage of the comparator circuit is reduced, the quantization range of the column analog-to-digital converter can be increased, and the dynamic range of the image sensor can be improved.

[0020] Further, the comparator circuit also includes a third capacitor and a fourth capacitor, one end of the third capacitor is connected to the gate of the first NMOS tube, and the other end of the third capacitor receives the first adjustment voltage; one end of the fourth capacitor is connected to the gate of the second NMOS tube, and the other end of the fourth capacitor receives the first adjustment voltage. When initializing the comparator circuit, the first switch and the second switch are controlled to be closed, and the offset voltage of the ramp voltage signal is stored in the first capacitor and the third capacitor. Thus, when the offset voltage of the comparator circuit is stored in the first capacitor and / or the third capacitor, the value of the first adjustment voltage is reduced, and the initialization voltage of the comparator circuit is pulled down by redistributing the charge between the first capacitor and the third capacitor at the input end of the comparator circuit. At this time, the offset voltage of the comparator circuit still exists on the first capacitor and the third capacitor without being lost, so that the range of variation of the external input voltage that can be quantified by the comparator circuit will be proportionally increased, thereby improving the quantization range of the column analog-to-digital converter, and also improving the dynamic range of the image sensor.

[0021] Furthermore, the embodiment of the present invention also provides a circuit capable of freely adjusting its initialization voltage, wherein the first terminal of the first switch at the non-inverting input terminal of the comparator circuit is connected to the second adjustment voltage V cn The initialization voltage of the comparator circuit can be directly set to the second adjustment voltage through the pulse and the first switch and the second switch. The voltage value of the second adjustment voltage needs to meet the variation range of the external input voltage that can be quantified by the comparator circuit, that is, it can be freely set, which can maximize the working range of the comparator circuit and improve the quantization range of the column analog-to-digital converter, thereby improving the dynamic range of the image sensor.

[0022] Furthermore, the power supply terminal of the current mirror unit of the comparator circuit receives the first power supply voltage, and the second adjustment voltage receives the first power supply voltage through one or more diodes connected in series. By designing diodes with different conduction voltages and the number of diodes connected in series, a reasonable second adjustment voltage can be set, thereby changing the initialization voltage of the comparator circuit, and reducing the mutual crosstalk of the column circuits working in parallel in the pixel circuit, thereby increasing the quantization range of the column analog-to-digital converter, and also increasing the dynamic range of the image sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a structural schematic diagram of an image sensor in the prior art;

[0024] Figure 2 for Figure 1 Schematic diagram of signal waveform of the image sensor shown;

[0025] Figure 3 is a schematic structural diagram of a first comparator circuit according to an embodiment of the present invention;

[0026] Figure 4 is a schematic structural diagram of a second comparator circuit according to an embodiment of the present invention;

[0027] Figure 5 is a schematic structural diagram of a third comparator circuit according to an embodiment of the present invention;

[0028] Figure 6 for Figure 5 The waveform diagram of some signals in the third comparator circuit shown;

[0029] Figure 7 is a schematic structural diagram of a fourth comparator circuit according to an embodiment of the present invention;

[0030] Figure 8 for Figure 7 Waveform diagram of some signals of the fourth comparator circuit shown;

[0031] Fig. 9 is a schematic structural diagram of a fifth comparator circuit according to an embodiment of the present invention;

[0032] Fig.10 4 is a schematic structural diagram of a sixth comparator circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] As mentioned in the background art, a conventional image sensor has a problem that its dynamic range is limited by the initialization voltage of the comparator.

[0034] like Figure 1 As shown, see Figure 1 and Figure 2 , Figure 1 is a structural schematic diagram of an image sensor in the prior art, Figure 2 for Figure 1 Schematic diagram of the waveform of the related signal in the image sensor. In order to enhance the image output effect of the image sensor in dark scenes and improve the dynamic range of the image sensor, a PGA circuit 102 is added between the pixel circuit 101 and the column analog-to-digital converter (not shown in the figure), and the column analog-to-digital converter includes a comparator circuit 103. Among them, in the pixel circuit 101, VDD is the power supply voltage, RG is the reset transistor, TG is the transfer transistor, RS is the selection transistor, and the transistor above RS is the amplifier transistor. In the image sensor circuit, the correlated double sampling technology (CDS for short) is usually used to eliminate the fixed noise of the circuit, and the voltage Vrst (that is, the voltage Vrst) that is stable after the pixel circuit 101 is initialized is converted into Figure 2 The input voltage V of the PGA circuit 102 from time t2 to time t3 in FIG. inThe value of ) is set as the reference voltage of the column analog-to-digital converter, and the output voltage V sig (i.e. Figure 2 The input voltage V of the PGA circuit 102 at and after time t4 in The value of ) is set as the signal voltage of the column ADC, and V rst >V sig , which means that the output voltage V of the pixel circuit 101 during the readout line time in becomes smaller, that is, the input voltage of the comparator circuit 103 changes to V rst -V sig .

[0035] In the PGA circuit 102, C s is the sampling capacitor of the PGA circuit 102, C f is the feedback capacitance of the PGA circuit 102, V in is the input voltage of the PGA circuit 102, V out is the output voltage of the PGA circuit 102, which amplifies the output voltage of the pixel circuit in a dark scene. After adding the PGA circuit 102, V out With V in The change in V out The change in , V in The change in ) are in opposite phase, and , where A=C s / C f Therefore, during the row readout time, the voltage change at the comparator input terminal can be expressed as RG tube applies voltage pulse from time t1 to time t2, V in The value will increase accordingly. The TG tube adds a voltage pulse from t3 to t4. out With V in The change in Figure 2 shown.

[0036] Those skilled in the art should understand that after the output voltage of the pixel circuit is sent to the PGA circuit and the signal is amplified, since the initialization voltage of the comparator circuit in the column conversion analog-to-digital converter is relatively high, namely VDD-VGS, where VGS is the gate-source voltage of the MOS tube, this exceeds the quantization range of the traditional column analog-to-digital converter and will limit the dynamic range of the image sensor.

[0037] To solve the above problem, see Figure 3The embodiment of the present invention provides a first comparator circuit 30, the comparator circuit 30 includes a current mirror unit 301, a first NMOS tube N1, a second NMOS tube N2, a first capacitor C1, a second capacitor C2, a first switch K1, a second switch K2 and a current source 302; wherein the input end 3011 of the current mirror unit 301 is connected to the source N1S of the first NMOS tube N1, and the output end 3012 of the current mirror unit 301 is connected to the source N2S of the second NMOS tube N2; the drain N1D of the first NMOS tube N1 and the drain N2D of the second NMOS tube N2 are connected to the output end 3021 of the current source 302; the gate N1G of the first NMOS tube N1 is connected to the first capacitor C1 to receive the ramp voltage signal V ramp The gate N2G of the second NMOS tube N2 receives the external input voltage V through the second capacitor C2 out One end K11 of the first switch K1 is connected to the source N1S of the first NMOS transistor N1, and the other end K12 of the first switch K1 is connected to the gate N1G of the first NMOS transistor N1; a first end K21 of the second switch K2 is connected to the source N2S of the second NMOS transistor N2, and the other end K22 of the second switch K2 is connected to the gate N2G of the second NMOS transistor N2.

[0038] Among them, the external input voltage V out It can be the output voltage of the pixel circuit.

[0039] Optionally, the current source 302 is a ground power source, and the voltage value of the output terminal 3021 of the current source 302 is the voltage value of the ground line, that is, 0V.

[0040] Those skilled in the art should understand that in conventional image sensor circuits without PGA circuits, NMOS transistors are generally used as input pairs of transistors of the comparator circuit. The input pairs of transistors of the comparator circuit correspond to MOS transistors that receive ramp voltage signals and external input voltages. Correspondingly, conventional image sensors with PGA circuits (e.g. Figure 1 In the image sensor circuit), the comparator circuit (e.g. Figure 1 The comparator circuit 103 in FIG. 1 uses a PMOS tube as the input pair tube of the comparator circuit, that is, Figure 3 The first NMOS tube N1 and the second NMOS tube N2 are replaced by two PMOS tubes. The embodiment of the present invention replaces the PMOS tube used in the input pair of the traditional comparator circuit with an NMOS tube, which can effectively reduce the initialization voltage of the comparator circuit to improve the dynamic range of the image sensor.

[0041] In one embodiment, the current mirror unit 301 includes a first load tube and a second load tube, the first load tube is arranged at the input end 3011 of the current mirror unit 301, and the second load tube is arranged at the output end 3012 of the current mirror unit 301, and the first load tube and the second load tube adopt an N-type silicon gate structure.

[0042] Optional, see Figure 3 and Figure 4 , Figure 4 Schematic diagram of the structure of the second comparator circuit 40 of the embodiment of the present invention, the first load tube and the second load tube are PMOS tubes. The first load tube is also the first PMOS tube P1, and its gate, drain, and source are represented by P1G, P1D, and P1S respectively; the second load tube is also the second PMOS tube P2, and its gate, drain, and source are represented by P2G, P2D, and P2S respectively. The gate P1G of the first PMOS tube P1 is connected to the gate P2G of the second PMOS tube P2, and the drain P1D of the first PMOS tube P1 and the drain P2D of the second PMOS tube P2 are connected to the output end of the voltage source, and the output voltage of the voltage source is represented by VDD. The gate P1G of the first PMOS transistor P1 is connected to the source P1S of the first PMOS transistor P1. The source P1S of the first PMOS transistor P1 corresponds to the input terminal 3011 of the current mirror unit 301. The source P2S of the second PMOS transistor P2 corresponds to the output terminal 3012 of the current mirror unit 301. The voltage of the output terminal 3012 of the current mirror unit 301 is recorded as V o1 .

[0043] The first PMOS transistor P1 and / or the second PMOS transistor P2 adopts an N-type silicon gate structure, that is, the gate electrodes (P1G and P2G) of the two PMOS transistors adopt N-type doping. Thus, the threshold voltage (denoted as Vth) of the PMOS transistors (i.e., P1 and P2) can be increased, so that the initialization voltage of the comparator circuit decreases, thereby increasing the quantization range of the column analog-to-digital converter, and further improving the dynamic range of the image sensor.

[0044] Figure 4 For other components and connection relationships in the comparator circuit 40, please refer to Figure 3 The relevant description of the comparator circuit 30 is not repeated here.

[0045] Optionally, the first switch K1 and the second switch K2 are implemented by switch tubes, respectively, by inputting a voltage Φ eq Control the closing and opening of the first switch K1 and the second switch K2.

[0046] The traditional comparator circuit can be found in Figure 3 and Figure 4The comparator circuits 30 and 40 in the embodiment of the present invention are different from the comparator circuits 30 or 40 in the embodiment of the present invention in that the conventional comparator circuit is to Figure 3 or Figure 4 The first NMOS tube N1 and the second NMOS tube N2 in the comparator circuit are replaced by two PMOS tubes, and the gates of the first PMOS tube P1 and the second PMOS tube P2 are not N-type doped. In order to suppress the offset voltage of the comparator, the traditional comparator circuit will add a Φ before the analog-to-digital converter quantization. eq Pulse, at this time Φ eq The high level is converted to the low level to control the closing of the first switch K1 and the second switch K2. The charges in the channels of the two switch tubes (i.e., the first switch K1 and the second switch K2) are injected to the two ends of the switch tubes, and the offset voltage of the comparator circuit is stored on the DC blocking capacitor C1 and / or C2. At the same time, the initialization voltage of the comparator circuit is set, which is approximately , where V GS is the voltage between the gate and source of the PMOS tube, and its voltage value is relatively high. Due to the high initial voltage of the comparator circuit, the external input voltage V that the column analog-to-digital converter can quantize is out The range is very small, about , that is, the initial voltage of the comparator circuit suppresses the quantization range of the comparator circuit.

[0047] In one embodiment, see Figure 5 , Figure 5 FIG. 5 is a schematic diagram of the structure of a third comparator circuit 50 according to an embodiment of the present invention. Figure 3 or Figure 4 The comparator circuit 30 or 40, the comparator circuit 50 also includes a third capacitor C3 and a fourth capacitor C4, one end C31 of the third capacitor C3 is connected to the gate N1G of the first NMOS tube N1, and the other end C32 of the third capacitor C3 receives the first regulation voltage V cm One end C41 of the fourth capacitor C4 is connected to the gate N2G of the second NMOS tube N2, and the other end C42 of the fourth capacitor C4 receives the first regulating voltage V cm .

[0048] In one embodiment, when the comparator circuit is initialized, the first switch and the second switch are controlled to be closed, and the offset voltage of the ramp voltage signal is stored in the first capacitor and the third capacitor.

[0049] According to the method of suppressing the offset voltage of the comparator circuit in the above-mentioned conventional comparator circuit, by Φ eq The pulse stores the offset voltage of the comparator circuit 50 in the capacitors C1 and / or C3.

[0050] In one embodiment, after initializing the comparator circuit, the first regulation voltage V is reduced. cm , the first regulation voltage V cm The reduction in It indicates that the reduction amount of the initialization common mode voltage of the comparator circuit is expressed by the following formula: ;in, is the change in the initialization common-mode voltage of the comparator circuit, is the capacitance of the first capacitor C1, is the capacitance of the third capacitor C3.

[0051] Specifically, the offset voltage of the comparator circuit 50 is stored in the capacitor C1 and / or C3, and the first adjustment voltage V is reduced. cm The initialization voltage of the comparator circuit 50 is pulled down by redistributing the charge between the capacitors C1 and C3 at the input end of the comparator circuit 50. At this time, the offset voltage of the comparator circuit 50 still exists on the capacitors C1 and / or C3 without being lost, so that the external input voltage V out The range of variation will increase proportionally, thereby increasing the quantization range of the column analog-to-digital converter and also increasing the dynamic range of the image sensor.

[0052] See also Figure 6 , Figure 6 for Figure 5 The waveform diagram of some signals in the third comparator circuit 50 shown in FIG. Figure 6 The t direction is the time development direction, and the voltage Φ eq The variation waveform of the first regulation voltage V cm The variation waveform of the first regulation voltage V cm The change in , V rampi The voltage variation waveform of the node is represented by a broken line 603, V outi The voltage variation waveform of the node is represented by a broken line 603. In order to suppress the offset voltage of the comparator circuit 50, a voltage is added before the analog-to-digital converter quantization. eq Pulse, at this time Φ eq From high level to low level (such as Figure 6 Between time t5 and t6 in the figure), the first switch K1 and the second switch K2 are controlled to be closed, and the charges in the channels of the two switch tubes (i.e., the first switch K1 and the second switch K2) are injected to the two ends of the switch tubes, and the offset voltage of the comparator circuit 50 is stored on the DC blocking capacitor C1 and / or C3. After that, Φ eq From low level to high level again (such as Figure 6 At time t6 and thereafter), at this time, the first regulating voltage V cm reduce The operating range of the comparator circuit 50 can be found in Figure 6 range.

[0053] In one embodiment, the power supply terminal of the current mirror unit of the comparator circuit receives a first power supply voltage, and the second regulation voltage receives the first power supply voltage via one or more diodes connected in series.

[0054] In one embodiment, the embodiment of the present invention further provides a comparator circuit, which includes a current mirror unit, a first NMOS tube, a second NMOS tube, a first capacitor, a second capacitor, a first switch, a second switch and a current source; wherein, the input end of the current mirror unit is connected to the source of the first NMOS tube, and the output end of the current mirror unit is connected to the source of the second NMOS tube; the drain of the first NMOS tube and the drain of the second NMOS tube are connected to the output end of the current source; the gate of the first NMOS tube is connected to the first capacitor to receive a ramp voltage signal; the gate of the second NMOS tube receives an external input voltage through the second capacitor; one end of the first switch is connected to the gate of the first NMOS tube, and the other end of the first switch is connected to the second adjustment voltage; one end of the second switch is connected to the gate of the second NMOS tube, and the other end of the second switch is connected to the source of the second NMOS tube.

[0055] See also Figure 4 and Figure 7 , Figure 7 FIG. 7 is a schematic diagram of the structure of a fourth comparator circuit 70 according to an embodiment of the present invention. Figure 4 The comparator circuit 40 in the embodiment of the present invention is a comparator circuit 70 which is a circuit capable of freely adjusting its initialization voltage. The adjustment of the initialization voltage includes: the first terminal K11 of the first switch K1 at the positive input terminal of the comparator circuit 70 is connected to the second adjustment voltage V cn , other connection methods remain unchanged, the switch tube K3 can still use the pulse voltage Φ eq control. Figure 7 For other components and numbers, see Figure 3 and Figure 4 The relevant instructions in will not be repeated here.

[0056] Please continue to see Figure 8 , Figure 8 is a waveform diagram of some signals of the fourth comparator circuit 70, Figure 8 The t direction is the time development direction, and the voltage Φ eq The changing waveform of V is represented by a broken line 801.rampi The voltage variation waveform of the node is represented by a broken line 802, V outi The voltage variation waveform of the node is represented by the broken line 803. In order to suppress the offset voltage of the comparator circuit 70, a voltage is added before the analog-to-digital converter quantization. eq Pulse, at this time Φ eq From high level to low level (such as Figure 8 Between time t5 and t6 in the figure), the first switch K1 and the second switch K2 are controlled to be closed, and the charges in the channels of the two switch tubes (i.e., the first switch K1 and the second switch K2) are injected to the two ends of the switch tubes, and the offset voltage of the comparator circuit 70 is stored on the DC blocking capacitor C2. After that, Φ eq From low level to high level again (such as Figure 6 At time t6 and thereafter), the operating range of the comparator circuit 70 can be seen from Figure 8 range.

[0057] By pulse Φ eq The first switch K1 and the second switch K2 can directly set the initialization voltage of the comparator circuit 70 to the second adjustment voltage V cn , the second regulation voltage V cn The voltage value needs to satisfy the external input voltage V that the comparator circuit 70 can quantize. out The variation range can be freely set, which can maximize the working range of the comparator circuit, increase the quantization range of the column analog-to-digital converter, and thus improve the dynamic range of the image sensor.

[0058] In one embodiment, the power supply terminal of the current mirror unit of the comparator circuit receives a first power supply voltage, and the second regulation voltage receives the first power supply voltage via one or more diodes connected in series.

[0059] Specifically, see Figure 7 and Fig. 9 , Fig. 9 is a schematic structural diagram of a fifth comparator circuit 90 according to an embodiment of the present invention, Figure 3 or Figure 4 The current mirror unit 301 ( Fig. 9 China-Israel Figure 4 The power supply terminal of the current mirror unit is used as an example to receive the first power supply voltage VDD, and the first regulation voltage is passed through one or more diodes ( Fig. 9 In the example, two identical diodes (represented by D1 and D2) are used to generate the second regulation voltage V cn The second regulation voltage V cn =VDD-2×Vd, where Vd is the forward conduction voltage of diodes D1 and D2. At this time, diode D1 and diode D2 are the same in size.

[0060] Therefore, by designing diodes with different conduction voltages and the number of diodes connected in series, a reasonable second adjustment voltage can be set, thereby changing the initialization voltage of the comparator circuit and reducing the mutual crosstalk of column circuits working in parallel in the pixel circuit, thereby increasing the quantization range of the column analog-to-digital converter and also increasing the dynamic range of the image sensor.

[0061] In one embodiment, the comparator circuit further includes a bias tube, the second regulating voltage is connected to the drain of the bias tube, the gate of the bias tube is connected to the third regulating voltage, and the source of the bias tube receives the second power supply voltage.

[0062] See also Fig. 9 and Fig.10 , Fig.10 is a schematic structural diagram of a sixth comparator circuit 100 according to an embodiment of the present invention, Fig. 9 One or more diodes in the circuit can also be realized by a transistor (ie, MOS tube) connected with two pins, for example, Fig.10 In the PMOS tube (in Fig.10 ) realizes Fig. 9 The effect of diodes D1 and D2.

[0063] The bias tube Fig.10 In the example, the biasing transistor (i.e., the NMOS transistor N3) is used to achieve the effect. It should be noted that other devices can also be used to achieve the effect of the biasing transistor (i.e., the NMOS transistor N3). The second regulating voltage V cn The gate of the bias tube N3 is connected to the drain of the bias tube N3 and the gate of the bias tube N3 is connected to the third regulating voltage V B The source of the bias transistor N3 receives the second power supply voltage. Further, the second power supply voltage is a ground voltage.

[0064] Optionally, the size of the bias tube is equal to the size of the first NMOS tube and equal to the size of the second NMOS tube.

[0065] Optionally, there are two diodes, and the size of a diode close to the second regulating voltage is equal to the size of the first load tube and equal to the size of the second load tube.

[0066] exist Fig. 9 In the comparator shown in FIG. 1 , the first switch K1 and the second switch K2 use the same signal Φ eq Control, in Φ eq When the first switch K1 and the second switch K2 are turned off, the charges in the channels of the first switch K1 and the second switch K2 are injected to both ends of the switches. In order to make the charges injected by the first switch K1 and the second switch K2 to the positive and negative input ends of the comparator circuit the same, Fig.10 Compared to Fig. 9 The NMOS tube N3 is added, and the PMOS tubes P3 and P4 are equivalent to active diodes connected in series. The NMOS tube N3 is used as a bias tube to provide current and the gate terminal voltage is connected to the third regulation voltage V B Among them, the size of P4 is the same as that of P1 and P2, and the size of N3 is the same as that of N1 and N2. The initialization voltage of the comparator circuit 100 is set at this time. ,in, is the gate-source voltage of P3 and P4. For the two ends of the second switch K2, there are the second NMOS tube N2 and the second capacitor C2 of the inverting input terminal device of the comparator circuit 100, and the second PMOS tube P2 and the second NMOS tube N2 of the output terminal device of the comparator circuit 100. For the two ends of the first switch K1, there are the first NMOS tube N1 and the first capacitor C1 of the positive input terminal of the comparator circuit, and the added branch PMOS tube P4 and the bias tube N3. Because the size of the added PMOS tube P4 / bias tube N3 is the same as that of the second PMOS tube P2 / second NMOS tube N2, the impedance and load capacitance seen at the two ends of the first switch K1 and the second switch K2 are the same, so that the charge injection of the first switch K1 and the second switch K2 to the positive and negative input terminals of the comparator circuit 100 is the same when they are turned off, thereby improving the image output effect of the image sensor. Here, the threshold voltage of the PMOS tube P3 / P4, the number of active diodes in series, and the gate voltage of the bias tube N3, that is, the third adjustment voltage V B To set a reasonable second regulation voltage V cn , which is the initialization voltage of the comparator circuit 100, and at the same time, the first switch K1 and the second switch K2 inject the same charge into the positive and negative input terminals of the comparator circuit 100, thereby improving the quantization range of the column analog-to-digital converter and also improving the dynamic range of the image sensor.

[0067] An embodiment of the present invention further provides an image sensor, the image sensor comprising a pixel circuit, a programmable gain amplifier (PGA), and a column analog-to-digital converter, one end of the programmable gain amplifier is connected to the pixel circuit, the other end of the programmable gain amplifier is connected to the column analog-to-digital converter, and the column analog-to-digital converter comprises Figures 3 to 10 Any of the comparator circuits described above. The image sensor can refer to Figure 1 The structure of the image sensor may also be the structure of other existing image sensors.

[0068] It should be understood that the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article indicates that the associated objects before and after are in an "or" relationship.

[0069] The "plurality" appearing in the embodiments of the present application refers to two or more.

[0070] The first, second, etc. descriptions appearing in the embodiments of the present application are only used for illustration and distinction of the description objects. There is no order, nor do they indicate any special limitation on the number of devices in the embodiments of the present application, and cannot constitute any limitation on the embodiments of the present application.

[0071] The "connection" that appears in the embodiments of the present application refers to various connection methods such as direct connection or indirect connection to achieve communication between devices, and the embodiments of the present application do not impose any limitations on this.

[0072] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A comparator circuit, characterized in that: The comparator circuit includes a current mirror unit, a first NMOS tube, a second NMOS tube, a first capacitor, a second capacitor, a first switch, a second switch and a current source; Wherein, the input end of the current mirror unit is connected to the source of the first NMOS tube, and the output end of the current mirror unit is connected to the source of the second NMOS tube; The drain of the first NMOS tube and the drain of the second NMOS tube are connected to the output end of the current source; The gate of the first NMOS tube is connected to the first capacitor to receive a ramp voltage signal; The gate of the second NMOS tube receives an external input voltage through the second capacitor; One end of the first switch is connected to the source of the first NMOS transistor, and the other end of the first switch is connected to the gate of the first NMOS transistor; One end of the second switch is connected to the source of the second NMOS transistor, and the other end of the second switch is connected to the gate of the second NMOS transistor.

2. The comparator circuit according to claim 1, characterized in that: The current mirror unit includes a first load tube and a second load tube, and the first load tube and the second load tube adopt an N-type silicon gate structure.

3. The comparator circuit according to claim 1 or 2, characterized in that: The comparator circuit further includes a third capacitor and a fourth capacitor, one end of the third capacitor is connected to the gate of the first NMOS tube, and the other end of the third capacitor receives a first adjustment voltage; One end of the fourth capacitor is connected to the gate of the second NMOS transistor, and the other end of the fourth capacitor receives the first regulating voltage.

4. The comparator circuit according to claim 3, characterized in that: When the comparator circuit is initialized, the first switch and the second switch are controlled to be closed, and the offset voltage of the ramp voltage signal is stored in the first capacitor and the third capacitor.

5. The comparator circuit according to claim 4, characterized in that: After initializing the comparator circuit, the first regulation voltage is reduced, and the reduction amount of the first regulation voltage is ΔV cm It indicates that the reduction amount of the initialization common mode voltage of the comparator circuit is expressed by the following formula: Wherein, ΔV is the change in the initialization common-mode voltage of the comparator circuit, C1 is the capacitance of the first capacitor, and C3 is the capacitance of the third capacitor.

6. A comparator circuit, characterized in that: The comparator circuit includes a current mirror unit, a first NMOS tube, a second NMOS tube, a first capacitor, a second capacitor, a first switch, a second switch and a current source; Wherein, the input end of the current mirror unit is connected to the source of the first NMOS tube, and the output end of the current mirror unit is connected to the source of the second NMOS tube; The drain of the first NMOS tube and the drain of the second NMOS tube are connected to the output end of the current source; The gate of the first NMOS tube is connected to the first capacitor to receive a ramp voltage signal; The gate of the second NMOS tube receives an external input voltage through the second capacitor; One end of the first switch is connected to the gate of the first NMOS tube, and the other end of the first switch is connected to the second regulation voltage; One end of the second switch is connected to the gate of the second NMOS transistor, and the other end of the second switch is connected to the source of the second NMOS transistor.

7. The comparator circuit according to claim 6, characterized in that: The current mirror unit includes a first load tube and a second load tube, and the first load tube and the second load tube adopt an N-type silicon gate structure.

8. The comparator circuit according to claim 6 or 7, characterized in that: The power supply terminal of the current mirror unit of the comparator circuit receives a first power supply voltage, and the second regulation voltage receives the first power supply voltage through one or more diodes connected in series.

9. The comparator circuit according to claim 8, characterized in that: It also includes a bias tube, the second regulating voltage is connected to the drain of the bias tube, the gate of the bias tube is connected to the third regulating voltage, and the source of the bias tube receives the second power supply voltage.

10. The comparator circuit according to claim 9, characterized in that: The size of the bias tube is equal to that of the first NMOS tube and equal to that of the second NMOS tube.

11. The comparator circuit according to claim 8, characterized in that: There are two diodes, and the size of the diode close to the second regulating voltage is equal to the size of the first load tube and the size of the second load tube.

12. An image sensor, comprising a pixel circuit, a programmable gain amplifier, and a column analog-to-digital converter, wherein one end of the programmable gain amplifier is connected to the pixel circuit, and the other end of the programmable gain amplifier is connected to the column analog-to-digital converter, characterized in that: The column analog-to-digital converter comprises the comparator circuit as claimed in any one of claims 1 to 5, or the column analog-to-digital converter comprises the comparator circuit as claimed in any one of claims 6 to 11.

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