Method for manufacturing a semiconductor memory and semiconductor memory

Abstract

The present invention provides a manufacturing method of a semiconductor memory and a semiconductor memory, relating to the technical field of storage devices, and is used to solve the technical problem of low yield of the memory. The manufacturing method of the semiconductor memory includes: providing a substrate, in which a plurality of spaced active regions are provided, and the active region includes a first contact region and a second contact region; forming a protrusion on each second contact region; forming a plurality of spaced bit line structures on the substrate; forming a first isolation layer covering the bit line structures and the substrate, and each filling hole of the first isolation layer exposes a protrusion, and the surface area of the protrusion exposed in the filling hole is larger than the overlapping area of the positive projection of the filling hole on the substrate and the second contact region; forming a wire in the filling hole, and the wire is electrically connected to the protrusion. By forming a protrusion on the substrate and electrically connecting the protrusion to the wire, while increasing the contact area between the wire and the protrusion, the depth of the filling hole is reduced, and there are fewer holes or gaps in the wire formed in the filling hole.

Description

Technical Field

[0001] The present invention relates to the technical field of storage devices, and in particular, to a manufacturing method of a semiconductor memory and a semiconductor memory. Background Art

[0002] Dynamic random access memory (DRAM) is a semiconductor memory that writes and reads data at high speed and randomly, and is widely used in data storage devices or apparatuses. A dynamic random access memory generally consists of multiple memory cells. Each memory cell usually includes a capacitor and a transistor. The capacitor stores data information, and the transistor controls the reading and writing of the data information in the capacitor.

[0003] In related technologies, a dynamic random access memory includes a substrate. The substrate includes an active region. The active region includes a first contact region and a second contact region. A bit line structure arranged at intervals and an isolation layer covering the bit line structure are provided on the substrate. The bit line structure is electrically connected to the first contact region of the active region. A contact hole is formed in the isolation layer, and a wire is filled in the contact hole. The wire is used to electrically connect the capacitor to the second contact region of the active region.

[0004] In order to increase the contact area between the wire and the second contact region, the contact hole usually extends into the substrate to increase the surface area of the second contact region exposed in the contact hole. However, during the manufacturing process of the dynamic random access memory, the wire filled in the contact hole is prone to holes or gaps, which affects the yield of the memory. Summary of the Invention

[0005] In view of the above problems, embodiments of the present invention provide a manufacturing method of a semiconductor memory and a semiconductor memory, which are used to reduce holes or gaps in the wire and improve the yield of the memory.

[0006] To achieve the above object, embodiments of the present invention provide the following technical solutions:

[0007] In a first aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor memory, which includes: providing a substrate, in which a plurality of spaced active regions are provided, the active regions include a first contact region and a second contact region located outside the first contact region, and the second contact region is exposed on the surface of the substrate; forming a protrusion on each of the second contact regions; forming a plurality of spaced bit line structures on the substrate, and each of the bit line structures is electrically connected to at least one of the first contact regions; forming a first isolation layer covering the bit line structures and the substrate, in which a plurality of filling holes are provided, each of the filling holes exposes a protrusion, and the surface area of the protrusion exposed in the filling hole is greater than the overlapping area of the orthographic projection of the filling hole on the substrate and the second contact region; forming a wire in the filling hole, and the wire is electrically connected to the protrusion.

[0008] The method for manufacturing a semiconductor memory provided by the embodiment of the present invention has the following advantages:

[0009] In the method for manufacturing a memory in the embodiment of the present invention, first, a substrate is provided, in which a plurality of spaced active regions are provided, the active regions include a first contact region and a second contact region located outside the first contact region, and the second contact region is exposed on the surface of the substrate; a protrusion is formed on each of the second contact regions; a plurality of spaced bit line structures are formed on the substrate, and each of the bit line structures is electrically connected to at least one of the first contact regions; a first isolation layer covering the bit line structures and the substrate is formed, in which a plurality of filling holes are provided, each of the filling holes exposes a protrusion, and the surface area of the protrusion exposed in the filling hole is greater than the overlapping area of the orthographic projection of the filling hole on the substrate and the second contact region; a wire is formed in the filling hole, and the wire is electrically connected to the protrusion. By forming a protrusion on the second contact region, and the surface area of the protrusion exposed in the filling hole is greater than the overlapping area of the orthographic projection of the filling hole on the substrate and the second contact region, the contact area between the wire formed in the filling hole and the protrusion is large, reducing the contact resistance between the wire and the protrusion. In addition, a protrusion located on the substrate is formed in the filling hole, so that the depth of the filling hole is reduced compared with the related art, so that when a wire is formed in the filling hole, there are fewer holes or gaps in the wire, improving the formation quality of the wire, and further improving the yield of the memory.

[0010] In the method for manufacturing a semiconductor memory as described above, the bit line structure extends in a first direction; taking a plane parallel to the first direction as a cross section, the cross-sectional shape of the protrusion is a bow shape.

[0011] In the method for manufacturing a semiconductor memory as described above, the orthographic projection of the protrusion on the substrate at least covers the second contact region.

[0012] In the method for manufacturing the semiconductor memory as described above, the distance between the edge of the orthographic projection of the protrusion on the substrate and the edge of the second contact region is 3 - 5 nm.

[0013] In the method for manufacturing the semiconductor memory as described above, the step of forming a protrusion on each of the second contact regions includes: epitaxially growing on each of the second contact regions to form the protrusion.

[0014] In the method for manufacturing the semiconductor memory as described above, the material of the protrusion is the same as that of the active region, the protrusion and the active region are doped with a preset ion, and the doping concentration of the protrusion is greater than that of the active region.

[0015] In the method for manufacturing the semiconductor memory as described above, the first contact region is exposed on the surface of the substrate; while forming a protrusion on each of the second contact regions, a protrusion is also formed on each of the first contact regions.

[0016] In the method for manufacturing the semiconductor memory as described above, a word line structure extending in the second direction is further formed in the substrate, the word line structure separates the first contact region and the second contact region of each active region, and the first contact regions and the second contact regions are arranged in a dot matrix pattern.

[0017] In the method for manufacturing the semiconductor memory as described above, the step of forming a plurality of spaced bit line structures on the substrate, each bit line structure connecting at least one of the first contact regions includes: forming a stacked first insulating layer, a second isolation layer, and a first conductive layer on the substrate, the first insulating layer covering the protrusion; forming a bit line contact window in the first conductive layer, the second isolation layer, and the first insulating layer, the bit line contact window penetrating through the first conductive layer, the second isolation layer, and the first insulating layer and extending to the substrate, the bit line contact window exposing the first contact region; forming a bit line contact in the bit line contact window, and removing the first conductive layer and the bit line contact on the second isolation layer, the remaining bit line contact being flush with the second isolation layer; forming a stacked second conductive layer and a third isolation layer on the bit line contact and the second isolation layer, the second conductive layer covering the bit line contact and the second isolation layer; etching the third isolation layer, the second conductive layer, the second isolation layer, and the bit line contact to form a bit line structure extending in the first direction, and the bit line structure passing through a plurality of the first contact regions located in the first direction.

[0018] In the method for manufacturing the semiconductor memory as described above, the second conductive layer includes a titanium layer formed on the bit line contact, a metal compound layer formed on the titanium layer, and a tungsten layer formed on the metal compound layer.

[0019] In the method for manufacturing a semiconductor memory as described above, the step of forming a first isolation layer covering the bit line structure and the substrate, with a plurality of filling holes provided in the first isolation layer, each filling hole exposing one of the protrusions, and the surface area of the protrusion exposed in the filling hole being greater than the overlapping area of the orthographic projection of the filling hole on the substrate and the second contact region includes: depositing the first isolation layer on the bit line structure, the first isolation layer covering the bit line structure and the first insulating layer; etching the first isolation layer to form the filling holes, the filling holes penetrating through the first isolation layer and opposite to the protrusions; etching the first insulating layer along the filling holes, the filling holes penetrating through the first insulating layer to expose the protrusions with the filling holes.

[0020] In the method for manufacturing a semiconductor memory as described above, the step of forming a wire in the filling hole, the wire being electrically connected to the protrusion includes: depositing a third conductive layer in the filling hole and on the first isolation layer, the third conductive layer filling the filling hole and covering the first isolation layer; etching the third conductive layer to remove the third conductive layer on the first isolation layer and a part of the third conductive layer in the filling hole, and the remaining third conductive layer forms the wire.

[0021] In the method for manufacturing a semiconductor memory as described above, after the step of forming a wire in the filling hole, the wire being electrically connected to the protrusion, the method for manufacturing the memory further includes: forming contact pads on the wires in each filling hole, the plurality of contact pads being spaced apart, and each contact pad being partially located in the filling hole and partially located on the first isolation layer.

[0022] In a second aspect, an embodiment of the present invention provides a semiconductor memory, which includes: a substrate, with a plurality of spaced active regions provided in the substrate, the active regions including a first contact region and a second contact region located outside the first contact region; a plurality of spaced bit line structures provided on the substrate, each bit line structure being electrically connected to at least one of the first contact regions; protrusions provided on the second contact region; a first isolation layer covering the bit line structures, the protrusions and the substrate, the first isolation layer being provided with a plurality of filling holes, the plurality of filling holes extending to the protrusions; wires provided in the filling holes, the wires being electrically connected to the protrusions, and the contact area between the wires and the protrusions being greater than the overlapping area of the orthographic projection of the filling holes on the substrate and the second contact region.

[0023] The semiconductor memory according to the embodiment of the present invention has the following advantages:

[0024] The memory in the embodiments of the present invention includes: a substrate, a bit line structure, a first isolation layer, and a wire; wherein, a plurality of spaced active regions are provided in the substrate, the active region includes a first contact region and a second contact region, the second contact region is located outside the first contact region, and a protrusion is provided on the second contact region; the bit line structure is provided on the substrate, and each of the plurality of spaced bit line structures is electrically connected to at least one first contact region; the first isolation layer is provided on the substrate and covers the bit line structure, the protrusion, and the substrate, and a plurality of filling holes are provided in the first isolation layer, and the protrusion is exposed in the filling holes; the wire is provided in the filling holes and is electrically connected to the protrusion, and the contact area between the wire and the protrusion is greater than the overlapping area of the orthographic projection of the filling hole on the substrate and the second contact region, so that the contact area between the wire and the protrusion is greater than the overlapping area between the wire and the second contact region when the protrusion is not provided, reducing the contact resistance between the wire and the protrusion. In addition, a protrusion located on the substrate is formed in the filling hole, so that the depth of the filling hole is reduced compared with the related art, so that there are fewer holes or gaps in the wire provided in the filling hole, improving the formation quality of the wire, and further improving the yield of the memory.

[0025] In the semiconductor memory as described above, the bit line structure extends in a first direction; taking a plane parallel to the first direction as a cross section, the cross-sectional shape of the protrusion is a bow shape.

[0026] In the semiconductor memory as described above, the orthographic projection of the protrusion on the substrate at least covers the second contact region. Description of the Drawings

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0028] Figure 1 It is a schematic structural diagram of a semiconductor memory in the related art;

[0029] Figure 2 It is a flowchart of the manufacturing method of the semiconductor memory in the embodiments of the present invention;

[0030] Figure 3 It is a top view of the substrate in the embodiments of the present invention;

[0031] Figure 4 It is a top view of the word line structure in the embodiments of the present invention;

[0032] Figure 5 It is a schematic structural diagram of the substrate in the embodiments of the present invention;

[0033] Figure 6 The top view after forming the protrusion in the embodiment of the present invention;

[0034] Figure 7 The structural schematic diagram after forming the protrusion in the embodiment of the present invention;

[0035] Figure 8 The structural schematic diagram after forming the bit line structure in the embodiment of the present invention;

[0036] Figure 9 The structural schematic diagram after forming the first isolation layer in the embodiment of the present invention;

[0037] Figure 10 The structural schematic diagram after forming the filling hole in the embodiment of the present invention;

[0038] Figure 11 The structural schematic diagram after forming the third conductive layer in the embodiment of the present invention;

[0039] Figure 12 The structural schematic diagram after forming the wire in the embodiment of the present invention;

[0040] Figure 13 The structural schematic diagram after forming the fifth conductive layer in the embodiment of the present invention;

[0041] Figure 14 The structural schematic diagram after forming the contact pad in the embodiment of the present invention;

[0042] Figure 15 The flowchart of forming the bit line structure in the embodiment of the present invention;

[0043] Figure 16 The structural schematic diagram after forming the first conductive layer in the embodiment of the present invention;

[0044] Figure 17 The structural schematic diagram after forming the bit line contact window in the embodiment of the present invention;

[0045] Figure 18 The structural schematic diagram after forming the bit line contact in the embodiment of the present invention;

[0046] Figure 19 The top view after forming the bit line contact in the embodiment of the present invention.

[0047] Explanation of reference numerals:

[0048] 100 - Substrate; 110 - Active region;

[0049] 111 - First contact region; 112 - Second contact region;

[0050] 120 - Shallow trench isolation structure; 130 - Word line structure;

[0051] 131 - Second insulating layer; 132 - Fourth conductive layer;

[0052] 133 - Capping layer; 200 - Protrusion;

[0053] 300 - First insulating layer; 400 - Bit line structure;

[0054] 410 - Second isolation layer; 420 - First conductive layer;

[0055] 430 - Bit line contact window; 440 - Bit line contact;

[0056] 450 - Second conductive layer; 460 - Third isolation layer;

[0057] 500 - First isolation layer; 510 - Filling hole;

[0058] 520 - Third conductive layer; 530 - Conducting wire;

[0059] 600 - Fifth conductive layer; 610 - Contact pad. Detailed implementation manners

[0060] In the related art, referring to Figure 1 , during the process of manufacturing a semiconductor memory, after forming a filling hole 510 in the first isolation layer 500, the substrate is etched along the filling hole 510 so that the bottom of the filling hole 510 is located within the substrate; then a conducting wire 530 is formed in the filling hole 510. When depositing and forming the conducting wire 530 in the filling hole 510, the depth of the filling hole 510 is relatively large, and holes or gaps are likely to be formed in the conducting wire 530, such as Figure 1 the area indicated by the dash-dotted circle in the middle. The existence of holes or gaps will affect the ability of the conducting wire 530 to transfer charges, resulting in a reduction in the performance of the semiconductor memory and even affecting the yield rate of the semiconductor memory.

[0061] In view of this, an embodiment of the present invention provides a method for manufacturing a semiconductor memory, which includes forming a protrusion on a region (second contact region) of the substrate corresponding to the filling hole; then forming a first isolation layer covering the substrate and the protrusion, the first isolation layer having a filling hole, the filling hole exposing the protrusion, and the surface area of the protrusion exposed in the filling hole being greater than the overlapping area of the orthographic projection of the filling hole on the substrate and the second contact region; and then forming a wire in the filling hole. The contact area between the wire and the protrusion is greater than the overlapping area between the wire and the second contact region when no protrusion is provided, reducing the contact resistance between the wire and the protrusion. In addition, a protrusion located on the substrate is formed in the filling hole, so that the depth of the filling hole is reduced compared with the related art, thereby reducing the holes or gaps of the wire provided in the filling hole, improving the formation quality of the wire, and further improving the yield of the memory.

[0062] In order to make the above objects, features, and advantages of the embodiments of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0063] Embodiment 1

[0064] Refer to Figure 2 An embodiment of the present invention provides a method for manufacturing a semiconductor memory, which includes the following steps:

[0065] Step S101: Provide a substrate, in which a plurality of spaced active regions are provided. The active regions include a first contact region and a second contact region located outside the first contact region, and the second contact region is exposed on the surface of the substrate.

[0066] Refer to Figure 3 The substrate 100 is used to support each film layer thereon. A source region 110 is provided in the substrate 100. The number of active regions 110 can be set to be multiple. As Figure 3 shown, a plurality of active regions 110 are arranged in an array. It can be understood that the central regions of the plurality of active regions 110 are arranged in a dot matrix.

[0067] A plurality of active regions 110 are arranged at intervals. For example, a Shallow Trench Isolation (STI) structure 120 is arranged between the active regions 110, and the plurality of active regions 110 are separated by the shallow trench isolation structure 120. The substrate 100 may be a semiconductor substrate, such as a silicon substrate, a germanium substrate, a silicon carbide (SiC) substrate, a silicon germanium (SiGe) substrate, or a Silicon on Insulator (SOI) substrate.

[0068] A trench is formed in the substrate 100 through a patterning process, and an insulating material (such as silicon oxide or silicon oxynitride) is filled in the trench, so as to define a plurality of active regions 110 separated by the shallow trench isolation structure 120 on the substrate 100. Exemplarily, the patterning process may be a Self-Aligned Double Patterning (SADP) process or a Self-Aligned Quadruple Patterning (SAQP) process.

[0069] Continue to refer to Figure 3 , the active region 110 is arranged obliquely and extends along the Figure 3 D direction shown in Figure 3 . The active region 110 includes a first contact region 111 and a second contact region 112. The second contact region 112 is located outside the first contact region 111. The first contact region 111 and the second contact region 112 are exposed on the surface of the substrate 100. The first contact region 111 is used for electrically connecting to the bit line structure, and the second contact region 112 is used for electrically connecting to the capacitor. Exemplarily, as shown in

[0070] Figure 4 Figure 5 Figure 5 Figure 4

[0071] Figure 4 Figure 4 shown, the first contact region 111 is located in the middle region of the active region 110, and the second contact region 112 is located in the edge region of the active region 110, that is, one second contact region 112 may be arranged on each side of the first contact region 111.

[0070] It should be noted that referring to Figure 4 and Figure 5 Figure 5 Figure 4

[0071] Figure 4 Figure 4 shown, the cross-section is a plane perpendicular to the X direction in Figure 4 . A word line structure 130 is further arranged in the substrate 100. The word line structure 130 is usually a Buried Word Line (BWL) structure 130. Multiple buried word line structures 130 may be arranged. The multiple buried word line structures 130 extend along the second direction and cross the active region 110, so as to separate the first contact region 111 and the second contact region 112 of the active region 110.

[0071] Figure 4 Figure 4As shown by the area enclosed by the center dash-dot line, which extends in the X direction, each embedded word line structure 130 passes through multiple active regions 110 in the same row, and each active region 110 corresponds to two embedded word line structures 130. Figure 4 The area shown by the dashed line in the middle is an active region 110. Two embedded word line structures 130 divide the active region 110 into a first contact region 111 at the center and two second contact regions 112 on both sides.

[0072] As Figure 4 and Figure 5 shown, the embedded word line structure 130 includes a second insulating layer 131, a fourth conductive layer 132, and a capping layer 133. Among them, the second insulating layer 131 is in contact with the active region 110. The second insulating layer 131 encloses a filling groove, and the fourth conductive layer 132 and the capping layer 133 on the fourth conductive layer 132 are arranged in the filling groove. The upper surface of the capping layer 133 is flush with the upper surface of the substrate 100. As Figure 4 shown in the top view, the upper surfaces of the capping layer 133 and the second insulating layer 131 are exposed, and the capping layer 133 is located in the middle of the second insulating layer 131. The material of the second insulating layer 131 includes silicon oxide, the material of the fourth conductive layer 132 includes one or more of titanium, tantalum, titanium nitride, tungsten nitride, tantalum nitride, tungsten silicon nitride compound, and the material of the capping layer 133 includes silicon nitride.

[0073] Step S102: Form a protrusion on each second contact region.

[0074] Referring to Figure 6 , there are multiple protrusions 200, and the multiple protrusions 200 correspond one-to-one to the multiple second contact regions 112, that is, one protrusion 200 is formed on each second contact region 112. The orthographic projection of the protrusion 200 on the substrate 100 at least covers the second contact region 112, that is, the second contact region 112 is located within the orthographic projection of the protrusion 200 on the substrate 100. As Figure 6 shown in the top view, the second contact region 112 is a dashed line, that is, the second contact region 112 is located below the protrusion 200 and the second contact region 112 is not exposed.

[0075] Exemplarily, the orthographic projection of the protrusion 200 on the substrate 100 has the same shape as the second contact region 112, for example, both are parallelograms. As Figure 7 shown, the distance L between the edge of the orthographic projection of the protrusion 200 on the substrate 100 and the edge of the second contact region 112 is 3 - 5 nm.

[0076] In some possible examples, referring to Figure 7 , Figure 7 the shown plane is perpendicular to the extending direction of the word line structure 130 ( Figure 6The cross-section in the X direction) is such that the surface of the protrusion 200 facing away from the substrate 100 is a curved surface, ensuring that the surface area of the surface of the protrusion 200 facing away from the substrate 100 is larger than the surface area of the second contact region 112 exposed to the substrate 100, so that a larger contact area is formed between the subsequently formed wire 530 and the protrusion 200, thereby reducing the contact resistance between the wire 530 and the protrusion 200. As Figure 7 shown, the surface of the protrusion 200 facing away from the substrate 100 is arc-shaped. Exemplarily, the cross-sectional shape of the protrusion 200 is a bow shape, a semi-circular shape, or a semi-elliptical shape.

[0077] The protrusion 200 can be formed by epitaxial growth on the second contact region 112, that is, one protrusion 200 is formed by epitaxial growth on each second contact region 112. Through epitaxial growth, the protrusion 200 can be made different from the second contact region 112 in terms of conduction type, resistivity, type and concentration of doped ions, etc. Exemplarily, the material of the protrusion 200 and the active region 110 can be the same, for example, both are silicon. The protrusion 200 and the active region 110 are doped with preset ions, and the preset ions in the protrusion 200 and the preset ions in the active region 110 can be of the same type. For example, the preset ions are one of N-type ions or P-type ions. The doping concentration of the protrusion 200 is greater than the doping concentration of the active region 110, so that the contact resistance of the electrical contact between the wire 530 and the protrusion 200 is reduced compared to the electrical contact between the wire 530 and the second contact region 112 of the active region 110.

[0078] It should be noted that, as Figure 6 and Figure 7 shown, when both the first contact region 111 and the second contact region 112 are exposed on the surface of the substrate 100, while forming the protrusion 200 on each second contact region 112, the protrusion 200 is also formed on each first contact region 111, that is, the protrusion 200 is formed on both the first contact region 111 and the second contact region 112 simultaneously, so as to reduce the difficulty of forming the protrusion 200 and facilitate the fabrication of the semiconductor memory. As Figure 6 shown, after the protrusion 200 is formed, the protrusions 200 are arranged in a dot matrix.

[0079] Step S103: Form a plurality of bit line structures arranged at intervals on the substrate, and each bit line structure is electrically connected to at least one first contact region.

[0080] Referring to Figure 8 , a plurality of bit line (Bit Line, abbreviated as BL) structures are formed on the substrate 100. The plurality of bit line structures 400 are parallel to each other and extend along the first direction, and each bit line is electrically connected to at least one first contact region 111. As Figure 8 shown, the bit line structure 400 extends in a direction perpendicular to the plane of the paper ( Figure 6extends in the Y direction (as shown), and each bit line structure 400 is in contact with the first contact regions 111 of a plurality of active regions 110 located in the same column (as shown by the dashed line), and the first contact region 111 of each active region 110 corresponds to one bit line structure 400. By contacting the bit line structure 400 with the first contact region 111, the bit line structure 400 is electrically connected to the first contact region 111. Figure 6 as shown by the dashed line

[0081] It can be understood that the first direction and the second direction can be perpendicular to each other. For example, in the top view as shown, Figure 6 the first direction is the vertical direction (Y direction), the second direction is the horizontal direction (X direction), and the active regions 110 are inclined. Referring to Figures 6 to 8 , the word line structure 130 is located in the substrate 100 and passes through the active regions 110 along the second direction; the bit line structure 400 is located on the substrate 100 and contacts the active regions 110 along the first direction. A first insulating layer 300 is provided between the bit line structure 400 and other regions of the substrate 100 to ensure that the bit line structure 400 is only electrically connected to the first contact regions 111.

[0082] The bit line structure 400 can be formed by a deposition process. For example, the bit line structure 400 is formed by a chemical vapor deposition (CVD for short), physical vapor deposition (PVD for short), or atomic layer deposition (ALD for short) process.

[0083] Step S104: Form a first isolation layer covering the bit line structure and the substrate. The first isolation layer is provided with a plurality of filling holes, each filling hole exposes a protrusion, and the surface area of the protrusion exposed in the filling hole is larger than the overlapping area of the orthographic projection of the filling hole on the substrate and the second contact region.

[0084] Referring to Figure 9 , the first isolation layer 500 is disposed on the substrate 100 and covers the bit line structure 400, supports and isolates the bit line structure 400, and serves as the matrix of the filling holes 510. The material of the first isolation layer 500 can be an insulating material, such as silicon nitride, etc.

[0085] Referring to Figure 10, a plurality of filling holes 510 are formed in the first isolation layer 500. The plurality of filling holes 510 are arranged at intervals, and each filling hole 510 exposes a protrusion 200, that is, there is a one-to-one correspondence between the plurality of filling holes 510 and the plurality of protrusions 200. The surface area of the protrusion 200 exposed in the filling hole 510 is greater than the overlapping area of the orthographic projection of the filling hole 510 on the substrate 100 and the second contact area 112, so that a larger contact area is formed between the subsequent formed wire 530 and the protrusion 200, improving the electrical performance between the wire 530 and the protrusion 200.

[0086] In some possible examples, the steps of forming the first isolation layer 500 covering the bit line structure 400 and the substrate 100, with a plurality of filling holes 510 provided in the first isolation layer 500, and each filling hole 510 exposing a protrusion 200, and the surface area of the protrusion 200 exposed in the filling hole 510 being greater than the overlapping area of the orthographic projection of the filling hole 510 on the substrate 100 and the second contact area 112 include:

[0087] Deposit the first isolation layer 500 on the bit line structure 400. The first isolation layer 500 covers the bit line structure 400 and the first insulating layer 300. The first isolation layer 500 covers the bit line structure 400, and the surface of the first isolation layer 500 facing away from the substrate 100 is flush.

[0088] After depositing the first isolation layer 500 on the bit line structure 400, etch the first isolation layer 500 to form filling holes 510. The filling holes 510 penetrate through the first isolation layer 500 and are opposite to the protrusions 200.

[0089] After forming the filling holes 510, etch the first insulating layer 300 along the filling holes 510. The filling holes 510 penetrate through the first insulating layer 300 to expose the protrusions 200. Using the protrusions 200 as an etching stop layer, etch the first insulating layer 300 along the filling holes 510. The bottom of the filling holes 510 is the surface of the protrusions 200. For example, a partial curved surface of the protrusions 200 exposed in the filling holes 510, and the exposed surface area of the protrusions 200 is greater than the cross-sectional area of the filling holes 510.

[0090] Step S105, form a wire in the filling hole, and the wire is electrically connected to the protrusion.

[0091] Refer to Figures 11 to 12 , the wire 530 fills the filling hole 510 and is in contact with the protrusion 200. Both the wire 530 and the protrusion 200 are made of conductive materials, and electrical connection between the two is achieved through contact. In some possible examples, the steps of forming the wire 530 in the filling hole 510 and the wire 530 being electrically connected to the protrusion 200 include:

[0092] Deposit a third conductive layer 520 in the filling hole 510 and on the first isolation layer 500. The third conductive layer 520 fills the filling hole 510 and covers the first isolation layer 500. As Figure 11 shown, the third conductive layer 520 covers the first isolation layer 500 and the substrate 100, and the top surface of the third conductive layer 520 is higher than the top surface of the first isolation layer 500, wherein the height direction refers to the direction away from the substrate 100. The material of the third conductive layer 520 can be polysilicon.

[0093] After depositing the third conductive layer 520, etch the third conductive layer 520 to remove the third conductive layer 520 on the first isolation layer 500 and a part of the third conductive layer 520 in the filling hole 510. The remaining third conductive layer 520 forms a wire 530. As Figure 12 shown, by depositing the third conductive layer 520 and performing a back-etch on the third conductive layer 520 to remove a part of the third conductive layer 520, the remaining third conductive layer 520 forms a plurality of spaced-apart wires 530, and the top surface of the wire 530 is lower than the surface of the first isolation layer 500.

[0094] It should be noted that referring to Figure 13 and Figure 14 , after forming a wire 530 in the filling hole 510 and the wire 530 is electrically connected to the protrusion 200, the manufacturing method of the semiconductor memory further includes: forming a contact pad 610 on the wire 530 in each filling hole 510. The plurality of contact pads 610 are spaced apart, and each contact pad 610 is partially located in the filling hole 510 and partially located on the first isolation layer 500.

[0095] As Figure 13 shown, form a fifth conductive layer 600 in the remaining filling holes 510 and on the first isolation layer 500. The fifth conductive layer 600 fills the remaining filling holes 510 and covers the first isolation layer 500. The fifth conductive layer 600 includes a cobalt silicide layer, a titanium nitride layer, and a tungsten layer that are sequentially stacked. Then etch the fifth conductive layer 600 on the first isolation layer 500 to form a plurality of spaced-apart contact pads 610. As Figure 14 shown, the lower part of the contact pad 610 is located in the filling hole 510, the upper part of the contact pad 610 is located on the first isolation layer 500, and there is a gap between the respective contact pads 610 to electrically isolate the contact pads 610 from each other.

[0096] In the manufacturing method of the memory in the embodiments of the present invention, first, a substrate 100 is provided. A plurality of spaced active regions 110 are provided in the substrate 100. The active region 110 includes a first contact region 111 and a second contact region 112 located outside the first contact region 111. The second contact region 112 is exposed on the surface of the substrate 100; a protrusion 200 is formed on each second contact region 112; a plurality of spaced bit line structures 400 are formed on the substrate 100, and each bit line structure 400 is electrically connected to at least one first contact region 111; a first isolation layer 500 covering the bit line structures 400 and the substrate 100 is formed. A plurality of filling holes 510 are provided in the first isolation layer 500. Each filling hole 510 exposes a protrusion 200, and the surface area of the protrusion 200 exposed in the filling hole 510 is larger than the overlapping area of the orthographic projection of the filling hole 510 on the substrate 100 and the second contact region 112; a wire 530 is formed in the filling hole 510, and the wire 530 is electrically connected to the protrusion 200. By forming the protrusion 200 on the second contact region 112, and the surface area of the protrusion 200 exposed in the filling hole 510 is larger than the overlapping area of the orthographic projection of the filling hole 510 on the substrate 100 and the second contact region 112, the contact area between the wire 530 formed in the filling hole 510 and the protrusion 200 is larger, reducing the contact resistance between the wire 530 and the protrusion 200. In addition, there is a protrusion 200 on the substrate 100 formed in the filling hole 510, so that the depth of the filling hole 510 is reduced compared with the related art. Thus, when the wire 530 is formed in the filling hole 510, there are fewer holes or gaps in the wire 530, improving the formation quality of the wire 530, and further improving the yield of the memory.

[0097] It should be noted that, referring to Figure 15 , the step of forming a plurality of spaced bit line structures 400 on the substrate 100, and each bit line structure 400 is at least connected to one first contact region 111 includes:

[0098] Step S1031: A first insulating layer, a second isolation layer and a first conductive layer are stacked on the substrate, and the first insulating layer covers the protrusion.

[0099] Referring to Figure 16 , a first insulating layer 300 is deposited on the substrate 100, and the first insulating layer 300 covers the protrusion 200; then a second isolation layer 410 is deposited on the first insulating layer 300; and then a first conductive layer 420 is deposited on the second isolation layer 410. The first insulating layer 300, the second isolation layer 410 and the first conductive layer 420 are stacked. The material of the first insulating layer 300 includes silicon oxide, the material of the second isolation layer 410 includes silicon nitride, and the material of the first conductive layer includes polysilicon.

[0100] Step S1032: A bit line contact window is formed within the first conductive layer, the second isolation layer, and the first insulating layer. The bit line contact window penetrates through the first conductive layer, the second isolation layer, and the first insulating layer and extends to the substrate, and the bit line contact window exposes the first contact region.

[0101] Referring Figure 17 , the bottom of the bit line contact window 430 is located in the substrate 100 and exposes the first contact region 111. The remaining first conductive layer 420, second isolation layer 410, and first insulating layer 300 form a plurality of cylindrical protrusions, which are arranged at intervals, and the bit line contact window 430 surrounds each cylindrical protrusion.

[0102] Step S1033: A bit line contact is formed within the bit line contact window, and the first conductive layer and the bit line contact on the second isolation layer are removed, and the remaining bit line contact is flush with the second isolation layer.

[0103] Referring Figure 18 and Figure 19 , the bit line contact 440 (Bit Line Contact, abbreviated as BLC) is filled in the bit line contact window 430, and the material of the bit line contact 440 can be polysilicon. After removing the first conductive layer 420 and a part of the bit line contact 440 on the second isolation layer 410, the top surface of the remaining bit line contact 440 is flush with the top surface of the second isolation layer 410, so as to facilitate the formation of a relatively flat other film layer thereon.

[0104] Step S1034: A stacked second conductive layer and third isolation layer are formed on the bit line contact and the second isolation layer, and the second conductive layer covers the bit line contact and the second isolation layer.

[0105] A second conductive layer 450 is deposited on the remaining bit line contact 440 and the second isolation layer 410, and the second conductive layer 450 covers the bit line contact 440 and the second isolation layer 410; then a third isolation layer 460 is deposited on the second conductive layer 450, and the material of the third isolation layer 460 can include silicon nitride.

[0106] In some possible examples, the second conductive layer 450 includes a titanium layer, a metal compound layer, and a tungsten layer, and the titanium layer, the metal compound layer, and the tungsten layer are stacked in sequence, and the titanium layer is in contact with the bit line contact 440. The material of the metal compound layer can be cobalt silicide. For example, metal cobalt is deposited on the bit line contact 440, and metal cobalt is combined with silicon in the bit line contact 440 under high-temperature conditions to generate cobalt silicide to improve the electrical performance of the second conductive layer 450.

[0107] Step S1035: The third isolation layer, the second conductive layer, the second isolation layer, and the bit line contact are etched to form a bit line structure extending in the first direction, and the bit line structure passes through a plurality of first contact regions located in the first direction.

[0108] Etch the third isolation layer 460, the second conductive layer 450, the second isolation layer 410, and the bit line contact 440 to form Figure 8 the bit line structure 400 as shown. The bit line structure 400 extends along the first direction. The bit line structure 400 is in contact with a plurality of active regions 110 located in the same row or the same column through the bit line contact 440. In one bit line structure 400, part of the region is in contact with the first contact region 111, and another part of the region is in contact with the first insulating layer 300. That is, along the extension direction of the bit line structure 400, the first contact region 111 and the first insulating layer 300 alternately contact the bit line structure 400.

[0109] Embodiment 2

[0110] Referring to Figures 1 to 14 , an embodiment of the present invention provides a semiconductor memory, which includes a substrate 100 for supporting the film layers thereon. Active regions 110 are provided in the substrate 100. The number of active regions 110 can be set to be multiple, and the multiple active regions 110 are spaced apart. For example, a shallow trench isolation structure is provided between the active regions 110 to separate the multiple active regions 110 through the shallow trench isolation structure 120.

[0111] The active region 110 includes a first contact region 111 and a second contact region 112. The second contact region 112 is located outside the first contact region 111, and the first contact region 111 and the second contact region 112 are exposed on the surface of the substrate 100. The first contact region 111 is used for electrically connecting the bit line structure 400, and the second contact region 112 is used for electrically connecting the capacitor. Exemplarily, the first contact region 111 is located in the middle region of the active region 110, and the second contact region 112 is located in the edge region of the active region 110. That is, one second contact region 112 can be provided on each side of the first contact region 111.

[0112] A word line structure 130 is also provided in the substrate 100. The word line structure 130 is usually an embedded word line structure 130. Multiple embedded word line structures 130 can be provided. The multiple embedded word line structures 130 extend along the second direction ( Figure 6 the X direction shown) and span across the active region 110, thereby separating the first contact region 111 and the second contact region 112 of the active region 110.

[0113] Protrusions 200 are provided on the second contact region 112 of the substrate 100. The number of protrusions 200 is multiple, and the multiple protrusions 200 correspond to the multiple second contact regions 112 one by one. That is, one protrusion 200 is formed on each second contact region 112. The positive projection of the protrusion 200 on the substrate 100 at least covers the second contact region 112. That is, the second contact region 112 is located within the positive projection of the protrusion 200 on the substrate 100.

[0114] Exemplarily, taking the plane parallel to the first direction ( Figure 6 the shown Y direction) as the cross-section, the cross-sectional shape of the protrusion 200 is a bow shape. The first direction is the extending direction of the bit line structure 400 disposed on the substrate 100. The orthographic projection of the protrusion 200 on the substrate 100 has the same shape as that of the second contact region 112, for example, both are parallelograms, and the distance L between the edge of the orthographic projection of the protrusion 200 on the substrate 100 and the edge of the second contact region 112 is 3 - 5 nm.

[0115] In some possible examples, the surface of the protrusion 200 facing away from the substrate 100 is a curved surface, so as to ensure that the surface area of the surface of the protrusion 200 facing away from the substrate 100 is larger than the surface area of the second contact region 112 exposed on the substrate 100, so that the subsequent formed wire 530 and the protrusion 200 have a larger contact area, reducing the contact resistance between the wire 530 and the protrusion 200.

[0116] A plurality of spaced bit line structures 400 are provided on the substrate 100. The plurality of bit line structures 400 are parallel to each other and extend along the first direction, and each bit line is electrically connected to at least one first contact region 111. The bit line structure 400 is in contact with the first contact region 111, thereby electrically connecting the bit line structure 400 and the first contact region 111.

[0117] The bit line structure 400 includes a third isolation layer 460, a second conductive layer 450, a second isolation layer 410, and a bit line contact 440. The bit line contact 440 and the second isolation layer 410 are alternately arranged. The bit line contact 440 is in contact with the first contact region 111, and the second isolation layer 410 is in contact with the first insulating layer 300. The top surface of the bit line contact 440 is flush with the top surface of the second isolation layer 410. The second conductive layer 450 is disposed on the bit line contact 440 and the second isolation layer 410, and the third isolation layer 460 is disposed on the second conductive layer 450.

[0118] In some possible examples, the second conductive layer 450 includes a titanium layer, a metal compound layer, and a tungsten layer. The titanium layer, the metal compound layer, and the tungsten layer are stacked in sequence, and the titanium layer is in contact with the bit line contact 440. The material of the metal compound layer can be metal silicide.

[0119] The first isolation layer 500 is disposed on the substrate 100 and covers the bit line structure 400, supports and isolates the bit line structure 400, and serves as the matrix for the filling holes 510. The material of the first isolation layer 500 can be an insulating material, such as silicon nitride, etc. A plurality of filling holes 510 are formed in the first isolation layer 500. The plurality of filling holes 510 are spaced apart, and each filling hole 510 exposes a protrusion 200, that is, there is a one-to-one correspondence between the plurality of filling holes 510 and the plurality of protrusions 200.

[0120] The wire 530 is filled in the filling hole 510, and the top surface of the wire 530 is lower than the top surface of the first isolation layer 500. The wire 530 is in contact with the protrusion 200. Both the wire 530 and the protrusion 200 are made of conductive materials, and the electrical connection between the two is achieved through the contact between the wire 530 and the protrusion 200. The contact area between the wire 530 and the protrusion 200 is larger than the overlapping area between the orthographic projection of the filling hole 510 on the substrate 100 and the second contact region 112, so that there is a larger contact area between the wire 530 and the protrusion 200, improving the electrical performance between the wire 530 and the protrusion 200.

[0121] One contact pad 610 corresponding to each wire 530 is provided on each wire 530. The multiple contact pads 610 are arranged at intervals to electrically isolate the contact pads 610 from each other. The lower part of the contact pad 610 is located in the filling hole 510 and is in contact with the wire 530. The upper part of the contact pad 610 is located on the first isolation layer 500. A capacitor can be provided on the contact pad 610, and the capacitor is electrically connected to the second contact region 112 through the contact pad 610 and the wire 530.

[0122] The memory in the embodiment of the present invention includes: a substrate 100, a bit line structure 400, a first isolation layer 500, and a wire 530; wherein, a plurality of spaced active regions 110 are provided in the substrate 100. The active region 110 includes a first contact region 111 and a second contact region 112. The second contact region 112 is located outside the first contact region 111, and a protrusion 200 is provided on the second contact region 112; the bit line structure 400 is provided on the substrate 100, and each of the plurality of spaced bit line structures 400 is electrically connected to at least one first contact region 111; the first isolation layer 500 is provided on the substrate 100 and covers the bit line structure 400, the protrusion 200, and the substrate 100. A plurality of filling holes 510 are provided in the first isolation layer 500, and the protrusion 200 is exposed in the filling holes 510; the wire 530 is provided in the filling holes 510 and is electrically connected to the protrusion 200. The contact area between the wire 530 and the protrusion 200 is larger than the overlapping area between the orthographic projection of the filling hole 510 on the substrate 100 and the second contact region 112, so that the contact area between the wire 530 and the protrusion 200 is larger than the overlapping area between the wire 530 and the second contact region 112 when the protrusion 200 is not provided, reducing the contact resistance between the wire 530 and the protrusion 200. In addition, the protrusion 200 located on the substrate 100 is formed in the filling hole 510, so that the depth of the filling hole 510 is reduced compared with the related art, so that there are fewer holes or gaps in the wire 530 provided in the filling hole 510, improving the formation quality of the wire 530, and further improving the yield of the memory.

[0123] In this specification, the embodiments or implementation manners are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other.

[0124] In the description of this specification, the description with reference to terms such as "one implementation manner", "some implementation manners", "illustrative implementation manner", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the implementation manner or example are included in at least one implementation manner or example of the present invention. In this specification, the illustrative expression of the above terms does not necessarily refer to the same implementation manner or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more implementation manners or examples.

[0125] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a semiconductor memory, characterized in that, Including: Providing a substrate, wherein a plurality of active regions are arranged at intervals in the substrate, the active region includes a first contact region and a second contact region located outside the first contact region, and the second contact region is exposed on the surface of the substrate; Forming a protrusion on each of the second contact regions; Forming a plurality of bit line structures arranged at intervals on the substrate, and each bit line structure is electrically connected to at least one of the first contact regions; Forming a first isolation layer covering the bit line structure and the substrate, wherein a plurality of filling holes are provided in the first isolation layer, each filling hole exposes one of the protrusions, and the surface area of the protrusion exposed in the filling hole is larger than the overlapping area between the orthographic projection of the filling hole on the substrate and the second contact region; Forming a wire in the filling hole, and the wire is electrically connected to the protrusion; 2. The manufacturing method of the semiconductor memory according to claim 1, characterized in that, The bit line structure extends in a first direction; Taking a plane parallel to the first direction as a cross section, the cross-sectional shape of the protrusion is a bow shape; 3. The manufacturing method of the semiconductor memory according to claim 1, characterized in that, The orthographic projection of the protrusion on the substrate at least covers the second contact region; 4. The manufacturing method of the semiconductor memory according to claim 3, wherein The distance between the edge of the orthographic projection of the protrusion on the substrate and the edge of the second contact region is 3-5 nm; 5. The method for manufacturing a semiconductor memory according to claim 1, wherein The step of forming a protrusion on each of the second contact regions includes: Epitaxially growing on each of the second contact regions to form the protrusion; 6. The manufacturing method of the semiconductor memory according to claim 5, characterized in that, The material of the protrusion is the same as that of the active region, the protrusion and the active region are doped with a preset ion, and the doping concentration of the protrusion is greater than the doping concentration of the active region; 7. The manufacturing method of the semiconductor memory according to claim 1, characterized in that, The first contact region is exposed on the surface of the substrate; While forming a protrusion on each of the second contact regions, a protrusion is also formed on each of the first contact regions; 8. The manufacturing method of the semiconductor memory according to claim 7, wherein A word line structure extending in a second direction is further formed in the substrate, the word line structure separates the first contact region and the second contact region of each active region, and the first contact region and the second contact region are arranged in a dot matrix; 9. The manufacturing method of the semiconductor memory according to any one of claims 1-8, characterized in that, The step of forming a plurality of bit line structures arranged at intervals on the substrate, and each bit line structure is at least connected to one of the first contact regions includes: Forming a stacked first insulating layer, a second isolation layer and a first conductive layer on the substrate, and the first insulating layer covers the protrusion; Forming a bit line contact window in the first conductive layer, the second isolation layer and the first insulating layer, the bit line contact window penetrates through the first conductive layer, the second isolation layer and the first insulating layer and extends to the substrate, and the bit line contact window exposes the first contact region; Forming a bit line contact in the bit line contact window, removing the first conductive layer and the bit line contact on the second isolation layer, and the remaining bit line contact is flush with the second isolation layer; Forming a stacked second conductive layer and a third isolation layer on the bit line contact and the second isolation layer, and the second conductive layer covers the bit line contact and the second isolation layer; Etching the third isolation layer, the second conductive layer, the second isolation layer and the bit line contact to form a bit line structure extending in the first direction, and the bit line structure passes through a plurality of the first contact regions located in the first direction.

10. The manufacturing method of the semiconductor memory according to claim 9, characterized in that, The second conductive layer includes a titanium layer formed on the bit line contact, a metal compound layer formed on the titanium layer, and a tungsten layer formed on the metal compound layer.

11. The manufacturing method of the semiconductor memory according to claim 9, wherein The step of forming a first isolation layer covering the bit line structure and the substrate, with a plurality of filling holes provided in the first isolation layer, each filling hole exposing one of the protrusions, and the surface area of the protrusion exposed in the filling hole being greater than the overlapping area of the orthographic projection of the filling hole on the substrate and the second contact region includes: Depositing the first isolation layer on the bit line structure, the first isolation layer covering the bit line structure and the first insulating layer; Etching the first isolation layer to form the filling holes, the filling holes penetrating the first isolation layer and opposite to the protrusions; Etching the first insulating layer along the filling holes, the filling holes penetrating the first insulating layer to expose the protrusions through the filling holes.

12. The manufacturing method of the semiconductor memory according to any one of claims 1-8, characterized in that, The step of forming a wire in the filling hole, the wire being electrically connected to the protrusion includes: Depositing a third conductive layer in the filling hole and on the first isolation layer, the third conductive layer filling the filling hole and covering the first isolation layer; Etching the third conductive layer to remove the third conductive layer on the first isolation layer and a part of the third conductive layer in the filling hole, and the remaining third conductive layer forms the wire.

13. The manufacturing method of the semiconductor memory according to claim 12, wherein After the step of forming a wire in the filling hole, the wire being electrically connected to the protrusion, the method for manufacturing the memory further includes: Forming contact pads on the wires in each filling hole, the plurality of contact pads being spaced apart, and each contact pad being partially located in the filling hole and partially located on the first isolation layer.

14. A semiconductor memory, characterized in that, Comprising: A substrate, with a plurality of spaced active regions provided in the substrate, the active regions including a first contact region and a second contact region located outside the first contact region; A plurality of spaced bit line structures provided on the substrate, each bit line structure being electrically connected to at least one of the first contact regions; Protrusions provided on the second contact regions; A first isolation layer covering the bit line structures, the protrusions and the substrate, the first isolation layer being provided with a plurality of filling holes, the plurality of filling holes extending to the protrusions; Wires provided in the filling holes, the wires being electrically connected to the protrusions, and the contact area between the wires and the protrusions being greater than the overlapping area of the orthographic projection of the filling holes on the substrate and the second contact regions.

15. The semiconductor memory according to claim 14, characterized in that, The bit line structure extends in a first direction; Taking a plane parallel to the first direction as a cross-section, the cross-sectional shape of the protrusion is a bow shape.

16. The semiconductor memory according to claim 14, wherein, The orthographic projection of the protrusion on the substrate at least covers the second contact region.

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