Display device

Abstract

A display device is provided. The display device includes: a substrate; a first electrode and a second electrode disposed on the substrate and spaced apart from each other; a light-emitting element disposed between the first electrode and the second electrode; an insulating pattern disposed on the light-emitting element; a first contact electrode disposed on one side of the insulating pattern to contact one end of the light-emitting element and the first electrode; and a second contact electrode disposed on the other side of the insulating pattern to contact the other end of the light-emitting element and the second electrode, wherein a surface of the insulating pattern includes a concave-convex pattern.

Description

Technical Field

[0001] The present disclosure relates to a display device. Background Art

[0002] In recent years, interest in information display has been increasing, and as a result, research and development of display devices are ongoing. Summary of the Invention

[0003] Technical issues

[0004] An object of the present disclosure is to provide a display device capable of simplifying the manufacturing process.

[0005] The objects are not limited to the above objects, and other technical objects not described will be clearly understood by those skilled in the art from the following description.

[0006] Technical Solution

[0007] According to an embodiment of the present disclosure for the above-mentioned purpose, a display device includes: a substrate; a first electrode and a second electrode, which are arranged on the substrate and spaced apart from each other; a light-emitting element, which is arranged between the first electrode and the second electrode; an insulating pattern, which is arranged on the light-emitting element; a first contact electrode, which is arranged on one side of the insulating pattern and contacts one end of the light-emitting element and the first electrode; and a second contact electrode, which is arranged on the other side of the insulating pattern and contacts the other end of the light-emitting element and the second electrode, and the surface of the insulating pattern includes a concave-convex pattern.

[0008] The first contact electrode and the second contact electrode may include the same material.

[0009] The insulating pattern may expose one end of the light emitting element and the other end of the light emitting element.

[0010] The first contact electrode and the second contact electrode may be spaced apart from each other with an insulating pattern interposed therebetween.

[0011] The display device may further include: an insulating layer covering the first contact electrode and the second contact electrode.

[0012] The insulating layer may cover the concavo-convex pattern.

[0013] The concavo-convex pattern may include a plurality of protruding portions and concave portions.

[0014] The display device may further include: a conductive material layer disposed in the recessed portion.

[0015] The conductive material layer may include the same material as the first contact electrode and the second contact electrode.

[0016] The thickness of the conductive material layer may be formed to be thinner than the thickness of the protruding portion.

[0017] The surface roughness of the side surface of the insulation pattern may be greater than the surface roughness of the upper surface of the insulation pattern.

[0018] The display device may further include a conductive pattern disposed on an upper surface of the insulating pattern.

[0019] The conductive pattern may be provided between the first contact electrode and the second contact electrode.

[0020] The conductive pattern may be electrically separated from the first contact electrode and the second contact electrode.

[0021] The conductive pattern may include the same material as the first contact electrode and the second contact electrode.

[0022] The thickness of the conductive pattern may be substantially the same as the thickness of the first contact electrode and the second contact electrode.

[0023] The display device may further include: an insulating layer disposed on the first contact electrode and the second contact electrode.

[0024] The insulating layer may directly cover side surfaces of the insulating pattern.

[0025] The insulating layer may not contact the upper surface of the insulating pattern.

[0026] The display device may further include: a conductive pattern disposed between an upper surface of the insulating pattern and the insulating layer.

[0027] Details of other embodiments are included in the detailed description and accompanying drawings.

[0028] Beneficial effects

[0029] According to the embodiment, since the insulating pattern includes the concavo-convex pattern, the first and second contact electrodes may be prevented from being short-circuited, and thus process economy may be improved by simultaneously forming the first and second contact electrodes.

[0030] The effects according to the embodiment are not limited to the above-exemplified contents, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 and Figure 2 are a perspective view and a cross-sectional view illustrating a light emitting element according to an embodiment.

[0032] Figure 3 and Figure 4 are a perspective view and a cross-sectional view showing a light emitting element according to another embodiment.

[0033] Figure 5 is a perspective view showing a light emitting element according to still another embodiment.

[0034] Figure 6 is a cross-sectional view showing a light emitting element according to still another embodiment.

[0035] Figure 7 is a perspective view showing a light emitting element according to still another embodiment.

[0036] Figure 8 is a plan view showing a display device according to an embodiment.

[0037] Figures 9 to 12 is a circuit diagram showing a pixel according to an embodiment.

[0038] Figure 13 and Figure 14 is a plan view showing a pixel according to an embodiment.

[0039] Figure 15 and Figure 16 is a cross-sectional view of a pixel according to an embodiment.

[0040] Figure 17 yes Figure 15 An enlarged cross-sectional view of area A.

[0041] Figure 18 is a cross-sectional view of a pixel according to another embodiment.

[0042] Figures 19 to 24 is a cross-sectional view of each process step of a method for manufacturing a display device according to an embodiment. DETAILED DESCRIPTION

[0043] Advantages and features and methods of achieving them will become clear with reference to the embodiments described in detail below in conjunction with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below, but can be implemented in various forms, and the present disclosure is limited only by the scope of the claims.

[0044] The case where an element or layer is referred to as being “on” another element or layer includes the case where the other layer or element is directly on the other element or between other layers. Throughout the specification, the same reference numerals refer to the same reference components.

[0045] Although the terms "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component described below may be the second component within the technical spirit. Unless the context clearly indicates otherwise, singular expressions (expressions) also include plural expressions.

[0046] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0047] Figure 1 and Figure 2 are perspective views and cross-sectional views showing a light emitting element according to an embodiment. Figure 1 and Figure 2 , a rod-shaped light emitting element LD having a cylindrical shape is shown in FIG, but the type and / or shape of the light emitting element LD is not limited thereto.

[0048] Reference Figure 1 and Figure 2 The light emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 disposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light emitting element LD may be configured as a stacked body in which the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 are sequentially stacked in one direction.

[0049] According to an embodiment, the light emitting element LD may be provided in a rod shape extending in one direction. The light emitting element LD may have one side end and another side end along the one direction.

[0050] According to an embodiment, one of the first and second semiconductor layers 11 and 13 may be disposed at one side end of the light emitting element LD, and the other may be disposed at the other side end of the light emitting element LD.

[0051] According to an embodiment, the light-emitting element LD may be a rod-shaped light-emitting diode manufactured in a rod shape. Here, the rod shape includes a rod-like shape or a strip-like shape (such as a cylinder or a polygonal cylinder) that is longer in the longitudinal direction than in the width direction (i.e., has an aspect ratio greater than 1), and the shape of its cross-section is not particularly limited. For example, the length L of the light-emitting element LD may be greater than its diameter D (or the width of the cross-section).

[0052] According to embodiments, the light emitting element LD may have a size as small as nanometer to micrometer (nanoscale to microscale), for example, a diameter D and / or a length L in the range of about 100 nm to about 10 μm. However, the size of the light emitting element LD is not limited thereto. For example, the size of the light emitting element LD may be variously changed according to the design conditions of various devices (for example, display devices, etc.) using the light emitting element LD as a light source.

[0053] The first semiconductor layer 11 may include at least one n-type (or N-type) semiconductor material. For example, the first semiconductor layer 11 may include one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include an n-type semiconductor material doped with a first conductive dopant (such as Si, Ge, or Sn), but is not limited thereto.

[0054] The active layer 12 may be provided on the first semiconductor layer 11 and may be formed in a single quantum well structure or a multi-quantum well structure. In an embodiment, a cladding layer (not shown) doped with a conductive dopant may be formed on and / or below the active layer 12. For example, the cladding layer may be formed of AlGaN or InAlGaN. According to an embodiment, materials such as AlGaN, InAlGaN, etc. may be used to form the active layer 12, and various materials other than the above materials may be used to construct the active layer 12. The active layer 12 may be provided between the first semiconductor layer 11 and a second semiconductor layer 13 to be described later.

[0055] When a voltage greater than or equal to a threshold voltage is applied to both ends of the light-emitting element LD, the light-emitting element LD can emit light when electron-hole pairs are recombined in the active layer 12. By controlling light emission of the light-emitting element LD using this principle, the light-emitting element LD can be used as a light source for various light-emitting devices including pixels of a display device.

[0056] The second semiconductor layer 13 may be provided on the active layer 12 and may include a semiconductor material of a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type (or P-type) semiconductor material. For example, the second semiconductor layer 13 may include at least one semiconductor material selected from the group consisting of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a p-type semiconductor material doped with a second conductive dopant such as Mg. However, the material constituting the second semiconductor layer 13 is not limited thereto, and various materials other than the above-mentioned materials may constitute the second semiconductor layer 13. According to an embodiment, the first length L1 of the first semiconductor layer 11 may be longer than the second length L2 of the second semiconductor layer 13.

[0057] As described above, when the active layer 12 and the semiconductor layers 11 and 13 of the light emitting element LD include nitrogen (N), the light emitting element LD can emit blue light having a central wavelength in the range of 400 nm to 500 nm or green light having a central wavelength in the range of 500 nm to 570 nm. However, it should be understood that the central wavelengths of blue light and green light are not limited to the above ranges and include all wavelength ranges that can be recognized as blue or green in the present technical field.

[0058] According to an embodiment, the light emitting element LD may further include an insulating film INF provided on the surface. The insulating film INF may be formed on the surface of the light emitting element LD to surround at least the outer peripheral surface of the active layer 12 and may also surround a region of the first semiconductor layer 11 and the second semiconductor layer 13.

[0059] According to an embodiment, the insulating film INF may expose both ends of the light emitting element LD having different polarities. For example, the insulating film INF may not cover and may expose one end of each of the first semiconductor layer 11 and the second semiconductor layer 13 located at both ends of the light emitting element LD in the longitudinal direction (for example, two planes (i.e., the upper surface and the lower surface) of a cylinder). In some other embodiments, the insulating film INF may expose both ends of the light emitting element LD having different polarities and the side surfaces of the semiconductor layers 11 and 13 adjacent to the two ends.

[0060] According to an embodiment, the insulating film can be constructed as a single layer or a multilayer (for example, a double layer constructed of aluminum oxide (Al2O3) and silicon dioxide (SiO2)) by including at least one insulating material among silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3) and titanium dioxide (TiO2), but is not necessarily limited to this.

[0061] In embodiments, the light emitting element LD may further include additional components in addition to the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and / or the insulating film INF. For example, the light emitting element LD may additionally include one or more phosphor layers, an active layer, a semiconductor material, and / or an electrode layer provided on one end side of the first semiconductor layer 11, the active layer 12, and / or the second semiconductor layer 13.

[0062] Figure 3 and Figure 4 are a perspective view and a cross-sectional view showing a light emitting element according to another embodiment.

[0063] Reference Figure 3 and Figure 4 According to an embodiment, the light emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 disposed between the first semiconductor layer 11 and the second semiconductor layer 13. According to an embodiment, the first semiconductor layer 11 may be provided in a central region of the light emitting element LD, and the active layer 12 may be provided on a surface of the first semiconductor layer 11 to surround at least one region of the first semiconductor layer 11. The second semiconductor layer 13 may be provided on a surface of the active layer 12 to surround at least one region of the active layer 12.

[0064] In addition, the light emitting element LD may further include an electrode layer 14 and / or an insulating film INF surrounding at least one region of the second semiconductor layer 13. For example, the light emitting element LD may include the electrode layer 14 provided on the surface of the second semiconductor layer 13 so as to surround one region of the second semiconductor layer 13, and the insulating film INF provided on the surface of the electrode layer 14 so as to surround at least one region of the electrode layer 14. That is, the light emitting element LD according to the above-described embodiment may be implemented as a core-shell structure including the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, the electrode layer 14, and the insulating film INF, which are sequentially provided from the center in an outer direction, and the electrode layer 14 and / or the insulating film INF may be omitted according to the embodiment.

[0065] In the embodiment, the light emitting element LD may be provided in a polygonal pyramid shape extending in any direction. For example, at least one region of the light emitting element LD may have a hexagonal pyramid shape. However, the shape of the light emitting element LD is not limited thereto and may be variously changed.

[0066] When the extending direction of the light emitting element LD is referred to as a length L direction, the light emitting element LD may have one side end and the other side end along the length L. According to an embodiment, one of the first semiconductor layer 11 and the second semiconductor layer 13 may be provided at one side end of the light emitting element LD, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 may be provided at the other side end of the light emitting element LD.

[0067] In the embodiment, the light-emitting element LD can be an ultra-small light-emitting diode having a core-shell structure manufactured in a polygonal prism shape (for example, a hexagonal pyramid shape with protruding ends). For example, the light-emitting element LD can have a size as small as nanometer to micrometer (for example, a width and / or length L in the range of nanometer or micrometer, respectively). However, the size, shape, etc. of the light-emitting element LD can be variously changed according to the design conditions of various devices (for example, display devices, etc.) using the light-emitting element as a light source.

[0068] In an embodiment, both ends of the first semiconductor layer 11 may have a protruding shape along the length L direction of the light emitting element LD. The shapes of the two ends of the first semiconductor layer 11 may be different from each other. For example, as the width narrows toward the upper portion, one end provided on the upper side of the two ends of the first semiconductor layer 11 may have a cone shape contacting one vertex. In addition, the other end of the first semiconductor layer 11 provided on the lower side of the two ends of the first semiconductor layer 11 may have a polygonal column shape having a constant width, but is not limited thereto. For example, in another embodiment, the first semiconductor layer 11 may have a cross-section of a polygonal shape, a step shape, etc. in which the width gradually narrows toward the lower portion. The shapes of the two ends of the first semiconductor layer 11 may be variously changed according to the embodiment and are not limited to the above-mentioned embodiment.

[0069] According to an embodiment, the first semiconductor layer 11 may be located at the core (i.e., the center (or central region) of the light emitting element LD). In addition, the light emitting element LD may be provided in a shape corresponding to the shape of the first semiconductor layer 11. For example, when the first semiconductor layer 11 has a hexagonal pyramid shape, the light emitting element LD may have a hexagonal pyramid shape.

[0070] Figure 5 1 is a perspective view showing a light emitting element according to another embodiment. Figure 5 , for the convenience of description, a portion of the insulating film INF is omitted.

[0071] Reference Figure 5 , the light emitting element LD may further include an electrode layer 14 disposed on the second semiconductor layer 13. The electrode layer 14 may be an ohmic contact electrode electrically connected to the second semiconductor layer 13, but is not necessarily limited thereto. According to an embodiment, the electrode layer 14 may be a Schottky contact electrode. The electrode layer 14 may include a metal or a metal oxide, and for example, Cr, Ti, Al, Au, Ni, ITO, IZO, ITZO and oxides or alloys thereof may be used alone or in combination. In addition, the electrode layer 14 may be substantially transparent or translucent. Therefore, the light generated in the active layer 12 of the light emitting element LD may pass through the electrode layer 14 and may be emitted to the outside of the light emitting element LD. Although not shown separately, in another embodiment, the light emitting element LD may further include an electrode layer disposed on the first semiconductor layer 11.

[0072] Figure 6 is a cross-sectional view showing a light emitting element according to still another embodiment.

[0073] Reference Figure 6 , the insulating film INF′ may have a curved shape in a corner region adjacent to the electrode layer 14. According to an embodiment, the curved surface may be formed by etching in a manufacturing process of the light emitting element LD.

[0074] Although not shown separately, in a light emitting element of another embodiment having a structure further including an electrode layer provided on the above-described first semiconductor layer 11 , the insulating film INF′ may also have a curved shape in a region adjacent to the electrode layer.

[0075] Figure 7 1 is a perspective view showing a light emitting element according to another embodiment. Figure 7 , for the convenience of description, a portion of the insulating film INF is omitted.

[0076] Reference Figure 7The light emitting element LD may further include a third semiconductor layer 15 disposed between the first semiconductor layer 11 and the active layer 12 , and a fourth semiconductor layer 16 and a fifth semiconductor layer 17 disposed between the active layer 12 and the second semiconductor layer 13 . Figure 7 The light emitting element LD and Figure 1 The embodiment of the present invention is different in that a plurality of semiconductor layers 15, 16 and 17 and electrode layers 14a and 14b are further provided, and the active layer 12 includes another element. In addition, since the arrangement and structure of the insulating film INF are different from Figure 1 The arrangement and structure of the insulating film are basically the same, so the repeated content is omitted and the different points are mainly described.

[0077] exist Figure 7 In the light-emitting element LD of the embodiment, each of the active layer 12 and the other semiconductor layers 11, 13, 15, 16, and 17 can be a semiconductor including at least phosphorus (P). That is, the light-emitting element LD according to the embodiment can emit red light having a central wavelength band ranging from 620 nm to 750 nm. However, it should be understood that the central wavelength band of red light is not limited to the above range and includes all wavelength ranges that can be recognized as red in the present technical field.

[0078] Specifically, when the light-emitting element LD emits red light, the first semiconductor layer 11 may include at least one or more of InAlGaP, GaP, AlGaP, InGaP, AlP, and InP doped with an n-type dopant. The first semiconductor layer 11 may be doped with an n-type dopant, such as Si, Ge, Se, Sn, or the like. In an exemplary embodiment, the first semiconductor layer 11 may be n-AlGaInP doped with n-type Si. The length of the first semiconductor layer 11 may range from 1.5 μm to 5 μm, but is not necessarily limited thereto.

[0079] When the light-emitting element LD emits red light, the second semiconductor layer 13 may be any one or more of InAlGaP, GaP, AlGaNP, InGaP, AlP, and InP doped with a p-type dopant. The second semiconductor layer 13 may be doped with a p-type dopant, for example, Mg, Zn, Ca, Ba, or the like. In an exemplary embodiment, the second semiconductor layer 13 may be p-GaP doped with p-type Mg. The length of the second semiconductor layer 13 may range from 0.08 μm to 0.25 μm, but is not necessarily limited thereto.

[0080] The active layer 12 may be provided between the first semiconductor layer 11 and the second semiconductor layer 13. Figure 1 The active layer 12 is the same as Figure 7The active layer 12 can also emit light in a specific wavelength band by including a single or multiple quantum well structure materials. For example, when the active layer 12 emits light in the red wavelength band, the active layer 12 can include materials such as AlGaP, AlInGaP, etc. In particular, when the active layer 12 has a structure in which quantum layers and well layers are alternately stacked in a multi-quantum well structure, the quantum layers can include materials such as AlGaP or AlInGaP, and the well layers can include materials such as GaP or AlInP. In an exemplary embodiment, the active layer 12 can emit red light with a central wavelength band of 620nm to 750nm by including AlGaInP as the quantum layers and AlInP as the well layers.

[0081] Figure 7 The light emitting element LD may include a clad layer disposed adjacent to the active layer 12. As shown in the drawings, the third semiconductor layer 15 and the fourth semiconductor layer 16 disposed between the first semiconductor layer 11 and the second semiconductor layer 13 on and below the active layer 12 may be clad layers.

[0082] The third semiconductor layer 15 may be provided between the first semiconductor layer 11 and the active layer 12. The third semiconductor layer 15 may be the same n-type semiconductor as the first semiconductor layer 11. For example, the first semiconductor layer 11 may be n-AlGaInP, and the third semiconductor layer 15 may be n-AlInP, but is not necessarily limited thereto.

[0083] The fourth semiconductor layer 16 may be disposed between the active layer 12 and the second semiconductor layer 13. The fourth semiconductor layer 16 may be a p-type semiconductor like the second semiconductor layer 13. For example, the second semiconductor layer 13 may be p-GaP, and the fourth semiconductor layer 16 may be p-AlInP.

[0084] The fifth semiconductor layer 17 may be disposed between the fourth semiconductor layer 16 and the second semiconductor layer 13. The fifth semiconductor layer 17 may be the same p-doped semiconductor as the second semiconductor layer 13 and the fourth semiconductor layer 16. In some embodiments, the fifth semiconductor layer 17 may function to reduce the lattice constant difference between the fourth semiconductor layer 16 and the second semiconductor layer 13. That is, the fifth semiconductor layer 17 may be a tensile strain barrier reduction (TSBR) layer. For example, the fifth semiconductor layer 17 may include p-GaInP, p-AlInP, p-AlGaInP, etc., but is not limited thereto. In addition, the lengths of the third semiconductor layer 15, the fourth semiconductor layer 16, and the fifth semiconductor layer 17 may range from 0.08 μm to 0.25 μm, but are not limited thereto.

[0085] The first electrode layer 14a and the second electrode layer 14b may be provided on the first semiconductor layer 11 and the second semiconductor layer 13, respectively. The first electrode layer 14a may be provided on the lower surface of the first semiconductor layer 11, and the second electrode layer 14b may be provided on the upper surface of the second semiconductor layer 13. However, the present disclosure is not limited thereto, and at least one of the first electrode layer 14a and the second electrode layer 14b may be omitted. For example, in the light emitting element LD, the first electrode layer 14a may not be provided on the lower surface of the first semiconductor layer 11, and only one second electrode layer 14b may be provided on the upper surface of the second semiconductor layer 13. Each of the first electrode layer 14a and the second electrode layer 14b may include Figure 5 The electrode layer 14 is made of at least one of the materials listed.

[0086] The following embodiments are described as applying Figure 1 and Figure 2 The example of the light emitting element LD shown in FIG. 1 is shown in FIG. 2 , but those skilled in the art may Figures 3 to 7 Light emitting elements of various shapes of the light emitting element LD shown in are applied to the embodiment.

[0087] Figure 8 is a plan view showing a display device according to an embodiment.

[0088] Figure 8 A display device (particularly, a display panel PNL provided in the display device) is shown as an example of a device capable of using the above-described light emitting element LD as a light source.

[0089] Reference Figure 8 The display panel PNL may include a substrate SUB and pixels PXL (or sub-pixels) disposed on the substrate SUB. Specifically, the display panel PNL and the substrate SUB may include a display area DA displaying an image and a non-display area NDA other than the display area DA.

[0090] The substrate SUB may be a rigid substrate or a flexible substrate, and the material or physical properties of the substrate SUB are not particularly limited. For example, the substrate SUB may be a rigid substrate formed of glass or tempered glass, or a flexible substrate formed of a film constructed of plastic or metal materials. In addition, the substrate SUB may be a transparent substrate, but is not limited thereto. For example, the substrate SUB may be a translucent substrate, an opaque substrate, or a reflective substrate.

[0091] The display panel PNL and the substrate SUB may include a display area DA for displaying a picture and a non-display area NDA in which no display is performed. The non-display area NDA may be provided to surround the display area DA, but is not necessarily limited thereto. The display area DA may include a plurality of pixels PXL. The pixel PXL may include at least one light emitting element LD driven by a scan signal and a data signal (e.g., according to a predetermined light source). Figures 1 to 7 A plurality of light emitting diodes may constitute the light source of the pixel PXL.

[0092] although Figure 8 An embodiment in which the pixels PXL are arranged in a stripe shape in the display area DA is illustrated, but the present disclosure is not limited thereto, and the pixels PXL may be provided in various pixel arrangement types such as pentile.

[0093] The pixels PXL may be connected to scan lines and data lines and may also be connected to high potential power lines and low potential power lines. The pixels PXL may emit light having brightness corresponding to data signals transmitted through the data lines in response to scan signals transmitted through the scan lines.

[0094] Figures 9 to 12 is a circuit diagram showing a pixel according to an embodiment.

[0095] Reference Figure 9 The pixel PXL includes a light source unit LSU for generating light of brightness corresponding to the data signal. In addition, the pixel PXL may further selectively include a pixel circuit PXC for driving the light source unit LSU.

[0096] The light source unit LSU may include at least one light-emitting element LD (e.g., a plurality of light-emitting elements LD) connected between a first power supply VDD and a second power supply VSS. For example, the light source unit LSU may include a first electrode ELT1 (also referred to as a "first pixel electrode" or a "first alignment electrode") connected to the first power supply VDD via a pixel circuit PXC and a first power line PL1, a second electrode ELT2 (also referred to as a "second pixel electrode" or a "second alignment electrode") connected to the second power supply VSS via a second power line PL2, and a plurality of light-emitting elements LD connected in parallel along the same direction between the first electrode ELT1 and the second electrode ELT2. In an embodiment, the first electrode ELT1 may be an anode electrode, and the second electrode ELT2 may be a cathode electrode.

[0097] Each of the light-emitting elements LD may include a first terminal (e.g., a P-type terminal) connected to a first power supply VDD via a first electrode ELT1 and / or a pixel circuit PXC, and a second terminal (e.g., an N-type terminal) connected to a second power supply VSS via a second electrode ELT2. That is, the light-emitting elements LD may be connected in parallel in a forward direction between the first electrode ELT1 and the second electrode ELT2. Each light-emitting element LD connected in the forward direction between the first power supply VDD and the second power supply VSS may constitute an effective light source, and the effective light sources may be aggregated to constitute a light source unit LSU of the pixel PXL.

[0098] According to an embodiment, the first power supply VDD and the second power supply VSS may have different potentials so that the light-emitting element LD emits light. For example, the first power supply VDD may be set to a high potential power supply, while the second power supply VSS may be set to a low potential power supply. In this case, during the emission period of the pixel PXL, the potential difference between the first power supply VDD and the second power supply VSS may be set to be equal to or greater than the threshold voltage of the light-emitting element LD.

[0099] According to an embodiment, one end (e.g., a P-type end) of the light emitting element LD constituting each light source unit LSU may be commonly connected to the pixel circuit PXC via one electrode of the light source unit LSU (e.g., the first electrode ELT1 of each pixel PXL), and may be connected to the first power supply VDD via the pixel circuit PXC and the first power supply line PL1. Furthermore, the other end (e.g., an N-type end) of the light emitting element LD may be commonly connected to the second power supply VSS via another electrode of the light source unit LSU (e.g., the second electrode ELT2 of each pixel PXL) and the second power supply line PL2.

[0100] The light-emitting element LD can emit light having a brightness corresponding to the drive current supplied by the corresponding pixel circuit PXC. For example, during each frame period, the pixel circuit PXC can supply a drive current corresponding to the grayscale value to be expressed in the corresponding frame to the light source unit LSU. The drive current supplied to the light source unit LSU can be divided and can flow to the light-emitting elements LD connected in the forward direction. Therefore, when each light-emitting element LD emits light having a brightness corresponding to the current flowing therethrough, the light source unit LSU can emit light having a brightness corresponding to the drive current.

[0101] In an embodiment, in addition to the light emitting elements LD configuring each effective light source, the light source unit LSU may further include at least one ineffective light source. For example, at least one reverse light emitting element LDrv may be further connected between the first electrode ELT1 and the second electrode ELT2.

[0102] Each reverse light-emitting element LDrv can be connected in parallel between the first electrode ELT1 and the second electrode ELT2 together with the light-emitting element LD constituting the effective light source, and can be connected between the first electrode ELT1 and the second electrode ELT2 in a direction opposite to the direction of the light-emitting element LD. For example, the N-type terminal of the reverse light-emitting element LDrv can be connected to the first power supply VDD via the first electrode ELT1 and the pixel circuit PXC, while the P-type terminal of the reverse light-emitting element LDrv can be connected to the second power supply VSS through the second electrode ELT2. Even if a predetermined driving voltage (for example, a driving voltage in the forward direction) is applied between the first electrode ELT1 and the second electrode ELT2, the reverse light-emitting element LDrv can remain in a deactivated state, and thus the reverse light-emitting element LDrv can basically remain in a non-emitting state.

[0103] In addition, according to an embodiment, at least one pixel PXL may further include at least one ineffective light source (not shown) that is not completely connected between the first electrode ELT1 and the second electrode ELT2. For example, at least one pixel PXL may further include at least one ineffective light emitting element located in the light source unit LSU and having a first end and a second end that are not completely connected to the first electrode ELT1 and the second electrode ELT2.

[0104] The pixel circuit PXC is connected between the first power supply VDD and the first electrode ELT1. The pixel circuit PXC can be connected to the scan line Si and the data line Dj of the corresponding pixel PXL. For example, when the pixel PXL is arranged on the i-th (i is a positive integer) horizontal line (row) and the j-th (j is a positive integer) vertical line (column) of the display area DA, the pixel circuit PXC of the pixel PXL can be connected to the i-th scan line Si and the j-th data line Dj of the display area DA.

[0105] According to an embodiment, the pixel circuit PXC may include a plurality of transistors and at least one capacitor. For example, the pixel circuit PXC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst.

[0106] The first transistor T1 is connected between the first power supply VDD and the light source unit LSU. For example, a first electrode (e.g., a source electrode) of the first transistor T1 may be connected to the first power supply VDD, and a second electrode (e.g., a drain electrode) of the first transistor T1 may be connected to the first electrode ELT1. Furthermore, a gate electrode of the first transistor T1 is connected to a first node N1. The first transistor T1 controls the drive current supplied to the light source unit LSU in response to the voltage of the first node N1. In other words, the first transistor T1 may be a drive transistor that controls the drive current of the pixel PXL.

[0107] The second transistor T2 is connected between the data line Dj and the first node N1. For example, a first electrode (e.g., a source electrode) of the second transistor T2 can be connected to the data line Dj, and a second electrode (e.g., a drain electrode) of the second transistor T2 can be connected to the first node N1. In addition, a gate electrode of the second transistor T2 is connected to the scan line Si. When a scan signal SSi having a gate-on voltage (e.g., a low-level voltage) is supplied from the scan line Si, the second transistor T2 is turned on to electrically connect the data line Dj and the first node N1.

[0108] For each frame period, a data signal DSj of a corresponding frame is supplied to the data line Dj, and the data signal DSj is transmitted to the first node N1 through the second transistor T2 that is turned on during a period in which the scan signal SSi of the gate-on voltage is supplied. That is, the second transistor T2 may be a switching transistor for transmitting each data signal DSj to the inside of the pixel PXL.

[0109] One electrode of the storage capacitor Cst is connected to the first power source VDD, and the other electrode is connected to the first node N1. During each frame period, the storage capacitor Cst is charged with a voltage corresponding to the data signal DSj supplied to the first node N1.

[0110] At the same time, Figure 9 In the embodiment, the transistors (eg, both the first transistor T1 and the second transistor T2) included in the pixel circuit PXC are shown as P-type transistors, but the present disclosure is not limited thereto. That is, at least one of the first transistor T1 and the second transistor T2 may be changed to an N-type transistor.

[0111] On the other hand, the structure of the pixel circuit PXC is not limited to Figure 9 For example, the pixel circuit PXC may be as shown in FIG. Figure 10 Furthermore, the pixel circuit PXC may be configured as a pixel circuit having various structures and / or driving methods.

[0112] Reference Figure 10 , the pixel circuit PXC may also be connected to the sensing control line SCLi and the sensing line SLj. For example, the pixel circuit PXC of the pixel PXL located on the i-th horizontal line and the j-th vertical line in the display area DA may be connected to the i-th sensing control line SCLi and the j-th sensing line SLj in the display area DA. The pixel circuit PXC may further include a third transistor T3. Alternatively, in another embodiment, the sensing line SLj may be omitted, and the characteristics of the pixel PXL may be detected by detecting the sensing signal SENj via the data line Dj of the corresponding pixel PXL (or an adjacent pixel).

[0113] The third transistor T3 is connected between the first transistor T1 and the sensing line SLj. For example, one electrode of the third transistor T3 may be connected to one electrode (e.g., the source electrode) of the first transistor T1 connected to the first electrode ELT1, and the other electrode of the third transistor T3 may be connected to the sensing line SLj. Meanwhile, when the sensing line SLj is omitted, the other electrode of the third transistor T3 may be connected to the data line Dj.

[0114] The gate electrode of the third transistor T3 is connected to the sensing control line SCLi. When the sensing control line SCLi is omitted, the gate electrode of the third transistor T3 can be connected to the scan line Si. The third transistor T3 can be turned on by a sensing control signal SCSi of a gate-on voltage (e.g., a high-level voltage) supplied to the sensing control line SCLi during a predetermined sensing period to electrically connect the sensing line SLj and the first transistor T1.

[0115] According to an embodiment, a sensing period may be a period for extracting characteristics of each pixel PXL disposed in the display area DA (e.g., the threshold voltage of the first transistor T1, etc.). During the sensing period, the first transistor T1 may be turned on by supplying a predetermined reference voltage, which can turn on the first transistor T1, to the first node N1 via the data line Dj and the second transistor T2, or by connecting each pixel PXL to a current source, etc. Furthermore, the first transistor T1 may be connected to a sensing line SLj by supplying a sensing control signal SCSi of a gate-on voltage to the third transistor T3 to turn on the third transistor T3. Thereafter, a sensing signal SENj may be obtained via the sensing line SLj, and the characteristics of each pixel PXL (including the threshold voltage of the first transistor T1, etc.) may be detected using the sensing signal SENj. Information regarding the characteristics of each pixel PXL may be used to convert image data, thereby compensating for characteristic variations between the pixels PXL disposed in the display area DA.

[0116] at the same time, Figure 10 The first transistor T1, the second transistor T2, and the third transistor T3 are all N-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first transistor T1, the second transistor T2, and the third transistor T3 may be changed to a P-type transistor. Figure 10 The embodiment in which the light source unit LSU is connected between the pixel circuit PXC and the second power source VSS is disclosed, but the present disclosure is not limited thereto. For example, in another embodiment, the light source unit LSU may be connected between the first power source VDD and the pixel circuit PXC.

[0117] also, Figure 9 and Figure 10The embodiment in which the effective light sources (ie, all the light emitting elements LD) of each light source unit LSU are connected in parallel is shown, but the present disclosure is not limited thereto. For example, in another embodiment of the present disclosure, Figure 11 and Figure 12 As shown in FIG, the light source unit LSU of each pixel PXL may be constructed as a series structure including at least two stages. Figure 11 and Figure 12 When the embodiment of Figure 9 and Figure 10 A detailed description of a configuration similar to or identical to that of the embodiments (eg, pixel circuit PXC) is provided.

[0118] Reference Figure 11 The light source unit LSU may include at least two light-emitting elements connected in series. For example, the light source unit LSU may include a first light-emitting element LD1, a second light-emitting element LD2, and a third light-emitting element LD3 connected in series in a forward direction between a first power supply VDD and a second power supply VSS. Each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 may constitute an effective light source.

[0119] Hereinafter, when a specific light-emitting element is referred to among the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3, the corresponding light-emitting element is referred to as "the first light-emitting element LD1," "the second light-emitting element LD2," or "the third light-emitting element LD3." Furthermore, when at least one of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 is arbitrarily referred to or the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 are collectively referred to, at least one of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3, or the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 will be referred to as "the light-emitting element LD."

[0120] A first end (e.g., a P-type end) of the first light emitting element LD1 is connected to a first power source VDD via a first electrode (i.e., a first electrode ELT1) of the light source unit LSU, etc. Furthermore, a second end (e.g., an N-type end) of the first light emitting element LD1 is connected to a first end (e.g., a P-type end) of the second light emitting element LD2 via a first intermediate electrode IET1.

[0121] The first terminal (e.g., P-type terminal) of the second light-emitting element LD2 is connected to the second terminal of the first light-emitting element LD1. In addition, the second terminal (e.g., N-type terminal) of the second light-emitting element LD2 is connected to the first terminal (e.g., P-type terminal) of the third light-emitting element LD3 through the second intermediate electrode IET2.

[0122] A first terminal (e.g., a P-type terminal) of the third light-emitting element LD3 is connected to a second terminal of the second light-emitting element LD2. Furthermore, a second terminal (e.g., an N-type terminal) of the third light-emitting element LD3 may be connected to a second power supply VSS via a second electrode (i.e., second electrode ELT2) of the light source unit LSU. In the above method, the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 may be sequentially connected in series between the first electrode ELT1 and the second electrode ELT2 of the light source unit LSU.

[0123] at the same time, Figure 11 An embodiment in which the light-emitting elements LD are connected in a three-stage series structure is shown, but the present disclosure is not limited thereto. For example, in another embodiment of the present disclosure, two light-emitting elements LD may be connected in a two-stage series structure, or four or more light-emitting elements LD may be connected in a four-stage or more series structure.

[0124] Assuming that the same brightness is expressed using light-emitting elements LD of the same conditions (for example, the same size and / or number), in a light source unit LSU having a structure in which the light-emitting elements LD are connected in series, the voltage applied between the first electrode ELT1 and the second electrode ELT2 can be increased and the magnitude of the driving current flowing through the light source unit LSU can be reduced compared to a light source unit LSU having a structure in which the light-emitting elements LD are connected in parallel. Therefore, when the light source unit LSU of each pixel PXL is constructed by applying a series structure, the panel current flowing through the display panel PNL can be reduced.

[0125] In an embodiment, at least one series stage may include a plurality of light emitting elements LD connected in parallel with each other. In this case, the light source unit LSU may be configured as a series / parallel hybrid structure. For example, the light source unit LSU may be configured as follows: Figure 12 The embodiment is constructed as in FIG.

[0126] Reference Figure 12 At least one series connection of the light source unit LSU may include a plurality of light-emitting elements LD connected in parallel in the forward direction. For example, the light source unit LSU may include at least one first light-emitting element LD1 disposed in a first series connection (also referred to as a "first connection"), at least one second light-emitting element LD2 disposed in a second series connection (also referred to as a "second connection") following the first series connection, and at least one third light-emitting element LD3 disposed in a third series connection (also referred to as a "third connection") following the second series connection. Furthermore, at least one of the first series connection, the second series connection, and the third series connection may include a plurality of light-emitting elements LD connected in the forward direction.

[0127] at the same time, Figure 12While the light source unit LSU is shown as being constructed from light-emitting elements LD arranged in three series stages, the present disclosure is not limited thereto. That is, the number of series stages forming the light source unit LSU can be varied in various ways. For example, the light source unit LSU can include a plurality of light-emitting elements LD arranged in four or more series stages. Furthermore, the number of light-emitting elements LD connected to each series stage in the forward direction can be varied in various ways.

[0128] According to an embodiment, the pixels PXL provided in the display area DA may include the same or similar number of light-emitting elements LD. For example, when supplying the light-emitting elements LD to each pixel PXL, the light-emitting elements LD may be aligned by controlling the light-emitting element ink (or, also referred to as "light-emitting element solution") including the light-emitting elements LD to be applied to the emission region of each pixel PXL in a uniform amount and controlling a uniform electric field to be applied to each pixel PXL. As a result, the light-emitting elements LD can be supplied relatively uniformly to the pixels PXL and aligned within the pixels PXL.

[0129] In an embodiment, Figure 12 As shown in , each pixel PXL may further include at least one reverse light emitting element LDrv disposed in at least one series stage. For example, at least one of the plurality of series stages may further include at least one reverse light emitting element LDrv connected in a direction opposite to that of the light emitting element LD.

[0130] However, even if the reverse light-emitting element LDrv is connected to at least one series stage, when at least one effective light source (e.g., the first light-emitting element LD1, the second light-emitting element LD2, and / or the third light-emitting element LD3) connected to the series stage in the forward direction is provided, the driving current of the pixel PXL also flows sequentially through each series stage. Therefore, the light source unit LSU emits light having a brightness corresponding to the driving current.

[0131] As in the above-described embodiment, each light source unit LSU may include a plurality of light-emitting elements LD connected in a forward direction between a first power supply VDD and a second power supply VSS to form each effective light source. Furthermore, the connection structure between the light-emitting elements LD may be variously modified depending on the embodiment. For example, the light-emitting elements LD may be connected only in series or only in parallel, or may be connected in a mixed series / parallel configuration.

[0132] Figure 13 and Figure 14 is a plan view showing a pixel according to an embodiment.

[0133] Figure 13 and Figure 14The structure of the pixel PXL is shown with the light source unit LSU of each pixel PXL as the center. However, according to embodiments, each pixel PXL may further selectively include a circuit element connected to the light source unit LSU (eg, a plurality of circuit elements constituting each pixel circuit PXC).

[0134] also, Figure 13 and Figure 14 In the embodiment shown, each light source unit LSU is connected to a predetermined power line (e.g., a first power line PL1 and / or a second power line PL2) via a first contact hole CH1 and a second contact hole CH2, a circuit element (e.g., at least one circuit element constituting a pixel circuit PXC), and / or a signal line (e.g., a scan line Si and / or a data line Dj). However, the present disclosure is not limited thereto. For example, in another embodiment, at least one of the first electrode ELT1 and the second electrode ELT2 of each pixel PXL can be directly connected to a predetermined power line and / or signal line without passing through a contact hole, an intermediate line, or the like.

[0135] First, refer to Figure 13 The pixel PXL may include a first electrode ELT1 and a second electrode ELT2 disposed in each emission area EMA, and at least one light-emitting element LD disposed between the first electrode ELT1 and the second electrode ELT2 (e.g., a plurality of light-emitting elements LD connected in parallel between the first electrode ELT1 and the second electrode ELT2). Furthermore, the pixel PXL may further include a first contact electrode CNE1 and a second contact electrode CNE2 electrically connecting the light-emitting element LD between the first electrode ELT1 and the second electrode ELT2.

[0136] The first electrode ELT1 and the second electrode ELT2 may be disposed in the emission area EMA of each pixel PXL. The emission area EMA may be a region in which the light emitting element LD (particularly, an effective light source completely connected between the first electrode ELT1 and the second electrode ELT2) of the light source unit LSU configuring each pixel PXL is disposed. Furthermore, in the emission area EMA, a predetermined electrode (e.g., the first electrode ELT1 and the second electrode ELT2 and / or the first contact electrode CNE1 and the second contact electrode CNE2) connected to the light emitting element LD may be disposed.

[0137] The first electrode ELT1 and the second electrode ELT2 may be disposed to be spaced apart from each other. For example, the first electrode ELT1 and the second electrode ELT2 may be disposed side by side to be spaced apart by a predetermined distance along the first direction (X-axis direction) in each emission area EMA.

[0138] At the same time, before the process of forming the pixel PXL (particularly, before the alignment of the light-emitting element LD is completed), the first electrodes ELT1 of the pixels PXL arranged in the display area DA can be connected to each other, and the second electrodes ELT2 of the pixels PXL can be connected to each other. In the step of aligning the light-emitting element LD, the first electrode ELT1 and the second electrode ELT2 can respectively receive a first alignment signal (or a first alignment voltage) and a second alignment signal (or a second alignment voltage). For example, either the first electrode ELT1 or the second electrode ELT2 can receive an alignment signal of an alternating current type, while the other of the first electrode ELT1 and the second electrode ELT2 can receive an alignment voltage with a constant voltage level (e.g., a ground voltage). That is, in the step of aligning the light-emitting element LD, a predetermined alignment signal can be applied to the first electrode ELT1 and the second electrode ELT2. As a result, an electric field can be formed between the first electrode ELT1 and the second electrode ELT2. The light-emitting element LD supplied to the emission area EMA of each pixel PXL can be self-aligned between the first electrode ELT1 and the second electrode ELT2 by the electric field. After the alignment of the light emitting elements LD is completed, the pixels PXL may be formed to be individually driven by disconnecting at least the first electrode ELT1 between the pixels PXL.

[0139] The first electrode ELT1 and the second electrode ELT2 may have various shapes. Figure 13 and Figure 14 As shown in , each of the first electrode ELT1 and the second electrode ELT2 may have a strip shape extending in one direction. For example, each of the first electrode ELT1 and the second electrode ELT2 may have a strip shape extending along a second direction (Y-axis direction) intersecting (e.g., orthogonal to) the first direction (X-axis direction).

[0140] at the same time, Figure 13 and Figure 14 Although the example in which one first electrode ELT1 and one second electrode ELT2 are disposed in each emission area EMA is shown, the number and arrangement of the first electrodes ELT1 and the second electrodes ELT2 disposed in the emission area EMA of the pixel PXL may be variously modified. For example, in another embodiment, a plurality of first electrodes ELT1 and / or a plurality of second electrodes ELT2 may be disposed in the emission area EMA of each pixel PXL.

[0141] When a plurality of first electrodes ELT1 are provided in one pixel PXL, the first electrodes ELT1 may be connected to each other integrally or non-integrally. For example, the first electrodes ELT1 may be connected integrally, or may be connected to each other by a bridge pattern located in a layer different from the layer of the first electrode ELT1 (for example, a circuit layer in which the pixel circuit PXC is provided). Similarly, when a plurality of second electrodes ELT2 are provided in one pixel PXL, the second electrodes ELT2 may be connected to each other integrally or non-integrally. For example, the second electrodes ELT2 may be connected integrally, or may be connected to each other by a bridge pattern located in a layer different from the layer of the second electrode ELT2. That is, the shape, quantity, arrangement direction, mutual setting relationship, etc. of the first electrode ELT1 and the second electrode ELT2 provided in each pixel PXL may be variously changed.

[0142] The first electrode ELT1 can be electrically connected to a predetermined circuit element (e.g., at least one transistor constituting the pixel circuit PXC), a power line (e.g., a first power line PL1), and / or a signal line (e.g., a scan line Si, a data line Dj, or a predetermined control line) through the first contact hole CH1. However, the present disclosure is not limited thereto. For example, in another embodiment, the first electrode ELT1 can be directly connected to a predetermined power line or signal line.

[0143] In an embodiment, the first electrode ELT1 may be electrically connected to a predetermined circuit element disposed below the first electrode ELT1 through a first contact hole CH1, and may be electrically connected to a first line through the circuit element. The first line may be a first power line PL1 for supplying a first power supply VDD, but is not limited thereto. For example, the first line may also be a signal line supplied with a predetermined first drive signal (e.g., a scan signal, a data signal, or a predetermined control signal).

[0144] The second electrode ELT2 can be electrically connected to a predetermined circuit element (e.g., at least one transistor constituting the pixel circuit PXC), a power line (e.g., a second power line PL2), and / or a signal line (e.g., a scan line Si, a data line Dj, or a predetermined control line) through the second contact hole CH2. However, the present disclosure is not limited thereto. For example, in another embodiment, the second electrode ELT2 can be directly connected to a predetermined power line or signal line.

[0145] In an embodiment, the second electrode ELT2 may be electrically connected to a second line disposed below the second electrode ELT2 through a second contact hole CH2. The second line may be a second power line PL2 for supplying a second power source VSS, but is not limited thereto. For example, the second line may also be a signal line supplied with a predetermined second drive signal (e.g., a scan signal, a data signal, or a predetermined control signal).

[0146] The light emitting element LD may be connected between the first electrode ELT1 and the second electrode ELT2. For example, each light emitting element LD may be disposed between the first electrode ELT1 and the second electrode ELT2 in the first direction (X-axis direction) and may be electrically connected between the first electrode ELT1 and the second electrode ELT2.

[0147] at the same time, Figure 13 and Figure 14 All the light emitting elements LD are shown to be uniformly aligned in the first direction (X-axis direction), but the present disclosure is not limited thereto. For example, at least one of the light emitting elements LD may be aligned along a diagonal direction between the first electrode ELT1 and the second electrode ELT2.

[0148] According to the embodiment, each light emitting element LD may be an ultra-small light emitting element having a size as small as, for example, nanometer to micrometer scale using a material having an inorganic crystal structure. Figures 1 to 7 However, the type and / or size of the light emitting element LD may be variously changed according to the design conditions of each light emitting device (e.g., pixel PXL) using the light emitting element LD as a light source.

[0149] Each light-emitting element LD may include a first end EP1 disposed toward the first electrode ELT1 and a second end EP2 disposed toward the second electrode ELT2. The first end EP1 of each light-emitting element LD may be electrically connected to the first electrode ELT1, and the second end EP2 of each light-emitting element LD may be electrically connected to the second electrode ELT2. For example, the first end EP1 of each light-emitting element LD may be electrically connected to the first electrode ELT1 via a first contact electrode CNE1, and the second end EP2 of each light-emitting element LD may be electrically connected to the second electrode ELT2 via a second contact electrode CNE2. In another embodiment, the first end EP1 of each light-emitting element LD may be electrically connected to the first electrode ELT1 by directly contacting the first electrode ELT1. Similarly, the second end EP2 of each light-emitting element LD may be electrically connected to the second electrode ELT2 by directly contacting the second electrode ELT2. In this case, the first contact electrode CNE1 and / or the second contact electrode CNE2 may be selectively formed.

[0150] According to an embodiment, the light-emitting element LD can be prepared in the form of being dispersed in a predetermined solution and can be supplied to the emission area EMA of the pixel PXL by various methods including an inkjet method or a slit coating method. For example, the light-emitting element LD can be mixed with a volatile solvent and supplied to the emission area EMA of each pixel PXL. At this time, when a predetermined alignment voltage (or alignment signal) is applied to the first electrode ELT1 and the second electrode ELT2 of the pixel PXL, the light-emitting element LD is aligned between the first electrode ELT1 and the second electrode ELT2 while an electric field is formed between the first electrode ELT1 and the second electrode ELT2. After the light-emitting element LD is aligned, the light-emitting element LD can be stably arranged between the first electrode ELT1 and the second electrode ELT2 by volatilizing the solvent or removing the solvent by other methods.

[0151] According to the embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 may be formed at both ends (eg, the first end EP1 and the second end EP2) of the light emitting element LD, respectively. Therefore, the light emitting element LD may be more stably connected between the first electrode ELT1 and the second electrode ELT2.

[0152] The first contact electrode CNE1 may be disposed on the first electrode ELT1 and the first end EP1 of the light-emitting element LD, overlapping the first electrode ELT1 and the first end EP1 of at least one light-emitting element LD adjacent to the first electrode ELT1. The first contact electrode CNE1 may electrically connect the first electrode ELT1 and the first end EP1 of the light-emitting element LD. Furthermore, the first contact electrode CNE1 may stably secure the first end EP1 of the light-emitting element LD. In another embodiment, when the first contact electrode CNE1 is not formed, the first end EP1 of the light-emitting element LD may be disposed so as to overlap the first electrode ELT1 adjacent to the first end EP1 and may be directly connected to the first electrode ELT1.

[0153] The second contact electrode CNE2 can be disposed on the second electrode ELT2 and the second end EP2 of the light-emitting element LD, overlapping the second electrode ELT2 and the second end EP2 of at least one light-emitting element LD adjacent to the second electrode ELT2. The second contact electrode CNE2 can electrically connect the second electrode ELT2 and the second end EP2 of the light-emitting element LD. Furthermore, the second contact electrode CNE2 can stably secure the second end EP2 of the light-emitting element LD. In another embodiment, when the second contact electrode CNE2 is not formed, the second end EP2 of the light-emitting element LD can be disposed so as to overlap the second electrode ELT2 adjacent to the second end EP2 and can be directly connected to the second electrode ELT2.

[0154] In the above embodiment, each light emitting element LD connected between the first electrode ELT1 and the second electrode ELT2 in the forward direction may constitute an effective light source of a corresponding pixel PXL. In addition, the effective light sources may be aggregated to constitute a light source unit LSU of a corresponding pixel PXL.

[0155] For example, when the first power source VDD (or a predetermined first control signal including a scan signal, a data signal, etc.) is applied to the first terminal EP1 of the light-emitting element LD via the first power source line PL1, the first electrode ELT1, the first contact electrode CNE1, etc., and the second power source VSS (or a predetermined second control signal including a scan signal, a data signal, etc.) is applied to the second terminal EP2 of the light-emitting element LD via the second power source line PL2, the second electrode ELT2, the second contact electrode CNE2, etc., the light-emitting element LD connected in the forward direction between the first electrode ELT1 and the second electrode ELT2 emits light. Therefore, light is emitted from the pixel PXL.

[0156] Reference Figure 14 The pixel PXL may further include a first bank BNK1 overlapping the first electrode ELT1 and the second electrode ELT2 and a second bank BNK2 surrounding each emission area EMA.

[0157] A first bank BNK1 (also referred to as a partition wall) may be provided under the first and second electrodes ELT1 and ELT2. For example, the first bank BNK1 may be provided under the first and second electrodes ELT1 and ELT2 to overlap one region of each of the first and second electrodes ELT1 and ELT2.

[0158] Since the first bank BNK1 is provided below a region of each of the first electrode ELT1 and the second electrode ELT2, the first electrode ELT1 and the second electrode ELT2 may protrude in an upward direction (third direction (Z-axis direction)) in the region where the first bank BNK1 is formed. The first bank BNK1 may constitute a reflective bank (also referred to as a "reflective partition wall") together with the first and second electrodes ELT1 and ELT2. For example, the first and second electrodes ELT1 and ELT2 and / or the first bank BNK1 may be formed of a reflective material, or at least one reflective material layer may be formed on the protruding sidewalls of the first and second electrodes ELT1 and ELT2 and / or the first bank BNK1. Therefore, light emitted from the first and second ends EP1 and EP2 of the light-emitting element LD facing the first and second electrodes ELT1 and ELT2 may be directed more toward the front of the display panel PNL. As described above, when a region of the first electrode ELT1 and the second electrode ELT2 protrudes in the upward direction through the first dam BNK1, the ratio of light generated in the pixel PXL in the front direction (third direction (Z-axis direction)) facing the display panel PNL can be increased, thereby improving the light efficiency of the pixel PXL.

[0159] Meanwhile, according to embodiments, the first bank BNK1 may be omitted. In this case, the first electrode ELT1 and the second electrode ELT2 may be formed to be substantially flat, or may be formed to have a concave-convex surface. For example, by forming each of the first electrode ELT1 and the second electrode ELT2 with a different thickness for each region, one region of the first electrode ELT1 and the second electrode ELT2 may protrude upward to form a concave-convex surface. Thus, light emitted from the light-emitting element LD can be directed toward the front direction of the display panel PNL (the third direction (Z-axis direction)).

[0160] The second bank BNK2 may be a structure that defines the emission area EMA of each pixel PXL and may be, for example, a pixel defining layer. For example, the second bank BNK2 may be provided in a boundary region of each pixel area PXA in which the pixel PXL is provided and / or in a region between adjacent pixels PXL to surround the emission area EMA of each pixel PXL.

[0161] like Figure 14 As shown in , the second bank BNK2 may overlap one region (e.g., both ends) of the first electrode ELT1 and the second electrode ELT2. In this case, the first contact hole CH1 and the second contact hole CH2 may be formed in the non-emission area NEA to overlap the second bank BNK2, or may be formed inside the emission area EMA to not overlap the second bank BNK2.

[0162] The second bank BNK2 can be constructed to include at least one light-blocking and / or reflective material to prevent light leakage between adjacent pixels PXL. For example, the second bank BNK2 can include various types of black matrix materials (e.g., at least one currently known light-blocking material), color filter materials of specific colors, etc. For example, the second bank BNK2 can be formed of a black opaque pattern to block light transmission. In embodiments, a reflective layer (not shown) can be formed on a surface (e.g., a side surface) of the second bank BNK2 to further improve the light efficiency of the pixels PXL.

[0163] Furthermore, during the supply of the light-emitting element LD to each pixel PXL, the second bank BNK2 can function as a dam structure defining each emission area EMA to which the light-emitting element LD is to be supplied. For example, each emission area EMA can be separated by the second bank BNK2, so that a desired type and / or amount of light-emitting element ink can be supplied to the emission area EMA.

[0164] In an embodiment, in the process of forming the first bank BNK1 of the pixel PXL, the second bank BNK2 may be formed at the same layer as the first bank BNK1 at the same time. In another embodiment, the second bank BNK2 may be formed in the same or different layer as the first bank BNK1 by a process separate from the process of forming the first bank BNK1.

[0165] Figure 15 and Figure 16 is a cross-sectional view of a pixel according to an embodiment. For example, Figure 15 It is along Figure 14 A cross-sectional view taken along line II' of Figure 16 It is along Figure 14 A sectional view taken along line II-II'. Figure 17 yes Figure 15 An enlarged cross-sectional view of area A.

[0166] To illustrate various circuit elements configuring the pixel circuit PXC, Figure 15 An arbitrary transistor T among the circuit elements is shown, Figure 16 A transistor (eg, Figure 9 Hereinafter, when it is not necessary to specify the first transistor T1 individually, the first transistor T1 is also collectively referred to as “transistor T”.

[0167] Meanwhile, the structure of the transistor T and the storage capacitor Cst, the position of each layer, etc. are not limited to Figure 16The embodiments shown in FIG. 3 and may be variously modified according to the embodiments. In addition, in the embodiments, the transistors T constituting each pixel circuit PXC may have substantially the same or similar structures as each other, but are not limited thereto. For example, in another embodiment, at least one of the transistors T constituting the pixel circuit PXC may have a cross-sectional structure different from that of the other transistors T and / or may be provided at a position different from that of the other transistors T.

[0168] Reference Figure 15 and Figure 16 , the pixel PXL according to the embodiment and the display device including the pixel PXL may include a circuit layer PCL and a light emitting element layer DPL disposed on the circuit layer PCL.

[0169] The circuit layer PCL may include a substrate SUB. The substrate SUB may be a rigid substrate or a flexible substrate, and its material or physical properties are not particularly limited. For example, the substrate SUB may be a rigid substrate formed of glass or tempered glass, or a flexible substrate formed of a thin film formed of a plastic or metal material. Furthermore, the substrate SUB may be a transparent substrate, but is not limited thereto.

[0170] The buffer layer BFL may be provided on the substrate SUB. The buffer layer BFL may serve to smooth the surface of the substrate SUB and prevent penetration of moisture or external air. The buffer layer BFL may be an inorganic layer constructed of a single layer or a multilayer.

[0171] Various circuit elements such as a transistor T and a storage capacitor Cst and various wires connected to the circuit elements may be disposed on the buffer layer BFL. Meanwhile, according to embodiments, the buffer layer BFL may be omitted, and in this case, at least one circuit element and / or wire may be directly disposed on one surface of the substrate SUB.

[0172] Each transistor T includes a semiconductor pattern SCL (also referred to as a "semiconductor layer" or an "active layer"), a gate electrode GE, and a first transistor electrode TE1 and a second transistor electrode TE2. Figure 15 and Figure 16 In the embodiment in which each transistor T includes a first transistor electrode TE1 and a second transistor electrode TE2 formed separately from the semiconductor pattern SCL, the present disclosure is not limited thereto. For example, in another embodiment, the first transistor electrode TE1 and / or the second transistor electrode TE2 included in at least one transistor T may be integrally constructed with each semiconductor pattern SCL.

[0173] The semiconductor pattern SCL may be disposed on the buffer layer BFL. For example, the semiconductor pattern SCL may be disposed between the substrate SUB on which the buffer layer BFL is formed and the gate insulating layer GI. The semiconductor pattern SCL may include a first region contacting each first transistor electrode TE1, a second region contacting each second transistor electrode TE2, and a channel region between the first and second regions. Depending on the embodiment, one of the first and second regions may be a source region, and the other may be a drain region.

[0174] According to an embodiment, the semiconductor pattern SCL may be a semiconductor pattern formed of polycrystalline silicon, amorphous silicon, an oxide semiconductor, etc. In addition, the channel region of the semiconductor pattern SCL may be an intrinsic semiconductor as a semiconductor pattern not doped with impurities, and each of the first and second regions of the semiconductor pattern SCL may be a semiconductor pattern doped with predetermined impurities.

[0175] In an embodiment, the semiconductor patterns SCL of the transistors T constituting each pixel circuit PXC may be formed of substantially the same or similar materials. For example, the semiconductor patterns SCL of the transistors T may be formed of any one of the same materials: polysilicon, amorphous silicon, and an oxide semiconductor. In another embodiment, a portion of the transistors T and the remaining portion of the transistors T may include semiconductor patterns SCL formed of different materials. For example, the semiconductor patterns SCL of a portion of the transistors T may be formed of polysilicon or amorphous silicon, while the semiconductor patterns SCL of another portion of the transistors T may be formed of an oxide semiconductor.

[0176] The gate insulating layer GI may be provided on the semiconductor pattern SCL. The gate insulating layer GI may be constructed as a single layer or multiple layers and may include at least one inorganic insulating material and / or organic insulating material. For example, the gate insulating layer GI may include various types of organic / inorganic insulating materials (including silicon nitride (SiN x ), silicon oxide (SiO x )wait).

[0177] The gate electrode GE may be disposed on the gate insulating layer GI. Figure 15 and Figure 16 The transistor T of a top gate structure is shown, but in another embodiment, the transistor T may have a bottom gate structure. In this case, the gate electrode GE may be disposed under the semiconductor pattern SCL to overlap the semiconductor pattern SCL.

[0178] The first interlayer insulating layer ILD1 may be provided on the gate electrode GE. For example, the first interlayer insulating layer ILD1 may be provided between the gate electrode GE and the first transistor electrode TE1 and the second transistor electrode TE2. The first interlayer insulating layer ILD1 may be configured as a single layer or a multilayer, and may include at least one inorganic insulating material and / or an organic insulating material. For example, the first interlayer insulating layer ILD1 may include various types of organic / inorganic insulating materials (including silicon nitride (SiN x ), silicon oxide (SiO x ), and the construction material of the first interlayer insulating layer ILD1 is not particularly limited.

[0179] The first transistor electrode TE1 and the second transistor electrode TE2 may be disposed on each semiconductor pattern SCL, with at least one first interlayer insulating layer ILD1 interposed therebetween. For example, the first transistor electrode TE1 and the second transistor electrode TE2 may be disposed with the gate insulating layer GI and the first interlayer insulating layer ILD1 interposed therebetween, and may be disposed on different ends of the semiconductor pattern SCL. The first transistor electrode TE1 and the second transistor electrode TE2 may be electrically connected to each semiconductor pattern SCL. For example, the first transistor electrode TE1 and the second transistor electrode TE2 may be connected to the first region and the second region of the semiconductor pattern SCL via contact holes passing through the gate insulating layer GI and the first interlayer insulating layer ILD1. Depending on the embodiment, one of the first transistor electrode TE1 and the second transistor electrode TE2 may be a source electrode, and the other may be a drain electrode.

[0180] At least one transistor T included in the pixel circuit PXC may be connected to at least one pixel electrode. Figure 9 The first transistor T1 shown in FIG. 1 and the like may be electrically connected to the first electrode ELT1 of the corresponding pixel PXL through a contact hole (eg, a first contact hole CH1 ) passing through the passivation layer PSV and / or the bridge pattern BRP.

[0181] The storage capacitor Cst includes a first capacitor electrode CE1 and a second capacitor electrode CE2 stacked on each other. Each of the first capacitor electrode CE1 and the second capacitor electrode CE2 may be constructed as a single layer or multiple layers. In addition, at least one of the first capacitor electrode CE1 and the second capacitor electrode CE2 may be provided in the same layer as at least one electrode or the semiconductor pattern SCL configuring the first transistor T1.

[0182] For example, the first capacitor electrode CE1 may be configured as a multi-layer electrode including a lower electrode LE provided in the same layer as the semiconductor pattern SCL of the first transistor T1 and an upper electrode UE provided in the same layer as the first transistor electrode TE1 and the second transistor electrode TE2 of the first transistor T1 and electrically connected to the lower electrode LE. Furthermore, the second capacitor electrode CE2 may be configured as a single-layer electrode provided in the same layer as the gate electrode of the first transistor T1 and between the lower electrode LE and the upper electrode UE of the first capacitor electrode CE1.

[0183] However, the structure and / or position of each of the first capacitor electrode CE1 and the second capacitor electrode CE2 may be variously modified. For example, in another embodiment, either of the first capacitor electrode CE1 and the second capacitor electrode CE2 may include a conductive pattern disposed in a layer different from the layer in which the electrodes of the first transistor T1 (e.g., the gate electrode GE and the first and second transistor electrodes TE1 and TE2) and the semiconductor pattern SCL are constructed. For example, the first capacitor electrode CE1 or the second capacitor electrode CE2 may have a single-layer structure or a multi-layer structure including a conductive pattern disposed on the second interlayer insulating layer ILD2.

[0184] In an embodiment, at least one signal line and / or power line connected to each pixel PXL may be provided on the same layer as one electrode of a circuit element configuring the pixel circuit PXC. For example, the scan line Si of each pixel PXL may be provided on the same layer as the gate electrode GE of the transistor T, and the data line Dj of each pixel PXL may be provided on the same layer as the first transistor electrode TE1 and the second transistor electrode TE2 of the transistor T.

[0185] The first power line PL1 and / or the second power line PL2 may be provided in the same layer as the gate electrode GE of the transistor T or the first and second transistor electrodes TE1 and TE2, or may be provided in a different layer from the gate electrode GE of the transistor T or the first and second transistor electrodes TE1 and TE2. For example, the second power line PL2 for supplying the second power source VSS may be provided on the second interlayer insulating layer ILD2 and may be at least partially covered by the passivation layer PSV. The second power line PL2 may be electrically connected to the second electrode ELT2 of the light source unit LSU provided on the passivation layer PSV via a second contact hole CH2 passing through the passivation layer PSV. However, the position and / or structure of the first power line PL1 and / or the second power line PL2 may be variously modified. For example, in another embodiment, the second power line PL2 may be provided in the same layer as the gate electrode GE of the transistor T or the first and second transistor electrodes TE1 and TE2, and may be electrically connected to the second electrode ELT2 via at least one bridge pattern and / or second contact hole CH2 (not shown).

[0186] The second interlayer insulating layer ILD2 may be provided on the first interlayer insulating layer ILD1 and may cover the first transistor electrode TE1 and the second transistor electrode TE2, the storage capacitor Cst, etc. located on the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 may be constructed as a single layer or a multilayer and may include at least one inorganic insulating material and / or an organic insulating material. For example, the second interlayer insulating layer ILD2 may include various types of organic / inorganic insulating materials (such as silicon nitride (SiN x ) or silicon oxide (SiO x ), and the construction material of the second interlayer insulating layer ILD2 is not particularly limited. A bridge pattern BRP for connecting at least one circuit element (e.g., the first transistor T1) included in the pixel circuit PXC to the first electrode ELT1, the first power line PL1, and / or the second power line PL2 may be provided on the second interlayer insulating layer ILD2.

[0187] However, according to an embodiment, the second interlayer insulating layer ILD2 may be omitted. In this case, the second interlayer insulating layer ILD2 may be omitted. Figure 16 The bridge pattern BRP and the like may be provided, and the second power line PL2 may be provided in a layer on which one electrode of the transistor T is provided.

[0188] The passivation layer PSV may be provided on circuit elements including the transistor T and the storage capacitor Cst and / or on lines including the first power line PL1 and the second power line PL2. The passivation layer PSV may be constructed as a single layer or multiple layers and may include at least one inorganic insulating material and / or an organic insulating material. For example, the passivation layer PSV may include at least an organic insulating layer and may substantially flatten the surface of the circuit layer PCL. The light-emitting element layer DPL may be provided on the passivation layer PSV.

[0189] The light-emitting element layer DPL may include a plurality of electrodes ELT1 and ELT2, a light-emitting element LD, and a first electrode ELT1 and a second electrode ELT2, which constitute the light source unit LSU of each pixel PXL, and include a plurality of contact electrodes CNE1 and CNE2 and an insulating pattern INP for more stably connecting the light-emitting element LD. In addition, the light-emitting element layer DPL may further optionally include a first bank BNK1 for causing an area of ​​each of the first electrode ELT1 and the second electrode ELT2 to protrude upward and / or a second bank BNK2 surrounding each emission area EMA. The first bank BNK1 may be provided on the passivation layer PSV of the circuit layer PCL. The first bank BNK1 may be formed in a separate or integrated pattern. The first bank BNK1 may protrude in a third direction (Z-axis direction) on one surface of the substrate SUB on which the circuit layer PCL is formed.

[0190] According to embodiments, the first bank BNK1 may have various shapes. In embodiments, the first bank BNK1 may be formed to have an inclined surface (eg, Figure 16 In another embodiment, the first bank BNK1 may have a cross-section of a semicircular shape, a semi-elliptical shape, etc., but is not limited thereto.

[0191] The first bank BNK1 may include an insulating material including at least one inorganic material and / or organic material. For example, the first bank BNK1 may include at least one inorganic layer including various inorganic insulating materials (such as silicon nitride (SiN x ) or silicon oxide (SiO x Alternatively, the first bank BNK1 may include an organic layer including at least one layer of various types of organic insulating materials, a photoresist layer, or the like, or may be constructed of a single-layer insulator or a multi-layer insulator including a combination of organic and inorganic materials. In other words, the construction material and / or pattern shape of the first bank BNK1 may be variously modified.

[0192] In an embodiment, the first bank BNK1 may function as a reflective member. For example, the first bank BNK1, together with the first electrode ELT1 and the second electrode ELT2 disposed on the first bank BNK1, may function as a reflective member that guides light emitted from each light-emitting element LD in a desired direction (e.g., the third direction (Z-axis direction)) to improve light efficiency of the pixel PXL. Depending on the embodiment, the first bank BNK1 may be omitted.

[0193] The first electrode ELT1 and the second electrode ELT2 constituting the pixel electrode of each pixel PXL may be disposed on the first bank BNK1. According to an embodiment, the first electrode ELT1 and the second electrode ELT2 may have a shape corresponding to the first bank BNK1. For example, the first electrode ELT1 and the second electrode ELT2 may protrude in the third direction (Z-axis direction) while each having an inclined surface or a curved surface corresponding to the first bank BNK1. Meanwhile, when the first bank BNK1 is not formed, the first electrode ELT1 and the second electrode ELT2 may be formed substantially flat on the passivation layer PSV, or may be formed to have different thicknesses for each region, so that one region may protrude in the third direction (Z-axis direction) of the substrate SUB.

[0194] Each of the first and second electrodes ELT1 and ELT2 may include at least one conductive material. For example, each of the first and second electrodes ELT1 and ELT2 may include at least one metal selected from various metal materials (including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), copper (Cu), and the like), and alloys thereof, conductive oxides (such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), zinc tin oxide (ZTO), gallium tin oxide (GTO), and fluorine-doped tin oxide (FTO)), and conductive polymers (such as PEDOT), but is not limited thereto. For example, each of the first and second electrodes ELT1 and ELT2 may include other conductive materials (such as carbon nanotubes or graphene). That is, each of the first electrode ELT1 and the second electrode ELT2 may have conductivity by including at least one of various conductive materials, and the construction material thereof is not particularly limited. In addition, the first electrode ELT1 and the second electrode ELT2 may include the same conductive material or different conductive materials.

[0195] The first insulating layer INS1 may be provided on one region of the first and second electrodes ELT1 and ELT2. For example, the first insulating layer INS1 may be formed to cover one region of each of the first and second electrodes ELT1 and ELT2, and may include an opening that exposes another region of each of the first and second electrodes ELT1 and ELT2. For example, the first insulating layer INS1 may expose one region of the first and second electrodes ELT1 and ELT2 on each first bank BNK1. Meanwhile, depending on embodiments, the first insulating layer INS1 may be omitted.

[0196] In an embodiment, the first insulating layer INS1 can be formed to substantially completely cover the first and second electrodes ELT1 and ELT2. After the light-emitting elements LD are supplied and aligned on the first insulating layer INS1, the first insulating layer INS1 can be partially opened to expose a region of each of the electrodes ELT1 and ELT2 in a region on each first bank BNK1. Alternatively, in another embodiment, after the light-emitting elements LD are supplied and aligned, the first insulating layer INS1 can be patterned in the form of a separate pattern that is only partially positioned below the light-emitting elements LD. After forming the first and second electrodes ELT1 and ELT2, the first insulating layer INS1 can be formed to cover the first and second electrodes ELT1 and ELT2 to prevent damage to the first and second electrodes ELT1 and ELT2 in subsequent processes. Furthermore, the first insulating layer INS1 can be used to stably support each light-emitting element LD.

[0197] The first insulating layer INS1 may be constructed as a single layer or multiple layers and may include at least one inorganic insulating material and / or organic insulating material. For example, the first insulating layer INS1 may include various types of currently known organic / inorganic insulating materials (including silicon nitride (SiN x ), silicon oxide (SiO x ) or aluminum oxide (Al 2 O 3 )). The structural material of the first insulating layer INS1 is not particularly limited.

[0198] A plurality of light-emitting elements LD may be supplied and aligned on the first insulating layer INS1. For example, the plurality of light-emitting elements LD may be supplied to the emission region of each pixel PXL by an inkjet method, a slit coating method, or various other methods. Furthermore, the light-emitting elements LD may be aligned between the first and second electrodes ELT1 and ELT2 with directionality by applying a predetermined alignment signal (or alignment voltage) to each of the first and second electrodes ELT1 and ELT2. In embodiments, the light-emitting elements LD may also be electrically connected to the first and second electrodes ELT1 and ELT2 via contact electrodes CNE1 and CNE2.

[0199] The insulating pattern INP may be provided on the light emitting element LD. For example, the insulating pattern INP may be partially provided on only one region including the central region of each light emitting element LD, while exposing one end and the other end of the light emitting element LD. The insulating pattern INP may be formed as an independent pattern. The insulating pattern INP may be constructed as a single layer or a multilayer, and may include at least one inorganic insulating material and / or an organic insulating material. For example, the insulating pattern INP may include various types of currently known organic / inorganic insulating materials (including silicon nitride (SiN x ), silicon oxide (SiO x ), aluminum oxide (Al2O3), etc.). When the insulating pattern INP is formed on the light emitting element LD after the alignment of the light emitting element LD is completed, the light emitting element LD can be prevented from being separated from the aligned position. In addition, the insulating pattern INP can prevent the contact electrodes CNE1 and CNE2 from being short-circuited, thereby stably ensuring the contact between the light emitting element LD and the contact electrodes CNE1 and CNE2. For a detailed description thereof, refer to Figure 17 .

[0200] Reference Figure 17 , one surface of the insulating pattern INP may include a concave-convex pattern PD. The concave-convex pattern PD may be formed by dry etching, but is not necessarily limited thereto. In an embodiment, the concave-convex pattern PD may include a plurality of protrusions P1 and recesses P2. The concave-convex pattern PD may have a shape in which a plurality of protrusions P1 and recesses P2 are irregularly arranged. That is, as Figure 17 As shown in FIG, a plurality of protrusion portions P1 and recessed portions P2 may be formed in various widths and heights. However, the present disclosure is not necessarily limited thereto, and the concavo-convex pattern PD may have a constant width and height.

[0201] A conductive material layer CL may be disposed in the recessed portion P2 of the concavo-convex pattern PD. The conductive material layer CL may be formed simultaneously with the contact electrodes CNE1 and CNE2, described later. In other words, the conductive material layer CL may be formed of the same material as the contact electrodes CNE1 and CNE2. The thickness HC of the conductive material layer CL in the third direction (Z-axis direction) may be smaller than the thickness HP of the protrusion P1 in the third direction (Z-axis direction). Here, the thickness HP of the protrusion P1 in the third direction (Z-axis direction) may represent the average thickness of the plurality of protrusions P1.

[0202] Contact electrodes CNE1 and CNE2 may be provided on one side and the other side of the insulating pattern INP. For example, the first contact electrode CNE1 and the second contact electrode CNE2 may be spaced apart from each other, with the insulating pattern INP between the first contact electrode CNE1 and the second contact electrode CNE2. The first contact electrode CNE1 may be provided on one side of the insulating pattern INP to contact the first electrode ELT1 and one end of the light-emitting element LD. Furthermore, the second contact electrode CNE2 may be provided on the other side of the insulating pattern INP to contact the second electrode ELT2 and the other end of the light-emitting element LD.

[0203] In an embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 can be formed from the same conductive layer. That is, the first contact electrode CNE1 and the second contact electrode CNE2 can be formed simultaneously. In this case, the number of masks can be reduced, thereby simplifying the manufacturing process of the display device. In addition, since it is difficult to form a conductive layer on the protrusion P1 of the concavo-convex pattern PD, the first contact electrode CNE1 and the second contact electrode CNE2 can be separated by the concavo-convex pattern PD. Therefore, even if the first contact electrode CNE1 and the second contact electrode CNE2 are formed simultaneously, the concavo-convex pattern PD can prevent a short circuit between the first contact electrode CNE1 and the second contact electrode CNE2.

[0204] The first contact electrode CNE1 and the second contact electrode CNE2 may include the same material. According to embodiments, the contact electrodes CNE1 and CNE2 may be formed of various transparent conductive materials. For example, the contact electrodes CNE1 and CNE2 may include at least one of various transparent conductive materials including ITO, IZO, and ITZO, and may be implemented to be substantially transparent or translucent to meet a predetermined light transmittance.

[0205] The second insulating layer INS2 may be disposed on the insulating pattern INP and the contact electrodes CNE1 and CNE2. The second insulating layer INS2 may directly cover the concavo-convex pattern PD of the insulating pattern INP and the contact electrodes CNE1 and CNE2. That is, the second insulating layer INS2 may directly contact the concavo-convex pattern PD of the insulating pattern INP and the contact electrodes CNE1 and CNE2. For example, the second insulating layer INS2 may be disposed on the entire surface of the substrate SUB. The second insulating layer INS2 may include at least one inorganic layer and / or organic layer. In an embodiment, the second insulating layer INS2 may include a thin-film encapsulation layer having a multi-layer structure. For example, the second insulating layer INS2 may be configured as a thin-film encapsulation layer having a multi-layer structure including at least two inorganic insulating layers and at least one organic insulating layer disposed between the at least two inorganic insulating layers, but is not necessarily limited thereto.

[0206] According to an embodiment, at least one coating layer OC may be further provided on the second insulating layer INS2. The coating layer OC may be constructed as a single layer or multiple layers and may include at least one inorganic insulating material and / or organic insulating material. For example, each coating layer OC may include various types of currently known organic / inorganic insulating materials.

[0207] According to the display device according to the above embodiment, since the insulating pattern INP includes the concavo-convex pattern PD, the first and second contact electrodes CNE1 and CNE2 can be prevented from being short-circuited, and thus process economy can be improved by simultaneously forming the first and second contact electrodes CNE1 and CNE2.

[0208] Hereinafter, a display device according to another embodiment of the present disclosure is described. In the following embodiments, the same configurations as those already described are denoted by the same reference numerals, and repeated descriptions are omitted or simplified.

[0209] Figure 18 is a cross-sectional view of a pixel according to another embodiment. Figure 18 is with Figure 15 The cross-sectional view corresponding to area A.

[0210] Reference Figure 18 , the display device according to this embodiment and Figures 1 to 17 The embodiment is different in that the insulation pattern INP partially includes the concavo-convex pattern PD.

[0211] Specifically, the upper surface S1 of the insulating pattern INP may not include the concavo-convex pattern PD, and only the side surface S2 of the insulating pattern INP may partially include the concavo-convex pattern PD. In this case, the surface roughness of the side surface S2 of the insulating pattern INP may be greater than that of the upper surface S1 of the insulating pattern INP.

[0212] The first contact electrode CNE1 and the second contact electrode CNE2 can be formed simultaneously from the same conductive layer. In this case, the number of masks can be reduced, thereby simplifying the manufacturing process of the display device as described above. Furthermore, the first contact electrode CNE1 and the second contact electrode CNE2 can be separated by the concavo-convex pattern PD of the side surface S2 of the insulating pattern INP. Therefore, even if the first contact electrode CNE1 and the second contact electrode CNE2 are formed simultaneously, the concavo-convex pattern PD described above can prevent short circuits between the first contact electrode CNE1 and the second contact electrode CNE2.

[0213] A conductive pattern CP may be further provided on the upper surface S1 of the insulating pattern INP. The conductive pattern CP may be provided between the first contact electrode CNE1 and the second contact electrode CNE2. The conductive pattern CP may be formed simultaneously with the contact electrodes CNE1 and CNE2. That is, the thickness of the conductive pattern CP in the third direction (Z-axis direction) may be substantially the same as the thickness of the contact electrodes CNE1 and CNE2 in the third direction (Z-axis direction). In addition, the conductive pattern CP may be formed of the same material as the contact electrodes CNE1 and CNE2. The conductive pattern CP may be floated by the concave-convex pattern PD of the side surface S2 of the insulating pattern INP. That is, the conductive pattern CP may be electrically separated from the first contact electrode CNE1 and the second contact electrode CNE2.

[0214] The second insulating layer INS2 may be disposed on the insulating pattern INP, the contact electrodes CNE1 and CNE2, and the conductive pattern CP. The second insulating layer INS2 may directly cover the side surface S2 of the insulating pattern INP. That is, the second insulating layer INS2 may directly contact the concavo-convex pattern PD of the side surface S2 of the insulating pattern INP. The conductive pattern CP may be interposed between the second insulating layer INS2 and the upper surface S1 of the insulating pattern INP, and thus the second insulating layer INS2 may not contact the upper surface S1 of the insulating pattern INP.

[0215] Subsequently, a method of manufacturing the display device according to the above-described embodiment is described.

[0216] Figures 19 to 24 is a cross-sectional view of each process step of the method for manufacturing a display device according to an embodiment. Figures 1 to 17 Substantially the same configuration is denoted by the same reference numerals, and detailed reference numerals are omitted.

[0217] Reference Figure 19 , a light-emitting element LD is supplied and aligned on the first insulating layer INS1. The light-emitting element LD can be prepared in a dispersed form in a predetermined solution, and can be supplied to the emission area of ​​each pixel PXL by an inkjet printing method or the like. For example, the light-emitting element LD can be mixed with a volatile solvent and dropped onto each emission area. At this time, when a predetermined voltage is supplied through the first electrode ELT1 and the second electrode ELT2, while an electric field is formed between the first electrode ELT1 and the second electrode ELT2, the light-emitting element LD can be aligned between the first electrode ELT1 and the second electrode ELT2. After the light-emitting element LD is aligned, the solvent can be evaporated or removed by other methods to stably arrange the light-emitting element LD between the first electrode ELT1 and the second electrode ELT2.

[0218] Reference Figure 20Then, an insulating material layer IML is formed on the light emitting element LD. The insulating material layer IML can be made of various types of currently known organic / inorganic insulating materials (including silicon nitride (SiN x ), silicon oxide (SiO x ), aluminum oxide (Al 2 O 3 ), etc. Subsequently, a photoresist pattern PR is formed on the insulating material layer IML, and then the insulating material layer IML is dry-etched using the photoresist pattern PR as a barrier.

[0219] Reference Figure 21 , the insulating pattern INP is formed by dry etching the insulating material layer IML. In this process, a small amount of residual layer of the photoresist pattern PR may remain on the insulating pattern INP. In a state where a small amount of the photoresist pattern PR exists on the insulating pattern INP, the insulating pattern INP may be further etched to form a concave-convex pattern PD (such as Figure 22 ). That is, the insulating pattern INP can be partially etched through a small amount of the photoresist pattern PR to form a plurality of protrusions P1 and a plurality of recessed portions P2. At this time, by adjusting the etching process conditions, the concavo-convex pattern PD can be easily formed on the surface of the insulating pattern INP. For example, by reducing the oxygen flow rate in the etching gas and shortening the etching time within a range in which a small amount of the photoresist pattern PR can remain, the concavo-convex pattern PD can be more easily formed.

[0220] Reference Figure 23 , the first contact electrode CNE1 and the second contact electrode CNE2 are simultaneously formed on the light-emitting element LD. This reduces the number of masks, simplifying the display device manufacturing process as described above. Furthermore, since forming a conductive layer on the protruding portion P1 of the concave-convex pattern PD is difficult, the first and second contact electrodes CNE1 and CNE2 can be separated. Therefore, even if the first and second contact electrodes CNE1 and CNE2 are formed simultaneously, the concave-convex pattern PD prevents short circuits between the first and second contact electrodes CNE1 and CNE2. According to embodiments, during the process of forming the first and second contact electrodes CNE1 and CNE2, a conductive material layer CL can be further formed in the recessed portion P2 of the concave-convex pattern PD.

[0221] Reference Figure 24 Subsequently, a second insulating layer INS2 may be formed on the insulating pattern INP, the first contact electrode CNE1, and the second contact electrode CNE2, thereby completing Figure 17The second insulating layer INS2 may be configured as a thin film encapsulation layer having a multi-layer structure including at least two inorganic insulating layers and at least one organic insulating layer interposed between the at least two inorganic insulating layers, but is not necessarily limited thereto.

[0222] It will be appreciated by those skilled in the art that the present disclosure may be implemented in a modified form without departing from the basic characteristics described above. Therefore, the disclosed method should be considered from a descriptive perspective rather than a restrictive perspective. The scope is indicated in the claims, not in the above description, and all differences within the scope are to be construed as included in the present disclosure.

Claims

1. A display device, comprising: substrate; a first electrode and a second electrode, disposed on the substrate and spaced apart from each other; a light-emitting element, disposed between the first electrode and the second electrode; an insulating pattern, disposed on the light-emitting element; a first contact electrode disposed on one side of the insulating pattern and contacting one end of the light emitting element and the first electrode; as well as a second contact electrode, disposed on the other side of the insulating pattern and contacting the other end of the light emitting element and the second electrode; Wherein, the surface of the insulating pattern includes a concave-convex pattern, The concave-convex pattern includes a plurality of protruding portions and concave portions, and Wherein, the display device further includes a conductive material layer arranged in the recessed portion.

2. The display device according to claim 1, wherein The first contact electrode and the second contact electrode include the same material.

3. The display device according to claim 1, wherein The insulating pattern exposes the one end of the light emitting element and the other end of the light emitting element.

4. The display device according to claim 1, wherein The first contact electrode and the second contact electrode are spaced apart from each other, and the insulation pattern is interposed between the first contact electrode and the second contact electrode.

5. The display device according to claim 1 , further comprising: An insulating layer covers the first contact electrode and the second contact electrode. The display device according to claim 5 , wherein: The insulating layer covers the concavo-convex pattern.

7. The display device according to claim 1, wherein The conductive material layer includes the same material as the first contact electrode and the second contact electrode.

8. The display device according to claim 1, wherein The thickness of the conductive material layer is formed to be thinner than the thickness of the protruding portion.

9. A display device, comprising: substrate; a first electrode and a second electrode, disposed on the substrate and spaced apart from each other; a light-emitting element, disposed between the first electrode and the second electrode; an insulating pattern, disposed on the light-emitting element; a first contact electrode disposed on one side of the insulating pattern and contacting one end of the light emitting element and the first electrode; a second contact electrode disposed on the other side of the insulating pattern and contacting the other end of the light emitting element and the second electrode; as well as a conductive pattern disposed on an upper surface of the insulating pattern, Wherein, the surface of the insulating pattern includes a concave-convex pattern, and The surface roughness of the side surface of the insulating pattern is greater than the surface roughness of the upper surface of the insulating pattern.

10. The display device according to claim 9, wherein The conductive pattern is disposed between the first contact electrode and the second contact electrode.

11. The display device according to claim 9, wherein The conductive pattern is electrically separated from the first contact electrode and the second contact electrode.

12. The display device according to claim 9, wherein The conductive pattern includes the same material as the first contact electrode and the second contact electrode.

13. The display device according to claim 9, wherein: The thickness of the conductive pattern is the same as that of the first contact electrode and the second contact electrode.

14. The display device according to claim 13, further comprising: An insulating layer is provided on the first contact electrode and the second contact electrode.

15. The display device according to claim 14, wherein The insulating layer directly covers the side surfaces of the insulating patterns.

16. The display device according to claim 14, wherein: The insulating layer does not contact the upper surface of the insulating pattern.

17. The display device according to claim 14, wherein: The conductive pattern is disposed between the upper surface of the insulating pattern and the insulating layer.

Images