Frame Encoding and Optical Network Unit (ONU) Synchronization in Passive Optical Networks (PON)

Abstract

A method is implemented by an ONU in a PON. The method includes receiving an encoded DS PHY frame from an OLT, the encoded DS PHY frame including codewords, the codewords including an SFC field and a payload, the SFC field and the payload being encoded with the same FEC; decoding the codewords using the FEC to obtain a decoded SFC field and a payload; performing a first verification on the decoded SFC field when a synchronization state machine is in a synchronized state; remaining in the synchronized state when the first verification is successful or exiting the synchronized state when the first verification is unsuccessful.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the priority of U.S. Provisional Patent Application No. 62 / 993,422, entitled "Synchronization State Machine for 50G - PON", filed on March 23, 2020 by Futurewei Technologies, Inc., which is incorporated herein by reference. Technical Field

[0003] The disclosed embodiments generally relate to optical networks, and more particularly to frame encoding and ONU synchronization in PON. Background Art

[0004] An optical network is a network that uses optical signals to carry data. Light sources such as lasers generate optical signals. Modulators modulate the optical signals with data to produce modulated optical signals. Various components transmit, propagate, amplify, receive, and process the modulated optical signals. Optical networks can implement multiplexing to achieve high bandwidth. Optical networks enable data centers, metropolitan area networks, PONs, long - haul transmission systems, and other applications. Summary of the Invention

[0005] In a first aspect, a method implemented by an ONU in a PON includes: receiving an encoded DS PHY frame from an OLT, the encoded DS PHY frame including codewords, the codewords including an SFC field and a payload, the SFC field and the payload being encoded with the same FEC; decoding the codewords using FEC to obtain a decoded SFC field and a payload; performing a first verification on the decoded SFC field when the synchronization state machine is in a synchronized state; and remaining in the synchronized state when the first verification is successful or exiting the synchronized state when the first verification is unsuccessful.

[0006] In a first implementation form of the first aspect, the codewords further include a PSync field, wherein the method further includes: performing a second verification on the PSync field when in the synchronized state; and remaining in the synchronized state when the second verification is successful or exiting the synchronized state when the second verification is unsuccessful.

[0007] In a second implementation form of the first aspect or the above - mentioned implementation forms of the first aspect, the method further includes: performing the second verification using K, where K≥7.

[0008] In a third implementation form of the first aspect or the above - mentioned implementation forms of the first aspect, the FEC uses LDPC codes.

[0009] In a fourth implementation form of the first aspect or the above implementation form of the first aspect, the LDPC code is based on a mother code of size (17,664, 14,592), where 17,664 is the bit length of the codeword and 14,592 is the bit length of the payload.

[0010] In a fifth implementation form of the first aspect or the above implementation form of the first aspect, the length of the LDPC code is 17,280 bits.

[0011] In a sixth implementation form of the first aspect or the above implementation form of the first aspect, the method further includes: initializing in the search state of the synchronization state machine; entering the pre-synchronization state of the synchronization state machine from the search state; and entering the synchronization state from the pre-synchronization state.

[0012] In a seventh implementation form of the first aspect or the above implementation form of the first aspect, the method further includes: entering the pre-synchronization state from the search state based on PSync pattern matching and SFC verification.

[0013] In an eighth implementation form of the first aspect or the above implementation form of the first aspect, the PSync pattern matching is based on K, where K ≥ 7.

[0014] In a ninth implementation form of the first aspect or the above implementation form of the first aspect, the SFC verification is based on the additional parity bits in the HEC field and BCH(63, 12).

[0015] In a tenth implementation form of the first aspect or the above implementation form of the first aspect, the method further includes: entering the synchronization state from the pre-synchronization state based on PSync pattern matching and SFC verification.

[0016] In an eleventh implementation form of the first aspect or the above implementation form of the first aspect, the PSync pattern matching is based on K, where K ≥ 7.

[0017] In a twelfth implementation form of the first aspect or the above implementation form of the first aspect, the SFC verification is based on two consecutive valid SFC readings.

[0018] In a thirteenth implementation form of the first aspect or the above implementation form of the first aspect, the method further includes: entering the pre-synchronization state from the search state only based on PSync pattern matching; and entering the synchronization state from the pre-synchronization state only based on PSync pattern matching.

[0019] In a fourteenth implementation form of the first aspect or the above implementation form of the first aspect, the PSync pattern matching is based on K, where K ≥ 7.

[0020] In the fifteenth implementation form of the first aspect or the above-mentioned implementation form of the first aspect, the PSync pattern matching is based on 64-bit PSync.

[0021] In the sixteenth implementation form of the first aspect or the above-mentioned implementation form of the first aspect, the PSync pattern matching is also based on K, where K = 7.

[0022] In the seventeenth implementation form of the first aspect or the above-mentioned implementation form of the first aspect, the PSync pattern matching is based on a 128-bit pattern.

[0023] In the eighteenth implementation form of the first aspect or the above-mentioned implementation form of the first aspect, the PSync pattern matching is also based on K, where 18 ≤ K ≤ 28.

[0024] In the nineteenth implementation form of the first aspect or the above-mentioned implementation form of the first aspect, the 128-bit pattern is [PSync PSync'], where PSync' is the opposite of PSync, and PSync is [0xC5E5 1840FD59 BB49].

[0025] In the twentieth implementation form of the first aspect or the above-mentioned implementation form of the first aspect, the method further includes: entering the pre-synchronization state from the search state only based on the PSync pattern matching; and entering the synchronization state from the pre-synchronization state based on the second verification of the first FEC codeword.

[0026] In the twenty-first implementation form of the first aspect or the above-mentioned implementation form of the first aspect, the method further includes: when the second verification fails, returning from the pre-synchronization state to the search state.

[0027] In the twenty-second implementation form of the first aspect or the above-mentioned implementation form of the first aspect, the PSync pattern matching is based on K, where K ≥ 7.

[0028] In the twenty-third implementation form of the first aspect or the above-mentioned implementation form of the first aspect, the PSync pattern matching is based on the 64-bit pattern [0xC5E5 1840FD59 BB49].

[0029] In the twenty-fourth implementation form of the first aspect or the above-mentioned implementation form of the first aspect, the PSync pattern matching is also based on K, where K = 7.

[0030] In the twenty-fifth implementation form of the first aspect or the above-mentioned implementation form of the first aspect, the PSync pattern matching is based on a 128-bit pattern.

[0031] In the twenty-sixth implementation form of the first aspect or the above-mentioned implementation form of the first aspect, the PSync pattern matching is also based on K, where 18 ≤ K ≤ 28.

[0032] In the twenty-seventh implementation form of the first aspect or the above-mentioned implementation form of the first aspect, the 128-bit pattern is [PSync PSync'], where PSync' is the opposite of PSync, and PSync is [0xC5E5 1840FD59 BB49].

[0033] In the twenty-eighth implementation form of the first aspect or the above-mentioned implementation form of the first aspect, the method further includes: entering the resynchronization state of the synchronization state machine from the synchronization state.

[0034] In the twenty-ninth implementation form of the first aspect or the above-mentioned implementation form of the first aspect, the method further includes: entering the resynchronization state from the synchronization state when the PSync pattern matches or the SFC verification fails.

[0035] In the thirtieth implementation form of the first aspect or the above-mentioned implementation form of the first aspect, the method further includes: returning from the resynchronization state to the synchronization state when the PSync pattern matches and the SFC verification is successful.

[0036] In the thirty-first implementation form of the first aspect or the above-mentioned implementation form of the first aspect, the method further includes: remaining in the resynchronization state up to (M–2) consecutive failures of the PSync pattern match and the SFC verification.

[0037] In the thirty-second implementation form of the first aspect or the above-mentioned implementation form of the first aspect, the method further includes: returning from the resynchronization state to the search state of the synchronization state machine when the PSync pattern matches or the SFC verification fails (M–1) times.

[0038] In the thirty-third implementation form of the first aspect or the above-mentioned implementation form of the first aspect, M≥2.

[0039] In the thirty-fourth implementation form of the first aspect or the above-mentioned implementation form of the first aspect, the method further includes: returning from the resynchronization state to the synchronization state when the PSync pattern matches and the SFC verification is successful.

[0040] In the thirty-fifth implementation form of the first aspect or the above-mentioned implementation form of the first aspect, the codeword further includes PSBd, and PSBd includes a PSync field and an SFC field.

[0041] In the thirty-sixth implementation form of the first aspect or the above-mentioned implementation form of the first aspect, PSBd is not scrambled.

[0042] In the thirty-seventh implementation form of the first aspect or the above-mentioned implementation form of the first aspect, within the codeword, only the PSync field is not scrambled.

[0043] In the thirty-eighth implementation form of the first aspect or the above-mentioned implementation form of the first aspect, before decoding the codeword, the method further includes descrambling the codeword using a descrambler.

[0044] In the thirty-ninth implementation form of the first aspect or the above-mentioned implementation form of the first aspect, the method further includes: using the scrambling polynomial x 58 +x 39 +1 to further descramble the codeword.

[0045] In the fortieth implementation form of the first aspect or the above-mentioned implementation form of the first aspect, the method further includes: using a variable starting bit sequence based on the SFC field to descramble the codeword.

[0046] In the forty-first implementation form of the first aspect or the above-mentioned implementation form of the first aspect, the variable starting bit sequence is [1 1 1 1 1 1 1 SFC], and where "SFC" represents the bits of the SFC field.

[0047] In the forty-second implementation form of the first aspect or the above-mentioned implementation form of the first aspect, the method further includes: using a fixed starting sequence based on a fixed bit pattern to descramble the codeword.

[0048] In the forty-third implementation form of the first aspect or the above-mentioned implementation form of the first aspect, the fixed starting bit sequence is 58 "1" bits.

[0049] In the forty-fourth implementation form of the first aspect or the above-mentioned implementation form of the first aspect, after decoding the codeword, the method further includes descrambling the payload using a descrambler.

[0050] In the forty-fifth implementation form of the first aspect or the above-mentioned implementation form of the first aspect, the method further includes: using the scrambling polynomial x 58 +x 39 +1 to descramble the payload.

[0051] In the forty-sixth implementation form of the first aspect or the above-mentioned implementation form of the first aspect, the descrambler is also based on the self-scrambling of the data.

[0052] In the forty-seventh implementation form of the first aspect or the above-mentioned implementation form of the first aspect, the descrambler is based on scrambling using a known bit pattern starting with a fixed starting bit sequence.

[0053] In the forty-eighth implementation form of the first aspect or the above-mentioned implementation form of the first aspect, the fixed starting bit sequence is 58 "1" bits.

[0054] In the forty-ninth implementation form of the first aspect or the above-mentioned implementation forms of the first aspect, the descrambler is based on scrambling using a known bit pattern with a variable starting bit sequence, and the variable starting bit sequence includes the decoded SFC field.

[0055] In the fiftieth implementation form of the first aspect or the above-mentioned implementation forms of the first aspect, the variable starting bit sequence is [1 1 1 1 1 1 1 SFC], and wherein, "SFC" represents the bits of the decoded SFC field.

[0056] In the fifty-first implementation form of the first aspect or the above-mentioned implementation forms of the first aspect, the variable starting bit sequence is [1 0 1 0 1 0 1 SFC], and wherein, "SFC" represents the bits of the decoded SFC field.

[0057] In the fifty-first implementation form of the first aspect or the above-mentioned implementation forms of the first aspect, the PON is 50G-PON.

[0058] In a second aspect, an ON includes: a memory for storing instructions; a processor coupled to the memory and for executing the instructions to perform any one of the first aspect or the above-mentioned implementation forms of the first aspect.

[0059] In a third aspect, a computer program product includes computer-executable instructions stored in a non-transitory medium, and when the computer-executable instructions are executed by a processor, cause the ON to perform any one of the first aspect or the above-mentioned implementation forms of the first aspect.

[0060] Any one of the above embodiments can be combined with any one of the above other embodiments to create a new embodiment. These and other features will be more clearly understood from the following detailed description in conjunction with the drawings and the claims. Description of the Drawings

[0061] To more comprehensively understand the present disclosure, reference is now made to the following brief description in conjunction with the drawings and specific embodiments, wherein like reference numerals represent like components.

[0062] Figure 1 is a schematic diagram of a PON.

[0063] Figure 2 is a schematic diagram of a device.

[0064] Figure 3 is a message sequence diagram of PON communication.

[0065] Figure 4 is a schematic diagram of a DS PHY frame in XG-PON.

[0066] Figure 5 It is a diagram of a synchronization state machine.

[0067] Figure 6 It is a schematic diagram of a DS PHY frame in 50G-PON.

[0068] Figure 7 It is a schematic diagram of an encoded DS PHY frame.

[0069] Figure 8 It is a diagram of the synchronization state machine provided by the first embodiment.

[0070] Figure 9 It is a diagram of the synchronization state machine provided by the second embodiment.

[0071] Figure 10 It is a diagram of the synchronization state machine provided by the third embodiment.

[0072] Figure 11 It is a flowchart showing the method for generating an encoded DS PHY frame provided by the embodiment.

[0073] Figure 12 It is a flowchart showing the method for decoding an encoded DS PHY frame provided by the embodiment.

[0074] Figure 13 It is a flowchart showing the synchronization method provided by the embodiment.

[0075] Figure 14 It is a flowchart showing the synchronization method provided by another embodiment. Detailed implementation manners

[0076] First, it should be understood that although the following provides illustrative implementations of one or more embodiments, the disclosed system and / or method can be implemented using any number of techniques, whether currently known or existing. The present disclosure should in no way be limited to the illustrative embodiments, diagrams, and techniques described below, including the exemplary designs and embodiments illustrated and described herein, but may be modified within the full scope of the appended claims and their equivalents.

[0077] The following abbreviations apply:

[0078] ASIC: Application-Specific Integrated Circuit

[0079] BCH: Bose–Chaudhuri–Hocquenghem

[0080] BER: Bit Error Ratio

[0081] CO: Central Office

[0082] CPU: Central Processing Unit

[0083] DS: Downstream

[0084] DSP: Digital Signal Processor

[0085] EO: Electrical-to-optical

[0086] FEC: Forward Error Correction

[0087] FPGA: Field-Programmable Gate Array

[0088] FtS: FEC then scramble

[0089] Gb / s: Gigabit(s) per second

[0090] HEC: Hybrid Error Control

[0091] IEEE: Institute of Electrical and Electronics Engineers

[0092] LDPC: Low-Density Parity-Check

[0093] ODN: Optical Distribution Network

[0094] OE: Optical-to-electrical

[0095] OLT: Optical Line Terminal

[0096] ONT: Optical Network Terminal

[0097] ONU: Optical Network Unit

[0098] PHY: Physical Layer

[0099] PON: Passive Optical Network

[0100] PON-ID: PON Identifier

[0101] PSBd: DS Physical Synchronization Block

[0102] PSync: Physical Synchronization (Sequence)

[0103] P2MP: Point-to-Multipoint

[0104] RAM: Random-Access Memory

[0105] RF: Radio Frequency

[0106] ROM: Read-Only Memory

[0107] RX: Receiver Unit

[0108] SFC: Superframe Counter

[0109] SRAM: Static RAM

[0110] StF: Scramble then FEC

[0111] sync: Synchronization

[0112] TCAM: Ternary Content-Addressable Memory

[0113] TX: Transmitter Unit

[0114] US: Upstream

[0115] XG-PON: 10-gigabit-capable PON

[0116] μs: microsecond

[0117] 50G-PON: 50-gigabit-capable PON

[0118] Figure 1 FIG. is a schematic diagram of PON 100. PON 100 includes an OLT 110, an ONU 120, and an ODN 130 that couples the OLT 110 to the ONU 120. PON 100 is a communication network that can distribute data between the OLT 110 and the ONU 120 without requiring active components. Instead, PON 100 can use passive optical components in the ODN 130 to distribute data.

[0119] The OLT 110 communicates with another network and the ONU 120. For example, the OLT 110 forwards data from another network to the ONU 120 and forwards data from the ONU 120 to another network. The OLT 110 is typically located in a central location, such as a CO, but it can also be located in other suitable locations.

[0120] The ODN 130 is a data distribution network that includes optical cables, couplers, splitters, distributors, and other suitable components. These components include passive optical components that do not require power to distribute data between the OLT 110 and the ONU 120. The ODN 130 can extend from the OLT 110 to the ONU 120 in the branched configuration shown, or it can be configured in any other suitable P2MP configuration.

[0121] The ONU 120 communicates with the OLT 110 and the customer. For example, the ONU 120 forwards data from the OLT 110 to the customer and forwards data from the customer to the OLT 110. The ONU 120 is similar to an ONT, and these terms can be used interchangeably. The ONU 120 is typically located in distributed locations, such as customer premises, but they can also be located in other suitable locations.

[0122] Figure 2It is a schematic diagram of device 200. Device 200 can implement OLT 110 and ONU 120. Device 200 includes: an input port 210 and an RX 220 or a receiving device for receiving data; a processor 230 or a processing device, or a logic unit, a baseband unit or a CPU for processing data; a TX 240 or a transmitting device and an output port 250 for transmitting data; a memory 260 or a data storage device for storing data. Device 200 may also include an OE component, an EO component or an RF component coupled to the input port 210, RX 220, TX 240 and output port 250 to provide an entry and exit for optical signals, electrical signals or RF signals.

[0123] Processor 230 is any combination of hardware, middleware, firmware or software. Processor 230 includes any combination of one or more CPU chips, cores, FPGAs, ASICs or DSPs. Processor 230 communicates with the input port 210, RX 220, TX 240, output port 250 and memory 260. Processor 230 includes a synchronization component 270 that implements the disclosed embodiments. Synchronization component 270 may include an FEC encoder and a scrambler / descrambler. In some embodiments, synchronization component 270 includes instructions executed by processor 230 to perform FEC encoder and scrambler / descrambler operations or functions. Therefore, including synchronization component 270 significantly improves the function of device 200 and enables device 200 to transform to different states. Alternatively, memory 260 stores synchronization component 270 as instructions, and processor 230 executes these instructions.

[0124] Memory 260 includes any combination of magnetic disks, tape drives or solid state drives. Device 200 may use memory 260 as an overflow data storage device to store these programs when device 200 selects programs for execution, and to store the instructions and data read by device 200 during the execution of these programs. Memory 260 may store additional or other data not mentioned herein. Memory 260 may be volatile or non-volatile, and may be any combination of ROM, RAM, TCAM or SRAM.

[0125] A computer program product may include computer-executable instructions stored in a non-transitory medium, which when executed by a processor cause the device to execute any embodiment. The non-transitory medium may be memory 260, the processor may be processor 230, and the device may be device 200.

[0126] Figure 3 It is a message sequence diagram 300 of PON communication. In step 310, OLT 110 generates a DS PHY frame. The DS PHY frame may be as Figure 4As shown. In step 320, the OLT 110 sends a signal stream to the ONU 120. The signal stream includes DS PHY frames. In step 330, the ONU 120 performs synchronization for each DS PHY frame. The ONU 120 can perform synchronization as described below. In step 340, the ONU 120 processes each DS PHY frame. For example, the ONU 120 can process the payload of the DS PHY frame to provide to the customer. In step 350, the ONU 120 generates US PHY frames. For example, the ONU 120 uses data from the customer to generate US PHY frames. Finally, in step 360, the ONU 120 sends a burst signal. The burst signal includes US PHY frames.

[0127] Figure 4 is a schematic diagram of the DS PHY frame 400 in XG-PON. The DS PHY frame 400 has 155,520 bytes, corresponding to 125 μs at a data rate of 9.95328 Gb / s in XG-PON. The DS PHY frame 400 includes 24 bytes of PSBd 410 and 155,496 bytes of payload 490. The PSBd 410 facilitates synchronization in the ONU 120. The PSBd 410 includes an 8-byte PSync field 420, an 8-byte SFC structure field 430, and an 8-byte PON-ID structure field 440. The PSync field 420 is fixed with a repeating 64-bit pattern. The SFC structure field 430 includes a 51-bit SFC field 450 and a 13-bit HEC field 460. The PON-ID structure field 440 includes a 51-bit PON-ID field 470 and a 13-bit HEC field 480. The payload 490 includes data intended for the customer of the ONU 120.

[0128] Figure 5 is a diagram of the synchronization state machine 500. The ONU 120 implements the synchronization state machine 500. The synchronization state machine 500 includes a search state 510, a pre-synchronization state 520, a synchronization state 530, and a re-synchronization state 540.

[0129] When the ONU 120 detects a valid DS signal, the ONU 120 enters the search state 510. In the search state 510, the ONU 120 searches for a locally stored predetermined PSync in the first DS PHY frame 400. Specifically, the ONU 120 searches for the PSync in the PSync field 420. If there is no exact PSync match, the ONU 120 remains in the search state 510. If there is an exact PSync match, the ONU 120 determines whether the 8 bytes immediately following the PSync form an available SFC, where an available SFC means an SFC for which the HEC indicates there are no uncorrectable errors. If so, the ONU 120 locally stores the 8 bytes as the SFC and enters the pre-synchronization state 520. If not, the ONU 120 remains in the search state 510.

[0130] In the pre-synchronization state 520, the ONU 120 searches for the PSync in the second DS PHY frame 400. The ONU 120 matches the PSync using the maximum allowable number of error bits K. In XG-PON, K = 2, such that the ONU 120 only needs to match 62 out of the 64 bits of the PSync. If there is no PSync match, the ONU 120 returns to the search state 510. If there is a PSync match, the ONU 120 determines whether the 8 bytes immediately following the PSync are verified as an SFC, where being verified as an SFC means the 8 bytes form an SFC for which the HEC indicates there are no uncorrectable errors. If so, the ONU 120 advances to the synchronization state 530. If not, the ONU 120 returns to the search state 510.

[0131] In the synchronization state 530, the ONU 120 continues to match the PSync and verify the SFC for additional DS PHY frames 400. Again, the ONU 120 uses K to match the PSync. If there is a PSync match and a verified SFC, the ONU 120 remains in the synchronization state 530. If there is no PSync match or no verified SFC, the ONU 120 enters the re-synchronization state 540.

[0132] In the re-synchronization state 540, the ONU 120 continues to match the PSync and verify the SFC for additional DS PHY frames 400. Again, the ONU 120 uses K to match the PSync. If there is a PSync match and a verified SFC, the ONU 120 returns to the synchronization state 530. If there is no PSync match or no verified SFC in M - 1 consecutive frames, the ONU 120 returns to the search state 510. M is a positive integer representing the maximum number of verification failures allowed starting from the synchronization state. For example, M = 3.

[0133] In XG-PON, the OLT 110 encodes the payload 490 using FEC. The target BER threshold of FEC in XG-PON is about 1e–3. This results in achieving synchronization within about 8 DS PHY frames 400 and a false synchronization loss occurring approximately once every 10 years. Compared with XG-PON, FEC in 50G-PON may be more powerful. The target BER threshold of FEC in 50G-PON can be about 3e–2, which is much higher than the 1e–3 BER threshold in XG-PON. At the higher BER threshold in 50G-PON, the HEC field 460 may not be able to reliably protect the SFC field 450. Specifically, achieving synchronization may require 100 DS PHY frames 400, which is much more than the 8 DS PHY frames 400 in XG-PON, and a false synchronization loss occurs less than once per second, which is much more frequent than once every 10 years. Therefore, it is necessary to improve the DS PHY frame 400 and the synchronization state machine 500 in the following way: provide fast synchronization and infrequent synchronization loss while maintaining a BER of 3e–2.

[0134] Embodiments of frame encoding and ONU synchronization in PON are disclosed herein. These embodiments provide that the OLT encodes the SFC field using the same FEC as that used by the OLT to encode the payload. The ONU decodes the SFC and uses the SFC in the synchronization state machine. The ONU also modifies the synchronization state machine by increasing K, using K in the search state, and not considering the SFC in the search state or the pre-synchronization state. These embodiments and other embodiments provide fast synchronization, which means achieving synchronization with a sufficiently small number of DS PHY frames. At the same time, these embodiments and other embodiments maintain or increase the probability of false synchronization loss and false synchronization lock, and at the same time provide a reasonable BER.

[0135] Figure 6 is a schematic diagram of a DS PHY frame 600 in 50G-PON. The DS PHY frame 600 is similar to Figure 4The DS PHY frame 400 therein. Specifically, the DS PHY frame 600 includes a PSBd 610 and a payload 690, which are respectively similar to the PSBd 410 and the payload 490. The PSBd 610 includes a PSync field 620, an SFC structure field 630, and a PON-ID structure field 640, which are respectively similar to the PSync field 420, the SFC structure field 430, and the PON-ID structure field 440. The SFC structure field 630 includes an SFC field 650 and an HEC field 660, which are respectively similar to the SFC field 450 and the HEC field 460. The PON-ID structure field 640 includes a PON-ID field 670 and an HEC field 680, which are respectively similar to the PON-ID field 470 and the HEC field 480.

[0136] However, different from the DS PHY frame 400 being 155,520 bytes, the DS PHY frame 600 is 777,600 bytes. Different from the payload 490 being 155,496 bytes, the payload 690 is 777,576 bytes.

[0137] The first embodiment

[0138] In the first embodiment, first, the OLT 110 encodes the PSBd 610 including the SFC field 650 using FEC to obtain Figure 7 the codeword shown. The ONU 120 receives the codeword and decodes the codeword. The FEC can be the same FEC used by the OLT 110 to encode the payload 690. The FEC can use an LDPC code. The LDPC code can be based on a mother code of size (17,664, 14,592), where 17,664 is the codeword length and 14,592 is the payload length. The mother code can be the same as the code used in IEEE 802.3ca, and the code matrix of the code used in IEEE 802.3ca is a 12×69 quasi-cyclic matrix with a cyclic size of 256, corresponding to a codeword length of 17,664 bits. The payload length of each codeword is 256×57 bits, or 14,592 bits, and the parity check length of each codeword is (12×69) bits, or 3,072 bits. The LDPC code can be a shortened version or a punctured version of the mother code. When 384 bits are removed from the parity check bits, the LDPC codeword length becomes 17,280 bits, such that each DS PHY frame 600 includes 360 codewords. The code rate of the resulting LDPC code (17,280, 14,592) is 0.844.

[0139] Figure 7It is a schematic diagram of the encoded DS PHY frame 700. The encoded DS PHY frame 700 is generated by encoding the DS PHY frame 600. Similarly, the DS PHY frame 600 is generated by decoding the encoded DS PHY frame 700. The encoded DS PHY frame 700 includes codeword 1 710, codeword 2 720, codeword 359 730, and codeword 360 740. The ellipsis between codeword 2 720 and codeword 359 730 indicates the existence of codewords 3 to 358. Each of the codewords 710 to 740 is 17,280 bits.

[0140] Codeword 1 710 includes PSBd 610, payload 750, and parity 760. PSBd 610 includes PSync field 620, SFC structure field 630, and PON-ID structure field 640. SFC structure field 630 includes SFC field 650 and HEC field 660. PON-ID structure field 640 includes PON-ID field 670 and HEC field 680. Payload 750 includes data that the OLT 110 wishes to transfer to the ONU 120, such as user data. Payload 750 can be a part of payload 690. Parity 760 includes bits that ensure accurate data transmission.

[0141] Codeword 360 740 includes a payload 770 similar to the payload 750 in codeword 1 710 and includes a parity 780 similar to the parity 760 in codeword 1 710. However, codeword 360 740 does not include a PSBd similar to PSBd 610 in codeword 1 710. Similarly, none of the remaining codewords 720 to 730 include PSBd 610.

[0142] Returning to the first embodiment, second, the OLT 110 scrambles the payload 490. The ONU 120 performs descrambling before or after decoding. When the ONU 120 verifies the SFC in the pre-synchronization state, the ONU 120 uses an XG-PON descrambler that uses a scrambling polynomial x with a variable starting bit sequence [1 1 1 1 1 1 1 SFC] 58 +x 39 +1, where "SFC" represents the bits of the SFC verified in the pre-synchronization state. When the ONU 120 does not verify the SFC in the pre-synchronization state, the ONU 120 uses a different descrambler that includes a scrambling polynomial x with a fixed starting bit sequence 58 +x 39 +1. The fixed starting bit sequence can include 58 "1" bits.

[0143] Third, the ONU 120 increases K to a suitable value. For example, the ONU 120 increases K such that K≥7. In addition, the ONU 120 uses K in the search state.

[0144] Figure 8 is a diagram of the synchronization state machine 800 provided by the first embodiment. The synchronization state machine 800 is similar to Figure 5 the synchronization state machine 500 in [reference]. Specifically, the synchronization state machine 800 includes a search state 810, a pre-synchronization state 820, a synchronization state 830, and a re-synchronization state 840, which are respectively similar to the search state 510, the pre-synchronization state 520, the synchronization state 530, and the re-synchronization state 540.

[0145] However, different from the ONU 120 precisely matching the PSync in the search state 510, in the search state 810, the ONU 120 uses K to match the PSync. Different from the ONU using K = 2 in the pre-synchronization state 520, the synchronization state 530, and the re-synchronization state 540, in the pre-synchronization state 820, the synchronization state 830, and the re-synchronization state 840, the ONU 120 increases K as described above. Different from the ONU 120 verifying the undecoded SFC in the synchronization state 530 and the re-synchronization state 540, in the synchronization state 830 and the re-synchronization state 840, the ONU 120 verifies the decoded SFC. Therefore, the ONU 120 does not decode the SFC until the synchronization state 830.

[0146] When N = 64, M = 3, and the BER threshold is 1e –3 , XG-PON provides a false synchronization loss probability of approximately 10 –13 , a false synchronization lock probability of approximately 10 –46 , approximately 10 years between false loss of synchronization, approximately 10 34 years between false lock synchronizations, and approximately 8 DS PHY frames 600 required for synchronization to occur. N represents the number of bits in the PSync field 620 and the locally stored predetermined PSync. In contrast, in the case where the BER threshold is 2e –2 , the first embodiment provides a false synchronization loss probability of approximately 10 –3 to 10 –22 , a false synchronization lock probability of approximately 10 –42 to 10 –26 , approximately 10 –9 to 10 10 years between false synchronization losses, approximately 10 30 to 10 14years, and about 30 to 10 DS PHY frames 600 required for synchronization to occur. The range corresponds to increasing K from 2 to 10. Thus, compared to XG-PON, the first embodiment maintains or even improves the probability of false synchronization loss and false synchronization lock at a worse BER 2e –2 while providing a reasonable number of DS PHY frames 600 required for synchronization. The increase in the number of DS PHY frames 600 required for synchronization is due to the difficulty in obtaining available and verified SFCs before decoding in the synchronization state 830.

[0147] Second Embodiment

[0148] In the second embodiment, the OLT 110 and the ONU 120 implement aspects of the first embodiment. Specifically, first, the OLT 110 encodes the PSBd 610 and the ONU 120 decodes the codeword. Second, the OLT 110 scrambles the PSBd 610 and the ONU 120 performs descrambling. Third, the ONU 120 increases K.

[0149] Fourth, in addition to those aspects of the first embodiment, in the search state or the pre-synchronization state, the ONU 120 does not consider the SFC. Instead, in the synchronization state, the ONU 120 first considers the SFC. This enables the ONU 120 to quickly enter the synchronization state, thereby reducing the number of DS PHY frames 600 required for synchronization to occur.

[0150] Fifth, the OLT 110 and the ONU 120 increase N. For example, the OLT 110 and the ONU 120 increase N such that N ≥ 128. The PSync field 620 may include 64-bit PSync followed by 64-bit PSync', where PSync' is the opposite of PSync. The 64-bit PSync may be [0xC5e5 1840fd59 bb49]. To accommodate the increased N, the OLT 110 and the ONU 120 may correspondingly reduce the number of bits in the payload 690.

[0151] Figure 9 is a diagram of the synchronization state machine 900 provided by the second embodiment. The synchronization state machine 900 is similar to Figure 8 the synchronization state machine 800 in. Specifically, the synchronization state machine 900 includes a search state 910, a pre-synchronization state 920, a synchronization state 930, and a re-synchronization state 940, which are similar to the search state 810, the pre-synchronization state 820, the synchronization state 830, and the re-synchronization state 840, respectively.

[0152] However, unlike in search state 810 where the ONU 120 determines whether the 8 bytes immediately following PSync form an available SFC, in search state 910, the ONU 120 does not make this determination. Unlike in pre-sync state 820 where the ONU 120 determines whether the 8 bytes immediately following PSync are verified as an SFC, in pre-sync state 920, the ONU 120 does not make this determination. Unlike in search state 810, pre-sync state 820, sync state 830, and resync state 840 where the ONU 120 uses N = 64, in search state 910, pre-sync state 920, sync state 930, and resync state 940, the ONU 120 uses N ≥ 128.

[0153] When N = 64, M = 3, and the BER threshold is 2e –2 then, the second embodiment provides a false sync loss probability of approximately 10 –3 to 10 –22 a false sync lock probability of approximately 10 –25 to 10 –9 between false sync losses of approximately 10 –9 to 10 10 years, between false sync locks of approximately 10 13 to 10 –3 years, and approximately 20 to 2 DS PHY frames 600 required for synchronization to occur. The ranges correspond to increasing K from 2 to 10. When K = 7, the false sync loss probability and the false sync lock probability are approximately the same. Additionally, when K ≥ 7, 2 DS PHY frames 600 are required for synchronization to occur. For these reasons, K = 7 can provide the best performance. Thus, compared to XG-PON, when N = 64, the second embodiment can increase the probability of false sync loss and provide a reasonable false sync lock probability while reducing the number of DS PHY frames 600 required for synchronization. Compared to the first embodiment, the second embodiment reduces the number of DS PHY frames 600 required for synchronization while providing a reasonable false sync loss probability.

[0154] When N = 128, M = 3, and the BER threshold is 5e –2 then, the second embodiment provides a false sync loss probability of approximately 10 –14 to 10 –34 a false sync lock probability of approximately 10 –27 to 10 –14 between false sync losses of approximately 10 2 to 10 22 years, between false sync locks of approximately 10 15 to 10 2years, and about 2 DS PHY frames 600 required for synchronization to occur. The range corresponds to increasing K from 18 to 28. Thus, compared with XG-PON, when N = 128, the second embodiment can increase the false synchronization lock probability and provide a reasonable false synchronization lock probability while reducing the number of DS PHY frames 600 required for synchronization. Compared with the first embodiment, the second embodiment reduces the number of DS PHY frames 600 required for synchronization while providing a reasonable false synchronization lock probability. Compared with the second embodiment when N = 64, the second embodiment when N = 128 further reduces the probabilities of false synchronization loss and false synchronization lock.

[0155] Third Embodiment

[0156] In the third embodiment, the OLT 110 and the ONU 120 implement aspects of the second embodiment. Specifically, first, the OLT 110 encodes the PSBd 610, and the ONU 120 decodes the codeword. Second, the OLT 110 scrambles the PSBd 610, and the ONU 120 performs descrambling. Third, the ONU 120 increases K. Fourth, in the search state or the pre-synchronization state, the ONU 120 does not consider the SFC, and first considers the SFC in the synchronization state. Fifth, the OLT 110 and the ONU 120 increase N.

[0157] Sixth, in addition to those aspects of the second embodiment, the ONU 120 verifies the first FEC codeword instead of PSync in the pre-synchronization state. In terms of position, the first FEC codeword can be the first codeword that the ONU 120 identifies as being encoded with FEC. For example, the first FEC codeword is the codeword 1 710.

[0158] Figure 10 is a diagram of the synchronization state machine 1000 provided by the third embodiment. The synchronization state machine 1000 is similar to Figure 9 the synchronization state machine 900 in. Specifically, the synchronization state machine 1000 includes a search state 1010, a pre-synchronization state 1020, a synchronization state 1030, and a re-synchronization state 1040, which are respectively similar to the search state 910, the pre-synchronization state 920, the synchronization state 930, and the re-synchronization state 940.

[0159] However, different from the ONU 120 matching the PSync in the pre-synchronization state 920, in the pre-synchronization state 1020, the ONU 120 verifies that the first FEC codeword is error-free or has no uncorrectable errors. If the ONU 120 verifies the first FEC codeword, the ONU 120 enters the synchronization state 1030. If the ONU 120 cannot verify the first FEC codeword, the ONU 120 returns to the search state 1010. This enables the ONU 120 to enter the synchronization state 1030 with a relatively low false synchronization locking probability.

[0160] When N = 64, M = 3, and the BER threshold is 2e –2 , the third embodiment provides a false synchronization loss probability of approximately 10 –3 to 10 –22 , a false synchronization locking probability of approximately 10 –86 to 10 –78 , between false synchronization losses of approximately 10 –9 to 10 10 years, between false synchronization lockings of approximately 10 73 to 10 65 years, and approximately 5 to 1 DS PHY frames 600 required for synchronization to occur. The range corresponds to increasing K from 2 to 10. When K ≥ 7, only one DS PHY frame 600 is required, and the ONU 120 can match the PSync and verify the first FEC codeword using the same DS PHY frame 600.

[0161] Line conditioning, FEC alignment, data framing, and layer ordering alternatives

[0162] The OLT 110 and the ONU 120 can implement various conditioning, coding, and scrambling alternatives. For example, the OLT 110 and the ONU 120 can implement a self-synchronizing scrambler or a frame-synchronizing scrambler line conditioning with block coding. The OLT 110 and the ONU 120 can implement frame synchronization with block coding or packet-based FEC alignment. The OLT 110 and the ONU 120 can implement periodic pattern or block-coded data framing. Finally, the OLT 110 and the ONU 120 can implement FtS or StF layer ordering. The above alternatives provide 36 design implementation combinations.

[0163] Figure 11It is a flowchart of the method 1100 for generating an encoded DS PHY frame provided by the embodiment. The OLT 110 implements the method 1100. In step 1110, the SFC field and the payload are encoded using FEC to form codewords. For example, the OLT 110 encodes the SFC field 650 and the payload 750 to form the codeword 1 710. In step 1120, an encoded DS PHY frame is generated using the codewords. For example, the OLT 110 uses the codeword 1 710 to generate the encoded DS PHY frame 700. Finally, in step 1130, the encoded DS PHY frame is transmitted. For example, the OLT 110 transmits the encoded DS PHY frame 700 to the ONU 120.

[0164] Figure 12 It is a flowchart of the method 1200 for decoding an encoded DS PHY frame provided by the embodiment. The ONU 120 implements the method 1200. In step 1210, the encoded DS PHY frame is received. For example, the ONU 120 receives the encoded DS PHY frame 700 from the OLT 110. In step 1220, the encoded DS PHY frame is parsed to obtain the codewords. For example, the ONU 120 parses the encoded DS PHY frame 700 to obtain the codeword 1 710. Finally, in step 1230, the codewords are decoded using FEC to obtain the SFC field and the payload. For example, the ONU 120 decodes the codeword 1 710 to obtain the SFC field 650 and the payload 750.

[0165] Figure 13 It is a flowchart of the synchronization method 1300 provided by the embodiment. The ONU 120 implements the method 1300. In step 1310, the synchronization state machine is initialized in the search state. For example, the ONU 120 initializes the synchronization state machine 800 in the search state 810, initializes the synchronization state machine 900 in the search state 910, or initializes the synchronization state machine 1000 in the search state 1010. In step 1320, the encoded DS PHY frame is received. For example, the ONU 120 receives the encoded DS PHY frame 700 from the OLT 110. Finally, in step 1330, when the PSync field matches the locally stored PSync with K error bits, the search state enters the pre-synchronization state of the synchronization state machine. For example, when the PSync field 620 matches the locally stored PSync, the ONU 120 enters the pre-synchronization state 820 from the search state 810, enters the pre-synchronization state 920 from the search state 910, or enters the pre-synchronization state 1020 from the search state 1010.

[0166] Figure 14It is a flowchart of the synchronization method 1400 provided by another embodiment. The ONU 120 implements the method 1400. In step 1410, an encoded DS PHY frame is received from the OLT. The encoded DS PHY frame includes codewords. The codewords include an SFC field and a payload. The SFC field and the payload are encoded using the same FEC. For example, the ONU 120 receives the encoded DS PHY frame 700 from the OLT 110. In step 1420, the codewords are decoded using the FEC to obtain the decoded SFC field and payload. For example, the ONU 120 decodes the codeword 1 710 to obtain the SFC field 650 and the payload 750.

[0167] In step 1430, when the synchronization state machine is in the synchronization state, a first verification is performed on the decoded SFC field. For example, when in the synchronization states 830, 930, or 1030, the ONU 120 verifies the SFC field 650. Finally, in step 1440, when the first verification is successful, it remains in the synchronization state, or when the first verification is unsuccessful, it exits the synchronization state. For example, the ONU 120 remains in the synchronization states 830, 930, or 1030 or enters the resynchronization states 840, 940, or 1040.

[0168] The method 1400 can implement additional embodiments. For example, the codewords further include a PSync field, and the method further includes: when in the synchronization state, performing a second verification on the PSync field; further remaining in the synchronization state when the second verification is successful; further exiting the synchronization state when the second verification is unsuccessful. The method further includes performing the second verification using K, where K≥7.

[0169] The FEC uses an LDPC code. The LDPC code is based on a mother code of size (17,664, 14,592), where 17,664 is the bit length of the codeword and 14,592 is the bit length of the payload. The length of the LDPC code is 17,280 bits.

[0170] The method further includes: initializing in the search state of the synchronization state machine; entering the pre-synchronization state of the synchronization state machine from the search state; entering the synchronization state from the pre-synchronization state. The method further includes entering the pre-synchronization state from the search state based on PSync pattern matching and SFC verification. The PSync pattern matching is based on K, where K≥7. The SFC verification is based on the additional parity bits in the HEC field and BCH(63,12). The method further includes entering the synchronization state from the pre-synchronization state based on PSync pattern matching and SFC verification. The PSync pattern matching is based on K, where K≥7. The SFC verification is based on two consecutive valid SFC readings. The method further includes: entering the pre-synchronization state from the search state based only on PSync pattern matching; entering the synchronization state from the pre-synchronization state based only on PSync pattern matching. The PSync pattern matching is based on K, where K≥7. The PSync pattern matching is based on 64-bit PSync. The PSync pattern matching is also based on K, where K = 7. The PSync pattern matching is based on a 128-bit pattern. The PSync pattern matching is also based on K, where 18≤K≤28. The 128-bit pattern is [PSync PSync'], where PSync' is the opposite of PSync, and where PSync is [0xC5E5 1840FD59 BB49]. The method further includes: entering the pre-synchronization state from the search state based only on PSync pattern matching; entering the synchronization state from the pre-synchronization state based on a second verification of the first FEC codeword. The method further includes returning to the search state from the pre-synchronization state when the second verification fails. The PSync pattern matching is based on K, where K≥7. The PSync pattern matching is based on the 64-bit pattern [0xC5E5 1840FD59 BB49]. The PSync pattern matching is also based on K, where K = 7. The PSync pattern matching is based on a 128-bit pattern. The PSync pattern matching is also based on K, where 18≤K≤28. The 128-bit pattern is [PSync PSync'], where PSync' is the opposite of PSync, and where PSync is [0xC5E51840FD59 BB49].

[0171] The method further includes entering a resynchronization state of a synchronization state machine from a synchronization state. The method further includes entering the resynchronization state from the synchronization state when a PSync pattern matches or an SFC verification fails. The method further includes returning from the resynchronization state to the synchronization state when the PSync pattern matches and the SFC verification succeeds. The method further includes: remaining in the resynchronization state for at most (M–2) consecutive failures of the PSync pattern match and the SFC verification. The method further includes returning from the resynchronization state to a search state of the synchronization state machine when the PSync pattern matches or the SFC verification fails (M–1) times. M≥2. The method further includes returning from the resynchronization state to the synchronization state when the PSync pattern matches and the SFC verification succeeds.

[0172] The codeword further includes a PSBd, and wherein the PSBd includes a PSync field and an SFC field. The PSBd is not scrambled. In the codeword, only the PSync field is not scrambled.

[0173] Before decoding the codeword, the method further includes descrambling the codeword using a descrambler. The method further includes further descrambling the codeword using a scrambling polynomial x 58 +x 39 +1. The method further includes further descrambling the codeword using a variable starting bit sequence based on the SFC field. The variable starting bit sequence is [1 1 1 1 1 1 1 SFC], and wherein, "SFC" represents the bits of the SFC field. The method further includes descrambling the codeword using a fixed starting sequence based on a fixed bit pattern. The fixed starting bit sequence is 58 "1" bits.

[0174] After decoding the codeword, the method further includes descrambling the payload using a descrambler. The method further includes descrambling the payload using a scrambling polynomial x 58 +x 39 +1. The descrambler is based on the self-scrambling of data. The descrambler is based on scrambling using a known bit pattern starting with a fixed starting bit sequence. The fixed starting bit sequence is 58 "1" bits. The descrambler is based on scrambling using a known bit pattern having a variable starting bit sequence that includes the decoded SFC field. The variable starting bit sequence is [1 1 1 1 1 1 1 SFC], and wherein, "SFC" represents the bits of the decoded SFC field. The variable starting bit sequence is [1 0 1 0 1 0 1 SFC], and wherein, "SFC" represents the bits of the decoded SFC field.

[0175] The PON is 50G-PON.

[0176] The ONU in the PON includes a receiving device and a processing device coupled to the receiving device. The receiving device is used to receive the encoded DS PHY frame from the OLT. The encoded DS PHY frame includes codewords. The codewords include an SFC field and a payload. The same FEC is used to encode the SFC field and the payload. The processing device is used to: decode the codewords using the FEC to obtain the decoded SFC field and the payload; perform a first verification on the decoded SFC field when the synchronization state machine is in a synchronized state; remain in the synchronized state when the first verification is successful; and exit the synchronized state when the first verification is unsuccessful.

[0177] Unless otherwise noted, the term "about" means a range that includes ±10% of the subsequent number. Although the present disclosure provides several embodiments, it should be understood that the disclosed systems and methods may be implemented in many other specific forms without departing from the spirit or scope of the present disclosure. These current examples should be considered illustrative rather than restrictive and are not intended to be limited to the details given herein. For example, various elements or components may be combined or integrated in another system, or may be omitted or not implemented.

[0178] In addition, technologies, systems, subsystems, and methods described and shown as discrete or separate in various embodiments may be combined or integrated with other systems, components, technologies, or methods without departing from the scope of the present disclosure. Other items shown or described as coupled may be directly coupled or may be indirectly coupled or communicate through some interface, device, or intermediate component in an electrical, mechanical, or other manner. Those skilled in the art can determine other examples of changes, substitutions, and alterations and make changes, substitutions, and alterations without departing from the spirit and scope of the present disclosure.

Claims

1. A method implemented by an optical network unit (ONU) in a passive optical network (PON), the method comprising: Receiving an encoded downstream (DS) physical layer (PHY) frame from an optical line terminal (OLT), the encoded DS PHY frame including codewords, the codewords including a superframe counter (SFC) field and a payload, and the SFC field and the payload being encoded with the same forward error correction (FEC), wherein the FEC uses a low density parity check (LDPC) code, and the length of the LDPC code is 17280 bits; Performing FEC decoding on the codewords to obtain a decoded SFC field and the payload; Performing a first verification on the decoded SFC field when the synchronization state machine is in a sync state; Remaining in the sync state when the first verification is successful or exiting the sync state when the first verification is unsuccessful.

2. The method according to claim 1, wherein The codewords further include a physical synchronization sequence (PSync) field, and wherein the method further comprises: Performing a second verification on the PSync field when in the sync state; Remaining in the sync state when the second verification is successful or exiting the sync state when the second verification is unsuccessful.

3. The method according to claim 2 further includes performing the second verification using a maximum allowable number of error bits ( K ), wherein K ≥ 7。 4. The method according to claim 1, wherein The LDPC code is based on a mother code of size (17664, 14592), where 17664 is the bit length of the codewords and 14592 is the bit length of the payload.

5. The method according to claim 1, further comprising: Initializing in a search state of the synchronization state machine; Entering a pre-sync state of the synchronization state machine from the search state; Entering the sync state from the pre-sync state.

6. The method according to claim 5, further comprising entering the pre-sync state from the search state based on physical synchronization sequence (PSync) pattern matching and SFC verification.

7. The method according to claim 6, wherein, The PSync pattern matching is based on a maximum allowable number of error bits ( K ), and wherein, K ≥ 7.

8. The method according to claim 6, wherein, The SFC verification is based on additional parity bits in a hybrid error correction (HEC) field and Bose–Chaudhuri–Hocquenghem (BCH) (63, 12).

9. The method according to claim 5, further comprising entering the sync state from the pre-sync state based on physical synchronization sequence (PSync) pattern matching and SFC verification.

10. The method according to claim 9, wherein, The PSync pattern matching is based on the maximum allowable number of error bits ( K ), and wherein, K ≥ 7.

11. The method according to claim 9, wherein, The SFC verification is based on two consecutive valid SFC readings.

12. The method according to claim 5, further comprising: Entering the pre-sync state from the search state based only on physical synchronization sequence (PSync) pattern matching; Entering the sync state from the pre-sync state based only on the PSync pattern matching.

13. The method according to claim 12, wherein The PSync pattern matching is based on the maximum allowable number of error bits ( K ), and wherein K ≥ 7.

14. The method according to claim 12, wherein, The PSync pattern matching is based on 64-bit PSync.

15. The method according to claim 14, wherein, The PSync pattern matching is also based on a maximum allowable number of error bits ( K ), and wherein K = 7.

16. The method according to claim 12, wherein, The PSync pattern matching is based on a 128-bit pattern.

17. The method according to claim 16, wherein, The PSync pattern matching is also based on a maximum allowable number of error bits ( K ), and wherein, 18 ≤ K ≤ 28.

18. The method according to claim 16, wherein, The 128-bit pattern is [PSync PSync'], where PSync' is the opposite of PSync, and where PSync is [0xC5E5 1840 FD59 BB49].

19. The method according to claim 5, further comprising: Enter the pre - synchronization state from the search state only based on physical synchronization sequence (PSync) pattern matching; Enter the synchronization state from the pre - synchronization state based on a second verification of the first FEC codeword.

20. The method according to claim 19, further comprising returning from the pre - synchronization state to the search state when the second verification fails.

21. The method according to claim 19, wherein The PSync pattern matching is based on the maximum allowable number of error bits ( K ), and wherein, K ≥ 7.

22. The method according to claim 19, wherein The PSync pattern matching is based on the 64 - bit pattern [0xC5E51840 FD59 BB49].

23. The method according to claim 22, wherein The PSync pattern matching is also based on a maximum allowable number of error bits ( K ), and wherein K = 7.

24. The method according to claim 19, wherein The PSync pattern matching is based on a 128 - bit pattern.

25. The method according to claim 24, wherein The PSync pattern matching is also based on a maximum allowable number of error bits ( K ), and wherein, 18 ≤ K ≤ 28.

26. The method according to claim 24, wherein, The 128 - bit pattern is [PSync PSync'], where PSync' is the opposite of PSync, and where PSync is [0xC5E5 1840 FD59 BB49].

27. The method according to claim 1, further comprising entering the resynchronization state of the synchronization state machine from the synchronization state.

28. The method according to claim 27, further comprising entering the resynchronization state from the synchronization state when the physical synchronization sequence (PSync) pattern matching or the SFC verification fails.

29. The method according to claim 27, further comprising returning from the resynchronization state to the synchronization state when the PSync pattern matching and the SFC verification are successful.

30. The method according to claim 27, further comprising maintaining the resynchronization state for at most ( M – 2) consecutive failures of physical synchronization sequence (PSync) pattern matching and SFC verification.

31. The method according to claim 27, further comprising returning from the resynchronization state to the search state of the synchronization state machine when a physical synchronization sequence (PSync) pattern matches or an SFC verification fails ( M – 1) times.

32. The method according to claim 31, wherein M ≥ 2。 33. The method according to claim 27, further comprising returning from the resynchronization state to the synchronization state when the physical synchronization sequence (PSync) pattern matching and the SFC verification are successful.

34. The method according to claim 1, wherein, The codeword further includes a DS physical synchronization block (PSBd), and wherein the PSBd contains a physical synchronization sequence (PSync) field and the SFC field.

35. The method according to claim 34, wherein, The PSBd is not scrambled.

36. The method according to claim 34, wherein, Within the codeword, only the PSync field is not scrambled.

37. The method according to claim 1, wherein Before decoding the codeword, the method further comprises descrambling the codeword using a descrambler.

38. The method according to claim 37 further comprises using a descrambling polynomial x 58 + x 39 + 1 to descramble the codeword.

39. The method according to claim 37, further comprising descrambling the codeword using a variable starting bit sequence based on the SFC field.

40. The method according to claim 39, wherein, The variable starting bit sequence is [1 1 1 1 1 1 1SFC], and wherein "SFC" represents the bits of the SFC field.

41. The method according to claim 37, further comprising descrambling the codeword using a fixed starting sequence based on a fixed bit pattern.

42. The method according to claim 41, wherein, The fixed starting sequence is 58 "1" bits.

43. The method according to claim 1, wherein, After decoding the codeword, the method further comprises descrambling the payload using a descrambler.

44. The method according to claim 43, further comprising using a scrambling polynomial x 58 + x 39 + 1 to descramble the payload.

45. The method according to claim 43, wherein, The descrambler is based on self - scrambling of data.

46. The method according to claim 43, wherein, The descrambler is based on scrambling using a known bit pattern starting with a fixed starting bit sequence.

47. The method according to claim 46, wherein, The fixed starting bit sequence is 58 "1" bits.

48. The method according to claim 43, wherein, The descrambler is based on scrambling using a known bit pattern with a variable starting bit sequence that includes the decoded SFC field.

49. The method according to claim 48, wherein, The variable start bit sequence is [1 1 1 1 1 1 1SFC], and wherein, "SFC" represents the bits of the decoded SFC field.

50. The method according to claim 48, wherein, The variable start bit sequence is [1 0 1 0 1 0 1SFC], and wherein, "SFC" represents the bits of the decoded SFC field.

51. The method according to claim 1, wherein, The PON is a PON supporting 50 gigabits (50G-PON).

52. An optical network unit (ONU) comprising: A receiver; A processor, coupled to the receiver and configured to execute the method according to any one of claims 1 to 51.

53. A computer program product comprising computer-executable instructions stored in a non-transitory medium, which when executed by a processor cause an optical network unit (ONU) to execute the method according to any one of claims 1 to 51.

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