Display substrate and display device

Abstract

A display substrate and a display device. A subpixel in the display substrate includes a light-emitting element and a pixel circuit. The light-emitting element includes a first electrode, a light-emitting layer, and a second electrode. The pixel circuit includes a first connection portion, a driving transistor, and a threshold compensation transistor. The first electrode of the threshold compensation transistor is electrically connected to the first electrode of the driving transistor, and the second electrode of the threshold compensation transistor is electrically connected to the gate of the driving transistor via the first connection portion. The subpixel includes a first-color subpixel pair, and the first-color subpixel pair includes a first pixel block and a second pixel block. The ratio of the overlapping area of ​​the orthographic projection of the second electrode of the first pixel block on the substrate and the orthographic projection of the first connection portion on the substrate to the overlapping area of ​​the orthographic projection of the second electrode of the second pixel block on the substrate and the orthographic projection of the first connection portion on the substrate is 0.8 to 1.2, thereby reducing the load difference of the gate nodes of the driving transistors in the two first-color subpixels.

Description

[0001] This application claims priority to PCT Application No. PCT / CN2019 / 098708, filed on July 31, 2019, and priority to PCT Application No. PCT / CN2019 / 098731, filed on July 31, 2019, and the disclosures of the above PCT applications are hereby incorporated by reference in their entirety as a part of this application for all purposes. Technical Field

[0002] At least one embodiment of the present disclosure relates to a display substrate and a display device. Background Art

[0003] With the development of organic light-emitting diode (OLED) display technology, such as active-matrix organic light-emitting diode (AMOLED) display technology, people's requirements for display quality are becoming increasingly higher. The design of pixel circuits in display products is crucial to the display characteristics of AMOLED products. Currently, how to improve the display characteristics of OLED devices has become a key research and development focus of OLED devices. Summary of the Invention

[0004] At least one embodiment of the present disclosure provides a display substrate and a display device.

[0005] At least one embodiment of the present disclosure provides a display substrate, comprising: a base substrate; a plurality of sub-pixels located on the base substrate, each of the sub-pixels comprising a light-emitting element and a pixel circuit, the light-emitting element comprising a first electrode, a light-emitting layer and a second electrode stacked in sequence, the second electrode being located between the light-emitting layer and the base substrate, the pixel circuit comprising a first connecting portion, a driving transistor and a threshold compensation transistor located between the second electrode and the base substrate, the first connecting portion extending along a first direction, the first electrode of the threshold compensation transistor being electrically connected to the first electrode of the driving transistor, and the second electrode of the threshold compensation transistor being electrically connected to the gate of the driving transistor through the first connecting portion. The multiple sub-pixels include at least one first color sub-pixel pair and multiple other color sub-pixels, each of the first color sub-pixel pairs includes a first pixel block and a second pixel block arranged along a second direction, the minimum distance between the first pixel block and the second pixel block in each of the first color sub-pixel pairs is not greater than the minimum distance between two same color sub-pixels in the multiple other color sub-pixels, and the angle between the second direction and the first direction is in the range of 80° to 100°; the first pixel block includes a first effective light-emitting area, the second pixel block includes a second effective light-emitting area, and in the first pixel block, the minimum distance between the orthographic projection of the first connecting portion on a straight line extending along the second direction and the orthographic projection of the first effective light-emitting area on the straight line is a first distance, or, The orthographic projection of the first connecting portion on the straight line extending along the second direction overlaps with the orthographic projection of the first effective light-emitting area on the straight line; in the second pixel block, the minimum distance between the orthographic projection of the first connecting portion on the straight line and the orthographic projection of the second effective light-emitting area on the straight line is the second distance, and the first distance is smaller than the second distance; in the first pixel block, the overlapping area of ​​the orthographic projection of the second electrode on the substrate and the orthographic projection of the first connecting portion on the substrate is the first overlapping area, and in the second pixel block, the overlapping area of ​​the orthographic projection of the second electrode on the substrate and the orthographic projection of the first connecting portion on the substrate is the second overlapping area, and the ratio of the first overlapping area to the second overlapping area is 0.8 to 1.2.

[0006] For example, in an embodiment of the present disclosure, in the first pixel block, the second electrode covers 60-90% of the area of ​​the first connection portion; in the second pixel block, the second electrode covers 60-90% of the area of ​​the first connection portion.

[0007] For example, in an embodiment of the present disclosure, the display substrate further includes: a data line disposed in the same layer as the first connecting portion and extending along the first direction. The plurality of sub-pixels further include at least one second color sub-pixel, and the effective light-emitting area of ​​each second color sub-pixel is shaped like a long strip extending along the second direction.

[0008] For example, in an embodiment of the present disclosure, in the first pixel block, the gate of the threshold compensation transistor is located on a side of the first connection portion away from the first effective light-emitting area; in the second pixel block, the gate of the threshold compensation transistor is located on a side of the first connection portion close to the second effective light-emitting area.

[0009] For example, in an embodiment of the present disclosure, the second electrode of each of the sub-pixels includes a main electrode and a connecting electrode. In the first pixel block, the shape of the main electrode is substantially the same as the shape of the first effective light-emitting area, the orthographic projection of the first effective light-emitting area on the substrate is located within the orthographic projection of the main electrode on the substrate, and the first effective light-emitting area overlaps with the first connecting portion; in the second pixel block, the shape of the main electrode is substantially the same as the shape of the second effective light-emitting area, the orthographic projection of the second effective light-emitting area on the substrate is located within the orthographic projection of the main electrode on the substrate, and the second effective light-emitting area does not overlap with the first connecting portion.

[0010] For example, in an embodiment of the present disclosure, in the first color sub-pixel pair, the second electrode also includes an auxiliary electrode connecting the main electrode and the connecting electrode, and the connecting electrode extends along the first direction. In the first pixel block, the auxiliary electrode is located on the side of the main electrode away from the second effective light-emitting area, and in the second pixel block, the auxiliary electrode is located on the side of the main electrode away from the first effective light-emitting area.

[0011] For example, in an embodiment of the present disclosure, in the second pixel block, a straight line where the first edge of the edge of the portion of the connecting electrode close to the auxiliary electrode extending along the first direction and away from the second effective light-emitting area is located overlaps with the first connecting portion, and the second edge of the auxiliary electrode away from the second effective light-emitting area is located on the side of the first connecting portion away from the second effective light-emitting area so that the auxiliary electrode covers the first connecting portion.

[0012] For example, in an embodiment of the present disclosure, the second edge extends along the first direction, and the straight line where the second edge is located is located on a side of the straight line where the first edge is located away from the second effective light-emitting area.

[0013] For example, in an embodiment of the present disclosure, in the first pixel block, the straight line where the third edge of the edge of the portion of the connecting electrode close to the auxiliary electrode extending along the first direction away from the first effective light-emitting area is located is located on the side of the first connecting portion away from the first effective light-emitting area.

[0014] For example, in an embodiment of the present disclosure, in the second pixel block, the edge of the portion of the auxiliary electrode close to the connecting electrode away from the second effective light-emitting area is not on the same straight line as the first edge of the connecting electrode; in the first pixel block, the fourth edge of the portion of the auxiliary electrode close to the connecting electrode away from the first effective light-emitting area is on the same straight line as the third edge of the connecting electrode.

[0015] For example, in an embodiment of the present disclosure, the pixel circuit of each of the sub-pixels also includes a first light-emitting control transistor and a second connection portion arranged on the same layer as the first connection portion, the first electrode of the first light-emitting control transistor is electrically connected to the first electrode of the driving transistor, and the second electrode of the first light-emitting control transistor is electrically connected to the connection electrode through the second connection portion, and in the first pixel block, the second connection portion is farther away from the first effective light-emitting area than the first connection portion in the second direction; in the second pixel block, the second connection portion is closer to the second effective light-emitting area than the first connection portion in the second direction.

[0016] For example, in an embodiment of the present disclosure, the display substrate further comprises: a planar layer located between the film layer where the second connecting portion is located and the film layer where the connecting electrode is located. The planar layer includes a plurality of via holes extending therethrough, and the connecting electrode in each of the sub-pixels is electrically connected to the second connecting portion via the via holes, wherein the via holes corresponding to the first pixel block are farther from the first effective light-emitting area than the first connecting portion of the first pixel block in the second direction; and the via holes corresponding to the second pixel block are closer to the second effective light-emitting area than the first connecting portion of the second pixel block in the second direction.

[0017] For example, in an embodiment of the present disclosure, in the pixel circuit of each of the sub-pixels, the threshold compensation transistor includes a first gate and a second gate, and in the first pixel block, the first gate is located on a side of the second gate close to the first effective light-emitting area, the straight line where the third edge of the connecting electrode is located overlaps with the first gate, and the portion of the auxiliary electrode away from the connecting electrode in the second direction away from the edge of the first effective light-emitting area is located on a side of the first gate away from the first effective light-emitting area so that the auxiliary electrode covers at least part of the first gate.

[0018] For example, in an embodiment of the present disclosure, in the first pixel block, the auxiliary electrode includes a first portion and a second portion connected to each other, the first portion is connected to the connecting electrode, the second portion covers at least a portion of the first gate, the edge of the first portion extending along the first direction and the third edge are located on the same straight line, and the edge of the second portion extending along the first direction is farther away from the first effective light-emitting area in the second direction than the edge of the first portion extending along the first direction.

[0019] For example, in an embodiment of the present disclosure, the second portion is located on a side of the second gate away from the connection electrode in the first direction.

[0020] For example, in an embodiment of the present disclosure, in the first pixel block, the auxiliary electrode covers a portion of the active layer between orthographic projections of the first gate and the second gate on the active layer.

[0021] For example, in an embodiment of the present disclosure, the multiple sub-pixels also include at least one third-color sub-pixel, and the shape of the effective light-emitting area of ​​the third-color sub-pixel is a long strip extending along the second direction. The second electrode of the third-color sub-pixel also includes an auxiliary electrode located on the side of the main electrode away from the connecting electrode and connected to the main electrode. In the third-color sub-pixel, the threshold compensation transistor includes a first gate and a second gate, and the second gate is located on the side of the first gate close to the effective light-emitting area of ​​the third-color sub-pixel in the first direction, and the auxiliary electrode covers a portion of the active layer between the positive projections of the second gate and the first gate on the active layer.

[0022] For example, in an embodiment of the present disclosure, the first color sub-pixel pair is a green sub-pixel pair, the second color sub-pixel is a red sub-pixel, and the third color sub-pixel is a blue sub-pixel.

[0023] For example, in an embodiment of the present disclosure, the shapes of the first effective light-emitting area and the second effective light-emitting area include pentagons, circles or water drop shapes, and the shapes of the effective light-emitting areas of the second color sub-pixel and the third color sub-pixel include hexagons or ellipses.

[0024] For example, in an embodiment of the present disclosure, the display substrate also includes: a power signal line extending along the first direction, the power signal line and the data line being in the same layer and alternately arranged; a scanning signal line extending along the second direction, and being located on the side of the film layer where the data line is located facing the base substrate; a reset power signal line extending along the second direction, and being located between the film layer where the scanning signal line is located and the film layer where the data line is located; a reset control signal line extending along the second direction, and being arranged in the same layer as the scanning signal line; and a light-emitting control signal line extending along the second direction, and being arranged in the same layer as the scanning signal line. The pixel circuit of each sub-pixel further includes a data write transistor, a storage capacitor, a second light emitting control transistor, a first reset transistor and a second reset transistor, wherein the first electrode of the data write transistor is electrically connected to the second electrode of the drive transistor, the second electrode of the data write transistor is electrically connected to the data line, and the gate of the data write transistor is electrically connected to the scan signal line; the first electrode of the storage capacitor is electrically connected to the power signal line, and the second electrode of the storage capacitor is electrically connected to the gate of the drive transistor; the gate of the threshold compensation transistor is electrically connected to the scan signal line to receive a compensation control signal; the first electrode of the first reset transistor is electrically connected to the reset power signal line, and the first reset The second electrode of the transistor is electrically connected to the gate of the driving transistor, and the gate of the first reset transistor is electrically connected to the reset control signal line; the first electrode of the second reset transistor is electrically connected to the reset power signal line, the second electrode of the second reset transistor is electrically connected to the second electrode of the light-emitting element, and the gate of the second reset transistor is electrically connected to the reset control signal line; the first electrode of the second light-emitting control transistor is electrically connected to the power signal line, the second electrode of the second light-emitting control transistor is electrically connected to the second electrode of the driving transistor, and the gate of the second light-emitting control transistor is electrically connected to the light-emitting control signal line; the gate of the first light-emitting control transistor is electrically connected to the light-emitting control signal line.

[0025] For example, in an embodiment of the present disclosure, the data line includes a first data line, the power signal line includes a first power signal line, and along a direction perpendicular to the base substrate, the second electrode of each second color sub-pixel overlaps with the first data line, the first power signal line and the second connection portion, and in the portion where the first data line, the first power signal line and the second connection portion overlap with the second electrode, the first power signal line and the first data line are located on both sides of the second connection portion, and the second connection portion includes a first sub-connection portion connected to each other and a first pad located on a side of the first sub-connection portion close to the first power signal line, the first sub-connection portion and the first pad both overlap with the second electrode, along the first direction, the size of the first sub-connection portion is larger than the size of the first pad, and the ratio of the minimum distance between the edges of the first sub-connection portion and the first data line close to each other to the minimum distance between the edges of the first pad and the first power signal line close to each other is 0.8 to 1.2.

[0026] For example, in an embodiment of the present disclosure, a straight line extending along the first direction and passing through the midpoint of a line connecting two opposite endpoints of the effective light-emitting area of ​​the second color sub-pixel in the second direction overlaps the second connecting portion.

[0027] For example, in an embodiment of the present disclosure, the data line also includes a second data line, the first data line and the second data line are alternately arranged, and the power signal line also includes a second power signal line, the second power signal line and the first power signal line are alternately arranged, and along the direction perpendicular to the substrate, the second electrode of each second-color sub-pixel overlaps with the first data line, the first power signal line, the second connection portion, the second data line and the second power signal line, and in the overlapping portion, the second power signal line is located on the side of the first data line away from the second connection portion, and the second data line is located on the side of the first power signal line away from the second connection portion.

[0028] For example, in an embodiment of the present disclosure, the shape of the first sub-connection portion is a rectangle extending along the first direction, and a straight line passing through the center of the effective light-emitting area of ​​the second color sub-pixel and extending along the first direction is located on the side of the straight line passing through the center of the first sub-connection portion and extending along the first direction close to the first pad.

[0029] For example, in an embodiment of the present disclosure, the pixel circuit also includes a third connection portion arranged in the same layer as the data line, the third connection portion extends along the first direction, the first electrode of the first reset transistor is electrically connected to the reset power signal line through the third connection portion, and along the direction perpendicular to the base substrate, the effective light-emitting area of ​​the second color sub-pixel overlaps with the third connection portion, and a straight line passing through the center of the effective light-emitting area of ​​the second color sub-pixel and extending along the first direction overlaps with the third connection portion, the second connection portion is located on one side of the straight line passing through the center of the effective light-emitting area of ​​the second color sub-pixel and extending along the second direction, and at least part of the third connection portion is located on the other side of the straight line.

[0030] For example, in an embodiment of the present disclosure, the display substrate further comprises an interlayer insulating layer located between the film layer where the data line is located and the base substrate. In the third color sub-pixel, the connecting electrode is connected to the second connecting portion via a first via hole penetrating the planar layer, and the second connecting portion is electrically connected to the pixel circuit via a first connecting hole penetrating the interlayer insulating layer. In a direction perpendicular to the base substrate, neither the first via hole nor the first connecting hole overlaps with the main electrode, and the orthographic projections of the first via hole and the first connecting hole on a first straight line extending along the first direction overlap.

[0031] For example, in an embodiment of the present disclosure, in the second color sub-pixel, the connecting electrode is connected to the second connecting portion through a second via hole penetrating the flat layer, the first via hole is located on a side of the effective light-emitting area of ​​the third color sub-pixel close to the effective light-emitting area of ​​the second color sub-pixel in the first direction, the second via hole is located on a side of the effective light-emitting area of ​​the second color sub-pixel close to the effective light-emitting area of ​​the third color sub-pixel in the first direction, and the first connecting line connecting the first via hole and the second via hole is not parallel to the second direction, and the second electrode of the second color sub-pixel and the second electrode of the third color sub-pixel do not overlap in the second direction.

[0032] For example, in an embodiment of the present disclosure, in the second color sub-pixel, the second connection portion is electrically connected to the pixel circuit through a second connection hole passing through the interlayer insulating layer, and the second line connecting the first connection hole and the second connection hole is parallel to the second direction.

[0033] For example, in an embodiment of the present disclosure, the effective light-emitting area of ​​the second color sub-pixel includes a first long side and a second long side extending along the second direction, the second long side is located on a side of the first long side away from the second via hole, and along a direction perpendicular to the base substrate, the extension line of the first long side overlaps with the first via hole; the effective light-emitting area of ​​the third color sub-pixel includes a third long side and a fourth long side extending along the second direction, the fourth long side is located on a side of the third long side away from the first via hole, and along the third direction, the extension line of the third long side overlaps with the second via hole.

[0034] For example, in an embodiment of the present disclosure, in the first sub-pixel block, the second connection portion is electrically connected to the pixel circuit through a third connection hole passing through the interlayer insulating layer; in the second sub-pixel block, the second connection portion is electrically connected to the pixel circuit through a fourth connection hole passing through the interlayer insulating layer, and the line connecting the third connection hole and the fourth connection hole basically coincides with the second line.

[0035] At least one embodiment of the present disclosure provides a display device including the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0037] Figure 1 A schematic diagram of a partial planar structure of a display substrate provided according to an embodiment of the present disclosure;

[0038] Figure 2 for Figure 1 An equivalent diagram of a pixel circuit of each sub-pixel shown;

[0039] Figure 3A A schematic diagram of a partial planar structure of a stacked structure of an active semiconductor layer and a first conductive layer of a portion of a pixel circuit provided according to an embodiment of the present disclosure;

[0040] Figure 3B A schematic diagram of a partial planar structure of a stacked structure of an active semiconductor layer, a first conductive layer, and a second conductive layer provided according to an embodiment of the present disclosure;

[0041] Figure 3C A schematic diagram of the positions of via holes in each insulating layer provided according to an embodiment of the present disclosure;

[0042] Figure 3D A schematic diagram of a partial planar structure of a source / drain metal layer provided according to an embodiment of the present disclosure;

[0043] Figure 3E A schematic diagram of a stacked structure of an active semiconductor layer, a first conductive layer, a second conductive layer, and a source-drain metal layer provided according to an embodiment of the present disclosure;

[0044] Figure 4 A schematic diagram of the second electrode and effective light-emitting area of ​​the light-emitting element of each sub-pixel provided according to an embodiment of the present disclosure;

[0045] Figure 5A A schematic diagram of the stacked structure of the light-emitting element and source / drain metal layer of each sub-pixel provided according to an embodiment of the present disclosure;

[0046] Figure 5B A schematic diagram of a stacked structure of a light-emitting element, an active semiconductor layer, a first conductive layer, and a source / drain metal layer of each sub-pixel provided according to an embodiment of the present disclosure;

[0047] Figure 5C A schematic diagram of a stacked structure of a light-emitting element, an active semiconductor layer, a first conductive layer, a second conductive layer, and a source / drain metal layer of each sub-pixel provided according to an embodiment of the present disclosure;

[0048] Figure 5D For the Figure 5C A cross-sectional view taken along line A1A2 shown;

[0049] Figure 5E For the Figure 5C A cross-sectional view taken along line A3A4 shown;

[0050] Figure 5F For the Figure 5C A cross-sectional view taken along line A5A6 shown;

[0051] Figure 5G For the Figure 5C A cross-sectional view taken along line A7A8 shown;

[0052] Figure 5H In one example of the embodiment of the present disclosure, Figure 5C A cross-sectional view taken along line A9A10 is shown;

[0053] Figure 5I In another example of the embodiment of the present disclosure, Figure 5C A cross-sectional view taken along line A9A10 is shown;

[0054] Figure 5J For the Figure 5C A cross-sectional view taken along line A11A12 shown;

[0055] Figure 6 A schematic diagram of a partial cross-sectional structure of a display substrate;

[0056] Figure 7 is a schematic diagram of a partial cross-sectional structure of another display substrate; and

[0057] Figure 8 A schematic diagram of a pixel arrangement structure in a display substrate. DETAILED DESCRIPTION

[0058] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0059] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are simply used to distinguish different components. The words "include" or "comprising" and similar terms mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0060] The features such as "parallel", "perpendicular" and "same" used in the embodiments of the present disclosure include the features such as "parallel", "perpendicular" and "same" in the strict sense, as well as the cases where "approximately parallel", "approximately perpendicular" and "approximately the same" contain certain errors, taking into account the errors associated with the measurement and the measurement of specific quantities (that is, the limitations of the measurement system), and are expressed as being within the acceptable deviation range for a specific value determined by a person of ordinary skill in the art. The "center" in the embodiments of the present disclosure can include a position strictly at the geometric center and a position approximately at the center of a small area around the geometric center. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of the value.

[0061] During the study, the inventors of this application discovered that in the GGRB pixel arrangement structure, each pixel includes a red sub-pixel, a blue sub-pixel and a green sub-pixel pair, and each sub-pixel includes a light-emitting element and a pixel circuit that drives the light-emitting element to emit light. When there is a difference in the gate node load of the driving transistor included in the pixel circuit of the two green sub-pixels included in the green sub-pixel pair, the brightness of the two green sub-pixels included in the green sub-pixel pair will be different when they emit light.

[0062] Embodiments of the present disclosure provide a display substrate and a display device. The display substrate includes a base substrate and a plurality of sub-pixels located on the base substrate. Each sub-pixel includes a light-emitting element and a pixel circuit. The light-emitting element includes a first electrode, a light-emitting layer, and a second electrode stacked in sequence, the second electrode being located between the light-emitting layer and the base substrate. The pixel circuit includes a first connecting portion, a driving transistor, and a threshold compensation transistor located between the second electrode and the base substrate. The first connecting portion extends along a first direction. The first electrode of the threshold compensation transistor is electrically connected to the first electrode of the driving transistor. The second electrode of the threshold compensation transistor is electrically connected to the gate of the driving transistor via the first connecting portion. The multiple sub-pixels include at least one first color sub-pixel pair and a plurality of other color sub-pixels, each first color sub-pixel pair includes a first pixel block and a second pixel block arranged along a second direction, a minimum distance between the first pixel block and the second pixel block in each first color sub-pixel pair is not greater than a minimum distance between two same color sub-pixels in the plurality of other color sub-pixels, and an angle between the second direction and the first direction is in a range of 80° to 100°; the first pixel block includes a first effective light-emitting area, the second pixel block includes a second effective light-emitting area, and in the first pixel block, a minimum distance between an orthographic projection of the first connecting portion on a straight line extending along the second direction and an orthographic projection of the first effective light-emitting area on the straight line is a distance, or the orthographic projection of the first connection portion on a straight line extending along the second direction overlaps with the orthographic projection of the first effective light-emitting area on the straight line; in the second pixel block, the minimum distance between the orthographic projection of the first connection portion on the straight line and the orthographic projection of the second effective light-emitting area on the straight line is the second distance, and the first distance is less than the second distance; in the first pixel block, the overlapping area of ​​the orthographic projection of the second electrode on the substrate and the orthographic projection of the first connection portion on the substrate is the first overlapping area, and in the second pixel block, the overlapping area of ​​the orthographic projection of the second electrode on the substrate and the orthographic projection of the first connection portion on the substrate is the second overlapping area, and the ratio of the first overlapping area to the second overlapping area is 0.8 to 1.2. In the embodiment of the present disclosure, in the two first color sub-pixels included in the first color sub-pixel pair, the ratio of the overlapping area between the second electrodes of the two light-emitting elements and the corresponding two first connection portions is 0.8 to 1.2, which can reduce the load difference of the gate nodes of the driving transistors in the two first color sub-pixels, thereby reducing the brightness difference of the two first color sub-pixels to improve the display characteristics of the display substrate.

[0063] The display substrate and the display device provided by the embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0064] Figure 1 FIG. 1 is a schematic diagram of a partial planar structure of a display substrate provided according to an embodiment of the present disclosure. Figure 1 As shown, the display substrate includes a base substrate 1 and a plurality of sub-pixels 10 located on the base substrate 1. Figure 1As shown, a plurality of sub-pixels 10 are arranged into a plurality of repeating units 20. Each repeating unit 20 includes a second color sub-pixel 200, a first color sub-pixel pair 100, and a third color sub-pixel 300 arranged along a first direction (the X direction shown in the figure), and the two first color sub-pixels 110 and 120 included in the first color sub-pixel pair 100 are arranged along a second direction (the Y direction shown in the figure, which is different from the first direction). A plurality of repeating units 20 are arranged along the first direction to form a plurality of repeating unit groups, a plurality of repeating unit groups are arranged along the second direction, and adjacent repeating unit groups in the plurality of repeating unit groups are staggered from each other along the first direction, that is, adjacent repeating unit groups have a certain offset along the first direction. Therefore, the sub-pixels of the same color in adjacent repeating unit groups are not aligned in the second direction. The pixels in the odd-numbered column repeating unit groups are arranged in the same manner, and the pixels in the even-numbered column repeating unit groups are arranged in the same manner.

[0065] For example, the offset of adjacent repeating unit groups in the first direction is approximately half the size of the repeating unit 20 in the first direction. For example, the size of the repeating unit 20 in the first direction is the pitch of the repeating unit 20 in the first direction. The pitch here refers to the distance between the centers of the effective light-emitting areas of two second-color sub-pixels 200 in two adjacent repeating units 20 along the first direction, where the center of the effective light-emitting area refers to the geometric center of the planar shape of the effective light-emitting area.

[0066] For example, the second direction and the first direction are two directions in the same plane, and the angle between the two directions is in the range of 80° to 100°. For example, the plane is the plane where the pixels are arranged. The repeating unit here only refers to the repetition of sub-pixels, and other structures can be different or the same. In addition, the above repetition refers to the approximate position, shape, and size. In some cases, for the needs of wiring or opening, the shape is slightly different, such as openings in different positions.

[0067] For example, Figure 1 As shown, the shape of the effective light-emitting area 201 of the second color sub-pixel 200 is a long strip extending along the second direction. For example, the shape of the effective light-emitting area 301 of the third color sub-pixel 300 is a long strip extending along the second direction. For example, the display substrate also includes a data line 420 located on the base substrate 10, and the data line 420 extends along the first direction. Therefore, the angle between the extension direction of the effective light-emitting area of ​​the second color sub-pixel and the extension direction of the data line is in the range of 80° to 100°. When the opening extension direction of the fine metal mask (FMM) used for evaporating each color sub-pixel is an angle between the extension direction of the data line and the extension direction is in the range of 80° to 100°, for example, 90°, the extension direction of the effective light-emitting area of ​​the second color sub-pixel is the same as the extension direction of the FMM opening.

[0068] For example, Figure 1 As shown, the shapes of the effective light-emitting areas 201 and 301 of the second color sub-pixel 200 and the third color sub-pixel 300 include a hexagon or an ellipse. In addition, although the shapes of the second color sub-pixel and the third color sub-pixel in the figure include a strict angle formed by two line segments, in some embodiments, the shapes of the effective light-emitting areas of the second color sub-pixel and the third color sub-pixel can both be rounded shapes, such as ellipses. That is, on the basis of the above-mentioned hexagonal shape, the corners of the effective light-emitting areas of the second color sub-pixel and the third color sub-pixel are rounded. For example, when forming an opening of the pixel defining layer, the corners of the opening will form a rounded shape, so that the shape of the effective light-emitting area formed is a rounded shape. The hexagon in the embodiment of the present disclosure may include a standard hexagon or an approximate hexagon, for example, a roughly hexagonal shape with a hexagonal outline, such as a rounded hexagon.

[0069] For example, in the embodiment of the present disclosure, the first color sub-pixel pair 100 is a green sub-pixel pair, the second color sub-pixel 200 is a red sub-pixel, and the third color sub-pixel 300 is a blue sub-pixel. However, this is not limiting, and the names of the color sub-pixels can be interchanged. In the embodiment of the present disclosure, a sub-pixel pair including two sub-pixels of the same color is a green sub-pixel pair; along the extension direction of the data line, the width of the effective light-emitting area of ​​the red sub-pixel is smaller than the width of the effective light-emitting area of ​​the blue sub-pixel; and the length of the effective light-emitting area of ​​the red sub-pixel is greater than the length of the effective light-emitting area of ​​the blue sub-pixel.

[0070] For example, Figure 2 for Figure 1 The equivalent diagram of the pixel circuit of each sub-pixel is shown in FIG. Figure 2 As shown, each sub-pixel 10 includes a light-emitting element 11 and a pixel circuit 12 for driving the light-emitting element 11 to emit light. The light-emitting element 11 includes a first electrode, a light-emitting layer, and a second electrode stacked in sequence. The second electrode is located between the light-emitting layer and the substrate. For example, Figure 5E The light-emitting element schematically includes a first electrode 310, a light-emitting layer 330, and a second electrode 320. The second electrode 320 is located between the light-emitting layer 330 and the base substrate 1. For example, the display substrate further includes a reset power signal line, a scan signal line, a power signal line, a reset control signal line, and a light-emitting control signal line located on the base substrate 10. For example, in the embodiments of the present disclosure, the names of the first electrode and the second electrode can be interchangeable.

[0071] For example, Figure 2As shown, each pixel circuit 12 includes a data writing transistor T4, a driving transistor T3, a threshold compensation transistor T2, and a first reset control transistor T7. The first electrode of the threshold compensation transistor T2 is connected to the first electrode of the driving transistor T3, and the second electrode of the threshold compensation transistor T2 is connected to the gate of the driving transistor T3; the first electrode of the first reset control transistor T7 is connected to the reset power signal line to receive the reset signal Vinit, and the second electrode of the first reset control transistor T7 is connected to the light emitting unit; the first electrode of the data writing transistor T4 is connected to the second electrode of the driving transistor T3. For example, Figure 2 As shown, the pixel circuit of each sub-pixel also includes a storage capacitor C, a first light-emitting control transistor T6, a second light-emitting control transistor T5, and a second reset transistor T1. The gate of the data writing transistor T4 is electrically connected to the scan signal line to receive the scan signal Gate; the first electrode of the storage capacitor C is electrically connected to the power signal line, and the second electrode of the storage capacitor C is electrically connected to the gate of the driving transistor T3; the gate of the threshold compensation transistor T2 is electrically connected to the scan signal line to receive the compensation control signal; the gate of the first reset transistor T7 is electrically connected to the reset control signal line to receive the reset control signal Reset(N+1); the first electrode of the second reset transistor T1 is electrically connected to the reset power signal line to receive the reset signal Vinit, and the second electrode of the second reset transistor T1 is electrically connected to the gate of the driving transistor T3. The gate of the second reset transistor T1 is electrically connected to the reset control signal line to receive the reset control signal Reset(N); the gate of the first light-emitting control transistor T6 is electrically connected to the light-emitting control signal line to receive the light-emitting control signal EM; the first electrode of the second light-emitting control transistor T5 is electrically connected to the power signal line to receive the first power signal VDD, the second electrode of the second light-emitting control transistor T5 is electrically connected to the second electrode of the driving transistor T3, the gate of the second light-emitting control transistor T5 is electrically connected to the light-emitting control signal line to receive the light-emitting control signal EM, and the first electrode of the light-emitting element 11 is connected to the voltage terminal VSS. The power signal line refers to a signal line that outputs the voltage signal VDD and can be connected to a voltage source to output a constant voltage signal, such as a positive voltage signal.

[0072] For example, the scanning signal and the compensation control signal can be the same, that is, the gate of the data writing transistor T3 and the gate of the threshold compensation transistor T2 can be electrically connected to the same signal line to receive the same signal, thereby reducing the number of signal lines. For example, the gate of the data writing transistor T3 and the gate of the threshold compensation transistor T2 can also be electrically connected to different signal lines, that is, the gate of the data writing transistor T3 is electrically connected to a first scanning signal line, and the gate of the threshold compensation transistor T2 is electrically connected to a second scanning signal line. The signals transmitted by the first scanning signal line and the second scanning signal line can be the same or different, thereby allowing the gate of the data writing transistor T3 and the threshold compensation transistor T2 to be controlled separately, thereby increasing the flexibility of controlling the pixel circuit.

[0073] For example, the light control signals input to the first light control transistor T6 and the second light control transistor T5 can be the same, that is, the gates of the first light control transistor T6 and the second light control transistor T5 can be electrically connected to the same signal line to receive the same signal, thereby reducing the number of signal lines. For example, the gates of the first light control transistor T6 and the second light control transistor T5 can also be electrically connected to different light control signal lines, respectively, and the signals transmitted by the different light control signal lines can be the same or different.

[0074] For example, the reset control signal input to the first reset transistor T7 and the second reset transistor T1 can be the same, that is, the gate of the first reset transistor T7 and the gate of the second reset transistor T1 can be electrically connected to the same signal line to receive the same signal, thereby reducing the number of signal lines. For example, the gate of the first reset transistor T7 and the gate of the second reset transistor T1 can also be electrically connected to different reset control signal lines, respectively. In this case, the signals on the different reset control signal lines can be the same or different.

[0075] For example, Figure 2 As shown, when the display substrate is working, in the first stage of picture display, the second reset transistor T1 is turned on to initialize the voltage of the N1 node; in the second stage of picture display, the data is stored in the N1 node through the data writing transistor T4, the driving transistor T3 and the threshold compensation transistor T2; in the third light-emitting stage, the second light-emitting control transistor T5, the driving transistor T3 and the first light-emitting control transistor T6 are all turned on, and the light-emitting element is forward-conducted to emit light.

[0076] It should be noted that, in the embodiment of the present disclosure, the pixel circuit of the sub-pixel can be Figure 2In addition to the 7T1C structure (i.e., seven transistors and one capacitor) shown, structures including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, are not limited in the present disclosure. It is sufficient to connect the data writing transistors T4 of the two pixel circuits and connect the N4 nodes of the two pixel circuits to jointly drive the same light-emitting unit to emit light.

[0077] Figure 3A FIG. 1 is a schematic diagram of a partial planar structure of an active semiconductor layer and a first conductive layer stacked structure of a portion of a pixel circuit according to an embodiment of the present disclosure. Figure 3A As shown, the active semiconductor layer 3100 can be formed by patterning a semiconductor material. The active semiconductor layer 3100 can be used to form the active layer of the second reset transistor T1, threshold compensation transistor T2, drive transistor T3, data write transistor T4, second emission control transistor T5, first emission control transistor T6, and first reset control transistor T7. The active semiconductor layer 3100 includes an active layer pattern (channel region) and a doping region pattern (source and drain doping region) for each transistor in each sub-pixel. The active layer pattern and doping region pattern of each transistor in the same pixel circuit are integrated.

[0078] It should be noted that the active layer may include an integrally formed low-temperature polysilicon layer, and the source and drain regions may be made conductive through doping, etc., to achieve electrical connection between the various structures. In other words, the active semiconductor layer of each transistor in each sub-pixel is a monolithic pattern formed of p-silicon, and each transistor in the same pixel circuit includes a doped region pattern (i.e., source and drain regions) and an active layer pattern, with the active layers of different transistors separated by doped structures.

[0079] For example, the active semiconductor layer 3100 may be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the source region and the drain region may be regions doped with n-type impurities or p-type impurities.

[0080] For example, the display substrate includes a gate insulating layer located on a side of the active semiconductor layer away from the base substrate, for insulating the active semiconductor layer 3100 from a subsequently formed first conductive layer 3200 (i.e., a gate metal layer). For example, the display substrate includes a first conductive layer 3200, which is disposed on the gate insulating layer and is thereby insulated from the active semiconductor layer 3100. The first conductive layer 3200 may include a second electrode CC2 of a capacitor C, a plurality of scan signal lines 430 extending along a second direction (the Y direction in the figure), a plurality of reset control signal lines 440, a plurality of light emission control signal lines 450, and gates of a second reset transistor T1, a threshold compensation transistor T2, a drive transistor T3, a data write transistor T4, a second light emission control transistor T5, a first light emission control transistor T6, and a first reset control transistor T7.

[0081] For example, Figure 3A As shown, the gate of the data write transistor T3 may be the portion where the scan signal line 430 overlaps with the active semiconductor layer 3100; the gate of the first light emission control transistor T6 may be the first portion where the light emission control signal line 450 overlaps with the active semiconductor layer 3100, and the gate of the second light emission control transistor T5 may be the second portion where the light emission control signal line 450 overlaps with the active semiconductor layer 3100. The gate of the second reset transistor T1 may be the first portion where the reset control signal line 440 overlaps with the active semiconductor layer 3100, and the gate of the first reset control transistor T7 may be the second portion where the reset control signal line 440 overlaps with the active semiconductor layer 3100. The threshold compensation transistor T2 may be a thin film transistor with a dual-gate structure, the first gate T2-g1 of the threshold compensation transistor T2 may be the portion where the protruding structure P protruding from the scan signal line 430 overlaps with the active semiconductor layer 3100, and the second gate T2-g2 of the threshold compensation transistor T2 may be the portion where the scan signal line 430 overlaps with the active semiconductor layer 3100. As shown Figure 3A As shown, the gate of the driving transistor T1 may be the second electrode CC2 of the capacitor C.

[0082] It should be noted that Figure 3A The dotted rectangular boxes in the figure show the overlapping parts of the active semiconductor layer 3100 and the first conductive layer 3200, that is, the channel region. As the channel region of each transistor, the active semiconductor layer on both sides of each channel region is conductively connected through processes such as ion doping to serve as the first and second electrodes of each transistor. The source and drain of the transistor can be symmetrical in structure, so the source and drain can be indistinguishable in physical structure. In the embodiments of the present disclosure, in order to distinguish the transistors, except for the gate as the control electrode, one of the electrodes is directly described as the first electrode and the other electrode is the second electrode, so the first and second electrodes of all or part of the transistors in the embodiments of the present disclosure can be interchangeable as needed.

[0083] For example, Figure 3A As shown, the scanning signal line 430 , the reset control signal line 440 and the light emitting control signal line 450 are arranged along the first direction (X direction). The scanning signal line 430 is located between the reset control signal line 440 and the light emitting control signal line 450 .

[0084] For example, in the first direction, the second electrode CC2 of the capacitor C (i.e., the gate of the driving transistor T1) is located between the scanning signal line 430 and the emission control signal line 450. The protruding structure P protruding from the scanning signal line 430 is located on a side of the scanning signal line 430 away from the emission control signal line 450.

[0085] For example, a first insulating layer is formed on the first conductive layer 3200 to insulate the first conductive layer 3200 from the second conductive layer 3300 to be formed subsequently.

[0086] Figure 3B FIG1 is a schematic diagram of a partial planar structure of a stacked structure of an active semiconductor layer, a first conductive layer, and a second conductive layer according to an embodiment of the present disclosure. Figure 3B As shown, the second conductive layer 330 includes a first electrode CC1 of the capacitor C and a plurality of reset power signal lines 410 extending along the second direction. The first electrode CC1 of the capacitor C and the second electrode CC2 of the capacitor C at least partially overlap to form the capacitor C.

[0087] For example, the second conductive layer 330 further includes a plurality of covering portions S. Each threshold compensation transistor T2 includes two gates T2-g1 and T2-g2, and an active semiconductor layer 3100 located between orthographic projections of the two gates on the active semiconductor layer 3100. Along a direction perpendicular to the substrate, the covering portion S overlaps the active semiconductor layer 3100 between the two gates.

[0088] For example, a second insulating layer is formed on the second conductive layer 3300 to insulate the second conductive layer 3300 from the subsequently formed source-drain metal layer 3400 .

[0089] For example, Figure 3C Schematic diagram of via positions in each insulating layer according to an embodiment of the present disclosure. Figure 3D Schematic diagram of a partial planar structure of a source / drain metal layer provided according to an embodiment of the present disclosure. Figure 3E Schematic diagram of the stacked structure of the active semiconductor layer, the first conductive layer, the second conductive layer and the source / drain metal layer provided according to an embodiment of the present disclosure. Figures 3C to 3E As shown, the source-drain metal layer 3400 includes a data line 420 and a power signal line 460 extending along the second direction. The data line 420 passes through the gate insulating layer 2 ( Figures 5D to 5H As shown), the first insulating layer 3 ( Figures 5D to 5H shown) and the second insulating layer 4 ( Figures 5D to 5H The via 3005 (shown) is electrically connected to the second electrode of the data write transistor T2. The power signal line 460 is electrically connected to the first electrode of the second light-emitting control transistor T5 through a via 3009 that penetrates the gate insulating layer 2, the first insulating layer 3, and the second insulating layer 4. The power signal line 460 and the data line 420 are arranged alternately along the first direction. The power signal line 460 is electrically connected to the first electrode CC1 of the capacitor C (for example, the first electrode 120-CC1 of the capacitor C of the second pixel block 120, or the first electrode 300-CC1 of the capacitor C of the third color sub-pixel 300) through a via 3007 that penetrates the second insulating layer 4. For example, the second insulating layer 4 is an interlayer insulating layer.

[0090] For example, a dual-gate threshold compensation transistor can reduce leakage current. For example, the active semiconductor layer between the two channels of the dual-gate threshold compensation transistor T2 is in a floating state when the threshold compensation transistor T2 is turned off, and is easily affected by the surrounding line voltage and jumps, thereby affecting the leakage current of the threshold compensation transistor T2, and further affecting the luminous brightness. In order to maintain the stability of the voltage of the active semiconductor layer between the two channels of the threshold compensation transistor T2, the covering portion S is designed to form a capacitor with the active semiconductor layer between the two channels of the threshold compensation transistor T2. The covering portion S can be connected to the power signal line 460 to obtain a constant voltage, so that the voltage of the active semiconductor layer in the floating state can be kept stable. The covering portion S overlaps with the active semiconductor layer between the two channels of the dual-gate threshold compensation transistor T2, and can also prevent the active semiconductor layer between the two gates from being illuminated by light and changing its characteristics, such as preventing the voltage of this part of the active semiconductor layer from changing, so as to prevent crosstalk. For example, as Figures 3C to 3E As shown, the power signal line 460 can be electrically connected to the cover portion S through a via 3003 penetrating the second insulating layer to provide the cover portion S with a constant voltage.

[0091] For example, a passivation layer 5 and a planarization layer 6 can be sequentially provided on the side of the source / drain metal layer 3400 away from the substrate. Figures 5D to 5H As shown) is used to protect the above-mentioned source and drain metal layer 3400. For example, the flat layer 6 can be located on the side of the passivation layer 5 away from the substrate. Of course, the embodiment of the present disclosure is not limited thereto. For example, the positions of the flat layer 6 and the passivation layer 5 can be interchanged, that is, the passivation layer can be located on the side of the flat layer away from the source and drain metal layer, or, as shown Figure 5I As shown, only the planarization layer 6 is provided, and no passivation layer 5 is provided.

[0092] For example, Figures 3C to 3E 、 Figure 5DAs shown, the pixel circuit of each sub-pixel further includes a first connecting portion 510 disposed in the same layer as the data line 420 , and the first connecting portion 510 extends along the first direction. The second electrode of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3 through the first connecting portion 510, and the first end of the first connecting portion 510 is connected to the second electrode of the threshold compensation transistor T2 (for example, the second electrode 110-T2-2 of the threshold compensation transistor T2 of the first pixel block 110, or the second electrode 120-T2-2 of the threshold compensation transistor T2 of the second pixel block 120, or the second electrode 200-T2-2 of the threshold compensation transistor T2 of the second color sub-pixel 200) through a via 3004 that penetrates the gate insulating layer 2, the first insulating layer 3 and the second insulating layer 4. The second end of the first connecting portion 510 is connected to the gate of the driving transistor T3 (for example, the gate 110-T3-g of the driving transistor T3 of the first pixel block 110, or the gate 120-T3-g of the driving transistor T3 of the second pixel block 120) through a via 3006 that penetrates the first insulating layer 3 and the second insulating layer 4. The pixel circuit of each sub-pixel also includes a second connecting portion 520 and a third connecting portion 530, which are provided in the same layer as the data line 420. The second connecting portion 520 is connected to the second electrode of the first light-emitting control transistor T6 via a via 3008 that penetrates the gate insulating layer 1, the first insulating layer 2, and the second insulating layer 3. One end of the third connecting portion 530 is connected to the first electrode of the first reset transistor T7 via a via 3002 that penetrates the gate insulating layer 1, the first insulating layer 2, and the second insulating layer 3. The other end of the third connecting portion 530 is connected to the reset power signal line 410 via a via 3001 that penetrates the second insulating layer. For example, the first connecting portion 510 overlaps with the first electrode CC1 of the capacitor C (e.g., the first electrode 110-CC1 of the first pixel block 110, or the first electrode 120-CC1 of the second pixel block 120).

[0093] For example, Figure 4 Schematic diagram of the second electrode and effective light-emitting area of ​​the light-emitting element of each sub-pixel provided according to an embodiment of the present disclosure, Figure 5A Schematic diagram of the stacked structure of the light-emitting element and source / drain metal layer of each sub-pixel provided according to an embodiment of the present disclosure. Figure 5B Schematic diagram of the stacked structure of the light-emitting element, active semiconductor layer, first conductive layer and source / drain metal layer of each sub-pixel provided according to an embodiment of the present disclosure. Figure 5C Schematic diagram of the stacked structure of the light emitting element of each sub-pixel and the active semiconductor layer, the first conductive layer, the second conductive layer and the source and drain metal layer provided in accordance with the embodiment of the present disclosure. Figures 4 to 5CAs shown, each first-color sub-pixel pair 100 includes a first pixel block 110 and a second pixel block 120 arranged along a second direction (Y direction). The first pixel block 110 includes a first effective light-emitting area 101, and the second pixel block 120 includes a second effective light-emitting area 102. In the first pixel block 110, the minimum distance between the orthographic projection of the first connecting portion 510 on a straight line extending along the second direction and the orthographic projection of the first effective light-emitting area 101 on the straight line is a first distance, or the orthographic projection of the first connecting portion 510 on the straight line extending along the second direction overlaps with the orthographic projection of the first effective light-emitting area 101 on the straight line. In the second pixel block 120, the minimum distance between the orthographic projection of the first connecting portion 510 on the straight line and the orthographic projection of the second effective light-emitting area 102 on the straight line is a second distance, and the first distance is less than the second distance. In the first pixel block 110, the overlapping area of ​​the orthographic projection of the second electrode 112 on the substrate and the orthographic projection of the first connecting portion 510 on the substrate is a first overlapping area; in the second pixel block 120, the overlapping area of ​​the orthographic projection of the second electrode 122 on the substrate and the orthographic projection of the first connecting portion 510 on the substrate is a second overlapping area, and the ratio of the first overlapping area to the second overlapping area is, for example, 0.8 to 1.2, for example, 0.9 to 1.1.

[0094] In the embodiment of the present disclosure, the display substrate further includes sub-pixels of other colors, and the minimum distance between the first pixel block and the second pixel block in each first-color sub-pixel pair is no greater than the minimum distance between two sub-pixels of the same color in the plurality of other-color sub-pixels. For example, if the first-color sub-pixel pair is a green sub-pixel pair, and the other-color sub-pixels include red sub-pixels, then the minimum distance between two green sub-pixels in the green sub-pixel pair is less than the minimum distance between two red sub-pixels.

[0095] For example, in the first pixel block 110, the minimum distance between the center of the orthographic projection of the first connecting portion 510 on the straight line extending along the second direction and the center of the orthographic projection of the first effective light-emitting area 101 on the above straight line is the first distance; in the second pixel block 120, the minimum distance between the center of the orthographic projection of the first connecting portion 510 on the above straight line and the center of the orthographic projection of the second effective light-emitting area 102 on the above straight line is the second distance, and the first distance is smaller than the second distance.

[0096] In the first color sub-pixel pair, when the distance between the geometric center of the first effective light-emitting area and the edge of the first connection part of the first pixel block close to the first effective light-emitting area is not equal to the distance between the geometric center of the second effective light-emitting area and the edge of the first connection part of the second pixel block close to the second effective light-emitting area, it is easy for the two first connection parts in the two first color sub-pixels to be covered by the two second electrodes in different areas, resulting in different capacitances formed between the first connection parts and the second electrodes in the two first color sub-pixels of the same first color sub-pixel pair, which in turn leads to differences in the gate node loads of the driving transistors in the two first color sub-pixels, and differences in the brightness of the two first color sub-pixels when emitting light.

[0097] In the disclosed embodiment, the ratio of the overlapping areas of the two second electrodes and the two first connecting portions in the two first-color sub-pixels of the same first-color sub-pixel pair is set to 0.8 to 1.2, for example, 0.9 to 1.1. For example, by making the overlapping areas of the two second electrodes and the two first connecting portions of the two first-color sub-pixels of the same first-color sub-pixel pair substantially equal, the difference in gate node loads of the drive transistors in the two first-color sub-pixels can be minimized, thereby ensuring that the brightness of the two first-color sub-pixels when emitting light is as close as possible.

[0098] For example, the ratio of the first overlapping area to the second overlapping area is 1, that is, the two overlapping areas are exactly the same, thereby ensuring that the brightness of the two first color sub-pixels when emitting light is the same.

[0099] For example, in the first pixel block 110, the second electrode 112 covers 60% to 90% of the area of ​​the first connection portion 510; in the second pixel block 120, the second electrode 122 covers 60% to 90% of the area of ​​the first connection portion 510. For example, in the first pixel block 110, the second electrode 112 covers 70% to 80% of the area of ​​the first connection portion 510 (the coverage area is the benefit of these); in the second pixel block 120, the second electrode 122 covers 70% to 80% of the area of ​​the first connection portion 510. For example, considering that a certain distance is maintained between the second electrode of the second pixel block and the second electrode of the third color sub-pixel (described later), the area of ​​the first connection portion covered by the second electrode of the second pixel block cannot be too large, for example, 70%. In order to ensure that the area of ​​the first connection portion covered by the second electrode of the first pixel block is approximately the same as the area of ​​the first connection portion covered by the second electrode of the second pixel block, the area of ​​the first connection portion covered by the second electrode of the first pixel block is set to, for example, 70%.

[0100] For example, Figures 4 to 5C As shown, the relative position relationship between the gate of the threshold compensation transistor T2 and the first connection portion 510 in each pixel circuit is substantially the same. For example, the first connection portion 510 is located between the gate of the threshold compensation transistor T2 and the second electrode of the data writing transistor T4.

[0101] For example, the two effective light-emitting areas in the first color sub-pixel pair 100 have substantially the same shape and size, and are axially symmetrically distributed about a straight line passing through the midpoint of a line connecting the centers of the two effective light-emitting areas and extending along the first direction as the central axis.

[0102] For example, the shapes of the first effective light-emitting area 101 and the second effective light-emitting area 102 may include a pentagon, a circle, or a teardrop shape. For example, the shape of the first effective light-emitting area 101 and the second effective light-emitting area 102 may be a pentagon, wherein the pentagon includes a set of parallel opposite sides (parallel to the second direction) and a vertical side (parallel to the first direction), the vertical side being perpendicular to the set of parallel opposite sides, the two vertical sides of the two effective light-emitting areas in each first color sub-pixel pair 100 being adjacent to each other, and each pentagon includes a sharp corner opposite to the vertical side, and the two sharp corners of the two effective light-emitting areas in each first color sub-pixel pair 100 are spaced apart from each other. For example, the distance between the two sharp corners of the two effective light-emitting areas in the first color sub-pixel pair 100 is greater than the length of the effective light-emitting areas of the second color sub-pixel 200 and the third color sub-pixel 300.

[0103] Furthermore, while the shape of the effective light-emitting area of ​​the first color sub-pixel in the figure strictly includes an angle formed by two line segments, in some embodiments, the effective light-emitting area of ​​the first color sub-pixel can be a rounded shape, such as a circle or a teardrop shape. That is, based on the aforementioned pentagonal shape, the corners of the effective light-emitting area of ​​the first color sub-pixel are rounded. For example, when forming an opening in the pixel-defining layer, the corners of the opening are rounded, thereby forming a light-emitting area with rounded corners.

[0104] For example, Figures 4 to 5C As shown, the first effective light-emitting area 101 and the second effective light-emitting area 102 are located between the two first connecting portions 510 in the first color sub-pixel pair 100, and the perpendicular midline M1 connecting the midpoints of the two vertical sides of the first and second effective light-emitting areas 101 and 102 is located on the side of the perpendicular midline M2 connecting the midpoints of the two first connecting portions 510 closer to the first connecting portion 510 of the first pixel block 110. Therefore, the distance between the center of the first effective light-emitting area and the corresponding first connecting portion is shorter than the distance between the center of the second effective light-emitting area and the corresponding first connecting portion.

[0105] For example, Figures 4 to 5CAs shown, in the first pixel block 110, the gate of the threshold compensation transistor T2 is located on the side of the first connection portion 510 away from the first effective light-emitting area 101. That is, in the first pixel block 110, the first connection portion 510 is closer to the first effective light-emitting area 101 than the gate of the threshold compensation transistor T2. In the second pixel block 120, the gate of the threshold compensation transistor T2 is located on the side of the first connection portion 510 close to the second effective light-emitting area 102. That is, in the second pixel block 120, the gate of the threshold compensation transistor T2 is closer to the second effective light-emitting area 102 than the first connection portion 510. As a result, the distance between the first connection portion of the second pixel block and the center of the second effective light-emitting area is greater than the distance between the first connection portion of the first pixel block and the first effective light-emitting area.

[0106] For example, Figures 4 to 5C As shown, the maximum length of the second electrode 122 of the second pixel block 120 along the second direction is greater than the maximum length of the second electrode 112 of the first pixel block 110 along the second direction, so that the overlapping areas of the second electrodes of the two first color sub-pixels and the corresponding first connection parts are substantially equal.

[0107] For example, Figures 4 to 5C As shown, the second electrode of each subpixel includes a main electrode and a connecting electrode. For example, the second electrode 112 in the first pixel block 110 includes a main electrode 1121 and a connecting electrode 1122. The shape of the main electrode 1121 is substantially the same as the shape of the first effective light-emitting area 101, such as a pentagon. For example, the orthographic projection of the first effective light-emitting area on the substrate lies within the orthographic projection of the main electrode on the substrate. For example, the orthographic projection of the main electrode 1121 on the substrate overlaps with the orthographic projection of the first connecting portion 510 on the substrate. For example, the second electrode 122 in the second pixel block 120 includes a main electrode 1221 and a connecting electrode 1122. The shape of the main electrode 1221 is substantially the same as the shape of the second effective light-emitting area 102, such as a pentagon. For example, the orthographic projection of the second effective light-emitting area on the substrate lies within the orthographic projection of the main electrode on the substrate. For example, the orthographic projection of the main electrode 1221 on the substrate does not overlap with the orthographic projection of the first connecting portion 510 on the substrate.

[0108] For example, Figures 4 to 5C As shown, in the first color sub-pixel pair 100, the second electrode further includes an auxiliary electrode connecting the main electrode and the connecting electrode. For example, the second electrode 112 in the first pixel block 110 further includes an auxiliary electrode 1123 connecting the main electrode 1121 and the connecting electrode 1122, and the connecting electrode 1122 extends along the first direction. For example, the second electrode 121 in the second pixel block 120 further includes an auxiliary electrode 1223 connecting the main electrode 1221 and the connecting electrode 1222.

[0109] For example, Figures 4 to 5C As shown, in the first pixel block 110, the auxiliary electrode 1123 is located on the side of the main electrode 1121 away from the second effective light-emitting area 102, and in the second pixel block 120, the auxiliary electrode 1223 is located on the side of the main electrode 1221 away from the first effective light-emitting area 101. In other words, the two auxiliary electrodes of the first color sub-pixel pair are located on the side of the two effective light-emitting areas away from each other.

[0110] For example, Figures 4 to 5C As shown, the second electrode in each first-color sub-pixel is an integrated structure, that is, the second electrode includes a main electrode, an auxiliary electrode, and a connecting electrode. To clearly describe the shape of the second electrode in the first-color sub-pixel and its relationship with other structures, the disclosed embodiment divides the second electrode in the first-color sub-pixel into a main electrode, an auxiliary electrode, and a connecting electrode.

[0111] For example, Figures 4 to 5C As shown, in the first color sub-pixel pair 100 , the two main electrodes 1121 and 1221 have substantially the same shape and size, the two auxiliary electrodes 1123 and 1223 have different shapes, and the two connecting electrodes 1122 and 1222 have different shapes.

[0112] For example, Figures 4 to 5C As shown, for example, the orthographic projection on the substrate of a first edge 1001 of the portion of the connecting electrode 1222 near the auxiliary electrode 1223 extending in the first direction, which is away from the second effective light-emitting area 102, overlaps with the orthographic projection on the substrate of the first connecting portion 510. For example, in the second pixel block 120, the second edge 1002 of the portion of the auxiliary electrode 1223 away from the connecting electrode, which is away from the second effective light-emitting area 102 in the Y direction, is located on a side of the first connecting portion 510 away from the second effective light-emitting area 102, such that the auxiliary electrode 1223 covers at least a portion of the first connecting portion 510. For example, the portion of the connecting electrode 1222 away from the auxiliary electrode 1223 is configured to be connected to the second connecting portion 520. According to the size of the via set in the flat layer, the width of the portion of the connecting electrode 1222 away from the auxiliary electrode 1223 along the Y direction is greater than the width of the portion of the connecting electrode 1222 close to the auxiliary electrode 1223 along the Y direction. As a result, the edge of the edge of the portion of the connecting electrode 1222 away from the auxiliary electrode 1223 extending along the first direction away from the second effective light-emitting area 102 is not on the same straight line as the first edge 1001.

[0113] For example, Figures 4 to 5CAs shown, in the first pixel block 110, a straight line on which the third edge 1003 of the portion of the connecting electrode 1122 extending in the first direction, which is close to the auxiliary electrode 1123 and is away from the first effective light-emitting area 101, lies is located on a side of the first connecting portion 510 away from the first effective light-emitting area 101. For example, the orthographic projection of the third edge 1003 of the portion of the connecting electrode 1122 close to the auxiliary electrode 1123 on the substrate does not overlap with the orthographic projection of the first connecting portion 510 on the substrate. For example, the portion of the connecting electrode 1122 away from the auxiliary electrode 1123 is configured to connect to the second connecting portion 520. Based on the size of the via hole provided in the planar layer, the width of the portion of the connecting electrode 1122 away from the auxiliary electrode 1123 along the Y direction is greater than the width of the portion of the connecting electrode 1122 close to the auxiliary electrode 1123 along the Y direction. As a result, the edge of the portion of the connecting electrode 1122 extending in the first direction, which is away from the first effective light-emitting area 101, and the third edge 1003 are not aligned with each other.

[0114] For example, Figures 4 to 5C As shown, in the first pixel block 110, the fourth edge 1004 of the portion of the auxiliary electrode 1123 that is connected to the connecting electrode 1122 (for example, the first portion 1123-1 of the auxiliary electrode 1123 described later) that is away from the first effective light-emitting area 101 is on the same straight line as the third edge 1003 of the connecting electrode 1122 to facilitate the production of the second electrode.

[0115] For example, in the second pixel block 120, the edge of the portion of the auxiliary electrode 1223 that is close to the connecting electrode 1222 and that is away from the second effective light-emitting area 102 is not aligned with the first edge 1001 of the connecting electrode 1222. For example, in the second pixel block 120, the second edge 1002 of the portion of the auxiliary electrode 1223 that is away from the connecting electrode 1222 and that extends along the first direction and that is away from the second effective light-emitting area 102 is not aligned with the first edge 1001 of the connecting electrode 1222. For example, in the second pixel block 120, the line on which the second edge 1002 of the auxiliary electrode 1223 lies is located on a side of the line on which the first edge 1001 of the connecting electrode 1221 lies that is away from the second effective light-emitting area 102, thereby covering the first connecting portion 510. For example, the connecting edge between the first edge 1001 and the second edge 1002 can be a straight line intersecting the X-direction, but is not limited thereto and can also be a broken line or a curved line.

[0116] The embodiment of the present disclosure schematically shows that the first edge, second edge, third edge and fourth edge are all straight edges for the convenience of manufacturing, but are not limited thereto. They can also be curved edges or broken line edges as long as the extension direction is along the X direction.

[0117] Since the third edge of the connecting electrode of the first pixel block is located on the side of the connecting electrode away from the first effective light-emitting area, the edge of the auxiliary electrode that is in contact with the connecting electrode and the third edge of the connecting electrode are located on the same straight line, which can also achieve coverage of the first connecting part. The edges of the auxiliary electrode and the connecting electrode that are close to each other and away from the first connecting part can be designed to be on the same straight line to facilitate production.

[0118] The straight line on which the first edge of the connecting electrode of the second pixel block lies overlaps with the first connecting portion. If the second edge of the auxiliary electrode of the second pixel block is aligned with the first edge of the connecting electrode, the area of ​​the first connecting portion covered by the auxiliary electrode of the second pixel block will be different from the area of ​​the corresponding first connecting portion covered by the auxiliary electrode of the first pixel block, resulting in a difference in brightness between the two first-color sub-pixels. Therefore, in the embodiment of the present disclosure, the first edge of the connecting electrode of the second pixel block and the second edge of the auxiliary electrode are not aligned, and the straight line on which the second edge of the auxiliary electrode lies is located on a side of the straight line on which the first edge of the connecting electrode lies away from the second effective light-emitting area, so that the overlapping area between the auxiliary electrode and the first connecting portion in the two first-color sub-pixels of the first-color sub-pixel pair is substantially the same, thereby reducing the load difference on the gate nodes of the driving transistors in the two first-color sub-pixels, thereby reducing the brightness difference between the two first-color sub-pixels and improving the display characteristics of the display substrate.

[0119] For example, Figures 3C to 5C As shown, the pixel circuit of each sub-pixel also includes a second connecting portion 520 provided on the same layer as the first connecting portion 510. The second connecting portion 520 is electrically connected to the second electrode of the first emission control transistor T6 via a via 3008 that penetrates the gate insulating layer, the first insulating layer, and the second insulating layer. The connecting electrode of the second electrode of each sub-pixel is connected to the second connecting portion via a via that penetrates the planar layer, thereby achieving a connection with the first emission control transistor.

[0120] For example, in the first pixel block 110, the second connection portion 520 is farther from the first effective light-emitting area 101 than the first connection portion 510 in the second direction. Thus, the connection electrode 1122 is farther from the first effective light-emitting area 101 in the second direction than the first connection portion 510. For example, in the second pixel block 120, the second connection portion 520 is closer to the second effective light-emitting area 102 than the first connection portion 510 in the second direction. Thus, the connection electrode 1222 is closer to the second effective light-emitting area 102 in the second direction than the first connection portion 510.

[0121] For example, Figures 3C to 5CAs shown, a planarization layer is provided between the film layer where the second connection portion 520 is located and the film layer where the connection electrode is located, or a passivation layer and a planarization layer are provided between the film layer where the second connection portion 520 is located and the film layer where the connection electrode is located. The planarization layer includes multiple vias 3010 extending therethrough, and the connection electrode in each sub-pixel is electrically connected to the second connection portion 520 via the vias 3010. For example, the corresponding vias 3010 in the first pixel block 110 are further away from the first effective light-emitting area 101 in the second direction than the first connection portion 510 in the first pixel block 110. As a result, the connection electrode 1122 is further away from the first effective light-emitting area 101 in the second direction than the first connection portion 510 in the second pixel block 120. For example, the corresponding vias 3010 in the second pixel block 120 are closer to the second effective light-emitting area 102 in the second direction than the first connection portion 510 in the second pixel block 120. As a result, the connection electrode 1222 is closer to the second effective light-emitting area 102 in the second direction than the first connection portion 510 in the second pixel block 120.

[0122] For example, Figures 4 to 5J As shown, in the first pixel block 110, the first gate 110-T2-g1 of the threshold compensation transistor T2 is located on the side of the second gate 110-T2-g2 close to the first effective light-emitting area 101 in the second direction, the straight line where the third edge 1003 of the connecting electrode 1122 is located overlaps with the first gate T2-g1, and the edge of the auxiliary electrode 1123 (such as the second portion 1123-2 of the auxiliary electrode 1123 described later) away from the first effective light-emitting area 101 is located on the side of the first gate T2-g1 away from the first effective light-emitting area 101 so that the auxiliary electrode 1123 covers the first gate T2-g1. For example, Figure 5G As shown, both the protruding structure P and the covering portion S (described later) overlap with the active semiconductor layer of the threshold compensation transistor T2. In the disclosed embodiment, by providing an auxiliary electrode in the first pixel block that covers the first gate of the threshold compensation transistor, it is possible to prevent external light from directly reaching the channel region of the threshold compensation transistor and to prevent the characteristic shift of the threshold compensation transistor caused by illumination during display of the display substrate.

[0123] For example, Figures 4 to 5CAs shown, in the first pixel block 110, the auxiliary electrode 1123 includes a first portion 1123-1 and a second portion 1123-2 that are connected to each other. The first portion 1123-1 is connected to the connecting electrode 1122, and the second portion 1123-2 covers at least a portion of the first gate electrode T2-g1 of the threshold compensation transistor T2. The fourth edge 1004 of the first portion 1123-1 extending in the first direction and the third edge 1003 of the connecting electrode 1122 are located on the same straight line, and the edge of the second portion 1123-2 extending in the first direction is farther away from the first effective light-emitting area 101 in the Y direction than the fourth edge 1004. For example, the second portion 1123-2 is located on a side of the second gate electrode T2-g2 of the threshold compensation transistor T2 that is farther away from the connecting electrode 1122 in the first direction. For example, in the first pixel block 110, the auxiliary electrode 1123 covers a portion of the active layer between the first gate electrode T2-g1 and the second gate electrode T2-g2 of the threshold compensation transistor T2.

[0124] In the embodiment of the present disclosure, a protrusion protruding toward the side away from the first effective light-emitting area is provided in the auxiliary electrode of the first pixel block to cover the first gate of the threshold compensation transistor and part of the active layer between the first gate and the second gate. This can ensure that the second electrode of the first pixel block can still cover a channel area of ​​the threshold compensation transistor even if there is a certain degree of alignment offset during the formation process, thereby preventing the transistor characteristics from being offset due to light, and further preventing the writing of the gate potential of the driving transistor from being affected.

[0125] In the embodiment of the present disclosure, the threshold compensation transistor has a dual-gate structure and has two channel regions. The second gate of the threshold compensation transistor in the first pixel block is not covered by the second electrode. In order to ensure that at least one channel region of the threshold compensation transistor is in a blocked state to ensure the characteristics of the threshold compensation transistor, a protrusion protruding toward the side away from the first effective light-emitting area is provided in the auxiliary electrode of the first pixel block, which can ensure that the first gate of the threshold compensation transistor is completely covered by the second electrode.

[0126] For example, the second electrode of the first pixel block covers one of the two gates of the threshold compensation transistor, and the second electrode of the second pixel block covers both gates of the threshold compensation transistor.

[0127] For example, along a direction perpendicular to the base substrate, the main body of the second electrode of the first pixel block overlaps with the covering portion S, and the main body of the second electrode of the second pixel block overlaps with the covering portion S.

[0128] For example, Figures 1 to 5CAs shown, the second electrode 320 of the third color sub-pixel 300 further includes an auxiliary electrode 323 located on a side of the main electrode 321 away from the connecting electrode 322 and connected to the main electrode 321. The shape of the main electrode 321 of the third color sub-pixel 300 is the same as that of the effective light-emitting area 301, for example, both are hexagonal or elliptical. The connecting electrode 322 is connected to the second connecting portion 520 via a via 3010 penetrating the planar layer to achieve connection with the first light-emitting control transistor T6.

[0129] For example, Figures 1 to 5H As shown, in the third color sub-pixel 300, the second gate 300-T2-g2 of the threshold compensation transistor T2 is located on the side of the first gate 300-T2-g1 close to the effective light-emitting area 301 of the third color sub-pixel 300, and the auxiliary electrode 323 covers a portion of the active layer between the second gate T2-g2 and the first gate T2-g1. Figure 5H As shown, both the protruding structure P and the covering portion S (described later) overlap with the active semiconductor layer of the threshold compensation transistor T2. In the disclosed embodiment, the threshold compensation transistor has a dual-gate structure with two channel regions. The first gate of the threshold compensation transistor in the third-color sub-pixel is not covered by the second electrode. To ensure that at least one channel region of the threshold compensation transistor is shielded and maintain the characteristics of the threshold compensation transistor, a protruding protrusion is provided on the side of the main electrode of the third-color sub-pixel away from the connecting electrode to form an auxiliary electrode. As a result, even if there is a certain degree of alignment offset during the formation of the second electrode, it can still completely cover one channel region of the threshold compensation transistor, preventing light-induced deviation of the transistor characteristics and, in turn, preventing the writing of the gate potential of the drive transistor from being affected.

[0130] For example, the light-emitting element may be a light-emitting element or an inorganic light-emitting element.

[0131] For example, Figure 5D As shown, a pixel defining layer 7 is provided on the side of the second electrode of each color sub-pixel away from the base substrate. The pixel defining layer 7 includes an opening 070 to expose part of the second electrode. When a subsequent organic light-emitting layer is formed in the opening 070 of the above-mentioned pixel defining layer 7, the organic light-emitting layer contacts the second electrode, so that this part can drive the organic light-emitting layer to emit light.

[0132] For example, Figure 6 FIG. 1 is a schematic diagram of a partial cross-sectional structure of a display substrate. Figure 6As shown, the display substrate includes a film layer 010, which includes a base substrate, an active semiconductor layer located on the base substrate, and at least one conductive layer located on the side of the active semiconductor layer away from the base substrate. The display substrate also includes a source / drain metal layer 011 located on the film layer 010. For example, the source / drain metal layer 011 may include data lines, power signal lines, and other traces. The display substrate also includes a planar layer 012 located on the side of the source / drain metal layer 011 away from the film layer 010, an anode 013 located on the side of the planar layer 012 away from the source / drain metal layer 011, and a pixel defining layer 014 located on the side of the anode 013 away from the planar layer 012. The pixel defining layer 014 includes multiple openings 015-017 for defining the light-emitting areas of the sub-pixels. The multiple openings 015-017 expose portions of the anode 013. When an organic light-emitting layer is subsequently formed in the openings 015-017 of the pixel defining layer 014, the organic light-emitting layer contacts the anode 013, thereby driving the organic light-emitting layer to emit light.

[0133] like Figure 6 As shown, the thickness of the source / drain metal layer 011 is relatively large, for example, 0.6-0.9 microns, which can cause the surface of the planar layer 012 located on the source / drain metal layer 011, facing the anode 013, to be uneven. For example, the distance between the surface of the planar layer 012 directly above the source / drain metal layer 011 (such as the data line, power signal line, and patterns made of the same layer and material) away from the film layer 010 and the surface of the film layer 010 away from the planar layer 012 is h1, and the distance between the surface of the planar layer 012 directly above the region where the source / drain metal layer 011 is not provided and the surface of the film layer 010 away from the planar layer 012 is h2, where h1>h2.

[0134] like Figure 6As shown, within opening 016, a portion of planar layer 012 is provided with source / drain metal layer 011 directly below, while another portion is not provided with source / drain metal layer 011 directly below. Consequently, the surface of planar layer 012 within opening 016 facing anode 013 is uneven, causing the surface of anode 013 located on planar layer 012 to be uneven as well. For example, for anode 013 located within opening 016, the distance between the surface of anode 013 located directly above source / drain metal layer 011, away from film layer 010, and the surface of film layer 010, away from anode 013, is h3. The distance between the surface of anode 013 located at a position where source / drain metal layer 011 is not provided, away from film layer 010, and the surface of film layer 010, away from anode 013, is h4, where h3>h4. As a result, anode 013 within opening 016 is "tilted." Similarly, the anode 013 in the opening 015 will also be "tilted", and due to the difference in the position of the source-drain metal layer 011, the "tilt direction" of the anode 013 in the opening 015 is different from the "tilt direction" of the anode 013 in the opening 016, resulting in inconsistent light intensity in different directions from the sub-pixels corresponding to the opening 015 and the opening 016. Taking the direction indicated by the arrow in the Y direction as the right, the light intensity emitted to the left and right sides of the sub-pixel light-emitting areas defined by the opening 015 and the opening 016 is inconsistent. There is no source-drain metal layer 011 directly below the anode 013 in the opening 017. Therefore, the surface of the anode 013 in the opening 017 is basically flat and does not "tilt". The sub-pixel light-emitting area defined by the opening 017 emits light with consistent intensity in different directions. For the light-emitting areas of three adjacent sub-pixels of different colors defined by openings 015-017, the anode 013 within opening 015 is tilted to the left, the anode 013 within opening 016 is tilted to the right, and the anode 013 within opening 017 is not tilted. As a result, the anodes 013 of the different-colored sub-pixels tilt in different directions, resulting in mismatched light intensities emitted from the light-emitting areas of the three sub-pixels to the left and right. Display devices using such display substrates can experience significant visual color shift, which appears to the human eye as red on one side and bluish on the other.

[0135] For example, in the first pixel block, the orthographic projection of the second electrode on the substrate overlaps with the orthographic projection of the gate of the driving transistor on the substrate; in the second pixel block, the orthographic projection of the second electrode on the substrate overlaps with the orthographic projection of the gate of the driving transistor on the substrate.

[0136] For example, in each color sub-pixel, the overlapping area between the orthographic projection of the second connecting portion on the base substrate and the orthographic projection of the first electrode of the capacitor on the base substrate is very small.

[0137] For example, Figure 5C and Figure 5JAs shown, the second electrode of the second color sub-pixel covers the vias 3009 and 3021 connecting the source-drain metal layer and the active semiconductor layer.

[0138] In another example of the embodiment of the present disclosure, Figures 3A to 5C As shown, the plurality of data lines 420 include a plurality of first data lines 421, and the plurality of power signal lines 460 include a plurality of first power signal lines 461. For example, along a third direction perpendicular to the base substrate, the second electrode 220 of the second color sub-pixel 200 overlaps with the first data line 421, the first power signal line 461, and the second connecting portion 520. In the portion where the first data line 421, the first power signal line 461, and the second connecting portion 520 overlap with the second electrode 220, the first power signal line 461 and the first data line 421 are located on both sides of the second connecting portion 520, and the minimum distance d1 ( d2 ) between the edges of the second connecting portion 520 and the first power signal line 461 that are close to each other is d3 . Figure 5B ) and the minimum distance d2 (shown) between the edge where the second connection portion 520 and the first data line 421 are close to each other Figure 5B 461) is 0.8 to 1.2. For example, the ratio of the minimum distance between the edges of the second connection portion 520 and the first power signal line 461 that are close to each other to the minimum distance between the edges of the second connection portion 520 and the first data line 421 that are close to each other is 0.9 to 1.1. For example, the ratio of the minimum distance between the edges of the second connection portion 520 and the first power signal line 461 that are close to each other to the minimum distance between the edges of the second connection portion 520 and the first data line 421 that are close to each other is 1.

[0139] In the embodiment of the present disclosure, the distance between the second connecting portion and the adjacent data line and power signal line is set to be approximately equal, so that the height difference between the middle area of ​​the second electrode of the second color sub-pixel (the area that does not overlap with the data line and the power signal line) and the two side areas (the area that overlaps with the data line and the power signal line) can be reduced, thereby improving the flatness of the second electrode of the second color sub-pixel and improving color deviation.

[0140] For example, the minimum distance between the first data line 421 and the first power signal line 461 can be 20 to 25 microns, and the maximum dimension of the second connection portion 520 along the Y direction can be 15 to 20 microns. The present disclosure is not limited thereto, as long as the distance between the first data line, the second connection portion, and the first power signal line is not less than 3 microns.

[0141] For example, Figures 3A to 5CAs shown, along the third direction, the effective light-emitting area 202 of each second color sub-pixel 200 overlaps with the first data line 421, the first power signal line 461 and the second connection portion 520, and in the portion where the first data line 421, the first power signal line 461 and the second connection portion 520 overlap with the effective light-emitting area 201 of the second color sub-pixel 200, the ratio of the distance between the edges of the second connection portion 520 and the first power signal line 461 close to each other to the distance between the edges of the second connection portion 520 and the first data line 421 close to each other is 0.8 to 1.2, for example, 0.9 to 1.1, thereby reducing the height difference between the middle area and the two side areas of the second electrode of the second color sub-pixel, improving the flatness of the second electrode in the effective light-emitting area of ​​the second color sub-pixel, and improving color deviation.

[0142] For example, Figures 3A to 5C As shown, in the portion of the second connection portion 520 that overlaps with the effective light-emitting area 202 of the second color sub-pixel 200, the distance between the second connection portion 520 and the first data line 421 is approximately equal to the distance between the second connection portion 520 and the first power signal line 461, which can further ensure the flatness of the second electrode located in the effective light-emitting area of ​​the second color sub-pixel to improve color deviation.

[0143] For example, Figures 3A to 5C As shown, the distances to the two endpoints of the effective light-emitting area 201 of the second color sub-pixel 200 in the Y direction (the direction intersecting the direction in which the data lines extend) are approximately equal, and the orthographic projection of a straight line extending along the X direction on the substrate overlaps with the orthographic projection of the second connecting portion 520 on the substrate. For example, the orthographic projection of a straight line extending along the X direction and passing through the midpoint of a line connecting two opposite endpoints of the effective light-emitting area 201 of the second color sub-pixel 200 in the Y direction overlaps with the orthographic projection of the second connecting portion 520 on the substrate. For example, the orthographic projection of a straight line extending along the X direction and passing through the midpoint of a line connecting two endpoints of the effective light-emitting area 201 of the second color sub-pixel 200 in the Y direction (the direction intersecting the direction in which the data lines extend) overlaps with the orthographic projection of the second connecting portion 520 on the substrate. Therefore, relative to the distribution positions of the first data line and the first power signal line, in the embodiment of the present disclosure, the center line of the effective light-emitting area 201 of the second color sub-pixel 200 extending along the first direction overlaps with the second connecting portion, which can improve the symmetry of the second electrode and improve color deviation.

[0144] For example, Figures 3A to 5CAs shown, the second connection portion 520 includes a first sub-connection portion 521 connected to each other and a first spacer 522 located on the side of the first sub-connection portion 521 near the first power signal line 461. The second electrode 220 of the second color sub-pixel 200 is electrically connected to the second electrode of the first emission control transistor T6 via the first sub-connection portion 521. For example, the first spacer and the first sub-connection portion are integrally structured. In the disclosed embodiment, the second connection portion is schematically divided into the first sub-connection portion and the first spacer to clearly illustrate the positional relationship between the second connection portion, the second electrode of the second color sub-pixel, and the effective light-emitting area.

[0145] For example, Figures 3A to 5C As shown, the first sub-connection portion 521 is shaped like a rectangle extending in the X direction. A straight line extending in the X direction through the center of the effective light-emitting area 201 of the second color sub-pixel 200 does not coincide with a second straight line extending in the X direction through the center of the first sub-connection portion 521. For example, the centerline passing through the center of the effective light-emitting area 201 of the second color sub-pixel 200 is located on the side of the centerline passing through the center of the first sub-connection portion 521 closer to the first spacer 522. As a result, the entire first sub-connection portion is offset to the left of the centerline extending in the X direction of the second color sub-pixel (to the right, as indicated by the arrow in the Y direction). Without the first spacer, the height difference between the two sides of the centerline of the second electrode of the second color sub-pixel would be large, resulting in poor symmetry of the second electrode and a tendency to cause color shift in the Y direction. In the embodiment of the present disclosure, a first pad is provided between the first sub-connecting portion and the first power signal line so that the position where the second connecting portion overlaps with the second electrode of the second color sub-pixel is located in the middle area of ​​the effective light-emitting area of ​​the second color sub-pixel. This can reduce the height difference between the middle area and the two side areas of the second electrode of the second color sub-pixel and improve the symmetry, which is beneficial to ensuring that the light intensity of the effective light-emitting area is consistent in all directions, thereby improving color deviation.

[0146] For example, Figures 3A to 5CAs shown, the second connection portion 520 in the second color sub-pixel 200 is L-shaped, and along the X-direction, the size of the first sub-connection portion 521 is larger than the size of the first spacer 522. For example, the second electrode 220 of the second color sub-pixel 200 includes a main electrode 221 and a connection electrode 222 that are connected to each other. The main electrode 221 has the same shape as the effective light-emitting area 201, for example, both are hexagonal or elliptical. For example, the orthographic projection of the effective light-emitting area of ​​the second color sub-pixel on the substrate lies within the orthographic projection of the main electrode on the substrate. For example, along a direction perpendicular to the substrate, a portion of the first sub-connection portion 521 overlaps with the main electrode 221, another portion of the first sub-connection portion 521 overlaps with the connection electrode 222 and is connected to the connection electrode 222 through a via 3010 in the planar layer. The first spacer 521 overlaps only with the main electrode 221 and does not overlap with the connection electrode 222. For example, the via 3010 (such as the first via 3011 described later) is farther away from the effective light-emitting area 201 of the second color sub-pixel 200 than the first pad 522. For example, more than 90% of the orthographic projection of the second connection portion 520 of the second color sub-pixel 200 on the base substrate falls within the orthographic projection of the second electrode 220 on the base substrate. In the embodiment of the present disclosure, the first pad can be provided only at the location of the second electrode of the first color sub-pixel to cooperate with the first sub-connection portion to improve the flatness and symmetry of the second electrode. In the embodiment of the present disclosure, it is schematically shown that the first pad is not provided outside the location of the second electrode, but it is not limited to this. The shape of the second connection portion in the second color sub-pixel can also be designed according to the process conditions and the actual needs of the product.

[0147] For example, Figures 3A to 5CAs shown, along the third direction, the effective light-emitting area 201 of the second color sub-pixel 200 overlaps with the third connection portion 530, and a straight line extending along the X-direction and passing through the geometric center of the effective light-emitting area 201 overlaps with the third connection portion 530. For example, the connection electrode 222 is located on a side of a straight line extending along the Y-direction and passing through the geometric center of the effective light-emitting area 201 that is away from the third connection portion 530. For example, the third connection portion 530 is substantially located in the middle of the effective light-emitting area 201 of the second color sub-pixel 200. For example, the second connection portion 520 and the third connection portion 530 are respectively located on either side of a straight line extending along the Y-direction and passing through the center of the effective light-emitting area 201 of the second color sub-pixel 200. In other words, the second connection portion 520 and the third connection portion 530 are respectively located on either side of the center line of the effective light-emitting area 201 of the second color sub-pixel 200 extending along the Y-direction. For example, the second connection portion 520 is located on one side of a line extending along the Y direction and passing through the center of the effective light-emitting area 201 of the second color sub-pixel 200, and at least a portion of the third connection portion 530 is located on the other side of the line. Compared to the data lines and power signal lines distributed on both sides of the effective light-emitting area, in the disclosed embodiment, the central region of the second electrode of the second color sub-pixel is covered by less source and drain metal layer. By providing a first spacer and positioning the third connection portion and the portion of the second connection portion including the first spacer that overlaps with the effective light-emitting area of ​​the second color sub-pixel in the central region of the effective light-emitting area, the height difference between the central region and the regions on both sides of the second electrode in the effective light-emitting area can be reduced, thereby improving flatness and thereby reducing color shift.

[0148] For example, Figures 3A to 5C As shown, the plurality of data lines 420 further include a plurality of second data lines 422, which are arranged in the same layer and alternately with the plurality of first data lines 421. The plurality of power signal lines 460 further include a plurality of second power signal lines 462, which are arranged in the same layer and alternately with the plurality of first power signal lines 461. For example, along the third direction, the second electrode 220 of each second color sub-pixel 200 overlaps with the first data line 421, the first power signal line 461, the second connecting portion 520, the second data line 422, and the second power signal line 462. In the overlapping portion, the second power signal line 462 is located on the side of the first data line 421 away from the second connecting portion 520, and the second data line 422 is located on the side of the first power signal line 461 away from the second connecting portion 520. That is, the second electrode 220 of the second color sub-pixel 200 overlaps with two data lines 420 and two power signal lines 460, and a first data line 421 and a second power signal line 462 are provided on one side of the second connection portion 520, and a second data line 422 and a first power signal line 461 are provided on the other side of the second connection portion 520.

[0149] For example, Figures 3A to 5C As shown, the effective light-emitting area 201 of each second color sub-pixel 200 overlaps with the first data line 421, the first power signal line 461, the second data line 422, and the second power signal line 462. In the overlapping portion, the ratio of the sum of the overlapping areas of the first power signal line 461 and the second data line 422 with the effective light-emitting area 201 to the sum of the overlapping areas of the second power signal line 462 and the first data line 421 with the effective light-emitting area 201 is 0.8 to 1.2, for example, 0.9 to 1.1. In the disclosed embodiment, both sides of the effective light-emitting area of ​​the second color sub-pixel overlap with the data lines and the power signal line, and the areas of the source and drain metal layers on both sides of the second connection portion of the second color sub-pixel that overlap with the effective light-emitting area are approximately equal. This ensures that the overlapping portion of the effective light-emitting area of ​​the second color sub-pixel and the source and drain metal layers has good symmetry, which helps prevent color shift.

[0150] For example, Figures 3A to 5C As shown, the first data line 421 overlapping with the second electrode 220 of the second color sub-pixel 200 is electrically connected to the second electrode of the data write transistor T4 of the first pixel block 110, and the second power signal line 462 overlapping with the second electrode 220 of the second color sub-pixel 200 is electrically connected to the first electrode of the second emission control transistor T5 of the first pixel block 110. For example, the first data line 421 and the second power signal line 420 overlapping with the second electrode 220 of the second color sub-pixel 200 both overlap with the second electrode 112 of the first pixel block 110. For example, the second electrode 112 of the first pixel block 110 has two overlapping portions with the first data line 421 and the second power signal line 462, and the two overlapping portions are located on either side of a straight line extending along the first direction and dividing the effective light-emitting area of ​​the first pixel block 110 into two portions of equal area. As a result, the second electrode of the first pixel block has good symmetry and flatness in the Y direction, which helps prevent color shift.

[0151] For example, Figures 3A to 5C As shown, the first power signal line 461, which overlaps with the second electrode 220 of the second color sub-pixel 200, is electrically connected to the first electrode of the second emission control transistor T5 of the second color sub-pixel 200, and the second data line 422, which overlaps with the second electrode 220 of the second color sub-pixel 200, is electrically connected to the second electrode of the data write transistor T4 of the second color sub-pixel. For example, the second electrode 122 of the second pixel block 120 has two overlapping portions with the second data line 422 and the first power signal line 461. These two overlapping portions are located on either side of a line extending along the X direction and passing through the center of the second effective emission area 201 of the second pixel block 120. As a result, the second electrode of the second pixel block has good symmetry and flatness in the Y direction, which helps prevent color shift.

[0152] For example, Figures 3A to 5C As shown, along a direction perpendicular to the base substrate, an edge of a side of the main electrode 1221 of the second pixel block 120 away from the auxiliary electrode 1223 overlaps with the first connection portion 510 of the second color sub-pixel 200 .

[0153] For example, Figures 3A to 5C As shown, along a direction perpendicular to the substrate, the second electrode 320 of each third color sub-pixel 300 overlaps with the first data line 421, the first power signal line 461, the second data line 422, and the second power signal line 462. For example, along a direction perpendicular to the substrate, the effective light-emitting area 301 of each third color sub-pixel 300 overlaps with the first data line 421, the first power signal line 461, the second data line 422, and the second power signal line 462. For example, the first data line 421 and the second power signal line 462 are located on one side of a center line extending in the X direction of the effective light-emitting area 301 of the third color sub-pixel 300, while the second data line 422 and the first power signal line 461 are located on the other side of the center line. For example, along a direction perpendicular to the substrate, in the overlapping portions of the second electrode 320 of each third color sub-pixel 300 with the first data line 421, the first power signal line 461, the second data line 422, and the second power signal line 462, the ratio of the sum of the overlapping areas of the first power signal line 461 and the second data line 442 with the effective light-emitting area 301 to the sum of the overlapping areas of the second power signal line 462 and the first data line 421 with the effective light-emitting area 301 is 0.8 to 1.2, for example, 0.9 to 1.1. Consequently, the portions of the second electrode 320 of the third color sub-pixel 300 located on both sides (where the data lines and the power signal lines overlap with the second electrode) overlap with the source and drain metal layers, and the overlapping portions are substantially symmetrically distributed, which helps reduce color shift.

[0154] For example, the second electrode 320 and the effective light-emitting area 301 of the third color sub-pixel 300 both overlap with the second connection portion 520. Furthermore, in the portion where the first data line 421, the first power signal line 461, and the second connection portion 520 overlap with the second electrode 320, the first power signal line 461 and the first data line 421 are located on opposite sides of the second connection portion 520. Furthermore, the ratio of the minimum distance between the edges of the second connection portion 520 and the first power signal line 461 that are adjacent to each other to the minimum distance between the edges of the second connection portion 520 and the first data line 421 that are adjacent to each other is no greater than 2.5, for example, no greater than 2. For example, a straight line extending along the X direction and passing through the center of the effective light-emitting area 301 of the third color sub-pixel 300 overlaps with the second connection portion 520. In the disclosed embodiment, positioning the second connection portion of the third color sub-pixel in the middle region of the effective light-emitting area can reduce the height difference between the second electrode in the middle region and on both sides of the effective light-emitting area (where the data lines and power signal lines overlap with the effective light-emitting area), thereby reducing color shift.

[0155] For example, Figures 3A to 5C As shown, the second connection portion 520 of the third color sub-pixel 300 includes a second sub-connection portion 523 and a second spacer 524 connected to each other. The second spacer 524 is located on a side of the second sub-connection portion 523 near the center of the effective light-emitting area 301 of the third color sub-pixel 300. For example, along a direction perpendicular to the substrate, the second spacer 524 overlaps with the effective light-emitting area 301, while the second sub-connection portion 523 does not overlap with the effective light-emitting area 301. For example, the second sub-connection portion and the second spacer are an integral structure. The embodiment of the present disclosure schematically divides the second connection portion into the second sub-connection portion and the second spacer to clearly illustrate the positional relationship between the second connection portion and the second electrode and the effective light-emitting area of ​​the third color sub-pixel.

[0156] For example, Figures 3A to 5C As shown, the second electrode 320 of the third color sub-pixel 300 includes a main electrode 321 and a connecting electrode 322, which are connected to each other. The main electrode 321 of the third color sub-pixel 300 has the same shape as the effective light-emitting area 301, for example, both are hexagonal or elliptical. For example, the orthographic projection of the effective light-emitting area of ​​the third color sub-pixel on the substrate is located within the orthographic projection of the main electrode on the substrate. For example, in a direction perpendicular to the substrate, the main electrode 321 overlaps with the second spacer 524, and the connecting electrode 322 overlaps with and is connected to the second sub-connecting portion 523. For example, in a direction perpendicular to the substrate, the main electrode 321 and the second sub-connecting portion 523 have substantially no overlap.

[0157] For example, Figures 3A to 5CAs shown, along a direction perpendicular to the substrate, the first connection portion 510 of the third color sub-pixel 300 overlaps with the effective light-emitting area 301. At least a portion of the first connection portion 510 of the third color sub-pixel 300 and the second spacer 524 are located on either side of a fourth straight line passing through the center of the effective light-emitting area 301 and extending along the Y direction. In the disclosed embodiment, the effective light-emitting area and the second electrode of the third color sub-pixel overlap with the first connection portion. By providing the second spacer at the edge of the effective light-emitting area away from the first connection portion, the height difference in the X direction of the middle region of the second electrode of the third color sub-pixel can be reduced, thereby improving the color shift of the third color sub-pixel.

[0158] For example, Figures 3A to 5C As shown, the second sub-connection portion 523 in the second connection portion 520 of the third color sub-pixel 300 is rectangular in shape. The side of the second sub-connection portion 523 closest to the first power signal line 461 is connected to the second electrode 320 via a via 3010 in the planar layer. The side of the second sub-connection portion 523 closest to the first data line 421 is connected to the second electrode of the first emission control transistor T6 via a via 3008 that passes through the gate insulating layer, the first insulating layer, and the second insulating layer. The rectangular shape in the embodiments of the present disclosure includes a standard rectangular shape and an approximately rectangular shape. For example, the approximately rectangular shape may include a shape with a generally rectangular overall outline, such as a rounded rectangle.

[0159] For example, Figures 3A to 5C As shown, the second spacer 524 in the second connection portion 520 of the third color sub-pixel 300 is rectangular in shape, and the two sides of the second spacer 524 extending in the X direction are aligned with the two sides of the second sub-connection portion 523 extending in the X direction, resulting in a rectangular shape for the second connection portion of the third color sub-pixel. In the disclosed embodiment, while the second spacer is added to reduce the height difference in the X direction between the middle region of the second electrode of the third color sub-pixel and the height difference in the Y direction between the second electrode, the rectangular shape of the second connection portion is set to facilitate manufacturing.

[0160] Figure 7 A schematic diagram of a partial cross-sectional structure of another display substrate. Figure 7 The display substrate shown includes Figure 6 The film layer 010, the source and drain metal layer 011, the planar layer 012, the anode 013 and the pixel definition layer 014 are shown. Figure 7 As shown, the planar layer 012 in the display substrate includes a via 018 to electrically connect the anode 013 to the source / drain metal layer 011. The pixel defining layer 014 includes an opening 019 to expose a portion of the anode 013. When the subsequent organic light-emitting layer is formed in the opening 019, the organic light-emitting layer contacts the anode 013 to form an effective light-emitting area.

[0161] like Figure 7 As shown, the via hole 018 is located outside the effective light-emitting area. Since the anode 013 located around the via hole 018 is tilted, a certain distance should be set between the effective light-emitting area and the via hole 018 to ensure the flatness of the anode 013 in the effective light-emitting area, thereby avoiding color deviation of the display substrate.

[0162] Figure 8 Schematic diagram of a pixel arrangement structure in a display substrate. Figure 8 As shown, the display substrate includes data lines 042 extending along the X direction. The display substrate also includes a red sub-pixel 021, a green sub-pixel pair 022, and a blue sub-pixel 023. The effective light-emitting areas of the red sub-pixel 021 and the blue sub-pixel 023 extend along the Y direction. For example, each sub-pixel includes a light-emitting element and a pixel circuit that drives the light-emitting element to emit light. The light-emitting element includes an anode, a light-emitting layer, and a cathode stacked in sequence in a direction away from the base substrate. The anode is connected to the connection portion 031 through a via 0310 to achieve connection with the thin film transistor in the pixel circuit. For example, the vias 0310 corresponding to the red sub-pixel 021, the green sub-pixel pair 022, and the blue sub-pixel 023 are arranged in a straight line along the Y direction. For example, the anode 0211 of the red sub-pixel 021 is connected to the connection portion 031 via a via 0310. A notch is provided on the long side of the effective light-emitting area 0211 of the red sub-pixel 021, near the via 0310, to avoid the via 0310 and ensure a suitable spacing (preset spacing), for example, 3 microns, between the effective light-emitting area 0211 and the via 0310. Similarly, a notch is also required on the long side of the effective light-emitting area of ​​the blue sub-pixel 023, near the via 0310, to avoid the via 0310 and ensure a preset spacing between the effective light-emitting area and the via 0310. This preset spacing refers to the minimum distance (for example, 3 microns) between the edge of the effective light-emitting area and the edge of the via to ensure that the via does not affect the light direction of the edge of the effective light-emitting area.

[0163] For example, the minimum distances between the edge of the third via hole in the first pixel block and the edges of the effective light-emitting areas of the second and fourth color sub-pixels are approximately equal and both are greater than 3 microns. For example, the minimum distances between the fourth via hole in the second pixel block and the edges of the effective light-emitting areas of the second and fourth color sub-pixels are both greater than 3 microns.

[0164] For example, the orthographic projection of the second electrode of the second color sub-pixel on the base substrate overlaps with the orthographic projection of the reset power signal line on the base substrate.

[0165] In another example of the embodiment of the present disclosure, Figures 4 to 5FAs shown, the second electrode 220 of the second color sub-pixel 200 is connected to the second connection portion 520 via a first via hole 3011 penetrating the planar layer, and the second electrode 320 of the third color sub-pixel 300 is connected to the second connection portion 520 via a second via hole 3012 penetrating the planar layer. The minimum distance between the orthographic projection of the effective light-emitting area 201 of the second color sub-pixel 200 on a straight line along the X direction (the direction in which the data line 420 extends) and the orthographic projection of the effective light-emitting area 301 of the third color sub-pixel 300 on the straight line is less than the sum of the dimensions of the first via hole and the predetermined distance between the edge of the first via hole and the edge of the effective light-emitting area, projected on the straight line. The first via 3011 is located in the X direction on a side of the effective light-emitting area 201 of the second color sub-pixel 200 that is close to the effective light-emitting area 301 of the third color sub-pixel 300. The second via 3012 is located in the X direction on a side of the effective light-emitting area 301 of the third color sub-pixel 300 that is close to the effective light-emitting area 201 of the second color sub-pixel 200. A first connecting line 3101 connecting the first via 3011 and the second via 3012 is not parallel to the Y direction. For example, the orthographic projections of the first via 3011, the fourth via 3014, and the third via 3013 on the substrate overlap with the orthographic projection of the light-emission control signal line 450 on the substrate. For example, the orthographic projection of the second via 3012 on the substrate does not overlap with the orthographic projection of the light-emission control signal line 450 on the substrate. The first connecting line is a straight line.

[0166] For example, the first line 3101 connecting the first via 3011 and the second via 3012 can refer to the line connecting the center of the first via and the center of the second via; it can also refer to the line connecting the point of the first via closest to the effective light-emitting area of ​​the second color sub-pixel and the point of the second via farthest from the effective light-emitting area of ​​the third color sub-pixel; it can also refer to the line connecting the point of the first via farthest from the effective light-emitting area of ​​the second color sub-pixel and the point of the second via closest to the effective light-emitting area of ​​the third color sub-pixel.

[0167] For example, the second electrode of the second color sub-pixel and the second electrode of the third color sub-pixel do not overlap in the second direction.

[0168] In the embodiment of the present disclosure, the distance between the effective light-emitting area of ​​the second color subpixel and the effective light-emitting area of ​​the third color subpixel in the X direction is small, for example, smaller than the sum of the dimensions of the first via hole and the preset spacing. Therefore, if the first via hole is disposed within the spacing between the effective light-emitting area of ​​the second color subpixel and the effective light-emitting area of ​​the third color subpixel in the X direction, the position of the first via hole and the effective light-emitting area of ​​the second color subpixel will conflict, thereby affecting the light emission of the second color subpixel. In the embodiment of the present disclosure, the position of the via hole (for example, at least one of the first via hole and the second via hole) located in the planarization layer is adjusted based on the position of the effective light-emitting area of ​​the second color subpixel and the third color subpixel. For example, the connection line between the first via hole and the second via hole corresponding to the second color subpixel and the third color subpixel, respectively, is not parallel to the extension direction of the scan signal line. This ensures the flatness of the second electrodes of the second color subpixel and the third color subpixel, thereby ensuring the consistency of the light intensity of the effective light-emitting area in all directions and effectively improving color shift.

[0169] For example, Figures 4 to 5C As shown, the angle between the first connecting line 3101 and the Y direction is 5° to 15°. By adjusting the positions of the first via hole and the second via hole, the embodiment of the present disclosure can reduce the probability of color deviation of the second color sub-pixel and the third color sub-pixel.

[0170] For example, Figures 4 to 5C As shown, the second via 3012 is located on a side of a second straight line 3102 extending along the Y direction and passing through the first via 3011, close to the effective light-emitting area 201 of the second color sub-pixel 200. For example, the orthographic projection of the first via 3011 on the straight line extending along the X direction does not overlap with the orthographic projection of the second via 3012 on the same straight line. In the disclosed embodiment, the distance between the effective light-emitting area of ​​the second color sub-pixel and the first via, as well as the distance between the effective light-emitting area of ​​the third color sub-pixel and the second via, is set relatively large. This ensures that the vias do not affect the flatness of the second electrode within the effective light-emitting area, thereby ensuring consistent light intensity in all directions from the effective light-emitting area and effectively improving color shift.

[0171] For example, Figures 4 to 5CAs shown, in the second color sub-pixel 200, the second connection portion 520 is electrically connected to the second electrode of the first emission control transistor T6 via a first connection hole 3021 penetrating the gate insulating layer, the first insulating layer, and the second insulating layer. In the third color sub-pixel 300, the second connection portion 520 is electrically connected to the second electrode of the first emission control transistor T6 via a second connection hole 3022 penetrating the gate insulating layer, the first insulating layer, and the second insulating layer, and a second connection line 3200 connecting the first connection hole 3021 and the second connection hole 3022 is parallel to the Y direction. For example, the second connection line 3200 connecting the first connection hole 3021 and the second connection hole 3022 can refer to a line connecting the center of the first connection hole and the center of the second connection hole; or a line connecting the point of the first connection hole closest to the effective emission area of ​​the second color sub-pixel and the point of the second connection hole farthest from the effective emission area of ​​the third color sub-pixel; or a line connecting the point of the first connection hole farthest from the effective emission area of ​​the second color sub-pixel and the point of the second connection hole closest to the effective emission area of ​​the third color sub-pixel.

[0172] For example, Figures 4 to 5C As shown, the effective light-emitting area 201 of the second color sub-pixel 200 includes a first long side 1011 and a second long side 1012 extending along the Y direction. The second long side 1012 is located on the side of the first long side 1011 away from the first via 3011. Along the third direction perpendicular to the base substrate, the extension line of the first long side 1011 overlaps with the second via 3012. For example, the orthographic projection of the second via 3012 on a straight line extending along the X direction overlaps with the orthographic projection of the second connection hole 3022 on the same line. In the embodiment of the present disclosure, when adjusting the position of the second via, the position of the second connection hole is taken into consideration, and the position of the second via penetrating the planar layer is not significantly adjusted in the X direction relative to the position of the second connection hole penetrating the gate insulating layer, the first insulating layer, and the second insulating layer, thereby reducing the impact on the overall pixel circuit structure.

[0173] For example, Figures 4 to 5CAs shown, the effective light-emitting area 301 of the third color sub-pixel 300 includes a third long side 1013 and a fourth long side 1014 extending along the Y direction. The fourth long side 1014 is located on the side of the third long side 1013 away from the second via hole 3012. In a direction perpendicular to the substrate, the extension of the fourth long side 1014 overlaps with the first via hole 3011. For example, in a direction perpendicular to the substrate, the first connection hole 3021 overlaps with the effective light-emitting area 201 of the second color sub-pixel 200. The first via hole 3011 is farther away from the effective light-emitting area 201 of the second color sub-pixel 200 than the first connection hole 3021. Furthermore, the orthographic projection of the first via hole 3011 on a line extending along the X direction does not overlap with the orthographic projection of the first connection hole 3021 on the same line. In the embodiment of the present disclosure, when adjusting the position of the first via hole, it is necessary to consider making a slight adjustment in the X direction of the position of the first via hole penetrating the planar layer relative to the position of the first connection hole penetrating the gate insulating layer, the first insulating layer, and the second insulating layer. It is also necessary to ensure the distance between the first via hole and the effective light-emitting area of ​​the second color sub-pixel to prevent affecting the consistency of the light-emitting intensity of the effective light-emitting area in all directions.

[0174] For example, Figures 4 to 5C As shown, the shortest distance between the first long side 1011 of the effective light-emitting area 201 of the second color sub-pixel 200 and the orthographic projection of the first via 3011 on the substrate is a first distance, and the shortest distance between the third long side 1013 of the effective light-emitting area 301 of the third color sub-pixel 300 and the orthographic projection of the second via 3012 on the substrate is a second distance. The ratio of the first distance to the second distance is 0.8 to 1.2, for example, 0.9 to 1.1. For example, the first distance and the second distance are completely equal. For example, the first distance and the second distance are both greater than 3 microns. The "shortest distance between the first long side 1011 and the orthographic projection of the first via 3011 on the substrate" refers to the distance between the point where the orthographic projection of the first via is closest to the orthographic projection of the first long side and the orthographic projection of the first long side. The "shortest distance between the third longest side 1013 and the orthographic projection of the second via 3012 on the substrate" refers to the distance between the point of the orthographic projection of the second via closest to the orthographic projection of the third longest side and the orthographic projection of the third longest side. In the disclosed embodiments, by setting a larger distance between the via in the planarization layer and the edge of the sub-pixel's effective light-emitting area, the via can be prevented from affecting the flatness of the second electrode within the effective light-emitting area, thereby ensuring consistent light intensity in all directions and effectively improving color shift.

[0175] For example, Figures 4 to 5CAs shown, the first long side 1011 of the effective light-emitting area 201 of the second color sub-pixel 200 is a straight line, and the third long side 1013 of the effective light-emitting area 301 of the third color sub-pixel 300 is a straight line. In the disclosed embodiment, the positions of the first and second via holes are adjusted to ensure that the via holes do not affect the effective light-emitting area. This also avoids designing the edge of the effective light-emitting area with a notch to avoid the via holes, avoids designing irregularly shaped openings in the pixel defining layer, and reduces problems during the manufacturing process.

[0176] For example, Figures 4 to 5C As shown, the second electrode 112 of the first pixel block 110 in the first color sub-pixel pair 100 is connected to the second connection portion 520 via a third via 3013 penetrating the planar layer. The second electrode 122 of the second pixel block 120 in the first color sub-pixel pair 100 is connected to the second connection portion 520 via a fourth via 3014 penetrating the planar layer. A first connecting line 3103 connecting the third via 3013 and the fourth via 3014 is substantially parallel to the Y direction. In the disclosed embodiment, the third and fourth vias are arranged on a straight line extending along the Y direction. This ensures a distance between the vias and the corresponding effective light-emitting areas while also facilitating manufacturing processes.

[0177] For example, the first line 3103 connecting the third via 3013 and the fourth via 3014 can refer to the line connecting the center of the third via and the center of the fourth via; it can also refer to the line connecting the point of the third via closest to the first effective light-emitting area and the point of the fourth via closest to the second effective light-emitting area; it can also refer to the line connecting the point of the third via farthest from the first effective light-emitting area and the point of the fourth via farthest from the second effective light-emitting area.

[0178] For example, Figures 4 to 5C As shown, the straight line along which the first connection line 3103 lies passes through the first via 3011 and does not pass through the second via 3012. In the disclosed embodiment, the first via connected to the second electrode of the second color sub-pixel, and the third and fourth vias connected to the second electrodes of the first color sub-pixel pair are substantially located along a straight line parallel to the scan signal line. This ensures that the distance between the first via and the corresponding effective light-emitting area is greater than 3 microns, while also facilitating manufacturing.

[0179] For example, Figures 4 to 5C As shown, along the third direction perpendicular to the base substrate, the straight line where the third long side 1013 of the effective light-emitting area 301 of the second color sub-pixel 300 lies overlaps with both the third via hole 3013 and the fourth via hole 3014 .

[0180] For example, Figures 4 to 5CAs shown, along the Y direction, a third via 3013 or a fourth via 3014 is provided between the first via 3011 and the second via 3012. That is, the third via 3013 and the fourth via are provided on both sides of the first via in the Y direction, or the third via 3013 and the fourth via are provided on both sides of the second via in the Y direction.

[0181] For example, Figures 4 to 5C As shown, in the first sub-pixel block 110, the second connection portion 520 is electrically connected to the second electrode of the first light-emitting control transistor T6 through the third connection hole 3023 penetrating the gate insulating layer, the first insulating layer and the second insulating layer; in the second sub-pixel block 120, the second connection portion 520 is electrically connected to the second electrode of the first light-emitting control transistor T6 through the fourth connection hole 3024 penetrating the gate insulating layer, the first insulating layer and the second insulating layer, and the fourth connection line 3400 connecting the third connection hole 3023 and the fourth connection hole 3024 roughly coincides with the second connection line 3200.

[0182] For example, the fourth connection line 3400 connecting the third connection hole 3023 and the fourth connection hole 3024 may refer to the line connecting the center of the third connection hole and the center of the fourth connection hole; it may also refer to the line connecting the point of the third connection hole closest to the first effective light-emitting area and the point of the fourth connection hole closest to the second effective light-emitting area; it may also refer to the line connecting the point of the third connection hole farthest from the first effective light-emitting area and the point of the fourth connection hole farthest from the second effective light-emitting area.

[0183] It should be noted that, in the embodiment of the present disclosure, the first direction represents the extension direction of the data line, and the second direction represents the extension direction of the scanning signal line, and the names of the above two directions can be interchanged; in the embodiment of the present disclosure, the first connection portion represents the connection portion connecting the second electrode of the threshold compensation transistor and the gate of the driving transistor, the second connection portion represents the connection portion connecting the second electrode of the first light-emitting control transistor and the second electrode of the light-emitting element, and the third connection portion represents the connection portion connecting the first electrode of the first reset transistor and the reset power supply signal line, and the names of the above three connection portions can be interchanged.

[0184] Another embodiment of the present disclosure provides a display device, which includes any of the above-mentioned display substrates.

[0185] For example, the display device provided in the embodiment of the present disclosure may be an organic light emitting diode display device.

[0186] For example, in the display device provided by the embodiment of the present disclosure, in the first color sub-pixel pair, for example, the green sub-pixel pair includes two first color sub-pixels, the ratio of the overlapping area between the second electrodes of the two light-emitting elements and the corresponding two first connection portions is 0.8 to 1.2, for example, 0.9 to 1.1. This can reduce the load difference of the gate nodes of the driving transistors in the two first color sub-pixels, thereby reducing the brightness difference of the two first color sub-pixels to improve the display characteristics of the display substrate.

[0187] For example, in the display device provided by the embodiment of the present disclosure, by setting an auxiliary electrode covering one of the two gates of the threshold compensation transistor in a first color sub-pixel pair, such as a green sub-pixel in a green sub-pixel pair, external light can be prevented from directly irradiating the channel region of the threshold compensation transistor, and the characteristic shift of the threshold compensation transistor caused by the illumination during display of the display substrate can be avoided, thereby preventing the writing of the gate potential of the driving transistor from being affected.

[0188] For example, in the display device provided by the embodiment of the present disclosure, the distance between the second connection portion of the second color sub-pixel, such as the red sub-pixel, and the adjacent data line and power signal line is set to be approximately equal, so that the height difference between the middle area of ​​the second electrode of the second color sub-pixel (the area that does not overlap with the data line and the power signal line) and the two side areas (the area that overlaps with the data line and the power signal line) can be reduced, thereby improving the flatness of the second electrode of the second color sub-pixel and improving color deviation.

[0189] For example, in the display device provided by the embodiment of the present disclosure, the effective light-emitting area and the second electrode of the third color sub-pixel, such as the blue sub-pixel, overlap with the first connecting portion. By setting a second pad at the edge of the effective light-emitting area away from the first connecting portion, the height difference of the middle area of ​​the second electrode of the third color sub-pixel in the extension direction of the scanning signal line and the extension direction of the data line can be reduced, which is beneficial to improving the color deviation of the third color sub-pixel.

[0190] For example, in the display device provided by the embodiment of the present disclosure, the position of the via (for example, at least one of the first via and the second via) located in the flat layer is adjusted according to the position of the effective light-emitting area of ​​the second color sub-pixel and the third color sub-pixel. For example, the connection line between the first via and the second via corresponding to the second color sub-pixel and the third color sub-pixel respectively is not parallel to the extension direction of the scanning signal line, which can ensure the flatness of the second electrode of the second color sub-pixel and the third color sub-pixel, thereby ensuring the consistency of the light-emitting intensity of the effective light-emitting area in all directions and effectively improving color deviation.

[0191] There are a few points to note:

[0192] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to conventional designs.

[0193] (2) In the absence of conflict, features in the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0194] The foregoing description is merely an exemplary embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. The scope of protection of the present disclosure is determined by the appended claims.

Claims

1. A display substrate, comprising: substrate; A plurality of sub-pixels are located on the base substrate, each of the sub-pixels including a light-emitting element and a pixel circuit, the light-emitting element including a first electrode, a light-emitting layer, and a second electrode stacked in sequence, the second electrode being located between the light-emitting layer and the base substrate, the pixel circuit including a first connecting portion, a driving transistor, and a threshold compensation transistor located between the second electrode and the base substrate, the first connecting portion extending along a first direction, a first electrode of the threshold compensation transistor being electrically connected to a first electrode of the driving transistor, and a second electrode of the threshold compensation transistor being electrically connected to a gate of the driving transistor via the first connecting portion. The plurality of sub-pixels include at least one first-color sub-pixel pair and a plurality of sub-pixels of other colors, each of the first-color sub-pixel pairs includes a first pixel block and a second pixel block arranged along a second direction, a minimum distance between the first pixel block and the second pixel block in each of the first-color sub-pixel pairs is no greater than a minimum distance between two sub-pixels of the same color in the plurality of sub-pixels of other colors, and an angle between the second direction and the first direction is in a range of 80° to 100°; The first pixel block includes a first effective light-emitting area, and the second pixel block includes a second effective light-emitting area. In the first pixel block, a minimum distance between an orthographic projection of the first connecting portion on a straight line extending along the second direction and an orthographic projection of the first effective light-emitting area on the straight line is a first distance, or the orthographic projection of the first connecting portion on the straight line extending along the second direction overlaps with the orthographic projection of the first effective light-emitting area on the straight line. In the second pixel block, a minimum distance between an orthographic projection of the first connecting portion on the straight line and an orthographic projection of the second effective light-emitting area on the straight line is a second distance, and the first distance is smaller than the second distance. In the first pixel block, the overlapping area of ​​the orthographic projection of the second electrode on the base substrate and the orthographic projection of the first connecting portion on the base substrate is a first overlapping area; in the second pixel block, the overlapping area of ​​the orthographic projection of the second electrode on the base substrate and the orthographic projection of the first connecting portion on the base substrate is a second overlapping area, and the ratio of the first overlapping area to the second overlapping area is 0.8~1.

2.

2. The display substrate according to claim 1, wherein In the first pixel block, the second electrode covers 60% to 90% of the area of ​​the first connecting portion; in the second pixel block, the second electrode covers 60% to 90% of the area of ​​the first connecting portion.

3. The display substrate according to claim 1, further comprising: a data line, provided in the same layer as the first connecting portion and extending along the first direction; The plurality of sub-pixels further include at least one second color sub-pixel, and the effective light-emitting area of ​​each second color sub-pixel is in the shape of a long strip extending along the second direction.

4. The display substrate according to claim 3, wherein: In the first pixel block, the gate of the threshold compensation transistor is located on a side of the first connection portion away from the first effective light-emitting area; in the second pixel block, the gate of the threshold compensation transistor is located on a side of the first connection portion close to the second effective light-emitting area.

5. The display substrate according to claim 3, wherein: The second electrode of each sub-pixel includes a main electrode and a connecting electrode. In the first pixel block, the shape of the main electrode is substantially the same as the shape of the first effective light-emitting area, the orthographic projection of the first effective light-emitting area on the base substrate is located within the orthographic projection of the main electrode on the base substrate, and the first effective light-emitting area overlaps with the first connecting portion; in the second pixel block, the shape of the main electrode is substantially the same as the shape of the second effective light-emitting area, the orthographic projection of the second effective light-emitting area on the base substrate is located within the orthographic projection of the main electrode on the base substrate, and the second effective light-emitting area does not overlap with the first connecting portion. The display substrate according to claim 5 , wherein: In the first color sub-pixel pair, the second electrode further includes an auxiliary electrode connecting the main electrode and the connecting electrode, and the connecting electrode extends along the first direction. In the first pixel block, the auxiliary electrode is located on a side of the main electrode away from the second effective light-emitting area. In the second pixel block, the auxiliary electrode is located on a side of the main electrode away from the first effective light-emitting area.

7. The display substrate according to claim 6, wherein: In the second pixel block, a straight line including a first edge of an edge of a portion of the connecting electrode close to the auxiliary electrode extending along the first direction and away from the second effective light-emitting area overlaps with the first connecting portion, and a second edge of the auxiliary electrode away from the second effective light-emitting area is located on a side of the first connecting portion away from the second effective light-emitting area so that the auxiliary electrode covers the first connecting portion.

8. The display substrate according to claim 7, wherein: The second edge extends along the first direction, and the straight line where the second edge is located is located on a side of the straight line where the first edge is located away from the second effective light-emitting area.

9. The display substrate according to claim 7, wherein: In the first pixel block, a straight line including a third edge of the edge of the connecting electrode close to the auxiliary electrode extending along the first direction and away from the first effective light emitting area is located on a side of the first connecting portion away from the first effective light emitting area.

10. The display substrate according to claim 9, wherein: In the second pixel block, an edge of a portion of the auxiliary electrode close to the connecting electrode and away from the second effective light-emitting area is not aligned with the first edge of the connecting electrode; In the first pixel block, a fourth edge of a portion of the auxiliary electrode close to the connecting electrode and away from the first effective light emitting area is on the same straight line as the third edge of the connecting electrode.

11. The display substrate according to claim 9, wherein: The pixel circuit of each sub-pixel further includes a first light emission control transistor and a second connection portion provided in the same layer as the first connection portion, wherein a first electrode of the first light emission control transistor is electrically connected to a first electrode of the driving transistor, and a second electrode of the first light emission control transistor is electrically connected to the connection electrode via the second connection portion. In the first pixel block, the second connection portion is farther away from the first effective light-emitting area than the first connection portion in the second direction; in the second pixel block, the second connection portion is closer to the second effective light-emitting area than the first connection portion in the second direction.

12. The display substrate according to claim 11, further comprising: The flat layer is located between the film layer where the second connecting portion is located and the film layer where the connecting electrode is located, The planar layer includes a plurality of via holes passing therethrough, and the connection electrode in each of the sub-pixels is electrically connected to the second connection portion through the via holes. The via hole corresponding to the first pixel block is farther away from the first effective light-emitting area than the first connection portion of the first pixel block in the second direction; the via hole corresponding to the second pixel block is closer to the second effective light-emitting area than the first connection portion of the second pixel block in the second direction.

13. The display substrate according to claim 12, wherein: In the pixel circuit of each sub-pixel, the threshold compensation transistor includes a first gate and a second gate. In the first pixel block, the first gate is located on the side of the second gate close to the first effective light-emitting area, the straight line where the third edge of the connecting electrode is located overlaps with the first gate, and the part of the auxiliary electrode away from the connecting electrode in the second direction is away from the edge of the first effective light-emitting area and is located on the side of the first gate away from the first effective light-emitting area so that the auxiliary electrode covers at least part of the first gate.

14. The display substrate according to claim 13, wherein: In the first pixel block, the auxiliary electrode includes a first portion and a second portion connected to each other, the first portion is connected to the connecting electrode, the second portion covers at least a portion of the first gate, the edge of the first portion extending along the first direction and the third edge are located on the same straight line, and the edge of the second portion extending along the first direction is farther away from the first effective light-emitting area in the second direction than the edge of the first portion extending along the first direction.

15. The display substrate according to claim 14, wherein: The second portion is located on a side of the second gate away from the connecting electrode in the first direction.

16. The display substrate according to claim 13, wherein: In the first pixel block, the auxiliary electrode covers a portion of the active layer between the first gate and the second gate.

17. The display substrate according to claim 12, wherein: The plurality of sub-pixels further include at least one third-color sub-pixel, wherein the effective light-emitting area of ​​the third-color sub-pixel is in the shape of a strip extending along the second direction, and the second electrode of the third-color sub-pixel further includes an auxiliary electrode located on a side of the main electrode away from the connecting electrode and connected to the main electrode. In the third color sub-pixel, the threshold compensation transistor includes a first gate and a second gate, the second gate is located on the side of the first gate close to the effective light-emitting area of ​​the third color sub-pixel in the first direction, and the auxiliary electrode covers part of the active layer of the second gate and the first gate.

18. The display substrate according to claim 17, wherein: The first color sub-pixel pair is a green sub-pixel pair, the second color sub-pixel is a red sub-pixel, and the third color sub-pixel is a blue sub-pixel.

19. The display substrate according to claim 17, wherein: The first effective light-emitting area and the second effective light-emitting area may have a pentagonal, circular, or teardrop shape, and the effective light-emitting areas of the second color sub-pixel and the third color sub-pixel may have a hexagonal or elliptical shape.

20. The display substrate according to claim 17, further comprising: Power signal lines extending along the first direction, the power signal lines and the data lines being arranged in the same layer and alternately; a scanning signal line extending along the second direction and located on a side of the film layer where the data line is located facing the base substrate; a reset power signal line extending along the second direction and located between the film layer where the scan signal line is located and the film layer where the data line is located; a reset control signal line extending along the second direction and arranged in the same layer as the scan signal line; as well as The light emitting control signal line extends along the second direction and is provided in the same layer as the scanning signal line. The pixel circuit of each sub-pixel further includes a data writing transistor, a storage capacitor, a second light emitting control transistor, a first reset transistor and a second reset transistor. The first electrode of the data writing transistor is electrically connected to the second electrode of the driving transistor, the second electrode of the data writing transistor is electrically connected to the data line, and the gate of the data writing transistor is electrically connected to the scanning signal line; A first electrode of the storage capacitor is electrically connected to the power signal line, and a second electrode of the storage capacitor is electrically connected to the gate of the driving transistor; The gate of the threshold compensation transistor is electrically connected to the scan signal line to receive a compensation control signal; A first electrode of the first reset transistor is electrically connected to the reset power signal line, a second electrode of the first reset transistor is electrically connected to the gate of the drive transistor, and the gate of the first reset transistor is electrically connected to the reset control signal line; A first electrode of the second reset transistor is electrically connected to the reset power signal line, a second electrode of the second reset transistor is electrically connected to the second electrode of the light emitting element, and a gate of the second reset transistor is electrically connected to the reset control signal line; A first electrode of the second light emitting control transistor is electrically connected to the power signal line, a second electrode of the second light emitting control transistor is electrically connected to the second electrode of the driving transistor, and a gate of the second light emitting control transistor is electrically connected to the light emitting control signal line; A gate of the first light emission control transistor is electrically connected to the light emission control signal line.

21. The display substrate according to claim 20, wherein: The data line includes a first data line, and the power signal line includes a first power signal line. Along the direction perpendicular to the base substrate, the second electrode of each second color sub-pixel overlaps with the first data line, the first power signal line and the second connection portion, and in the portion where the first data line, the first power signal line and the second connection portion overlap with the second electrode, the first power signal line and the first data line are located on both sides of the second connection portion, and the second connection portion includes a first sub-connection portion connected to each other and a first pad located on a side of the first sub-connection portion close to the first power signal line, the first sub-connection portion and the first pad both overlap with the second electrode, along the first direction, the size of the first sub-connection portion is larger than the size of the first pad, and the ratio of the minimum distance between the edges of the first sub-connection portion and the first data line close to each other to the minimum distance between the edges of the first pad and the first power signal line close to each other is 0.8~1.

2.

22. The display substrate according to claim 21, wherein A straight line passing through a midpoint of a line connecting two opposite end points of the effective light-emitting area of ​​the second color sub-pixel in the second direction and extending along the first direction overlaps the second connecting portion.

23. The display substrate according to claim 21, wherein The data line also includes a second data line, and the first data line and the second data line are alternately arranged. The power signal line also includes a second power signal line, and the second power signal line and the first power signal line are alternately arranged. Along the direction perpendicular to the base substrate, the second electrode of each second-color sub-pixel overlaps with the first data line, the first power signal line, the second connecting portion, the second data line and the second power signal line, and in the overlapping portion, the second power signal line is located on the side of the first data line away from the second connecting portion, and the second data line is located on the side of the first power signal line away from the second connecting portion.

24. The display substrate according to claim 21, wherein The shape of the first sub-connection portion is a rectangle extending along the first direction, and a straight line passing through the center of the effective light-emitting area of ​​the second color sub-pixel and extending along the first direction is located on the side of the straight line passing through the center of the first sub-connection portion and extending along the first direction close to the first pad.

25. The display substrate according to claim 24, wherein: The pixel circuit also includes a third connection portion arranged in the same layer as the data line, the third connection portion extends along the first direction, the first electrode of the first reset transistor is electrically connected to the reset power signal line through the third connection portion, and along the direction perpendicular to the base substrate, the effective light-emitting area of ​​the second color sub-pixel overlaps with the third connection portion, and a straight line passing through the center of the effective light-emitting area of ​​the second color sub-pixel and extending along the first direction overlaps with the third connection portion, the second connection portion is located on one side of the straight line passing through the center of the effective light-emitting area of ​​the second color sub-pixel and extending along the second direction, and at least a portion of the third connection portion is located on the other side of the straight line.

26. The display substrate according to claim 20, further comprising: The interlayer insulating layer is located between the film layer where the data line is located and the base substrate. Among them, in the third color sub-pixel, the connecting electrode is connected to the second connecting part through a first via hole penetrating the flat layer, and the second connecting part is electrically connected to the pixel circuit through a first connecting hole penetrating the interlayer insulating layer. Along the direction perpendicular to the base substrate, the first via hole and the first connecting hole do not overlap with the main electrode, and the first via hole and the first connecting hole have overlapping direct projections on the first straight line extending along the first direction.

27. The display substrate according to claim 26, wherein: In the second color sub-pixel, the connecting electrode is connected to the second connecting portion through a second via hole penetrating the flat layer, the first via hole is located on a side of the effective light-emitting area of ​​the third color sub-pixel close to the effective light-emitting area of ​​the second color sub-pixel in the first direction, the second via hole is located on a side of the effective light-emitting area of ​​the second color sub-pixel close to the effective light-emitting area of ​​the third color sub-pixel in the first direction, and the first connecting line connecting the first via hole and the second via hole is not parallel to the second direction, and the second electrode of the second color sub-pixel and the second electrode of the third color sub-pixel do not overlap in the second direction.

28. The display substrate according to claim 27, wherein: In the second color sub-pixel, the second connection portion is electrically connected to the pixel circuit through a second connection hole penetrating the interlayer insulating layer, and a second connection line connecting the first connection hole and the second connection hole is parallel to the second direction.

29. The display substrate according to claim 27, wherein: The effective light-emitting area of ​​the second color sub-pixel includes a first long side and a second long side extending along the second direction, the second long side is located on the side of the first long side away from the second via hole, and the extension line of the first long side overlaps with the first via hole in the direction perpendicular to the base substrate; the effective light-emitting area of ​​the third color sub-pixel includes a third long side and a fourth long side extending along the second direction, the fourth long side is located on the side of the third long side away from the first via hole, and the extension line of the third long side overlaps with the second via hole in the direction perpendicular to the base substrate.

30. The display substrate according to claim 28, wherein In the first pixel block, the second connection portion is electrically connected to the pixel circuit through a third connection hole passing through the interlayer insulating layer; in the second pixel block, the second connection portion is electrically connected to the pixel circuit through a fourth connection hole passing through the interlayer insulating layer, and the line connecting the third connection hole and the fourth connection hole basically coincides with the second line.

31. A display device comprising the display substrate according to any one of claims 1 to 30.

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