Array substrate and display device

Abstract

An array substrate is provided. The array substrate includes a plurality of first type data lines and a plurality of second type data lines. Each of the plurality of first type data lines passes through sub-pixel openings of a plurality of sub-pixels of a first color and does not pass through sub-pixel openings of any sub-pixel of a second color or any sub-pixel of a third color, the first color, the second color, and the third color being three different colors. Each of the plurality of second type data lines does not pass through any sub-pixel opening. A respective sub-pixel opening of a sub-pixel of the first color includes a first area and a second area. A ratio of a first area of the first area to a second area of the second area is in a range of 2:8 to 8:2.

Description

TECHNICAL FIELD

[0001] The present application relates to display technology, and in particular, to an array substrate and a display device. BACKGROUND

[0002] Organic light emitting diode (OLED) displays are one of the hotspots in the field of flat panel display research today. Unlike thin film transistor liquid crystal displays (TFT-LCDs) that use a stable voltage to control brightness, OLEDs are driven by a driving current that needs to be kept constant to control luminance. An OLED display panel includes a plurality of pixel units configured with pixel driving circuits arranged in a plurality of rows and a plurality of columns. Each pixel driving circuit includes a driving transistor having a gate terminal connected to one gate line per row and a drain terminal connected to one data line per column. When the row in which the pixel unit is selected is turned on, a switching transistor connected to the driving transistor is turned on, and a data voltage is applied from the data line to the driving transistor via the switching transistor, so that the driving transistor outputs a current corresponding to the data voltage to the OLED device. The OLED device is driven to emit light of a corresponding brightness. SUMMARY

[0003] In one aspect, the present disclosure provides an array substrate including a plurality of first type data lines and a plurality of second type data lines; wherein each of the plurality of first type data lines passes through sub-pixel openings of a plurality of sub-pixels of a first color and does not pass through sub-pixel openings of any sub-pixel of a second color nor any sub-pixel of a third color, the first color, the second color, and the third color being three different colors; each of the plurality of second type data lines does not pass through any sub-pixel opening; a first plane containing a normal projection of a respective one of the plurality of first type data lines on a second plane divides a respective sub-pixel opening of a sub-pixel of the first color into a first area and a second area, the first plane being orthogonal to the second plane, the second plane containing a surface of a pixel defining layer; and a ratio of a first area of the first area to a second area of the second area is in a range of 2:8 to 8:2.

[0004] Optionally, a ratio of a total number of the plurality of first type data lines to a total number of the plurality of second type data lines is in a range of 0.2 to 4.

[0005] Optionally, the array substrate further includes a first anode of a first light emitting element, the first anode including a main body portion and a protruding portion protruding from one side of the main body portion along a first direction; and a normal projection of the protruding portion on a base substrate at least partially overlaps a normal projection of a semiconductor material portion of a third transistor on the base substrate, the semiconductor material portion extending along the first direction.

[0006] Optionally, a projection of the protrusion onto the base substrate at least partially overlaps with a projection of the gate of the third transistor onto the base substrate.

[0007] Optionally, the array substrate further comprises a second anode of a second light emitting element, the second anode comprising a main body portion and a protrusion protruding from one side of the main body portion along a second direction; and a projection of the protrusion onto a base substrate at least partially overlaps with a projection of a semiconductor material portion of the third transistor onto the base substrate, the semiconductor material portion extending along the first direction.

[0008] Optionally, the array substrate further comprises a third anode of a third light emitting element, the third anode comprising a main body portion, a first protrusion and a second protrusion protruding from two sides of the main body portion along a first direction respectively; the first protrusion and the second protrusion are located on a same side of a gate line controlling the third transistor; a ratio of a first dimension of the first protrusion along the second direction to a second dimension of the second protrusion along the second direction is in a range of 0.1 to 8.0; and a ratio of a first area of the first protrusion to a second area of the second protrusion is in a range of 0.1 to 8.0.

[0009] Optionally, a ratio of the first area of the first protrusion to a main body area of the main body portion is in a range of 0.01 to 0.1; a ratio of the second area of the second protrusion to the main body area of the main body portion is in a range of 0.02 to 0.2; and the second area of the second protrusion is greater than the first area of the first protrusion.

[0010] Optionally, a projection of the first protrusion onto a base substrate at least partially overlaps with a projection of a first semiconductor material portion of the third transistor in a first adjacent sub-pixel onto the base substrate, the first semiconductor material portion extending along the first direction; and a projection of the first protrusion onto the base substrate at least partially overlaps with a projection of a second semiconductor material portion of the third transistor in a second adjacent sub-pixel onto the base substrate, the second semiconductor material portion extending along the first direction, the first adjacent sub-pixel and the second adjacent sub-pixel directly adjacent to each other.

[0011] Optionally, a shortest distance between the sub-pixel opening and an edge of the anode other than an edge of the anode connected to the anode contact pad is different; wherein the light emitting layer is connected to the anode through the sub-pixel opening extending through the pixel defining layer.

[0012] Optionally, the array substrate comprises: a first transistor in a pixel driving circuit of a current stage; a sixth transistor in a second pixel driving circuit in a previous stage, wherein the first transistor and the sixth transistor are commonly controlled by a same reset control signal line; a plurality of first reset signal lines; and an initialization connection line connecting a source of the first transistor and a corresponding one of the plurality of first reset signal lines, the corresponding one of the plurality of first reset signal lines being configured to provide a reset signal to the source of the first transistor through the initialization connection line; wherein the initialization connection line is located on a same side of an active layer or a gate of the first transistor and an active layer or a gate of the sixth transistor along a first direction.

[0013] Optionally, the array substrate further comprises: a first planarization layer; a first data line and a balance block on the first planarization layer, wherein the balance block is electrically connected to a corresponding one of a plurality of voltage supply lines through a via hole extending through the first planarization layer; a second planarization layer on a side of the first data line and the balance block away from the first planarization layer; a first anode of a first light emitting element on a side of the second planarization layer away from the first planarization layer; and a pixel definition layer on a side of the first anode away from the second planarization layer and defining a corresponding first sub-pixel opening; wherein a footprint of the first anode on a base substrate at least partially overlaps with a footprint of the balance block on the base substrate and at least partially overlaps with a footprint of the first data line on the base substrate.

[0014] Optionally, along the first direction, the footprints of the first data line and the balance block on the base substrate are respectively located on opposite sides of a footprint of the corresponding first sub-pixel opening on the base substrate; and the footprint of the corresponding first sub-pixel opening on the base substrate does not overlap with the footprint of the first data line on the base substrate and does not overlap with the footprint of the balance block on the base substrate.

[0015] Optionally, the first anode comprises a main body portion and a protruding portion protruding from a side of the main body portion along a first direction; a footprint of the protruding portion on a base substrate at least partially overlaps with a footprint of a semiconductor material portion of a third transistor on the base substrate, the semiconductor material portion extending along the first direction; a footprint of the main body portion on the base substrate at least partially overlaps with a footprint of the first data line on the base substrate and at least partially overlaps with a footprint of the balance block on the base substrate; and a footprint of the protruding portion on the base substrate at least partially overlaps with a footprint of the balance block on the base substrate.

[0016] Optionally, the array substrate comprises: a base substrate; a plurality of data lines; a plurality of light emitting elements in a plurality of sub-pixels, respectively; and a pixel defining layer on the base substrate, the pixel defining layer defining a plurality of sub-pixel openings; wherein the plurality of light emitting elements comprises a first light emitting element in each first sub-pixel, a second light emitting element in each second sub-pixel, a third light emitting element in each third sub-pixel, and a fourth light emitting element in each fourth sub-pixel; the plurality of sub-pixel openings comprises each first sub-pixel opening, each second sub-pixel opening, each third sub-pixel opening, and each fourth sub-pixel opening extending through the pixel defining layer, respectively; a first light emitting layer of the first light emitting element is connected to a first anode of the first light emitting element through the corresponding first sub-pixel opening; a second light emitting layer of the second light emitting element is connected to a second anode of the second light emitting element through the corresponding second sub-pixel opening; a third light emitting layer of the third light emitting element is connected to a third anode of the third light emitting element through the corresponding third sub-pixel opening; a fourth light emitting layer of the fourth light emitting element is connected to a fourth anode of the fourth light emitting element through the corresponding fourth sub-pixel opening; each of the each first sub-pixel opening, the each second sub-pixel opening, and the each fourth sub-pixel opening is not crossed by any data line; and one data line of the plurality of data lines crosses the corresponding third sub-pixel opening.

[0017] Optionally, the plurality of sub-pixel openings comprises a plurality of minimum repeating units, each minimum repeating unit of the plurality of minimum repeating units comprises a corresponding first sub-pixel opening, a corresponding second sub-pixel opening, a corresponding third sub-pixel opening, and a corresponding fourth sub-pixel opening; the plurality of data lines comprises a plurality of data line repeating groups, each group of the plurality of data line repeating groups comprises a first data line, a second data line, a third data line, and a fourth data line arranged continuously, and is configured to provide data signals to the corresponding first sub-pixel, the corresponding second sub-pixel, the corresponding third sub-pixel, and the corresponding fourth sub-pixel, respectively; and the fourth data line crosses the corresponding third sub-pixel opening.

[0018] Optionally, the corresponding first sub-pixel opening, the corresponding second sub-pixel opening, the corresponding third sub-pixel opening, and the corresponding fourth sub-pixel opening in each minimum repeating unit of the plurality of minimum repeating units are arranged continuously along a row; the first data line, the second data line, the third data line, and the fourth data line are arranged continuously along the row; the corresponding first sub-pixel opening is between the first data line and the second data line; the corresponding second sub-pixel opening is between the second data line and the third data line; the fourth data line crosses the corresponding third sub-pixel opening; and the corresponding fourth sub-pixel opening is located on a side of the fourth data line away from the third data line.

[0019] Optionally, the respective first sub-pixel opening, the respective second sub-pixel opening, the respective third sub-pixel opening and the respective fourth sub-pixel opening are located in a first minimum repeating unit in a first row of two closest adjacent rows; a second minimum repeating unit in a second row of the two closest adjacent rows has a displacement of twice an inter-data-line distance relative to the first minimum repeating unit along a first direction, the inter-data-line distance being a shortest distance between two closest data lines along the first direction; the second minimum repeating unit in the second row comprises a second respective first sub-pixel opening, a second respective second sub-pixel opening, a second respective third sub-pixel opening and a second respective fourth sub-pixel opening arranged consecutively along the row; and the second data line passes through the second respective second sub-pixel opening in the second row.

[0020] Optionally, a first plane containing a projection of the fourth data line on a second plane divides the respective third sub-pixel opening into a first area and a second area, the first plane being perpendicular to the second plane, the second plane containing a surface of the pixel defining layer; and a ratio of a first area of the first area to a second area of the second area is in a range from 2:8 to 8:2.

[0021] Optionally, a ratio of a first area of the first area to a second area of the second area is in a range from 1:1.5 to 1.5:1; and the respective third sub-pixel opening is substantially mirror-symmetrical with respect to a plane perpendicular to the pixel defining layer and intersecting a projection of the fourth data line on the pixel defining layer.

[0022] Optionally, the fourth data line passes through the third anode; a projection of the fourth data line on the third anode divides the third anode into a first anode area and a second anode area; and a ratio of a first area of the first anode area to a second area of the second anode area is in a range from 2:8 to 8:2.

[0023] Optionally, an area of a projection of any data line on the second anode is smaller than an area of a projection of any data line on the first anode, and smaller than an area of a projection of any data line on the third anode; and an area of a projection of any data line on the fourth anode is smaller than an area of a projection of any data line on the first anode, and smaller than an area of a projection of any data line on the third anode.

[0024] Optionally, an edge of the second anode is at least partially covered by a projection of a data line adjacent to the edge of the second anode on the second anode; and an edge of the fourth anode is at least partially covered by a projection of a data line adjacent to the edge of the fourth anode on the fourth anode.

[0025] Optionally, an edge of the first anode is at least partially covered by a positive projection of a data line on the first anode adjacent to the edge of the first anode.

[0026] Optionally, a minimum repeating unit of the plurality of sub-pixels of the array substrate comprises a respective first sub-pixel, a respective second sub-pixel, a respective third sub-pixel, and a respective fourth sub-pixel; the respective second sub-pixel and the respective fourth sub-pixel are sub-pixels of a same color, which is different from a color of the respective first sub-pixel and different from a color of the respective third sub-pixel; the second light-emitting element and the fourth light-emitting element are light-emitting elements of a same color, which is different from a color of the first light-emitting element and different from a color of the third light-emitting element; the first anode, the second anode, and the third anode have different areas and different shapes; and the first anode, the third anode, and the fourth anode have different areas and different shapes.

[0027] Optionally, the second anode and the fourth anode are anodes of two light-emitting elements of a same color; the second anode comprises a first main portion, a first extra portion, and a second extra portion; the fourth anode comprises a second main portion and a third extra portion; the first main portion is a combination of a rectangular portion and a triangular portion; the second main portion is a combination of a rectangular portion and a triangular portion; the first main portion and the second main portion have substantially the same shape; the first extra portion is adjacent to the triangular portion of the first main portion; the second extra portion is adjacent to a side of the rectangular portion of the first main portion away from the triangular portion of the first main portion; the third extra portion is adjacent to the triangular portion of the second main portion; the first extra portion, the first main portion, and the second extra portion are sequentially arranged along a direction substantially parallel to the plurality of data lines; and the second main portion and the third extra portion are sequentially arranged along a direction substantially parallel to the plurality of data lines.

[0028] Optionally, the array substrate further comprises a first anode of a first light-emitting element, the first anode comprises a main portion and a protruding portion protruding from a side of the main portion along a first direction; and a positive projection of the protruding portion on the base substrate at least partially overlaps with a positive projection of a semiconductor material portion of a third transistor on the base substrate, the semiconductor material portion extends along the first direction.

[0029] Optionally, the array substrate further comprises a second anode of a second light emitting element, the second anode comprising a main portion and a protruding portion protruding from a side of the main portion away from a portion of the second anode connected to an anode contact pad along a second direction; and a footprint of the protruding portion on the base substrate at least partially overlaps with a footprint of a semiconductor material portion of a third transistor on the base substrate, the semiconductor material portion extending along the first direction.

[0030] Optionally, the array substrate further comprises a third anode of a third light emitting element, the third anode comprising a main portion, a first protruding portion and a second protruding portion protruding from two sides of the main portion along a first direction, respectively; a footprint of the first protruding portion and the second protruding portion on a plane substantially overlaps with each other, the plane being parallel to a second direction and intersecting the anode; a ratio of a first dimension of the first protruding portion along the second direction to a second dimension of the second protruding portion along the second direction is in a range from 0.1 to 8.0; and a ratio of a first area of the first protruding portion to a second area of the second protruding portion is in a range from 0.1 to 8.0.

[0031] Optionally, a footprint of the first protruding portion on the base substrate at least partially overlaps with a footprint of a first semiconductor material portion of a third transistor in a first adjacent sub-pixel on the base substrate, the first semiconductor material portion extending along the first direction; and a footprint of the first protruding portion on the base substrate at least partially overlaps with a footprint of a second semiconductor material portion of the third transistor in a second adjacent sub-pixel on the base substrate, the second semiconductor material portion extending along the first direction, the first adjacent sub-pixel and the second adjacent sub-pixel being directly adjacent to each other.

[0032] Optionally, the array substrate further comprises: a plurality of pixel driving circuits respectively in the plurality of sub-pixels and configured to respectively drive the plurality of light emitting elements, wherein each pixel driving circuit of the plurality of pixel driving circuits comprises a plurality of transistors and a storage capacitor, the storage capacitor comprises a first capacitor electrode, a second capacitor electrode electrically connected to a corresponding voltage supply line, and an insulating layer between the first capacitor electrode and the second capacitor electrode; a semiconductor material layer on the base substrate; and a node connection line in the same layer as the corresponding voltage supply line, the node connection line being connected to the first capacitor electrode through a first main via hole and connected to the semiconductor material layer through a second main via hole; wherein a first anode of the first light emitting element in a corresponding first sub-pixel has an orthographic projection on the base substrate that at least partially overlaps with an orthographic projection of the node connection line on the base substrate in the corresponding first sub-pixel; a second anode of the second light emitting element in a corresponding second sub-pixel has an orthographic projection on the base substrate that at least partially overlaps with an orthographic projection of the node connection line on the base substrate in the corresponding second sub-pixel; and a third anode of the third light emitting element in a corresponding third sub-pixel has an orthographic projection on the base substrate that at least partially overlaps with an orthographic projection of the node connection line on the base substrate in the corresponding third sub-pixel, and at least partially overlaps with an orthographic projection of the node connection line on the base substrate in the corresponding fourth sub-pixel.

[0033] Optionally, the orthographic projection of the first anode on the base substrate in the corresponding first sub-pixel covers the orthographic projection on the base substrate of a portion of the node connection line in the corresponding first sub-pixel at a position connected to the first capacitor electrode; the orthographic projection of the second anode on the base substrate in the corresponding second sub-pixel covers the orthographic projection on the base substrate of a portion of the node connection line in the corresponding second sub-pixel at a position connected to the first capacitor electrode; and the orthographic projection of the third anode on the base substrate in the corresponding third sub-pixel covers the orthographic projection on the base substrate of a portion of the node connection line in the corresponding fourth sub-pixel at a position connected to the first capacitor electrode, and partially overlaps with the orthographic projection on the base substrate of a portion of the node connection line in the corresponding third sub-pixel at a position connected to the first capacitor electrode.

[0034] Optionally, the orthographic projection of the third anode on the base substrate at least partially overlaps with the orthographic projection on the base substrate of a third transistor in the corresponding third sub-pixel, and at least partially overlaps with the orthographic projection on the base substrate of a third transistor in the corresponding fourth sub-pixel, the corresponding fourth sub-pixel being adjacent to the corresponding third sub-pixel.

[0035] Optionally, a positive projection of the third anode on the base substrate at least partially overlaps a positive projection of an active layer of the third transistor in the respective third sub-pixel on the base substrate, at least partially overlaps a positive projection of a source of the third transistor in the respective fourth sub-pixel on the base substrate, and at least partially overlaps a positive projection of an active layer of the third transistor in the respective fourth sub-pixel on the base substrate.

[0036] Optionally, a positive projection of the first anode on the base substrate at least partially overlaps a positive projection of a third transistor in the respective first sub-pixel on the base substrate.

[0037] Optionally, a positive projection of the first anode on the base substrate covers a positive projection of a source of the third transistor in the respective first sub-pixel on the base substrate partially overlaps, and at least partially overlaps a positive projection of an active layer of the third transistor in the respective first sub-pixel on the base substrate.

[0038] Optionally, a positive projection of the second anode on the base substrate at least partially overlaps a positive projection of a third transistor in the respective second sub-pixel on the base substrate.

[0039] Optionally, a positive projection of the second anode on the base substrate partially overlaps a positive projection of an active layer of the third transistor in the respective second sub-pixel on the base substrate.

[0040] Optionally, the array substrate further comprises: a semiconductor material layer on the base substrate; a gate insulating layer on a side of the semiconductor material layer distal from the base substrate; an insulating layer on a side of the gate insulating layer distal from the base substrate; an interlayer dielectric layer on a side of the insulating layer distal from the gate insulating layer; a relay electrode layer on a side of the interlayer dielectric layer distal from the insulating layer; a first planarization layer on a side of the relay electrode layer distal from the interlayer dielectric layer; an anode contact pad layer on a side of the first planarization layer distal from the interlayer dielectric layer; and a second planarization layer on a side of the anode contact pad layer distal from the first planarization layer; wherein the pixel defining layer is on a side of the second planarization layer distal from the base substrate; wherein each anode is on a side of the second planarization layer distal from the first planarization layer; and each light emitting layer is on a side of each anode distal from the second planarization layer; wherein in the respective first sub-pixel, the first anode is connected to a first anode contact pad through a first via extending through the second planarization layer; in the respective second sub-pixel, the second anode is connected to a second anode contact pad through a second via extending through the second planarization layer; in the respective third sub-pixel, the third anode is connected to a third anode contact pad through a third via extending through the second planarization layer; and in the respective fourth sub-pixel, the fourth anode is connected to a fourth anode contact pad through a fourth via extending through the second planarization layer.

[0041] Optionally, the array substrate further comprises a plurality of voltage supply lines extending along the second direction respectively; wherein each of the plurality of voltage supply lines comprises a first inclined portion, a second inclined portion, a first parallel portion connecting the first inclined portion and the second inclined portion, a second parallel portion connected to the first parallel portion through the second inclined portion; the first parallel portion and the second parallel portion extend along a direction substantially parallel to the second direction respectively; the first inclined portion extends along a first inclined angle relative to the first direction; the second inclined portion extends along a second inclined angle relative to the first direction; the first inclined angle and the second inclined angle are complementary angles; the center lines of the first parallel portion and the second parallel portion along the direction substantially parallel to the second direction are spaced apart by a width greater than zero; each of the plurality of voltage supply lines comprises a repeating pattern of the first inclined portion, the first parallel portion, the second inclined portion, the second parallel portion connected sequentially; the first parallel portions in each of the plurality of voltage supply lines are arranged along a first arrangement direction substantially parallel to the second direction; the second parallel portions in each of the plurality of voltage supply lines are arranged along a second arrangement direction substantially parallel to the second direction; and the first parallel portion and the second inclined portion combine to surround one side of the connecting portion connected to a corresponding one of the plurality of data lines through a via extending through the first planarization layer and connected to the source electrode of the second transistor through a via extending through the interlayer dielectric layer, the insulating layer and the gate insulating layer.

[0042] Optionally, the array substrate further comprises a plurality of voltage supply lines each extending along the second direction; and an anti-interference block in the same layer as the second capacitor electrode, a respective one of the plurality of voltage supply lines being connected to the anti-interference block through a third main via; wherein the anti-interference block comprises a base, a first arm and a second arm; the respective one of the plurality of voltage supply lines is connected to the base through the third main via; the first arm comprises a first end portion and a first connecting bridge portion connecting the base and the first end portion; the second arm comprises a second end portion and a second connecting bridge portion connecting the base and the second end portion; the first end portion and the first connecting bridge portion are arranged along a direction substantially parallel to the second direction; the second end portion and the second connecting bridge portion are arranged along a direction substantially parallel to the second direction; a longitudinal side of the base is along a direction substantially parallel to the first direction; a lateral side of the base is along a direction substantially parallel to the second direction; the base has a substantially rectangular shape; the first end portion has a substantially rectangular shape; the second end portion has a substantially rectangular shape; the first connecting bridge portion has a pseudo-triangular shape; and the second connecting bridge portion has a triangular shape.

[0043] Optionally, each of the plurality of pixel driving circuits further comprises a driving transistor; a projection of the first anode in each first sub-pixel on the base substrate at least partially overlaps with a projection of the second capacitor electrode in each first sub-pixel on the base substrate; a projection of the second anode in each second sub-pixel on the base substrate at least partially overlaps with a projection of the second capacitor electrode in each second sub-pixel on the base substrate; a projection of the third anode in each third sub-pixel on the base substrate at least partially overlaps with a projection of the second capacitor electrode in each third sub-pixel on the base substrate; and a projection of the first anode in each first sub-pixel on the base substrate at least partially overlaps with a projection of an active layer of the driving transistor in each first sub-pixel on the base substrate; a projection of the second anode in each second sub-pixel on the base substrate at least partially overlaps with a projection of an active layer of the driving transistor in each second sub-pixel on the base substrate; a projection of the third anode in each third sub-pixel on the base substrate at least partially overlaps with a projection of an active layer of the driving transistor in each third sub-pixel on the base substrate; and a projection of the fourth anode in each fourth sub-pixel on the base substrate at least partially overlaps with a projection of an active layer of the driving transistor in each fourth sub-pixel on the base substrate.

[0044] In one aspect, the present disclosure provides a display device comprising an array substrate described herein or manufactured by a method described herein, and an integrated circuit connected to the array substrate. BRIEF DESCRIPTION OF DRAWINGS

[0045] According to various disclosed embodiments, the following drawings are merely examples for illustrative purposes and are not intended to limit the scope of the present disclosure.

[0046] FIG. 1 is a plan view of an array substrate in some embodiments according to the present disclosure.

[0047] FIG. 2A is a circuit diagram showing a structure of a pixel driving circuit in some embodiments according to the present disclosure.

[0048] FIG. 2B is a circuit diagram showing a structure of a pixel driving circuit in some embodiments according to the present disclosure.

[0049] FIG. 3A is a diagram showing a structure of a plurality of sub-pixels of an array substrate in some embodiments according to the present disclosure.

[0050] FIG. 3B is a diagram showing a sub-pixel arrangement of a plurality of sub-pixels of an array substrate in some embodiments according to the present disclosure.

[0051] FIG. 3C is a diagram showing FIG. 3A a structure of a semiconductor material layer in a plurality of sub-pixels of an array substrate shown in FIG. 1.

[0052] FIG. 3D is a diagram showing FIG. 3A a structure of a first conductive layer in a plurality of sub-pixels of an array substrate shown in FIG. 1.

[0053] FIG. 3E is a diagram showing FIG. 3A a structure of a second conductive layer in a plurality of sub-pixels of an array substrate shown in FIG. 1.

[0054] FIG. 3F is a diagram showing FIG. 3A a structure of a first signal line layer in a plurality of sub-pixels of an array substrate shown in FIG. 1.

[0055] FIG. 3G is a diagram showing FIG. 3A a structure of a second signal line layer in a plurality of sub-pixels of an array substrate shown in FIG. 1.

[0056] FIG. 3H is a diagram showing FIG. 3A a structure of an anode in a plurality of sub-pixels of an array substrate shown in FIG. 1.

[0057] FIG. 3I is a diagram illustrating FIG. 3A of the array substrate shown in

[0058] FIG. 3J is a diagram illustrating

[0059] FIG. 4A is a cross-sectional view along the line A-A' in FIG. 3A

[0060] FIG. 4B is a cross-sectional view along the line B-B' in FIG. 3A

[0061] FIG. 4C FIG. 3A is a cross-sectional view along the line C-C' in

[0062] FIG. 4D FIG. 3A is a cross-sectional view along the line D-D' in

[0063] FIG. 5A is a cross-sectional view of the array substrate.

[0064] FIG. 5B is a diagram illustrating a cross-sectional view of the array substrate.

[0065] FIG. 5C is a diagram illustrating a cross-sectional view of the array substrate.

[0066] FIG. 5D is a diagram illustrating a cross-sectional view of the array substrate.

[0067] FIG. 6 illustrates a structural difference between the second anode and the fourth anode in some embodiments of the present disclosure.

[0068] FIG. 7 illustrates a front projection of the fourth data line on the pixel defining layer in some embodiments of the present disclosure.

[0069] FIG. 8A is a diagram illustrating a structure of a plurality of sub-pixels of the array substrate in some embodiments of the present disclosure.

[0070] FIG. 8B is a diagram illustrating FIG. 8A of the array substrate shown in

[0071] FIG. 8C is a diagram illustrating FIG. 8A ​​​​A cross-sectional view along the dotted line VL in FIG. 17.

[0072] FIG. 8D A front projection of the fourth data line on the third anode is shown.

[0073] FIG. 8E is a cross-sectional view along the line E-E' in FIG. 18. FIG. 8C

[0074] FIG. 9A is a cross-sectional view along the line F-F' in FIG. 19.

[0075] FIG. 9B is a cross-sectional view along the line G-G' in FIG. 20. FIG. 9A

[0076] FIG. 9C FIG. 9A

[0077] FIG. 9D FIG. 9A

[0078] FIG. 10 A partial structure of a voltage supply line is shown.

[0079] FIG. 11 A detailed structure of an anti-interference block is shown.

[0080] FIG. 12 is a cross-sectional view along the line H-H' in FIG. 21. FIG. 3A A cross-sectional view along the dotted line VL in FIG. 17.

[0081] FIG. 13 is a cross-sectional view along the line I-I' in FIG. 22.

[0082] FIG. 14A is a cross-sectional view along the line J-J' in FIG. 23.

[0083] FIG. 14B is a cross-sectional view along the line K-K' in FIG. 24.

[0084] FIG. 14C is a cross-sectional view along the line L-L' in FIG. 25.

[0085] ​​​​​​FIG. 14D FIG. 1 is a diagram illustrating a structure of a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure.

[0086] FIG. 14E is a cross-sectional view along the line H-H’ in FIG. 14E DETAILED DESCRIPTION

[0087] The present disclosure will now be described in greater detail with reference had to the following examples. It should be noted that the following description of some embodiments presented herein is for purposes of illustration and description only. It is not intended to be exhaustive or to limit the disclosure to the precise form described.

[0088] The present disclosure provides, among other things, an array substrate and a display device that substantially overcome one or more problems due to limitations and disadvantages of the related art. In one aspect, the present disclosure provides an array substrate. In some embodiments, the array substrate includes a plurality of first type data lines and a plurality of second type data lines. Optionally, each of the plurality of first type data lines passes through sub-pixel openings of a plurality of sub-pixels of a first color and does not pass through sub-pixel openings of any sub-pixels of a second color and does not pass through sub-pixel openings of any sub-pixels of a third color, the first color, the second color, and the third color being three different colors; each of the plurality of second type data lines does not pass through any sub-pixel openings. Optionally, a first plane containing a normal projection of a respective one of the plurality of first type data lines on a second plane divides a respective sub-pixel opening of a sub-pixel of the first color into a first area and a second area, the first plane being orthogonal to the second plane, the second plane containing a surface of a pixel defining layer. Optionally, a ratio of a first area of the first area to a second area of the second area is in a range of 2:8 to 8:2. Optionally, a ratio of a total number of the plurality of first type data lines to a total number of the plurality of second type data lines is in a range of 0.2 to 4, for example, 0.3 to 3.

[0089] ​In some embodiments, an array substrate includes a base substrate; a plurality of data lines; a plurality of light emitting elements in a plurality of sub-pixels, respectively; and a pixel defining layer on the base substrate, the pixel defining layer defining a plurality of sub-pixel openings. Optionally, the plurality of light emitting elements includes a first light emitting element in each first sub-pixel, a second light emitting element in each second sub-pixel, a third light emitting element in each third sub-pixel, and a fourth light emitting element in each fourth sub-pixel. Optionally, the plurality of sub-pixel openings includes each first sub-pixel opening, each second sub-pixel opening, each third sub-pixel opening, and each fourth sub-pixel opening extending through the pixel defining layer, respectively. Optionally, a first light emitting layer of the first light emitting element is connected to a first anode of the first light emitting element through the corresponding first sub-pixel opening. Optionally, a second light emitting layer of the second light emitting element is connected to a second anode of the second light emitting element through the corresponding second sub-pixel opening. Optionally, a third light emitting layer of the third light emitting element is connected to a third anode of the third light emitting element through the corresponding third sub-pixel opening. Optionally, a fourth light emitting layer of the fourth light emitting element is connected to a fourth anode of the fourth light emitting element through the corresponding fourth sub-pixel opening. Optionally, each of the each first sub-pixel opening, the each second sub-pixel opening, and the each fourth sub-pixel opening is not crossed by any data line. Optionally, one data line of the plurality of data lines crosses the corresponding third sub-pixel opening.

[0090] FIG. 1 is a plan view of an array substrate in some embodiments according to the present disclosure. Referring to FIG. 1 , the array substrate includes an array of sub-pixels Sp. Each sub-pixel includes an electronic element, such as a light emitting element. In one example, the light emitting element is driven by a pixel driving circuit PDC. The array substrate includes a plurality of gate lines GL, a plurality of data lines DL, a plurality of voltage supply lines Vdd (e.g., high voltage supply lines), and a plurality of second voltage supply lines (e.g., low voltage supply lines Vss). The light emission of each of the sub-pixels Sp is driven by the pixel driving circuit PDC. In one example, a high voltage signal (e.g., VDD signal) is input to the pixel driving circuit PDC connected to an anode of the light emitting element through a corresponding one of the plurality of voltage supply lines Vdd; a low voltage signal (e.g., VSS signal) is input to a cathode of the light emitting element through a corresponding one of the plurality of second voltage supply lines (e.g., low voltage supply lines Vss). The voltage difference between the high voltage signal (e.g., VDD signal) and the low voltage signal (e.g., VSS signal) is a driving voltage AV, which drives the light emitting element to emit light.

[0091] Various suitable pixel drive circuits can be used in the present array substrate. Examples of suitable drive circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, and 8T2C. In some embodiments, each of the plurality of pixel drive circuits is a 7T1C drive circuit. Various suitable light emitting elements can be used in the present array substrate. Examples of suitable light emitting elements include organic light emitting diodes, quantum dot light emitting diodes, and micro light emitting diodes. Optionally, the light emitting element is a micro light emitting diode. Optionally, the light emitting element is an organic light emitting diode that includes an organic light emitting layer.

[0092] FIG. 2A is a circuit diagram illustrating a structure of a pixel drive circuit in some embodiments according to the present disclosure. Referring to FIG. 2A In some embodiments, the pixel drive circuit includes a drive transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first transistor T1 having a gate connected to a respective one of a plurality of first reset control signal lines rst1, a source connected to a respective one of a plurality of first reset signal lines Vint1, and a drain connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the drive transistor Td; a second transistor T2 having a gate connected to a gate line GL, a source connected to a data line DL, and a drain connected to the source of the drive transistor Td; a third transistor T3 having a gate connected to the gate line GL, a source connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the drive transistor Td, and a drain connected to the drain of the drive transistor Td; a fourth transistor T4 having a gate connected to a respective one of a plurality of emission control signal lines em, a source connected to a respective one of a plurality of voltage supply lines Vdd, and a drain connected to the source of the drive transistor Td and the drain of the second transistor T2; a fifth transistor T5 having a gate connected to a respective one of the plurality of emission control signal lines em, a source connected to the drain of the drive transistor Td and the drain of the third transistor T3, and a drain connected to an anode of a light emitting element LE; and a sixth transistor T6 having a gate connected to a respective one of a plurality of second reset control signal lines rst2, a source connected to a respective one of a plurality of second reset signal lines Vint2, and a drain connected to the drain of the fifth transistor and the anode of the light emitting element LE. The second capacitor electrode Ce2 is connected to a respective one of the plurality of voltage supply lines Vdd and the source of the fourth transistor T4.

[0093] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the source of the third transistor T3. The second node N2 is connected to the drain of the fourth transistor T4, the drain of the second transistor T2, and the source of the driving transistor Td. The third node N3 is connected to the drain of the driving transistor Td, the drain of the third transistor T3, and the source of the fifth transistor T5. The fourth node N4 is connected to the drain of the fifth transistor T5, the drain of the sixth transistor T6, and the anode of the light-emitting element LE.

[0094] FIG. 3A This is a diagram illustrating the structure of a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure. FIG. 3B This is a schematic diagram illustrating the sub-pixel arrangement of a plurality of subpixels in an array substrate according to some embodiments of the present disclosure. (Refer to...) FIG. 3A and FIG. 3B In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels includes a first sub-pixel sp1, a second sub-pixel sp2, a third sub-pixel sp3, and a fourth sub-pixel sp4. Optionally, each pixel of the array substrate includes a first sub-pixel sp1, a second sub-pixel sp2, a third sub-pixel sp3, and a fourth sub-pixel sp4. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a repeating array in the format S1-S2-S3-S4, where S1 represents each first sub-pixel sp1, S2 represents each second sub-pixel sp2, S3 represents each third sub-pixel sp3, and S4 represents each fourth sub-pixel sp4. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C4 format, where C1 represents each first sub-pixel sp1 of a first color, C2 represents each second sub-pixel sp2 of a second color, C3 represents each third sub-pixel sp3 of a third color, and C4 represents each fourth sub-pixel sp4 of a fourth color. In another example, the S1-S2-S3-S4 format is the C1-C2-C3-C2' format, where C1 represents each first sub-pixel sp1 of the first color, C2 represents each second sub-pixel sp2 of the second color, C3 represents each third sub-pixel sp3 of the third color, and C2' represents each fourth sub-pixel sp4 of the second color. In yet another example, the C1-C2-C3-C2' format is the RGBG format, where each first sub-pixel sp1 is a red sub-pixel, each second sub-pixel sp2 is a green sub-pixel, each third sub-pixel sp3 is a blue sub-pixel, and each fourth sub-pixel sp4 is a green sub-pixel.

[0095] like FIG. 3Aand FIG. 3B As shown, in some embodiments, a minimum repeating unit of the plurality of sub-pixels of the array substrate comprises a respective first sub-pixel sp1, a respective second sub-pixel sp2, a respective third sub-pixel sp3, and a respective fourth sub-pixel sp4. FIG. 3A A total of eight sub-pixels of the plurality of sub-pixels sp arranged adjacent to each other are shown. Each of the respective first sub-pixel sp1, the respective second sub-pixel sp2, the respective third sub-pixel sp3, and the respective fourth sub-pixel sp4 comprises a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a driving transistor Td. In some embodiments, the plurality of sub-pixels sp are arranged in an array having a plurality of rows along a first direction DR1 and a plurality of columns along a second direction DR2. Optionally, the first direction DR1 is perpendicular to the second direction DR2. Optionally, the first direction DR1 and the second direction DR2 cross each other at an angle unequal to 90 degrees.

[0096] FIG. 3C is a diagram showing a structure of a semiconductor material layer in a plurality of sub-pixels of an array substrate. FIG. 3A is a diagram showing a structure of a first conductive layer in a plurality of sub-pixels of an array substrate. FIG. 3D is a diagram showing a structure of a second conductive layer in a plurality of sub-pixels of an array substrate. FIG. 3A is a diagram showing a structure of a first signal line layer in a plurality of sub-pixels of an array substrate. FIG. 3E is a diagram showing a structure of a second signal line layer in a plurality of sub-pixels of an array substrate. FIG. 3A is a diagram showing a structure of an anode in a plurality of sub-pixels of an array substrate. FIG. 3F is a cross-sectional view along line A-A' in FIG. 3A is a cross-sectional view along line B-B' in FIG. 3G is a cross-sectional view along line C-C' in FIG. 3A is a cross-sectional view along line D-D' in FIG. 3H is a cross-sectional view along line D-D' in FIG. 3A is a cross-sectional view along line D-D' in FIG. 4A is a cross-sectional view along line D-D' in FIG. 3A is a cross-sectional view along line D-D' in is a cross-sectional view along line D-D' in

[0097] is a cross-sectional view along line D-D' in FIG. 4B is a cross-sectional view along line D-D' in FIG. 3A is a cross-sectional view along line D-D' in FIG. 4C is a cross-sectional view along line D-D' in FIG. 3A is a cross-sectional view along line D-D' in FIG. 4D is a cross-sectional view along line D-D' in FIG. 3A is a cross-sectional view along line D-D' in FIG. 3A to FIG. 3H is a cross-sectional view along line D-D' in FIG. 4A to FIG. 4DIn some embodiments, the array substrate includes a base substrate BS, a semiconductor material layer SML on the base substrate BS, a gate insulating layer GI on a side of the semiconductor material layer SML distal to the base substrate BS, a first conductive layer on a side of the gate insulating layer GI distal to the semiconductor material layer SML, an insulating layer IN on a side of the first conductive layer distal to the gate insulating layer GI, a second conductive layer on a side of the insulating layer IN distal to the first conductive layer, an interlayer dielectric layer ILD on a side of the second conductive layer distal to the insulating layer IN, a first signal line layer on a side of the interlayer dielectric layer ILD distal to the second conductive layer, a first planarization layer PLN1 on a side of the first signal line layer distal to the interlayer dielectric layer ILD, a second signal line layer on a side of the first planarization layer PLN1 distal to the first signal line layer, a second planarization layer PLN2 on a side of the second signal line layer distal to the first planarization layer PLN1, and an anode layer on a side of the second planarization layer PLN2 distal to the second signal line layer.

[0098] Referring to FIG. 2A , FIG. 3A and FIG. 3C In some embodiments, in each sub-pixel, the semiconductor material layer has an overall structure. In FIG. 3C , the first sub-pixel on the left is labeled with a mark indicating the regions corresponding to the plurality of transistors in the pixel driving circuit, including the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the driving transistor Td. FIG. 3CIn some embodiments, the first conductive layer includes a plurality of gate lines GL, a plurality of first reset control signal lines rst1, a plurality of light-emitting control signal lines em, a plurality of second reset control signal lines rst2, and a first capacitor electrode Ce1 of the storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the first conductive layer. For example, the conductive material can be deposited on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for manufacturing the first conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the plurality of gate lines GL, the plurality of first reset control signal lines rst1, the plurality of light-emitting control signal lines em, the plurality of second reset control signal lines rst2, and the first capacitor electrode Ce1 are located in the same layer.

[0099] Referring to FIG. 2A , FIG. 3A , FIG. 3D , FIG. 4A and FIG. 4B In some embodiments, the first conductive layer includes a plurality of gate lines GL, a plurality of first reset control signal lines rst1, a plurality of light-emitting control signal lines em, a plurality of second reset control signal lines rst2, and a first capacitor electrode Ce1 of the storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the first conductive layer. For example, the conductive material can be deposited on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for manufacturing the first conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the plurality of gate lines GL, the plurality of first reset control signal lines rst1, the plurality of light-emitting control signal lines em, the plurality of second reset control signal lines rst2, and the first capacitor electrode Ce1 are located in the same layer.

[0100] As used herein, the term “same layer” refers to a relationship between layers that are formed simultaneously in the same step. In one example, the plurality of gate lines GL and the first capacitor electrode Ce1 are in the same layer when the plurality of gate lines GL and the first capacitor electrode Ce1 are formed by one or more steps of the same patterning process from the same material layer. In another example, the plurality of gate lines GL and the first capacitor electrode Ce1 can be formed in the same layer by performing the steps of forming the plurality of gate lines GL and the steps of forming the first capacitor electrode Ce1 simultaneously. The term “same layer” does not always mean that the thickness of the layer or the height of the layer is the same in a cross-sectional view.

[0101] Referring to FIG. 2A , FIG. 3A and FIG. 3E In some embodiments, the second conductive layer includes the plurality of first reset signal lines Vint1, the second capacitor electrode Ce2 of the storage capacitor Cst, the immunity protection block IPB, and the plurality of second reset signal lines Vint2. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second conductive layer. For example, the conductive material can be deposited on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for manufacturing the second conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the plurality of first reset signal lines Vint1, the plurality of second reset signal lines Vint2, the immunity protection block IPB, and the second capacitor electrode Ce2 are in the same layer. Referring to FIG. 2A , FIG. 3A , FIG. 3D and FIG. 4B In some embodiments, the immunity protection block IPB is in the same layer as the second capacitor electrode Ce2. A respective one of the plurality of voltage supply lines Vdd is connected to the immunity protection block IPB through a third main via v3. Optionally, the third main via v3 extends through the interlayer dielectric layer ILD.

[0102] Referring to FIG. 2A , FIG. 3A , FIG. 3C and FIG. 3FIn some embodiments, the first signal line layer includes a plurality of voltage supply lines Vdd, a node connection line Cln, a second connection line Cl2, and a third connection line Cl3. The node connection line Cln connects together the first capacitor electrode Cel and the source of the third transistor T3 in each sub-pixel. The second connection line Cl2 connects together a respective one of the plurality of first reset signal lines Vintl and the source of the first transistor Tl in the respective sub-pixel. The third connection line Cl3 connects together a respective one of the plurality of second reset signal lines Vint2 and the source of the sixth transistor T6 in the respective sub-pixel. In some embodiments, the first signal line layer also includes a relay electrode RE in a respective one of the plurality of sub-pixels sp. The relay electrode connects the source of the fifth transistor T5 in the respective one of the plurality of sub-pixels sp to the anode contact pad in the respective one of the plurality of sub-pixels sp. Various suitable conductive materials and various suitable fabrication methods can be used to fabricate the signal line layer. For example, the conductive material can be deposited on the substrate and patterned by a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the plurality of voltage supply lines Vdd, the plurality of data lines DL, the node connection line Cln, the second connection line Cl2, the third connection line Cl3, and the relay electrode RE are located in the same layer.

[0103] FIG. 4C is a cross-sectional view along the C-C' line in FIG. 3A . Referring to FIG. 2A , FIG. 3A , FIG. 3F and FIG. 4C In some embodiments, the second connection line Cl2 connects together a respective one of the plurality of first reset signal lines Vintl and the source SI of the first transistor Tl in each sub-pixel. The respective one of the plurality of first reset signal lines Vintl is configured to provide a reset signal to the source SI of the first transistor Tl in each sub-pixel through the second connection line Cl2. Optionally, the second connection line Cl2 is connected to the respective one of the plurality of first reset signal lines Vintl through a fifth main via v5 extending through the interlayer dielectric layer ILD. Optionally, the second connection line Cl2 is connected to the source SI of the first transistor Tl in each sub-pixel via a sixth main via v6 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI.

[0104] FIG. 4D is a cross-sectional view along the D-D' line in FIG. 3A . Referring to FIG. 2A , FIG. 3A ,FIG. 3F and FIG. 4D In some embodiments, a third connection line Cl3 connects a corresponding one of the plurality of second reset signal lines Vint2 to the source S6 of a sixth transistor T6 in each sub-pixel. The corresponding one of the plurality of second reset signal lines Vint2 is configured to provide a reset signal to the source S6 of the sixth transistor T6 in each sub-pixel via the second connection line Cl2. Optionally, the third connection line Cl3 is connected to a corresponding one of the plurality of second reset signal lines Vint2 via a seventh main via v7 extending through the interlayer dielectric layer ILD. Optionally, the third connection line Cl3 is connected to the source S6 of the sixth transistor T6 in each sub-pixel via an eighth main via v8 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI.

[0105] Reference FIG. 2A , FIG. 3A and FIG. 3G In some embodiments, the second signal line layer includes multiple data lines DL. Optionally, the second signal line layer also includes an anode contact pad ACP in each of the multiple sub-pixels sp. The anode contact pad ACP is electrically connected to the source of a fifth transistor T5 in each of the multiple sub-pixels sp via a relay electrode in each of the multiple sub-pixels sp. Reference FIG. 2A , FIG. 3A , FIG. 3F , FIG. 3G and FIG. 4B In some embodiments, each of the multiple data lines DL is connected to the connection portion CP through a via v4-1 extending through the first planarization layer PLN-1, and the connection portion CP is connected to the source S2 of the second transistor through a via v4-2 extending through the interlayer dielectric layer ILD, the insulating layer IN and the gate insulating layer GI.

[0106] Reference FIG. 2A , FIG. 3A , FIG. 3D , FIG. 3E and FIG. 4AIn some embodiments, the second capacitor electrode Ce2 on the base substrate BS has a footprint that completely covers the footprint of the first capacitor electrode Cel on the base substrate BS with a margin, except for the hole region H where a portion of the second capacitor electrode Ce2 is absent. In some embodiments, the signal line layer includes a node connection line Cln on a side of the interlayer dielectric layer ILD distal from the second capacitor electrode Ce2. The node connection line Cln is in the same layer as the plurality of voltage supply lines Vdd. Optionally, the array substrate further includes a first main via vl in the hole region H and extending through the interlayer dielectric layer ILD and the insulating layer IN. Optionally, the node connection line Cln is connected to the first capacitor electrode Cel through the first main via vl. In some embodiments, the first capacitor electrode Cel is on a side of the gate insulating layer IN distal from the base substrate BS. Optionally, the array substrate further includes a first main via vl and a second main via v2. The first main via vl is in the hole region H and extends through the interlayer dielectric layer ILD and the insulating layer IN. The second main via v2 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, the node connection line Cln is connected to the first capacitor electrode Cel through the first main via vl and to the semiconductor material layer SML through the second main via v2. Optionally, the node connection line Cln is connected to the source S3 of the third transistor T3, as shown in FIG. 4A

[0107] Referring to FIG. 2A FIG. 3A FIG. 3E FIG. 4B In some embodiments, the interference prevention block IPB is in the same layer as the second capacitor electrode Ce2. A respective one of the plurality of voltage supply lines Vdd is connected to the interference prevention block IPB through a third main via v3. Optionally, the third main via v3 extends through the interlayer dielectric layer ILD. Optionally, a footprint of the interference prevention block IPB on the base substrate BS partially overlaps a footprint of the respective one of the plurality of voltage supply lines Vdd on the base substrate BS. Optionally, a footprint of the interference prevention block IPB on the base substrate BS at least partially overlaps a footprint of the active layer ACT3 of the third transistor T3 on the base substrate BS. Optionally, a footprint of the interference prevention block IPB on the base substrate BS at least partially overlaps a footprint of the drain Dl of the first transistor Tl on the base substrate BS. Optionally, a footprint of a portion of the interference prevention block IPB on the base substrate BS and a footprint of a portion of the respective one of the plurality of voltage supply lines Vdd on the base substrate BS collectively overlap a footprint of a portion of the active layer ACT3 of the third transistor T3 on the base substrate BS.

[0108] ​​​​As used herein, an active layer refers to a component of a transistor that includes at least a portion of a layer of semiconductor material whose orthogonal projection onto the base substrate overlaps the orthogonal projection onto the base substrate of a gate. As used herein, a source refers to a component of a transistor that is connected to one side of an active layer, and a drain refers to a component of a transistor that is connected to another side of an active layer. In the case of a dual-gate transistor (e.g., the third transistor T3), an active layer refers to a component of a transistor that includes a first portion of a layer of semiconductor material, a second portion of the layer of semiconductor material, and a third portion between the first portion and the second portion, where the orthogonal projection onto the base substrate of the first portion of the layer of semiconductor material overlaps the orthogonal projection onto the base substrate of a first gate, and the orthogonal projection onto the base substrate of the second portion of the layer of semiconductor material overlaps the orthogonal projection onto the base substrate of a second gate. In the case of a dual-gate transistor, a source refers to a component of a transistor that is connected to one side of the first portion that is distal to the third portion, and a drain refers to a component of a transistor that is connected to one side of the second portion that is distal to the third portion.

[0109] Reference FIG. 2A , FIG. 3A and FIG. 3H In some embodiments, the array substrate includes a first anode AD1 in each first sub-pixel sp1, a second anode AD2 in each second sub-pixel sp2, a third anode AD3 in each third sub-pixel sp3, and a fourth anode AD4 in each fourth sub-pixel sp4. The first anode AD1, the second anode AD2, the third anode AD3, and the fourth anode AD4 are anodes of first light-emitting elements, second light-emitting elements, third light-emitting elements, and fourth light-emitting elements, respectively, in each first sub-pixel sp1, each second sub-pixel sp2, each third sub-pixel sp3, and each fourth sub-pixel sp4, respectively. In some embodiments, the array substrate further includes a pixel defining layer PDL located at a side of the first anode AD1, the second anode AD2, the third anode AD3, and the fourth anode AD4 distal to the second planarization layer PLN2. The array substrate further includes a respective first sub-pixel opening SA1, a respective second sub-pixel opening SA2, a respective third sub-pixel opening SA3, a respective fourth sub-pixel opening SA4 extending through the pixel defining layer PDL, respectively. In some embodiments, each first sub-pixel sp1 is a red sub-pixel, the first anode AD1 is an anode of the red sub-pixel; each second sub-pixel sp2 is a first green sub-pixel, the second anode AD2 is an anode of the first green sub-pixel; each third sub-pixel sp3 is a blue sub-pixel, the third anode AD3 is an anode of the blue sub-pixel; and each fourth sub-pixel sp4 is a second green sub-pixel, the fourth anode AD4 is an anode of the second green sub-pixel.

[0110] The inventors of the present disclosure found that uniformity of anodes in a display panel can adversely affect image display. For example, color shift can be caused by anode tilting. It was found in the present disclosure that signal lines underneath the anodes can significantly affect the degree of anode tilting. In one example, underneath the anodes, signal lines are provided on one side, while there are no signal lines on the other side. This results in a surface of a planarization layer on top of the signal lines being uneven. The uneven surface of the planarization layer in turn causes the anodes on top of the planarization layer to tilt to the right side. FIG. 5A is a cross-sectional view of an array substrate. As shown in FIG. 5A , the presence of signal lines 1 underneath the left portion of the planarization layer 2 causes the planarization surface to be uneven, which in turn causes the anodes 3 on top of the planarization layer 2 to tilt to the right side. The tilted anodes reflect more light toward the right side of the display panel. In the display panel, the anodes associated with sub-pixels of different colors have different tilting angles, and thus the light reflected by the anodes in the sub-pixels of different colors reflects the light of different colors at different angles. The cumulative effect of this problem causes color shift at large viewing angles.

[0111] FIG. 5B is a schematic diagram showing a cross-sectional view of an array substrate. As shown in FIG. 5B , there are no signal lines 1 underneath the third anode 3-3 which is not tilted. Signal lines 1 are underneath the anodes 3-1 and 3-2. However, the signal lines are only underneath the right portion of the anode 3-1 and only underneath the left portion of the anode 3-2, which causes the two anodes to tilt. The anodes 3-1, 3-2 and 3-3 are anodes of a red sub-pixel, anodes of a green sub-pixel and anodes of a blue sub-pixel, respectively. Because the tilting angles of the anodes in the three sub-pixels of different colors are different from each other, color shift occurs at large viewing angles.

[0112] FIG. 5C is a schematic diagram showing a cross-sectional view of an array substrate. As shown in FIG. 5C , signal lines are present underneath the left and right portions of the anode 3-1 and underneath the left and right portions of the anode 3-2. There are no signal lines underneath the anode 3-3. All the anodes are substantially not tilted, thus mitigating the color shift problem.

[0113] FIG. 5D is a schematic diagram showing a cross-sectional view of an array substrate. As shown in FIG. 5D , signal lines are present underneath the central portion of the anode 3-1 and underneath the central portion of the anode 3-2. There are no signal lines underneath the anode 3-3. All the anodes are substantially not tilted, thus mitigating the color shift problem.

[0114] The present array substrate employs a complex structure of anodes and connection lines to achieve a flat surface of the planarization layer underneath the anodes. Thus, the color shift problem can be mitigated.FIG. 3I is shown FIG. 3A is a diagram showing superposition of anode and data line in a plurality of sub-pixels of the array substrate. Referring to FIG. 3I In some embodiments, the array substrate includes a plurality of data lines, a plurality of light emitting elements respectively in a plurality of sub-pixels, and a pixel defining layer PDL on the base substrate, the pixel defining layer defining a plurality of sub-pixel openings. The plurality of light emitting elements includes a first light emitting element in each first sub-pixel sp1, a second light emitting element in each second sub-pixel sp2, a third light emitting element in each third sub-pixel sp3, and a fourth light emitting element in each fourth sub-pixel sp4. The plurality of sub-pixel openings includes a respective first sub-pixel opening SA1, a respective second sub-pixel opening SA2, a respective third sub-pixel opening SA3, and a respective fourth sub-pixel opening SA4, each extending through the pixel defining layer PDL. A first light emitting layer of the first light emitting element is connected to a first anode AD1 of the first light emitting element through the respective first sub-pixel opening SA1; a second light emitting layer of the second light emitting element is connected to a second anode AD2 of the second light emitting element through the respective second sub-pixel opening SA2; a third light emitting layer of the third light emitting element is connected to a third anode AD3 of the third light emitting element through the respective third sub-pixel opening SA3; and a fourth light emitting layer of the fourth light emitting element is connected to a fourth anode AD4 of the fourth light emitting element through the respective fourth sub-pixel opening SA4.

[0115] In some embodiments, each of the respective first sub-pixel opening SA1, the respective second sub-pixel opening SA2, and the respective fourth sub-pixel opening SA4 is not crossed by any data line. As FIG. 3I is shown, one of the plurality of data lines crosses the respective third sub-pixel opening SA3.

[0116] In some embodiments, the plurality of sub-pixel openings includes a plurality of minimum repeating units. Each minimum repeating unit in the plurality of minimum repeating units includes the respective first sub-pixel opening SA1, the respective second sub-pixel opening SA2, the respective third sub-pixel opening SA3, and the respective fourth sub-pixel opening SA4. Optionally, as FIG. 3IAs shown, the respective first sub-pixel opening SA1, the respective second sub-pixel opening SA2, the respective third sub-pixel opening SA3, and the respective fourth sub-pixel opening SA4 in each of the plurality of minimum repeating units are consecutively arranged (e.g., along a row). In the context of the present disclosure, the minimum repeating unit does not have to be the minimum repeating unit in the entire array substrate. The minimum repeating unit can be the minimum repeating unit in a local region of the array substrate (e.g., a central region of the array substrate). Optionally, the local region with the minimum repeating unit includes at least three minimum repeating units along the row direction. Optionally, the local region with the minimum repeating unit includes at least three minimum repeating units along the column direction.

[0117] In some embodiments, the plurality of data lines includes a first data line dl1, a second data line dl2, a third data line dl3, and a fourth data line dl4, which are configured to provide data signals to the respective first sub-pixel sp1, the respective second sub-pixel sp2, the respective third sub-pixel sp3, and the respective fourth sub-pixel sp4, respectively. Optionally, the plurality of data lines includes a plurality of data line repeating groups. Optionally, each of the plurality of data line repeating groups includes the first data line dl1, the second data line dl2, the third data line dl3, and the fourth data line dl4. Optionally, the first data line dl1, the second data line dl2, the third data line dl3, and the fourth data line dl4 are consecutively arranged (e.g., along a row). As FIG. 3I As shown, in some embodiments, the fourth data line dl4 passes through the respective third sub-pixel opening SA3. Optionally, none of the plurality of data lines passes through the respective first sub-pixel opening SA1, the respective second sub-pixel opening SA2, or the respective fourth sub-pixel opening SA4.

[0118] In some embodiments, the respective first sub-pixel opening SA1, the respective second sub-pixel opening SA2, the respective third sub-pixel opening SA3, and the respective fourth sub-pixel opening SA4 are consecutively arranged along a row; and the first data line dl1, the second data line dl2, the third data line dl3, and the fourth data line dl4 are consecutively arranged along a row. As FIG. 3I As shown, the respective first sub-pixel opening SA1 is between the first data line dl1 and the second data line dl2; the respective second sub-pixel opening SA2 is between the second data line dl2 and the third data line dl3; the fourth data line dl4 passes through the respective third sub-pixel opening SA3; and the respective fourth sub-pixel opening SA4 is located on a side of the fourth data line dl4 away from the third data line dl3.

[0119] FIG. 3J FIG. 5 is a diagram illustrating a superposition of an anode and data lines in a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure. Referring to FIG. 5, the array substrate includes a plurality of minimum repeating units 500. Each of the plurality of minimum repeating units 500 includes a respective first sub-pixel sp1, a respective second sub-pixel sp2, a respective third sub-pixel sp3, and a respective fourth sub-pixel sp4. As shown, each of the plurality of minimum repeating units 500 includes a respective first sub-pixel opening SA1, a respective second sub-pixel opening SA2, a respective third sub-pixel opening SA3, and a respective fourth sub-pixel opening SA4. FIG. 3JIn some embodiments, the respective first sub-pixel opening SA1, the respective second sub-pixel opening SA2, the respective third sub-pixel opening SA3, and the respective fourth sub-pixel opening SA4 are in a first minimum repeating unit in a first row of the two closest adjacent rows. A plurality of minimum repeating units includes a second minimum repeating unit in a second row of the two closest adjacent rows. The second minimum repeating unit has a displacement of twice the data line-to-data line distance relative to the first minimum repeating unit along the row direction, the data line-to-data line distance being the shortest distance between two closest data lines along the row direction. In the context of the present disclosure, the shortest distance between two closest data lines along the row direction refers to the shortest distance between two closest data lines along the row direction in the display. Optionally, the data line-to-data line distance is equal to half of the sub-pixel-to-sub-pixel distance of the same color, where the sub-pixel-to-sub-pixel distance of the same color refers to the distance between the centers of two sub-pixels of the same color in the same row. Optionally, the second minimum repeating unit in the second row includes a second respective first sub-pixel opening 2SA1, a second respective second sub-pixel opening 2SA2, a second respective third sub-pixel opening 2SA3, and a second respective fourth sub-pixel opening 2SA4 arranged consecutively along the row. As shown in FIG. 7, the fourth data line dl4 passes through the respective third sub-pixel opening SA3; and the second data line dl2 passes through the second respective second sub-pixel opening 2SA2 in the second row. FIG. 3J

[0120] In some embodiments, the minimum repeating unit of the plurality of sub-pixels of the array substrate includes a respective first sub-pixel sp1, a respective second sub-pixel sp2, a respective third sub-pixel sp3, and a respective fourth sub-pixel sp4. In some embodiments, two of the respective first sub-pixel, the respective second sub-pixel, the respective third sub-pixel, and the respective fourth sub-pixel are sub-pixels of the same color (e.g., green). Optionally, the respective second sub-pixel sp2 and the respective fourth sub-pixel sp4 are sub-pixels of the same color, which is different from the color of the respective first sub-pixel sp1 and also different from the color of the respective third sub-pixel sp3. In one example, the respective second sub-pixel sp2 and the respective fourth sub-pixel sp4 are green sub-pixels, the respective first sub-pixel sp1 is a red sub-pixel, and the respective third sub-pixel sp3 is a blue sub-pixel. In some embodiments, two of the first light emitting element, the second light emitting element, the third light emitting element, and the fourth light emitting element are light emitting elements of the same color (e.g., green). Optionally, the second light emitting element and the fourth light emitting element are light emitting elements of the same color, which is different from the color of the first light emitting element and also different from the color of the third light emitting element. In one example, the second light emitting element and the fourth light emitting element are green light emitting elements, the first light emitting element is a red light emitting element, and the third light emitting element is a blue light emitting element. ​

[0121] In some embodiments, as shown in FIG. 3I the first anode AD1, the second anode AD2 and the third anode AD3 have different areas and different shapes. In some embodiments, as shown in FIG. 3I the first anode AD1, the second anode AD2 and the fourth anode AD4 have different areas and different shapes. Alternatively, as shown in FIG. 3I the first anode AD1, the second anode AD2, the third anode AD3 and the fourth anode AD4 have different areas and different shapes. In one example, the second anode AD2 and the fourth anode AD4 are anodes of two light-emitting elements of the same color. FIG. 6 Structural differences between the second anode and the fourth anode in some embodiments according to the present disclosure are shown. Referring to FIG. 6 In some embodiments, the second anode AD2 includes a first main portion MP1, a first extra portion EP1 and a second extra portion EP2; the fourth anode AD4 includes a second main portion MP2 and a third extra portion EP3.

[0122] In some embodiments, the first main portion MP1 is a combination of a rectangular portion and a triangular portion, and the second main portion MP2 is a combination of a rectangular portion and a triangular portion. Alternatively, the first main portion MP1 and the second main portion MP2 have substantially the same shape (and size). Alternatively, the first extra portion EP1 is adjacent to the triangular portion of the first main portion MP1. Alternatively, the second extra portion EP2 is adjacent to a side of the rectangular portion of the first main portion MP1 away from the triangular portion of the first main portion MP1. Alternatively, the third extra portion EP3 is adjacent to the triangular portion of the second main portion MP2.

[0123] Alternatively, the first extra portion EP1, the first main portion MP1, the second extra portion EP2 are sequentially arranged along a direction substantially parallel to the plurality of data lines (e.g., the second direction DR2). Alternatively, the second main portion MP2 and the third extra portion EP3 are sequentially arranged along a direction substantially parallel to the plurality of data lines (e.g., the second direction DR2).

[0124] FIG. 7 Orthographic projections of the fourth data line on the pixel-defining layer in some embodiments according to the present disclosure are shown. Referring to FIG. 7In some embodiments, the first plane, which contains the orthogonal projection Pdl4 of the fourth data line on the second plane containing the surface of the pixel defining layer PDL, divides the respective third sub-pixel opening SA3 into a first region R1 and a second region R2. Optionally, the first plane is orthogonal to the second plane. In some embodiments, a ratio of a first area of the first region to a second area of the second region is in a range from 2:8 to 8:2, such as from 2:8 to 3:8, from 3:8 to 1:2, from 1:2 to 5:8, from 5:8 to 6:8, from 6:8 to 7:8, from 7:8 to 1:1, from 1:1 to 8:7, from 8:7 to 8:6, from 8:6 to 8:5, from 8:5 to 1:2, from 1:2 to 3:8, or from 3:8 to 2:8. Optionally, a ratio of the first area of the first region to the second area of the second region is in a range from 1:1.5 to 1.5:1, such as from 1:1.5 to 1:1.4, from 1:1.4 to 1:1.3, from 1:1.3 to 1:1.2, from 1:1.2 to 1:1.1, from 1:1.1 to 1:1, from 1:1 to 1.1:1, from 1.1:1 to 1.2:1, from 1.2:1 to 1.3:1, from 1.3:1 to 1.4:1, or from 1.4:1 to 1.5:1. In one example, the first area of the first region R1 is equal to the second area of the second region R2. In the context of the present disclosure, the first plane is the plane containing the orthogonal projection Pdl4, or is the plane containing the orthogonal projection on the second plane of a line in the fourth data line, the second plane containing the surface of the pixel defining layer PDL, the line in the fourth data line extending along a direction parallel to the direction of extension of the fourth data line.

[0125] Optionally, each third sub-pixel opening SA3 has substantially mirror symmetry about a plane Pm perpendicular to the pixel defining layer PDL and intersecting the orthogonal projection Pdl4 of the fourth data line on the pixel defining layer PDL. As used herein, the term substantially mirror symmetry means that two objects have mirror symmetry within 10% error, such as within 8% error, within 6% error, within 4% error, within 2% error, or within 1% error. In one example, at least 90% of a first object overlaps with a second object after a mirror symmetry operation is performed on the first object, and at least 90% of the second object overlaps with the first object after a mirror symmetry operation is performed on the second object.

[0126] Optionally, each third sub-pixel opening SA3 has a hexagonal shape. Optionally, the orthogonal projection Pdl4 of the fourth data line on the pixel defining layer PDL substantially overlaps with a center line of the hexagonal shape.

[0127] FIG. 8A FIG. 1 is a diagram illustrating a structure of a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure. FIG. 8B FIG. 2 is a diagram illustrating a structure of a plurality of sub-pixels of an array substrate according to some embodiments of the present disclosure. FIG. 8AA diagram showing the structure of anodes in a plurality of sub-pixels of an array substrate. FIG. 8C is shown FIG. 8A A diagram showing the superposition of anodes and data lines in a plurality of sub-pixels of an array substrate. FIG. 8A The layers in the array substrate shown other than the anode layer have similar structures to those described in FIG. 3B to FIG. 3G Reference is made to FIG. 8A , FIG. 8B and FIG. 8C In some embodiments, the fourth data line dl4 passes through the third anode AD3 and through the respective third sub-pixel opening SA3. Optionally, none of the plurality of data lines passes through the second anode AD2. Optionally, none of the plurality of data lines passes through the fourth anode AD4. Optionally, none of the plurality of data lines passes through the first anode AD1. By having none of the plurality of data lines pass through each of the second anode AD2, the fourth anode AD4 or the first anode AD1, a highly planar planarization surface can be achieved underneath each of these anodes.

[0128] In some embodiments, the area of the orthogonal projection of any data line on the second anode AD2 is smaller than the area of the orthogonal projection of any data line on the first anode AD1, and smaller than the area of the orthogonal projection of any data line on the third anode AD3. In some embodiments, the area of the orthogonal projection of any data line on the fourth anode AD4 is smaller than the area of the orthogonal projection of any data line on the first anode AD1, and smaller than the area of the orthogonal projection of any data line on the third anode AD3. Optionally, an edge of the second anode is at least partially covered by the orthogonal projection of a data line on the second anode that is adjacent to the edge of the second anode. Optionally, an edge of the fourth anode is at least partially covered by the orthogonal projection of a data line on the fourth anode that is adjacent to the edge of the fourth anode.

[0129] In some embodiments, an edge of the first anode AD1 is at least partially covered by the orthogonal projection of a data line on the first anode AD1 that is adjacent to the edge of the first anode AD1.

[0130] FIG. 8D A diagram showing the orthogonal projection of a fourth data line on a third anode in some embodiments of the present disclosure is shown. Reference is made to FIG. 8DIn some embodiments, the orthogonal projection Pdl4 of the fourth data line on the third anode AD3 divides the third anode into a first anode region AR1 and a second anode region AR2. In some embodiments, a ratio of a first area of the first anode region AR1 to a second area of the second anode region AR2 is in a range from 2:8 to 8:2, for example, from 2:8 to 3:8, from 3:8 to 1 :2, from 1 :2 to 5:8, from 5:8 to 6:8, from 6:8 to 7:8, from 7:8 to 1 :1, from 1 :1 to 8:7, from 8:7 to 8:6, from 8:6 to 8:5, from 8:5 to 1 :2, from 1 :2 to 3:8, or from 3:8 to 2:8. Optionally, the ratio of the first area of the first region to the second area of the second region is in a range from 1 :1.5 to 1.5:1, for example, from 1 :1.5 to 1 :1.4, from 1 :1.4 to 1 :1.3, from 1 :1.3 to 1 :1.2, from 1 :1.2 to 1 :1.1, from 1 :1.1 to 1 :1, from 1 :1 to 1.1 :1, from 1.1 :1 to 1.2:1, from 1.2:1 to 1.3:1, from 1.3:1 to 1.4:1, or from 1.4:1 to 1.5:1. In one example, the first area of the first anode region AR1 is equal to the second area of the second anode region AR2. By having the fourth data line dl4 pass through the third anode AD3 in the described manner, a highly planar planarization surface can be achieved underneath the third anode AD3.

[0131] In some embodiments, the third anode AD3 has a first edge E1 on a first side of a perpendicular projection Pdl4 of the fourth data line on the third anode AD3, wherein the first edge E1 is parallel to the fourth data line and is the edge on the first side S1 that is farthest from the perpendicular projection Pdl4 of the fourth data line on the third anode AD3; and a second edge E2 on a second side of the perpendicular projection Pdl4 of the fourth data line on the third anode AD3, wherein the second edge E2 is parallel to the fourth data line and is the edge on the second side S2 that is farthest from the perpendicular projection Pdl4 of the fourth data line on the third anode AD3. Optionally, a ratio of a first shortest distance dm1 between the first edge E1 and the perpendicular projection Pdl4 of the fourth data line on the third anode AD3 to a second shortest distance dm2 between the second edge E2 and the perpendicular projection Pdl4 of the fourth data line on the third anode AD3 is in a range from 2:8 to 8:2, e.g., 2:8 to 3:8, 3:8 to 1:2, 1:2 to 5:8, 5:8 to 6:8, 6:8 to 7:8, 7:8 to 1:1, 1:1 to 8:7, 8:7 to 8:6, 8:6 to 8:5, 8:5 to 1:2, 1:2 to 3:8, or 3:8 to 2:8. Optionally, the ratio of the first shortest distance dm1 to the second shortest distance dm2 is in a range from 1:1.5 to 1.5:1, e.g., 1:1.5 to 1:1.4, 1:1.4 to 1:1.3, 1:1.3 to 1:1.2, 1:1.2 to 1:1.1, 1:1.1 to 1:1, 1:1 to 1.1:1, 1.1:1 to 1.2:1, 1.2:1 to 1.3:1, 1.3:1 to 1.4:1, or 1.4:1 to 1.5:1.

[0132] In some embodiments, the perpendicular projection of the first node on the base substrate at least partially overlaps with the perpendicular projection of the anode on the base substrate. Referring to FIG. 2A , FIG. 3A to FIG. 3H and FIG. 4AIn some embodiments, the orthogonal projection of the first anode AD1 in each first sub-pixel sp1 on the base substrate BS at least partially overlaps with the orthogonal projection of the node connection line Cln in each first sub-pixel sp1 on the base substrate BS; the orthogonal projection of the second anode AD2 in each second sub-pixel sp2 on the base substrate BS at least partially overlaps with the orthogonal projection of the node connection line Cln in each second sub-pixel sp2 on the base substrate BS; the orthogonal projection of the third anode AD3 in each third sub-pixel sp3 on the base substrate BS at least partially overlaps with the orthogonal projection of the node connection line Cln in each third sub-pixel sp3 on the base substrate BS, and at least partially overlaps with the orthogonal projection of the node connection line Cln in each fourth sub-pixel sp4 on the base substrate BS. Optionally, the orthogonal projection of the fourth anode AD4 in each fourth sub-pixel sp4 on the base substrate BS does not overlap with the orthogonal projection of any node connection line.

[0133] In some embodiments, the orthogonal projection of the first anode AD1 in each first sub-pixel sp1 on the base substrate BS at least partially overlaps with the orthogonal projection of the first capacitor electrode Cel in each first sub-pixel sp1 on the base substrate BS; the orthogonal projection of the second anode AD2 in each second sub-pixel sp2 on the base substrate BS at least partially overlaps with the orthogonal projection of the first capacitor electrode Cel in each second sub-pixel sp2 on the base substrate BS; the orthogonal projection of the third anode AD3 in each third sub-pixel sp3 on the base substrate BS at least partially overlaps with the orthogonal projection of the first capacitor electrode Cel in each third sub-pixel sp3 on the base substrate BS, and at least partially overlaps with the orthogonal projection of the first capacitor electrode Cel in each fourth sub-pixel sp4 on the base substrate BS. Optionally, the orthogonal projection of the fourth anode AD4 in each fourth sub-pixel sp4 on the base substrate BS does not overlap with the orthogonal projection of any first capacitor electrode on the base substrate BS.

[0134] Optionally, the orthogonal projection of the first anode AD1 in each first sub-pixel sp1 onto the base substrate BS at least partially overlaps with the orthogonal projection of the second capacitor electrode Ce2 in each first sub-pixel sp1 onto the base substrate BS; the orthogonal projection of the second anode AD2 in each second sub-pixel sp2 onto the base substrate BS at least partially overlaps with the orthogonal projection of the second capacitor electrode Ce2 in each second sub-pixel sp2 onto the base substrate BS; the orthogonal projection of the third anode AD3 in each third sub-pixel sp3 onto the base substrate BS at least partially overlaps with the orthogonal projection of the second capacitor electrode Ce2 in each third sub-pixel sp3 onto the base substrate BS, and at least partially overlaps with the orthogonal projection of the second capacitor electrode Ce2 in each fourth sub-pixel sp4 onto the base substrate BS. Optionally, the orthogonal projection of the fourth anode AD4 in each fourth sub-pixel sp4 onto the base substrate BS does not overlap with the orthogonal projection of any second capacitor electrode.

[0135] Optionally, the orthogonal projection of the first anode AD1 in each first sub-pixel sp1 onto the base substrate BS at least partially overlaps with the orthogonal projection of the active layer ACTd of the drive transistor Td in each first sub-pixel sp1 onto the base substrate BS; the orthogonal projection of the second anode AD2 in each second sub-pixel sp2 onto the base substrate BS at least partially overlaps with the orthogonal projection of the active layer ACTd of the drive transistor Td in each second sub-pixel sp2 onto the base substrate BS; the orthogonal projection of the third anode AD3 in each third sub-pixel sp3 onto the base substrate BS at least partially overlaps with the orthogonal projection of the active layer ACTd of the drive transistor Td in each third sub-pixel sp3 onto the base substrate BS, and at least partially overlaps with the orthogonal projection of the active layer ACTd of the drive transistor Td in each fourth sub-pixel sp4 onto the base substrate BS. Optionally, the orthogonal projection of the fourth anode AD4 in each fourth sub-pixel sp4 onto the base substrate BS does not overlap with the orthogonal projection of any active layer of a drive transistor onto the base substrate BS.

[0136] Optionally, the orthogonal projection of the first anode AD1 in each first sub-pixel sp1 on the base substrate BS covers the orthogonal projection on the base substrate BS of a portion of the node connection line Cln in each first sub-pixel sp1 at a position connected to the first capacitor electrode Cel; the orthogonal projection of the second anode AD2 in each second sub-pixel sp2 on the base substrate BS covers the orthogonal projection on the base substrate BS of a portion of the node connection line Cln in each second sub-pixel sp2 at a position connected to the first capacitor electrode Cel; the orthogonal projection of the third anode AD3 in each third sub-pixel sp3 on the base substrate BS covers the orthogonal projection on the base substrate BS of a portion of the node connection line Cln in each fourth sub-pixel sp4 at a position connected to the first capacitor electrode Cel, and partially overlaps with the orthogonal projection on the base substrate BS of a portion of the node connection line Cln in each third sub-pixel sp3 at a position connected to the first capacitor electrode Cel.

[0137] In the present array substrate, the N1 nodes of the pixel driving circuit and the orthogonal projection of the anode on the base substrate BS at least partially overlap, the load between each anode in each sub-pixel and the load between each pixel driving circuit can be kept consistent with each other, thereby improving the image display uniformity.

[0138] FIG. 9A FIG. 1 is a diagram illustrating anode and semiconductor material layer in an array substrate according to some embodiments of the present disclosure. FIG. 9B is a cross-sectional view along line E-E' in FIG. 9A FIG. 2 is a cross-sectional view along line E-E' in FIG. 9A and FIG. 9B In some embodiments, the orthogonal projection of the third anode AD3 of the third light emitting element in each third sub-pixel on the base substrate BS at least partially overlaps with the orthogonal projection on the base substrate BS of the third transistor in the corresponding third sub-pixel, and at least partially overlaps with the orthogonal projection on the base substrate BS of the third transistor in the corresponding fourth sub-pixel adjacent to the corresponding third sub-pixel. Optionally, the orthogonal projection of the third anode AD3 on the base substrate BS partially overlaps with the orthogonal projection on the base substrate BS of the active layer ACT3 of the third transistor in the corresponding third sub-pixel, covers the orthogonal projection on the base substrate BS of the source S3 of the third transistor in the corresponding fourth sub-pixel, and partially overlaps with the orthogonal projection on the base substrate BS of the active layer ACT3 of the third transistor in the corresponding fourth sub-pixel.

[0139] FIG. 9C is a cross-sectional view along line F-F' in FIG. 9A FIG. 3 is a cross-sectional view along line F-F' in FIG. 9A and FIG. 9CIn some embodiments, the orthographic projection of the first anode AD1 onto the base substrate BS at least partially overlaps with the orthographic projection of the third transistor in the respective first sub-pixel onto the base substrate BS. Optionally, the orthographic projection of the first anode AD1 onto the base substrate BS covers the orthographic projection of the source S3 of the third transistor in the respective first sub-pixel onto the base substrate BS and partially overlaps with the orthographic projection of the active layer ACT3 of the third transistor in the respective first sub-pixel onto the base substrate BS.

[0140] In the present array substrate, the orthographic projection of the anode onto the base substrate BS at least partially overlaps with the active layer of the third transistor, respectively. Since the anodes are usually made of reflective material, they can prevent the ultraviolet light from shining on the active layer, thereby protecting the transistor.

[0141] FIG. 9D is a cross-sectional view along the line G-G' in FIG. 9A . Referring to FIG. 9A and FIG. 9D In some embodiments, the orthographic projection of the second anode AD2 onto the base substrate BS at least partially overlaps with the orthographic projection of the third transistor in the respective second sub-pixel onto the base substrate BS. Optionally, the orthographic projection of the second anode AD2 onto the base substrate BS partially overlaps with the orthographic projection of the active layer ACT3 of the third transistor in the respective second sub-pixel onto the base substrate BS.

[0142] FIG. 8E is a cross-sectional view along the dashed line VL in FIG. 8C . Referring to FIG. 8C and FIG. 8E In some embodiments, in each first sub-pixel sp1, the first anode AD1 is connected to the first anode contact pad ACP1 by a first via V1-1 extending through the second planarization layer PLN-2; in each second sub-pixel sp2, the second anode AD2 is connected to the second anode contact pad ACP2 by a second via V2-1 extending through the second planarization layer PLN-2; in each third sub-pixel sp3, the third anode AD3 is connected to the third anode contact pad ACP3 by a third via V3-1 extending through the second planarization layer PLN-2; in each fourth sub-pixel sp4, the fourth anode AD4 is connected to the fourth anode contact pad ACP4 by a fourth via V4-1 extending through the second planarization layer PLN-2. In some embodiments, the dashed line VL along the first direction DR1 passes through the first via V1-1, the second via V2-1, the third via V3-1 and the fourth via V4-1.

[0143] In some embodiments, the shortest distance between the edge of the first anode AD1, excluding the edge of the first anode AD1 connected to the first anode contact pad ACP1 through the first via V1-1, and the corresponding first sub-pixel opening SA1 is different. Optionally, the shortest distance between the edge of the second anode AD2, excluding the edge of the second anode AD2 connected to the second anode contact pad ACP2 through the second via V2-1, and the corresponding second sub-pixel opening SA2 is not different. Optionally, the shortest distance between the edge of the third anode AD3, excluding one edge of the third anode AD3 connected to the third anode contact pad ACP3 through the third via V3-1, and the corresponding third sub-pixel opening SA3 is different.

[0144] FIG. 10 A partial structure of a voltage supply line according to some embodiments of the present disclosure is shown. Reference FIG. 10 In some embodiments, each of the plurality of voltage supply lines Vdd includes a first inclined portion INP1, a second inclined portion INP2, a first parallel portion PA1 connecting the first inclined portion INP1 and the second inclined portion INP2, and a second parallel portion PA2 connected to the first parallel portion PA1 via the second inclined portion INP2. The first parallel portion PA1 and the second parallel portion PA2 extend along directions substantially parallel to a second direction DR2. The first inclined portion INP1 extends along a first inclined angle α1 relative to the first direction DR1. The second inclined portion INP2 extends along a second inclined angle α2 relative to the first direction DR2. Optionally, the first inclined angle α1 and the second inclined angle α2 are supplementary angles, for example, α1 + α2 = 180°. The center lines of the first parallel portion PA1 and the second parallel portion PA2, respectively, along directions substantially parallel to the second direction DR2, are spaced apart by a width w greater than zero.

[0145] like FIG. 10 As shown, each of the multiple voltage supply lines Vdd comprises a repeating pattern of a first sloping portion INP1, a first parallel portion PA1, a second sloping portion INP2, and a second parallel portion PA2 connected in sequence. In the context of this disclosure, the term "repeating pattern" refers to a completely repeating pattern, or a substantially repeating pattern that allows deviations from a completely repeating pattern of less than 5% (e.g., less than 4%, less than 3%, less than 2%, or less than 1%). In the context of this disclosure, the repeating pattern need not be a repeating pattern that spans the entire array substrate. A repeating pattern can be a repeating pattern in a localized area of ​​the array substrate (e.g., the central region of the array substrate).

[0146] The first parallel portion in each of the plurality of voltage supply lines Vdd is arranged along a first arrangement direction substantially parallel to the second direction DR2. The second parallel portion in each of the plurality of voltage supply lines Vdd is arranged along a second arrangement direction substantially parallel to the second direction DR2. The first arrangement direction is substantially parallel to the second arrangement direction. As used herein, the term “substantially parallel” refers to an angle in the range of 0 degrees to about 45 degrees, for example, 0 degrees to about 5 degrees, 0 degrees to about 10 degrees, 0 degrees to about 15 degrees, 0 degrees to about 20 degrees, 0 degrees to about 25 degrees, 0 degrees to about 30 degrees.

[0147] Referring to FIG. 10 , FIG. 3A , FIG. 3F With FIG. 4B , the first inclined portion INP1, the first parallel portion PA1, and the second inclined portion INP2 collectively enclose a side of a connection portion CP connected to a respective one of the plurality of data lines DL through a via v4-1 extending through the first planarization layer PLN-1 and connected to the source S2 of the second transistor through a via v4-2 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI.

[0148] FIG. 11 A detailed structure of the anti-interference block is shown in accordance with some embodiments of the present disclosure. Referring to FIG. 3A , FIG. 4B and FIG. 11 , in some embodiments, the anti-interference block IPB includes a base B, a first arm AM1, and a second arm AM2. A respective one of the plurality of voltage supply lines Vdd is connected to the base B through a third main via v3. Optionally, the first arm AM1 includes a first terminal portion TP1 and a first connection bridge portion CP1 connecting the base B and the first terminal portion TP1. Optionally, the second arm AM2 includes a second terminal portion TP2, and a second connection bridge portion CP2 connecting the base B and the second terminal portion TP2.

[0149] Optionally, the first terminal portion TP1 and the first connection bridge portion CP1 are arranged along a direction substantially parallel to the second direction DR2. Optionally, the second terminal portion TP2 and the second connection bridge portion CP2 are arranged along a direction substantially parallel to the second direction DR2. Optionally, a longitudinal side of the base B is along a direction substantially parallel to the first direction DR1, and a lateral side of the base B is along a direction substantially parallel to the second direction DR2.

[0150] Optionally, the base portion B has a substantially rectangular shape. Optionally, the first tip portion TP1 has a substantially rectangular shape. Optionally, the second tip portion TP2 has a substantially rectangular shape. Optionally, the first connecting bridge portion CP1 has a pseudo triangular shape. Optionally, the second connecting bridge portion CP2 has a triangular shape.

[0151] FIG. 12 is a diagram illustrating FIG. 3A the superposition of the anodes and the light emitting layers in the plurality of sub-pixels of the array substrate shown. Reference is made to FIG. 12 In some embodiments, the first light emitting layer EM1 of the first light emitting element is connected to the first anode AD1 of the first light emitting element through the respective first sub-pixel opening SA1; the second light emitting layer EM2 of the second light emitting element is connected to the second anode AD2 of the second light emitting element through the respective second sub-pixel opening SA2; the third light emitting layer EM3 of the third light emitting element is connected to the third anode AD3 of the third light emitting element through the respective third sub-pixel opening SA3; and the fourth light emitting layer EM4 of the fourth light emitting element is connected to the fourth anode AD4 of the fourth light emitting element through the respective fourth sub-pixel opening SA4. Optionally, as shown in FIG. 12 the second light emitting layer EM2 and the fourth light emitting layer EM4 from two directly adjacent second light emitting elements and fourth light emitting elements, respectively, are part of the overall structure.

[0152] In some embodiments, the array substrate includes multiple first-type data lines (e.g., a fourth data line dl4) and multiple second-type data lines (e.g., a first data line dl1, a second data line dl2, and a third data line dl3). Optionally, a corresponding line of the multiple first-type data lines passes through a sub-pixel opening of a plurality of sub-pixels of a first color (e.g., a corresponding third sub-pixel opening SA3), but does not pass through any sub-pixel opening of a second color (e.g., a corresponding first sub-pixel opening SA1), nor does it pass through any sub-pixel opening of a third color (e.g., a corresponding second sub-pixel opening SA2 and a corresponding fourth sub-pixel opening SA4). The first color (e.g., blue), the second color (e.g., red), and the third color (e.g., green) are three different colors. A corresponding line of the multiple second-type data lines (e.g., a first data line dl1, a second data line dl2, and a third data line dl3) does not pass through any sub-pixel opening. Optionally, a first plane divides the corresponding sub-pixel opening of a first color sub-pixel into a first region and a second region. The first plane includes the orthographic projection of a corresponding one of a plurality of first-type data lines onto a second plane containing a pixel-defining layer. The first plane is orthogonal to the second plane. Optionally, the ratio of the first area of ​​the first region to the second area of ​​the second region is in the range of 2:8 to 8:2. Optionally, the ratio of the total number of the plurality of first-type data lines to the total number of the plurality of second-type data lines is in the range of 0.2 to 4, for example, 0.3 to 3, 0.4 to 2, or 0.5 to 1.5. FIG. 3I and FIG. 3J As shown, in one example, the ratio of the total number of multiple first-type data lines to the total number of multiple second-type data lines is 1:1.

[0153] FIG. 13 This is a diagram illustrating the structure of the anode in an array substrate according to some embodiments of the present disclosure. (See reference...) FIG. 13 In some embodiments, the first anode AD1 includes a body portion 1MP and a protrusion 1P projecting from one side of the body portion 1MP along a row direction (e.g., a first direction DR1). See also... FIG. 13 , FIG. 3A and FIG. 3C The orthographic projection of the protrusion 1P on the substrate at least partially overlaps with the orthographic projection of the semiconductor material portion (e.g., polysilicon portion) of the compensation transistor (e.g., the third transistor T3) on the substrate, the semiconductor material portion extending in the row direction. Optionally, the orthographic projection of the protrusion 1P on the substrate at least partially overlaps with the orthographic projection of the gate of the compensation transistor (e.g., the third transistor T3) on the substrate.

[0154] refer to FIG. 13In some embodiments, the second anode AD2 includes a main portion 2MP and a protrusion 2P protruding from one side of the main portion 2MP along the column direction (e.g., the second direction DR2). Referring to FIG. 13 , FIG. 3A and FIG. 3C , a projection of the protrusion 2P on the base substrate at least partially overlaps with a projection of a semiconductor material portion of a compensation transistor (e.g., the third transistor T3) on the base substrate, the semiconductor material portion extending along the row direction.

[0155] Referring to FIG. 13 , in some embodiments, the third anode AD3 includes a main portion 3MP and a first protrusion 3P and a second protrusion 3P’ protruding from two sides of the main portion 3MP along the row direction (e.g., the first direction DR1), respectively. Referring to FIG. 13 , FIG. 3A and FIG. 3C , a projection of the first protrusion 3P and the second protrusion 3P’ on a plane substantially overlaps with each other, the plane being parallel to the column direction (e.g., the second direction DR2) and intersecting (e.g., perpendicularly intersecting) the third anode AD3. Optionally, the first protrusion 3P and the second protrusion 3P’ are located on the same side of a gate line GL for controlling the third transistor T3. In one example, the first protrusion 3P and the second protrusion 3P’ are substantially arranged along the row direction. Optionally, a ratio of a first dimension of the first protrusion 3P along the column direction to a second dimension of the second protrusion 3P’ along the column direction is in a range of 0.1 to 8.0. Optionally, a ratio of a first area of the first protrusion 3P to a second area of the second protrusion 3P’ is in a range of 0.2 to 5. Referring to FIG. 13 , FIG. 3A and FIG. 3C , a projection of the first protrusion 3P on the base substrate at least partially overlaps with a projection of a first semiconductor material portion (e.g., a first polysilicon portion) of a compensation transistor (e.g., the third transistor T3) in a first adjacent sub-pixel on the base substrate, the first semiconductor material portion extending along the row direction. Optionally, a projection of the first protrusion 3P on the base substrate at least partially overlaps with a projection of a second semiconductor material portion (e.g., a second polysilicon portion) of a compensation transistor (e.g., the third transistor T3) in a second adjacent sub-pixel on the base substrate, the second semiconductor material portion extending along the row direction, the first adjacent sub-pixel and the second adjacent sub-pixel being directly adjacent to each other. Optionally, a ratio of a first area of the first protrusion 3P to a main area of the main portion 3MP is in a range of 0.01 to 0.1. Optionally, a ratio of a second area of the second protrusion 3P’ to the main area of the main portion 3MP is in a range of 0.02 to 0.2. Optionally, the second area of the second protrusion 3P’ is greater than the first area of the first protrusion 3P.

[0156] Referring to FIG. 3C In some embodiments, the first transistor T1 is located in a pixel driving circuit of a current stage, the reset transistor (e.g., the sixth transistor T6) is located in a second pixel driving circuit of a previous stage, and the first transistor T1 and the reset transistor are commonly controlled by a same reset control signal line (e.g., rst1 in FIG. 3D In some embodiments, referring to FIG. 3A , FIG. 3C and FIG. 3F , an initialization connection line (e.g., the second connection line Cl2 in FIG. 3F ) connects a respective one of a plurality of first reset signal lines rst and the source of the first transistor T1, the respective one of the plurality of first reset signal lines being configured to provide a reset signal to the source of the first transistor T1 through the initialization connection line. Optionally, the initialization connection line is located on a same side of the active layer or the gate of the first transistor T1 and the reset transistor along a row direction.

[0157] FIG. 14A is a diagram illustrating a structure of a second signal line layer in a plurality of sub-pixels of the array substrate shown in FIG. 3A is a diagram illustrating a superposition of an anode and a second signal line layer in a plurality of sub-pixels of an array substrate in some embodiments of the present disclosure. FIG. 14B is a diagram illustrating a superposition of a first signal line layer and a second signal line layer in a plurality of sub-pixels of an array substrate in some embodiments of the present disclosure. Referring to FIG. 14C In some embodiments, the second signal line layer further comprises a balancing block BB located between the first data line dl1 and the second data line dl2, the balancing block BB being electrically connected to a respective one of a plurality of voltage supply lines Vdd through a via extending through the first planarization layer PLN1. A footprint of the first anode AD1 on the base substrate at least partially overlaps a footprint of the balancing block BB on the base substrate. FIG. 14A to FIG. 14C Referring to

[0158] and FIG. 14A to FIG. 14C In some embodiments, a footprint of the main portion 1MP of the first anode AD1 on the base substrate at least partially overlaps a footprint of the first data line dl1 on the base substrate, and at least partially overlaps a footprint of the balancing block BB on the base substrate. A footprint of the protrusion 1P on the base substrate at least partially overlaps a footprint of the balancing block BB on the base substrate. FIG. 13

[0159] is a diagram illustrating a structure of a plurality of sub-pixels of an array substrate in some embodiments of the present disclosure. FIG. 14D is a cross-sectional view along the line H-H’ in FIG. 14E FIG. 14E FIG. 14A to FIG. 14E ​​As shown, along the first direction DR1, the first data line dl1 and the orthographic projection of the balance block BB on the base substrate BS are respectively located on opposite sides of the orthographic projection of the corresponding first sub-pixel opening SA1 on the base substrate BS. The orthographic projection of the corresponding first sub-pixel opening SA1 on the base substrate BS does not overlap with the orthographic projection of the first data line dl1 on the base substrate BS, and does not overlap with the orthographic projection of the balance block BB on the base substrate BS. By locating the balance block BB under the first anode AD1, the signal lines (the first data line dl1 and the balance block BB) are more evenly distributed under the left and right portions of the first anode AD1, thereby preventing the first anode AD1 from tilting. Thus, the color shift problem can be mitigated.

[0160] In another aspect, the present disclosure provides a display panel comprising the array substrate described herein or manufactured by the method described herein and a counter substrate facing the array substrate. Optionally, the display panel is an organic light-emitting diode display panel. Optionally, the display panel is a micro light-emitting diode display panel.

[0161] In another aspect, the present disclosure provides a display device comprising the array substrate described herein or manufactured by the method described herein and one or more integrated circuits connected to the array substrate.

[0162] In another aspect, the present disclosure provides a method of manufacturing an array substrate. In some embodiments, the method includes forming a plurality of data lines on a base substrate; forming a plurality of light emitting elements in a plurality of sub-pixels, respectively; and forming a pixel defining layer on the base substrate, the pixel defining layer defining a plurality of sub-pixel openings. Optionally, forming the plurality of light emitting elements includes forming a first light emitting element in a corresponding first sub-pixel, forming a second light emitting element in a corresponding second sub-pixel, forming a third light emitting element in a corresponding third sub-pixel, and forming a fourth light emitting element in a corresponding fourth sub-pixel. Optionally, forming the plurality of sub-pixel openings includes forming a corresponding first sub-pixel opening, forming a corresponding second sub-pixel opening, forming a corresponding third sub-pixel opening, and forming a corresponding fourth sub-pixel opening, the sub-pixel openings extending through the pixel defining layer, respectively. Optionally, a first light emitting layer of the first light emitting element is formed to connect to a first anode of the first light emitting element through the corresponding first sub-pixel opening. Optionally, a second light emitting layer of the second light emitting element is formed to connect to a second anode of the second light emitting element through the corresponding second sub-pixel opening. Optionally, a third light emitting layer of the third light emitting element is formed to connect to a third anode of the third light emitting element through the corresponding third sub-pixel opening. Optionally, a fourth light emitting layer of the fourth light emitting element is formed to connect to a fourth anode of the fourth light emitting element through the corresponding fourth sub-pixel opening. Optionally, forming the plurality of data lines includes forming a first data line, forming a second data line, forming a third data line, and forming a fourth data line, the data lines configured to provide data signals to the corresponding first sub-pixel, the corresponding second sub-pixel, the corresponding third sub-pixel, and the corresponding fourth sub-pixel, respectively. Optionally, the data lines are formed such that each of the corresponding first sub-pixel opening, the corresponding second sub-pixel opening, and the corresponding fourth sub-pixel opening is not crossed by any of the data lines. Optionally, the corresponding third sub-pixel opening is crossed by one of the plurality of data lines.

[0163] In some embodiments, the plurality of sub-pixel openings includes a plurality of minimum repeating units, each minimum repeating unit of the plurality of minimum repeating units including a corresponding first sub-pixel opening, a corresponding second sub-pixel opening, a corresponding third sub-pixel opening, and a corresponding fourth sub-pixel opening; the plurality of data lines includes a plurality of data line repeating groups, each group of the plurality of data line repeating groups including a first data line, a second data line, a third data line, and a fourth data line arranged contiguously, and configured to provide data signals to the corresponding first sub-pixel, the corresponding second sub-pixel, the corresponding third sub-pixel, and the corresponding fourth sub-pixel, respectively. Optionally, the fourth data line is formed to cross the corresponding third sub-pixel opening.

[0164] In some embodiments, the respective first sub-pixel opening, the respective second sub-pixel opening, the respective third sub-pixel opening and the respective fourth sub-pixel opening in a respective one of the plurality of repeating units are arranged continuously along a row. The first data line, the second data line, the third data line and the fourth data line are arranged continuously along the row. The respective first sub-pixel opening is formed between the first data line and the second data line. The respective second sub-pixel opening is formed between the second data line and the third data line. The respective third sub-pixel opening is formed to be passed through by the fourth data line. The respective fourth sub-pixel opening is formed on a side of the fourth data line away from the third data line.

[0165] In some embodiments, the respective first sub-pixel opening, the respective second sub-pixel opening, the respective third sub-pixel opening and the respective fourth sub-pixel opening are in a first minimum repeating unit in a first row of two closest adjacent rows; a second minimum repeating unit in a second row of the two closest adjacent rows has a displacement relative to the first minimum repeating unit along a row direction of twice an inter-data-line distance, the inter-data-line distance being a shortest distance between two closest data lines along the row direction. The second minimum repeating unit in the second row comprises a second respective first sub-pixel opening, a second respective second sub-pixel opening, a second respective third sub-pixel opening and a second respective fourth sub-pixel opening arranged continuously along the row. Optionally, the second data line is formed to pass through the second respective second sub-pixel opening in the second row.

[0166] In some embodiments, a first plane containing a normal projection of the fourth data line on a second plane containing a surface of the pixel-defining layer divides the respective third sub-pixel opening into a first area and a second area. Optionally, the first plane is orthogonal to the second plane. Optionally, a ratio of a first area of the first area to a second area of the second area is in a range from 2:8 to 8:2.

[0167] In some embodiments, a ratio of a first area of the first area to a second area of the second area is in a range from 1:1.5 to 1.5:1. Optionally, the respective third sub-pixel opening is formed to be substantially mirror-symmetrical with respect to a plane that is perpendicular to the pixel-defining layer and intersects a normal projection of the fourth data line on the pixel-defining layer.

[0168] In some embodiments, the fourth data line is formed to pass through the third anode. Optionally, a normal projection of the fourth data line on the third anode divides the third anode into a first anode area and a second anode area. Optionally, a ratio of a first area of the first anode area to a second area of the second anode area is in a range from 2:8 to 8:2.

[0169] In some embodiments, an area of a positive projection of any of the data lines on the second anode is less than an area of a positive projection of any of the data lines on the first anode, and less than an area of a positive projection of any of the data lines on the third anode. In some embodiments, an area of a positive projection of any of the data lines on the fourth anode is less than an area of a positive projection of any of the data lines on the first anode, and less than an area of a positive projection of any of the data lines on the third anode.

[0170] In some embodiments, none of the data lines of the plurality of data lines are formed to pass through the second anode or the fourth anode.

[0171] In some embodiments, an edge of the first anode is at least partially covered by a positive projection of a data line on the first anode adjacent to the edge of the first anode.

[0172] In some embodiments, none of the data lines of the plurality of data lines are formed to pass through the first anode.

[0173] In some embodiments, the plurality of sub-pixels of the array substrate are formed to have a minimum repeating unit comprising a respective first sub-pixel, a respective second sub-pixel, a respective third sub-pixel, and a respective fourth sub-pixel. Optionally, the respective second sub-pixel and the respective fourth sub-pixel are sub-pixels of a same color, which is different from a color of the respective first sub-pixel and different from a color of the respective third sub-pixel. Optionally, the second light emitting element and the fourth light emitting element are light emitting elements of a same color, which is different from a color of the first light emitting element and different from a color of the third light emitting element. Optionally, the first anode, the second anode, and the third anode are formed to have different areas and different shapes. Optionally, the first anode, the third anode, and the fourth anode are formed to have different areas and different shapes. Optionally, the first anode, the second anode, the third anode, and the fourth anode are formed to have different areas and different shapes.

[0174] In some embodiments, the second anode and the fourth anode are anodes of two light emitting elements of the same color. Optionally, the second anode is formed to include a first main portion, a first extra portion, and a second extra portion. Optionally, the fourth anode is formed to include a second main portion and a third extra portion. Optionally, the first main portion is a combination of a rectangular portion and a triangular portion. Optionally, the second main portion is a combination of a rectangular portion and a triangular portion. Optionally, the first main portion and the second main portion have substantially the same shape. Optionally, the first extra portion is adjacent to the triangular portion of the first main portion. Optionally, the second extra portion is adjacent to a side of the rectangular portion of the first main portion that is away from the triangular portion of the first main portion. Optionally, the third extra portion is adjacent to the triangular portion of the second main portion. Optionally, the first extra portion, the first main portion, and the second extra portion are arranged in sequence along a direction substantially parallel to the plurality of data lines. Optionally, the second main portion and the third extra portion are arranged in sequence along a direction substantially parallel to the plurality of data lines.

[0175] In some embodiments, the method further includes forming a plurality of gate lines, forming a plurality of first reset control signal lines, forming a plurality of first reset signal lines, forming a plurality of voltage supply lines, forming a plurality of pixel driving circuits respectively in a plurality of sub-pixels and configured to respectively drive a plurality of light emitting elements, forming a semiconductor material layer on the base substrate, and forming a node connection line. The plurality of gate lines, the plurality of first reset control signal lines, and the plurality of first reset signal lines are formed to respectively extend along a first direction. The plurality of voltage supply lines are formed to respectively extend along a second direction. Optionally, forming a respective one of the plurality of pixel driving circuits includes forming a plurality of transistors, and forming a storage capacitor. Optionally, forming the storage capacitor includes forming a first capacitor electrode, forming a second capacitor electrode electrically connected to a respective voltage supply line, and forming an insulating layer. The insulating layer is formed between the first capacitor electrode and the second capacitor electrode. Optionally, the node connection line is formed in a same layer as the respective voltage supply line, connected to the first capacitor electrode through a first main via, and connected to the semiconductor material layer through a second main via. Optionally, a first anode of the first light emitting element in each first sub-pixel has a footprint on the base substrate that at least partially overlaps with a footprint of the node connection line on the base substrate in the respective first sub-pixel. Optionally, a second anode of the second light emitting element in each second sub-pixel has a footprint on the base substrate that at least partially overlaps with a footprint of the node connection line on the base substrate in the respective second sub-pixel. Optionally, a third anode of the third light emitting element in each third sub-pixel has a footprint on the base substrate that at least partially overlaps with a footprint of the node connection line on the base substrate in the respective third sub-pixel, and at least partially overlaps with a footprint of the node connection line on the base substrate in the respective fourth sub-pixel.

[0176] In some embodiments, the footprint of the first anode in the respective first sub-pixel on the base substrate covers a portion of the footprint of the node connection line on the base substrate in the respective first sub-pixel at a location connected to the first capacitor electrode. Optionally, the footprint of the second anode in the respective second sub-pixel on the base substrate covers a portion of the footprint of the node connection line on the base substrate in the respective second sub-pixel at a location connected to the first capacitor electrode. Optionally, the footprint of the third anode in the respective third sub-pixel on the base substrate covers a portion of the footprint of the node connection line on the base substrate in the respective fourth sub-pixel at a location connected to the first capacitor electrode, and partially overlaps with a portion of the footprint of the node connection line on the base substrate in the respective third sub-pixel at a location connected to the first capacitor electrode.

[0177] In some embodiments, a positive projection of the third anode onto the base substrate at least partially overlaps a positive projection of a third transistor in the respective third sub-pixel onto the base substrate and at least partially overlaps a positive projection of a third transistor in the respective fourth sub-pixel onto the base substrate, the respective fourth sub-pixel being adjacent to the respective third sub-pixel.

[0178] In some embodiments, a positive projection of the third anode onto the base substrate partially overlaps a positive projection of an active layer of the third transistor in the respective third sub-pixel onto the base substrate, covers a positive projection of a source of a third transistor in the respective fourth sub-pixel onto the base substrate, and partially overlaps a positive projection of an active layer of the third transistor in the respective fourth sub-pixel onto the base substrate.

[0179] In some embodiments, a positive projection of the first anode onto the base substrate at least partially overlaps a positive projection of a third transistor in the respective first sub-pixel onto the base substrate.

[0180] In some embodiments, a positive projection of the first anode onto the base substrate covers a positive projection of a source of a third transistor in each first sub-pixel onto the base substrate and partially overlaps a positive projection of an active layer of a third transistor in each first sub-pixel onto the base substrate.

[0181] In some embodiments, a positive projection of the second anode onto the base substrate at least partially overlaps a positive projection of a third transistor in the respective second sub-pixel onto the base substrate.

[0182] In some embodiments, a positive projection of the second anode onto the base substrate partially overlaps a positive projection of an active layer of a third transistor in the respective second sub-pixel onto the base substrate.

[0183] In some embodiments, the method further includes forming a semiconductor material layer on the base substrate; forming a gate insulating layer on a side of the semiconductor material layer distal from the base substrate; forming an insulating layer on a side of the gate insulating layer distal from the base substrate; forming an interlayer dielectric layer on a side of the insulating layer distal from the gate insulating layer; a relay electrode layer on a side of the interlayer dielectric layer distal from the insulating layer; forming a first planarization layer on a side of the relay electrode layer distal from the interlayer dielectric layer; forming an anode contact pad layer on a side of the first planarization layer distal from the interlayer dielectric layer; and forming a second planarization layer on a side of the anode contact pad layer distal from the first planarization layer. Optionally, the pixel defining layer is formed on a side of the second planarization layer distal from the base substrate. Optionally, each anode is formed on a side of the second planarization layer distal from the first planarization layer; and each light emitting layer is formed on a side of each anode distal from the second planarization layer. Optionally, in the respective first sub-pixel, the first anode is formed to be connected to a first anode contact pad through a first via extending through the second planarization layer; in the respective second sub-pixel, the second anode is formed to be connected to a second anode contact pad through a second via extending through the second planarization layer; in the respective third sub-pixel, the third anode is formed to be connected to a third anode contact pad through a third via extending through the second planarization layer; and in the respective fourth sub-pixel, the fourth anode is formed to be connected to a fourth anode contact pad through a fourth via extending through the second planarization layer.

[0184] In some embodiments, the shortest distance between each edge of the first anode other than the edge of the first anode connected to the first anode contact pad through the first via and the respective first sub-pixel opening is different. Optionally, the shortest distance between each edge of the second anode other than the edge of the second anode connected to the second anode contact pad through the second via and the respective second sub-pixel opening is different. Optionally, the shortest distance between each edge of the third anode other than the edge of the third anode connected to the third anode contact pad through the third via and the respective third sub-pixel opening is different.

[0185] In some embodiments, forming a respective one of the plurality of voltage supply lines includes forming a first inclined portion, forming a second inclined portion, forming a first parallel portion connecting the first inclined portion and the second inclined portion, and forming a second parallel portion connected to the first parallel portion through the second inclined portion. Optionally, the first parallel portion and the second parallel portion are formed to respectively extend along a direction substantially parallel to the second direction. Optionally, the first inclined portion is formed to extend along a first inclined angle with respect to the first direction. Optionally, the second inclined portion is formed to extend along a second inclined angle with respect to the first direction. Optionally, the first inclined angle and the second inclined angle are complementary angles. Optionally, the first parallel portion and the second parallel portion are spaced apart by a width w greater than zero along a center line thereof in the direction substantially parallel to the second direction. Optionally, each of the plurality of voltage supply lines is formed to include a repeating pattern of sequentially connected first inclined portion, first parallel portion, second inclined portion, and second parallel portion. Optionally, the first parallel portion in each of the plurality of voltage supply lines is arranged along a first arrangement direction substantially parallel to the second direction. Optionally, the second parallel portion in each of the plurality of voltage supply lines is arranged along a second arrangement direction substantially parallel to the second direction. Optionally, the first parallel portion and the second inclined portion are combined to form a side around a connection portion connected to a respective one of the plurality of data lines through a via extending through the first planarization layer and connected to a source of the second transistor through a via extending through the interlayer dielectric layer, the insulating layer, and the gate insulating layer.

[0186] In some embodiments, the method further comprises forming an anti-interference block in a same layer as the second capacitor electrode, a respective one of the plurality of voltage supply lines being connected to the anti-interference block through a third main via. Optionally, forming the anti-interference block comprises forming a base portion, forming a first arm, and forming a second arm. Optionally, the respective one of the plurality of voltage supply lines is formed to be connected to the base portion through the third main via. Optionally, forming the first arm comprises forming a first end portion and forming a first connecting bridge portion connecting the base portion and the first end portion. Optionally, forming the second arm comprises forming a second end portion and forming a second connecting bridge portion connecting the base portion and the second end portion. Optionally, the first end portion and the first connecting bridge portion are arranged along a direction substantially parallel to the second direction. Optionally, the second end portion and the second connecting bridge portion are arranged along a direction substantially parallel to the second direction. Optionally, a longitudinal side of the base portion is along a direction substantially parallel to the first direction. Optionally, a transverse side of the base portion is along a direction substantially parallel to the second direction. Optionally, the base portion has a substantially rectangular shape. Optionally, the first end portion has a substantially rectangular shape. Optionally, the second end portion has a substantially rectangular shape. Optionally, the first connecting bridge portion has a pseudo-triangular shape. Optionally, the second connecting bridge portion has a triangular shape.

[0187] The foregoing description of embodiments of the application has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the application to the precise form disclosed. The description was presented as illustrative of the broadest aspects of the application that are and were anticipated to be within the scope of the application. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described in order to best explain the principles of the application and its best mode of practical application to thereby enable others skilled in the art to best utilize the application and various embodiments with various modifications as are suited to the particular use or implementation. The scope of the application is intended to be defined by the claims appended hereto and their equivalents, wherein all terms are meant to be construed in their broadest reasonable sense unless otherwise indicated. Accordingly, the terms "the invention," "the present invention," and the like, do not necessarily refer to the description throughout this entire patent document or to any particular embodiment described herein. Rather, these terms mean "one" or "an" embodiment of the present application, and this application can include any number of embodiments, including singular and plural alternatives. The language of this patent document is not legally intended to limit the scope of the present application unless otherwise explicitly so stated. The claims appended hereto are intended to be construed to cover the alternatives and modifications as would be included within the spirit and scope of the present application. Furthermore, the claims can refer to use of "a first," "a second," and / or "the other" element, member, step, etc. These claims should be interpreted to be naming the elements in a broad manner and should not be interpreted to be limiting the elements to the number of elements specified. Any advantages and benefits of the described embodiments are not to be construed as limitations on the scope of the application, but as exemplifications of the various forms the application can take. It is to be understood that not necessarily all objects or advantages can be achieved in accordance with any particular embodiment described herein and that therefore not necessarily every embodiment described herein will be practiced. Also, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains" or "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises, has, contains, or contains any element or a combination thereof, can include additional elements not expressly listed or the element can be integral to the process, method, article, or apparatus. Any steps, operations, processes or functions specified in the description or claims can be performed in any order or simultaneously.

Claims

1. An array substrate comprising a plurality of first type data lines and a plurality of second type data lines; wherein each of the plurality of first type data lines passes through sub-pixel openings of a plurality of sub-pixels of a first color and does not pass through sub-pixel openings of any sub-pixel of a second color nor any sub-pixel of a third color, the first color, the second color and the third color being three different colors; each of the plurality of second type data lines does not pass through any sub-pixel opening; a first plane divides a respective sub-pixel opening of the sub-pixel of the first color into a first area and a second area, wherein the first plane contains a normal projection of a respective one of the plurality of first type data lines on a second plane, and the second plane contains a surface of a pixel defining layer, the first plane being orthogonal to the second plane; and a ratio of a first area of the first area to a second area of the second area is in a range of 2:8 to 8:2; the array substrate further comprises: a third anode of a third light emitting element, the third anode comprising a main portion, a first protruding portion and a second protruding portion protruding from two sides of the third anode main portion along a first direction, respectively; the first protruding portion and the second protruding portion are located on a same side of a gate line of a third transistor; a ratio of a first dimension of the first protruding portion along a second direction to a second dimension of the second protruding portion along the second direction is in a range of 0.1 to 8.0; and a ratio of a first area of the first protruding portion to a second area of the second protruding portion is in a range of 0.1 to 8.

0.

2. The array substrate according to claim 1, wherein, a ratio of a total number of the plurality of first type data lines to a total number of the plurality of second type data lines is in a range of 0.2 to 4.

3. The array substrate of claim 1, further comprising a first anode of a first light emitting element, the first anode comprising a main portion and a protruding portion protruding from one side of the first anode main portion along a first direction; and a normal projection of the protruding portion of the first anode on a base substrate at least partially overlaps a normal projection of a semiconductor material portion of a third transistor on the base substrate, the semiconductor material portion extending along the first direction.

4. The array substrate according to claim 3, wherein, a normal projection of the protruding portion of the first anode on the base substrate at least partially overlaps a normal projection of a gate of a third transistor on the base substrate.

5. The array substrate of claim 1, further comprising a second anode of a second light emitting element, the second anode comprising a main portion and a protruding portion protruding from one side of the second anode main portion along a second direction; and a normal projection of the protruding portion of the second anode on a base substrate at least partially overlaps a normal projection of a semiconductor material portion of a third transistor on the base substrate, the semiconductor material portion extending along a first direction.

6. The array substrate of claim 1, wherein, a ratio of a first area of the first protruding portion to a main area of the third anode main portion is in a range of 0.01 to 0.1; a ratio of a second area of the second protruding portion to the main area of the third anode main portion is in a range of 0.02 to 0.2; and a ratio of a first area of the first protruding portion to a main area of the third anode main portion is in a range of 0.01 to 0.1; a ratio of a second area of the second protruding portion to the main area of the third anode main portion is in a range of 0.02 to 0.2; and The second area of the second protrusion is greater than the first area of the first protrusion.

7. The array substrate of claim 1, wherein, A projection of the first protrusion on a base substrate at least partially overlaps with a projection of a first semiconductor material portion of a third transistor in a first adjacent sub-pixel on the base substrate, the first semiconductor material portion extending along a first direction; and A projection of the first protrusion on the base substrate at least partially overlaps with a projection of a second semiconductor material portion of the third transistor in a second adjacent sub-pixel on the base substrate, the second semiconductor material portion extending along the first direction, the first adjacent sub-pixel and the second adjacent sub-pixel being directly adjacent to each other.

8. The array substrate of claim 1, wherein, A shortest distance between a sub-pixel opening and an edge of an anode other than an edge of the anode connected to an anode contact pad is different; wherein the light-emitting layer is connected to the anode through the sub-pixel opening extending through the pixel-defining layer.

9. The array substrate of claim 1, comprising: a first transistor in a pixel driving circuit of a current stage; a sixth transistor in a second pixel driving circuit in a previous stage, wherein the first transistor and the sixth transistor are commonly controlled by a same reset control signal line; a plurality of first reset signal lines; and an initialization connection line connecting a respective one of the plurality of first reset signal lines and a source of the first transistor, the respective one of the plurality of first reset signal lines being configured to provide a reset signal to the source of the first transistor through the initialization connection line; wherein the initialization connection line is located on a same side of an active layer or a gate of the first transistor and an active layer or a gate of the sixth transistor along a first direction.

10. The array substrate of claim 1, further comprising: a first planarization layer; a first data line and a balance block on the first planarization layer, wherein the balance block is electrically connected to a respective one of a plurality of voltage supply lines through a via extending through the first planarization layer; a second planarization layer on a side of the first data line and the balance block away from the first planarization layer; a first anode of a first light-emitting element on a side of the second planarization layer away from the first planarization layer; and a pixel-defining layer on a side of the first anode away from the second planarization layer and defining a respective first sub-pixel opening; wherein a projection of the first anode on a base substrate at least partially overlaps with a projection of the balance block on the base substrate and at least partially overlaps with a projection of the first data line on the base substrate.

11. The array substrate of claim 10, wherein, In a first direction, the projections of the first data line and the balance block on the base substrate are respectively located on opposite sides of a projection of the respective first sub-pixel opening on the base substrate; and the projection of the respective first sub-pixel opening on the base substrate does not overlap with the projection of the first data line on the base substrate and does not overlap with the projection of the balance block on the base substrate.

12. The array substrate of claim 10, wherein, The first anode includes a main portion and a protruding portion protruding from one side of the first anode main portion in a first direction; A projection of the protruding portion on the base substrate at least partially overlaps with a projection of a semiconductor material portion of a third transistor on the base substrate, the semiconductor material portion extending in the first direction; A projection of the first anode main portion on the base substrate at least partially overlaps with a projection of the first data line on the base substrate, and at least partially overlaps with a projection of the balance mass on the base substrate; and A projection of the protruding portion on the base substrate at least partially overlaps with a projection of the balance mass on the base substrate.

13. The array substrate of claim 1, comprising: a base substrate; a plurality of data lines; a plurality of light emitting elements in a plurality of sub-pixels, respectively; and a pixel defining layer on the base substrate, the pixel defining layer defining a plurality of sub-pixel openings; wherein the plurality of light emitting elements includes a first light emitting element in each first sub-pixel, a second light emitting element in each second sub-pixel, a third light emitting element in each third sub-pixel, and a fourth light emitting element in each fourth sub-pixel; the plurality of sub-pixel openings includes each first sub-pixel opening, each second sub-pixel opening, each third sub-pixel opening, each fourth sub-pixel opening extending through the pixel defining layer, respectively; a first light emitting layer of the first light emitting element is connected to a first anode of the first light emitting element through the corresponding first sub-pixel opening; a second light emitting layer of the second light emitting element is connected to a second anode of the second light emitting element through the corresponding second sub-pixel opening; a third light emitting layer of the third light emitting element is connected to a third anode of the third light emitting element through the corresponding third sub-pixel opening; a fourth light emitting layer of the fourth light emitting element is connected to a fourth anode of the fourth light emitting element through the corresponding fourth sub-pixel opening; each of the each first sub-pixel opening, the each second sub-pixel opening, and the each fourth sub-pixel opening is not crossed by any data line; and one data line of the plurality of data lines crosses the corresponding third sub-pixel opening. the plurality of sub-pixel openings includes a plurality of minimum repeating units, each minimum repeating unit of the plurality of minimum repeating units includes a corresponding first sub-pixel opening, a corresponding second sub-pixel opening, a corresponding third sub-pixel opening, and a corresponding fourth sub-pixel opening; 14. The array substrate of claim 13, wherein, the plurality of data lines includes a plurality of data line repeating groups, each group of the plurality of data line repeating groups includes a first data line, a second data line, a third data line, and a fourth data line arranged contiguously, and is configured to provide data signals to the corresponding first sub-pixel, the corresponding second sub-pixel, the corresponding third sub-pixel, and the corresponding fourth sub-pixel, respectively; and the fourth data line crosses the corresponding third sub-pixel opening. ​ 15. The array substrate of claim 14, wherein, the respective first sub-pixel opening, the respective second sub-pixel opening, the respective third sub-pixel opening and the respective fourth sub-pixel opening in each of the plurality of minimum repeat units are arranged continuously along a row; the first data line, the second data line, the third data line and the fourth data line are arranged continuously along the row; the respective first sub-pixel opening is between the first data line and the second data line; the respective second sub-pixel opening is between the second data line and the third data line; the fourth data line passes through the respective third sub-pixel opening; and the respective fourth sub-pixel opening is located on a side of the fourth data line away from the third data line.

16. The array substrate of claim 15, wherein, the respective first sub-pixel opening, the respective second sub-pixel opening, the respective third sub-pixel opening and the respective fourth sub-pixel opening are located in a first minimum repeat unit in a first row of two closest adjacent rows; a second minimum repeat unit in a second row of the two closest adjacent rows has a displacement of twice an inter-data-line distance relative to the first minimum repeat unit along a first direction, the inter-data-line distance being a shortest distance between two closest data lines along the first direction; the second minimum repeat unit in the second row comprises a second respective first sub-pixel opening, a second respective second sub-pixel opening, a second respective third sub-pixel opening and a second respective fourth sub-pixel opening arranged continuously along the row; and the second data line passes through the second respective second sub-pixel opening in the second row.

17. The array substrate of claim 14, wherein, a first plane divides the respective third sub-pixel opening into a first region and a second region, wherein the first plane contains a normal projection of the fourth data line on a second plane, and the second plane contains a surface of the pixel-defining layer, the first plane being perpendicular to the second plane; and a ratio of a first area of the first region to a second area of the second region is in a range of 2:8 to 8:

2.

18. The array substrate of claim 17, wherein, a ratio of a first area of the first region to a second area of the second region is in a range of 1:1.5 to 1.5:1; and the respective third sub-pixel opening is substantially mirror-symmetrical relative to a plane perpendicular to the pixel-defining layer and intersecting a normal projection of the fourth data line on the pixel-defining layer.

19. The array substrate of claim 14, wherein, the fourth data line passes through the third anode; a normal projection of the fourth data line on the third anode divides the third anode into a first anode region and a second anode region; and a ratio of a first area of the first anode region to a second area of the second anode region is in a range of 2:8 to 8:

2.

20. The array substrate of claim 13, wherein, an area of a normal projection of any data line on the second anode is smaller than an area of a normal projection of any data line on the first anode, and smaller than an area of a normal projection of any data line on the third anode; and an area of a normal projection of any data line on the fourth anode is smaller than an area of a normal projection of any data line on the first anode, and smaller than an area of a normal projection of any data line on the third anode.

21. The array substrate of claim 20, wherein, an edge of the second anode is at least partially covered by a normal projection, onto the second anode, of a data line adjacent to the edge of the second anode; and an edge of the fourth anode is at least partially covered by a normal projection, onto the fourth anode, of a data line adjacent to the edge of the fourth anode.

22. The array substrate of claim 13, wherein, an edge of the first anode is at least partially covered by a normal projection, onto the first anode, of a data line adjacent to the edge of the first anode.

23. The array substrate of claim 13, wherein, a minimum repeating unit of the plurality of sub-pixels of the array substrate includes a respective first sub-pixel, a respective second sub-pixel, a respective third sub-pixel, and a respective fourth sub-pixel; the respective second sub-pixel and the respective fourth sub-pixel are sub-pixels of a same color, which color is different from a color of the respective first sub-pixel and different from a color of the respective third sub-pixel; the second light emitting element and the fourth light emitting element are light emitting elements of a same color, which color is different from a color of the first light emitting element and different from a color of the third light emitting element; the first anode, the second anode, and the third anode have different areas and different shapes; and the first anode, the third anode, and the fourth anode have different areas and different shapes.

24. The array substrate of claim 23, wherein, the second anode and the fourth anode are anodes of two light emitting elements of a same color; the second anode includes a first main portion, a first extra portion, and a second extra portion; the fourth anode includes a second main portion and a third extra portion; the first main portion is a combination of a rectangular portion and a triangular portion; the second main portion is a combination of a rectangular portion and a triangular portion; the first main portion and the second main portion have substantially the same shape; the first extra portion is adjacent to a triangular portion of the first main portion; the second extra portion is adjacent to a side of a rectangular portion of the first main portion that is away from a triangular portion of the first main portion; the third extra portion is adjacent to a triangular portion of the second main portion; the first extra portion, the first main portion, and the second extra portion are sequentially arranged along a direction substantially parallel to the plurality of data lines; and the second main portion and the third extra portion are sequentially arranged along a direction substantially parallel to the plurality of data lines.

25. The array substrate of claim 13, further comprising a first anode of a first light emitting element, the first anode including a main portion and a protrusion protruding from a side of the first anode main portion along a first direction; and a normal projection, onto the base substrate, of the protrusion of the first anode at least partially overlaps a normal projection, onto the base substrate, of a semiconductor material portion of a third transistor, the semiconductor material portion extending along the first direction.

26. The array substrate of claim 13, further comprising a second anode of a second light emitting element, the second anode including a main portion and a protrusion, the protrusion of the second anode protruding from a side of the main portion of the second anode that is away from a portion of the second anode connected to an anode contact pad along a second direction; and a normal projection, onto the base substrate, of the protrusion of the second anode at least partially overlaps a normal projection, onto the base substrate, of a semiconductor material portion of a third transistor, the semiconductor material portion extending along the second direction. A projection of the second anode onto the base substrate at least partially overlaps with a projection of a semiconductor material portion of a third transistor onto the base substrate, the semiconductor material portion extending along the first direction.

27. The array substrate of claim 1, wherein, Comprises: a base substrate; a projection of the first protrusion onto the base substrate at least partially overlaps with a projection of a first semiconductor material portion of a third transistor in a first adjacent sub-pixel onto the base substrate, the first semiconductor material portion extending along the first direction; and a projection of the first protrusion onto the base substrate at least partially overlaps with a projection of a second semiconductor material portion of the third transistor in a second adjacent sub-pixel onto the base substrate, the second semiconductor material portion extending along the first direction, the first adjacent sub-pixel and the second adjacent sub-pixel being directly adjacent to each other.

28. The array substrate of claim 13, further comprising: a plurality of pixel driving circuits respectively in the plurality of sub-pixels and configured to respectively drive a plurality of light emitting elements, wherein each pixel driving circuit of the plurality of pixel driving circuits comprises a plurality of transistors and a storage capacitor, the storage capacitor comprising a first capacitor electrode, a second capacitor electrode electrically connected to a corresponding voltage supply line, and an insulating layer between the first capacitor electrode and the second capacitor electrode; a semiconductor material layer on the base substrate; and a node connection line in a same layer as the corresponding voltage supply line, the node connection line connected to the first capacitor electrode through a first main via and to the semiconductor material layer through a second main via; wherein a projection of a first anode of the first light emitting element in a corresponding first sub-pixel onto the base substrate at least partially overlaps with a projection of the node connection line in the corresponding first sub-pixel onto the base substrate; a projection of a second anode of the second light emitting element in a corresponding second sub-pixel onto the base substrate at least partially overlaps with a projection of the node connection line in the corresponding second sub-pixel onto the base substrate; and a projection of a third anode of the third light emitting element in a corresponding third sub-pixel onto the base substrate at least partially overlaps with a projection of the node connection line in the corresponding third sub-pixel onto the base substrate, and at least partially overlaps with a projection of the node connection line in a corresponding fourth sub-pixel onto the base substrate.

29. The array substrate of claim 28, wherein, the projection of the first anode in the corresponding first sub-pixel onto the base substrate covers a portion of the projection of the node connection line in the corresponding first sub-pixel onto the base substrate at a location where the node connection line is connected to the first capacitor electrode; the projection of the second anode in the corresponding second sub-pixel onto the base substrate covers a portion of the projection of the node connection line in the corresponding second sub-pixel onto the base substrate at a location where the node connection line is connected to the first capacitor electrode; and ​ A normal projection of the third anode on the base substrate covers a normal projection of a portion of the node connection line in the corresponding fourth sub-pixel at a location connected to the first capacitor electrode on the base substrate, and partially overlaps with a normal projection of a portion of the node connection line in the corresponding third sub-pixel at a location connected to the first capacitor electrode on the base substrate.

30. The array substrate of claim 28, wherein, A normal projection of the third anode on the base substrate at least partially overlaps with a normal projection of a third transistor in the corresponding third sub-pixel on the base substrate, and at least partially overlaps with a normal projection of a third transistor in the corresponding fourth sub-pixel on the base substrate, the corresponding fourth sub-pixel being adjacent to the corresponding third sub-pixel.

31. The array substrate of claim 30, wherein, A normal projection of the third anode on the base substrate at least partially overlaps with a normal projection of an active layer of the third transistor in the corresponding third sub-pixel on the base substrate, at least partially overlaps with a normal projection of a source of a third transistor in the corresponding fourth sub-pixel on the base substrate, and at least partially overlaps with a normal projection of an active layer of the third transistor in the corresponding fourth sub-pixel on the base substrate.

32. The array substrate of claim 28, wherein, A normal projection of the first anode on the base substrate at least partially overlaps with a normal projection of a third transistor in the corresponding first sub-pixel on the base substrate.

33. The array substrate of claim 32, wherein, A normal projection of the first anode on the base substrate covers a normal projection of a portion of the source of the third transistor in the corresponding first sub-pixel on the base substrate, and at least partially overlaps with a normal projection of a portion of the active layer of the third transistor in the corresponding first sub-pixel on the base substrate.

34. The array substrate of claim 28, wherein, A normal projection of the second anode on the base substrate at least partially overlaps with a normal projection of a third transistor in the corresponding second sub-pixel on the base substrate.

35. The array substrate of claim 34, wherein, A normal projection of the second anode on the base substrate partially overlaps with a normal projection of an active layer of the third transistor in the corresponding second sub-pixel on the base substrate.

36. The array substrate of claim 28, further comprising: a layer of semiconductor material on the base substrate; a gate insulating layer on a side of the layer of semiconductor material distal from the base substrate; an insulating layer on a side of the gate insulating layer distal from the base substrate; an interlayer dielectric layer on a side of the insulating layer distal from the gate insulating layer; a relay electrode layer on a side of the interlayer dielectric layer distal from the insulating layer; a first planarization layer on a side of the relay electrode layer distal from the interlayer dielectric layer; an anode contact pad layer on a side of the first planarization layer distal from the interlayer dielectric layer; and a second planarization layer on a side of the anode contact pad layer distal from the first planarization layer; wherein the pixel defining layer is on a side of the second planarization layer distal from the base substrate. wherein the pixel defining layer is on a side of the second planarization layer distal from the base substrate. wherein each anode is located on a side of the second planarization layer distal from the first planarization layer; and each light-emitting layer is located on a side of each anode distal from the second planarization layer; wherein, in the respective first sub-pixel, the first anode is connected to a first anode contact pad through a first via extending through the second planarization layer; in the respective second sub-pixel, the second anode is connected to a second anode contact pad through a second via extending through the second planarization layer; in the respective third sub-pixel, the third anode is connected to a third anode contact pad through a third via extending through the second planarization layer; and in the respective fourth sub-pixel, the fourth anode is connected to a fourth anode contact pad through a fourth via extending through the second planarization layer.

37. The array substrate of claim 28, further comprising: a layer of semiconductor material on the base substrate; a gate insulating layer on a side of the layer of semiconductor material distal from the base substrate; an insulating layer on a side of the gate insulating layer distal from the base substrate; an interlayer dielectric layer on a side of the insulating layer distal from the gate insulating layer; and a plurality of voltage supply lines extending along a second direction, respectively; wherein each of the plurality of voltage supply lines comprises a first inclined portion, a second inclined portion, a first parallel portion connecting the first inclined portion and the second inclined portion, a second parallel portion connected to the first parallel portion through the second inclined portion; the first parallel portion and the second parallel portion extend along a direction substantially parallel to the second direction, respectively; the first inclined portion extends along a first inclination angle with respect to the first direction; the second inclined portion extends along a second inclination angle with respect to the first direction; the first inclination angle and the second inclination angle are complementary to each other; the first parallel portion and the second parallel portion are spaced apart by a width greater than zero along a centerline of the first parallel portion and the second parallel portion, respectively, which is substantially parallel to the second direction; each of the plurality of voltage supply lines comprises a repeating pattern of the first inclined portion, the first parallel portion, the second inclined portion, the second parallel portion connected in sequence; the first parallel portion in each of the plurality of voltage supply lines is arranged along a first arrangement direction which is substantially parallel to the second direction; the second parallel portion in each of the plurality of voltage supply lines is arranged along a second arrangement direction which is substantially parallel to the second direction; and the first parallel portion and the second inclined portion, in combination, surround a side of the connection portion which is connected to a respective one of the plurality of data lines through a via extending through a first planarization layer, and to a source electrode of a second transistor through a via extending through the interlayer dielectric layer, the insulating layer, and the gate insulating layer.

38. The array substrate of claim 28, further comprising a plurality of voltage supply lines extending in the second direction, respectively. and an anti-interference block in the same layer as the second capacitor electrode, a respective one of the plurality of voltage supply lines being connected to the anti-interference block through a third main via; wherein, the anti-interference block comprises a base, a first arm, and a second arm; the respective one of the plurality of voltage supply lines is connected to the base through the third main via hole; the first arm comprises a first end portion and a first connecting bridge portion connecting the base and the first end portion; the second arm comprises a second end portion and a second connecting bridge portion connecting the base and the second end portion; the first end portion and the first connecting bridge portion are arranged along a direction substantially parallel to the second direction; the second end portion and the second connecting bridge portion are arranged along a direction substantially parallel to the second direction; a longitudinal side of the base is along a direction substantially parallel to the first direction; a transverse side of the base is along a direction substantially parallel to the second direction; the base has a substantially rectangular shape; the first end portion has a substantially rectangular shape; the second end portion has a substantially rectangular shape; the first connecting bridge portion has a pseudo-triangular shape; and the second connecting bridge portion has a triangular shape. each of the plurality of pixel driving circuits further comprises a driving transistor; 39. The array substrate of claim 28, wherein, a normal projection of the first anode in each first sub-pixel on the base substrate at least partially overlaps with a normal projection of the second capacitor electrode in each first sub-pixel on the base substrate; a normal projection of the second anode in each second sub-pixel on the base substrate at least partially overlaps with a normal projection of the second capacitor electrode in each second sub-pixel on the base substrate; and a normal projection of the third anode in each third sub-pixel on the base substrate at least partially overlaps with a normal projection of the second capacitor electrode in each third sub-pixel on the base substrate; and a normal projection of the first anode in each first sub-pixel on the base substrate at least partially overlaps with a normal projection of an active layer of a driving transistor in each first sub-pixel on the base substrate; a normal projection of the second anode in each second sub-pixel on the base substrate at least partially overlaps with a normal projection of an active layer of a driving transistor in each second sub-pixel on the base substrate; a normal projection of the third anode in each third sub-pixel on the base substrate at least partially overlaps with a normal projection of an active layer of a driving transistor in each third sub-pixel on the base substrate; and a normal projection of the fourth anode in each fourth sub-pixel on the base substrate at least partially overlaps with a normal projection of an active layer of a driving transistor in each fourth sub-pixel on the base substrate.

40. A display device comprising the array substrate according to any one of claims 1 to 39 and an integrated circuit connected to the array substrate. ​ ​ ​ ​ ​

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