Array substrate and display device

Abstract

An array substrate is provided. The array substrate includes gate lines extending along a first direction. The gate lines include a plurality of wide portions and a plurality of narrow portions arranged along the first direction, respectively, a first dimension of the plurality of wide portions along a second direction is greater than a second dimension of the plurality of narrow portions, the second direction is at an angle in a range of 80 degrees to 100 degrees with respect to the first direction. A respective wide portion of the plurality of wide portions in a respective sub-pixel overlaps a projection on the base substrate of a portion of the semiconductor material layer in the respective sub-pixel, thereby forming an active layer of the data write transistor in the respective sub-pixel.

Description

Technical Field

[0001] The present invention relates to display technology, and in particular to an array substrate and a display device. Background Art

[0002] In recent years, miniaturized electro-optical devices, including micro-light-emitting diodes (micro-LEDs), have been proposed and developed. Micro-LED-based display panels offer the advantages of high brightness, high contrast, fast response, and low power consumption. Micro-LED-based display technology has found widespread application in the display field, including smartphones and smartwatches. Summary of the Invention

[0003] In one aspect, the present disclosure provides an array substrate, comprising: a base substrate; a semiconductor material layer on the base substrate; a gate line extending along a first direction; a plurality of pixel driving circuits in a plurality of sub-pixels, the plurality of pixel driving circuits being configured to drive a plurality of light-emitting elements respectively; wherein each of the plurality of pixel driving circuits comprises a driving transistor, a data writing transistor, and a compensation transistor, the driving transistor being configured to generate a driving current for driving the light-emitting element to emit light, the data writing transistor being configured to write a voltage into the gate of the driving transistor; the gate line comprising a plurality of pixel driving circuits extending along the first direction, the plurality of pixel driving circuits being configured to drive the plurality of sub-pixels respectively, the plurality of pixel driving circuits being configured to drive the ... sub-pixels respectively, the plurality of pixel driving circuits being configured to drive the plurality of sub-pixels respectively, the plurality of pixel driving circuits being configured to drive the plurality of sub-pixels respectively, the plurality of pixel driving circuits being configured to drive the plurality of sub-pixels respectively, the plurality of pixel driving circuits being configured to drive the plurality of sub-pixels respectively, the plurality of pixel driving circuits being configured to drive the plurality of sub-pixels respectively, the plurality of pixel driving circuits being configured to drive the plurality of sub-pixels respectively, the plurality of pixel driving circuits being configured to drive the plurality of sub-pixels respectively, the plurality of pixel driving circuits being configured to drive the plurality of sub-pixels respectively, the plurality of pixel driving circuits being configured to drive the plurality of sub-pixels respectively, the plurality of pixel A plurality of wide portions and a plurality of narrow portions are arranged in a direction, along a second direction, a first dimension of the plurality of wide portions is greater than a second dimension of the plurality of narrow portions, and the second direction forms an angle in the range of 80 degrees to 100 degrees relative to the first direction; a positive projection of a corresponding width of the plurality of wide portions in a corresponding sub-pixel on the base substrate overlaps with a positive projection of a portion of the semiconductor material layer in the corresponding sub-pixel on the base substrate, thereby forming an active layer of the data writing transistor in the corresponding sub-pixel; and a ratio of a channel length to a channel width of the active layer of the data writing transistor is in the range of 1.5:1 to 3:1.

[0004] Optionally, a ratio of the channel length to the channel width of the active layer of the data write transistor is in a range of 2:1 to 3:1.

[0005] Optionally, the plurality of wide portions and the plurality of narrow portions are alternately arranged along the first direction; and the plurality of wide portions are respectively located in each sub-pixel along the first direction.

[0006] Optionally, the plurality of wide portions have a first line width; the plurality of narrow portions have a second line width; and a ratio of the first line width to the second line width is in a range of 1.1:1 to 3:1.

[0007] Alternatively, each of the plurality of wide portions has the first size greater than the second size by protruding toward both sides along the second direction relative to each of the plurality of narrow portions.

[0008] Optionally, each pixel driving circuit among the multiple pixel driving circuits also includes a storage capacitor, the storage capacitor including a first capacitor electrode, a second capacitor electrode and an insulating layer between the first capacitor electrode and the second capacitor electrode; the second capacitor electrode includes a main body portion and a connecting portion, the connecting portion connecting the main body portions of the second capacitor electrodes from two adjacent sub-pixels along the first direction; the main body portion has a wider portion and a narrower portion, the width of the wider portion along the second direction is greater than the width of the narrower portion along the direction perpendicular to the first direction; and the corresponding wide portions among the multiple wide portions and the narrower portions have their positive projections on the line arranged along the first direction at least partially overlap with each other.

[0009] Optionally, each pixel driving circuit among the multiple pixel driving circuits also includes a storage capacitor, the storage capacitor including a first capacitor electrode, a second capacitor electrode, and an insulating layer between the first capacitor electrode and the second capacitor electrode; the second capacitor electrode includes a main body portion and a connecting portion, the connecting portion connecting the main body portions of the second capacitor electrodes from two adjacent sub-pixels along the first direction; and the corresponding wide portions among the multiple wide portions and the connecting portion have their positive projections on the line arranged along the first direction at least partially overlap with each other.

[0010] Optionally, the array substrate further includes a data line extending along the second direction; each column of pixel driving circuit corresponds to the data line; the data line includes a main data line portion and a protruding data line portion; the size of the protruding data line portion along the first direction is larger than the size of the main data line portion along the first direction; wherein the orthographic projection of each of the multiple wide portions on the base substrate partially overlaps with the orthographic projection of the data line on the base substrate, thereby forming an overlapping portion, and the ratio of the size of the overlapping portion along the first direction to the size of the main data line portion along the first direction is in the range of 10% to 100%.

[0011] Optionally, the array substrate further includes a data line extending along the second direction; each column of pixel driving circuit corresponds to the data line; the data line includes a main data line portion and a protruding data line portion; the size of the protruding data line portion along the first direction is larger than the size of the main data line portion along the first direction; wherein the orthographic projection of any one of the multiple wide portions on the base substrate is spaced apart from the orthographic projection of the data line on the base substrate.

[0012] Optionally, the array substrate further comprises a node connection line, wherein the node connection line connects the gate of the driving transistor to one of the source and the drain of the compensation transistor; wherein the plurality of sub-pixels include a first sub-pixel configured to emit light of a first color; a second sub-pixel configured to emit light of a second color; and a third sub-pixel configured to emit light of a third color; and the orthographic projections of the first node in the first sub-pixel, the first node in the second sub-pixel, and the first node in the third sub-pixel on the base substrate are respectively formed by the first anode of the first light-emitting element in the first sub-pixel, the second anode of the second light-emitting element in the second sub-pixel, and the The third anode of the third light-emitting element in the third sub-pixel covers at least 50% of its orthographic projection on the base substrate, and each first node in each sub-pixel includes the corresponding gate and corresponding node connection line of the driving transistor in each sub-pixel; and the orthographic projections of the node connection line in the first sub-pixel, the node connection line in the second sub-pixel and the node connection line in the third sub-pixel on the base substrate are respectively covered by at least 80% of the orthographic projections of the first anode of the first light-emitting element in the first sub-pixel, the second anode of the second light-emitting element in the second sub-pixel and the third anode of the third light-emitting element in the third sub-pixel on the base substrate.

[0013] In another aspect, the present disclosure provides a display device including the array substrate described herein or manufactured by the method described herein.

[0014] On the other hand, the present disclosure provides an array substrate, comprising a plurality of pixel driving circuits respectively in a plurality of sub-pixels, the plurality of pixel driving circuits being configured to respectively drive a plurality of light-emitting elements; wherein each pixel driving circuit in the plurality of pixel driving circuits comprises a driving transistor and a compensation transistor; wherein the array substrate comprises: a node connection line, the node connection line connecting the gate of the driving transistor with one of the first electrode and the second electrode of the compensation transistor; wherein the plurality of sub-pixels comprise a first sub-pixel configured to emit light of a first color; a second sub-pixel configured to emit light of a second color; and a third sub-pixel configured to emit light of a third color; and a first node in the first sub-pixel, a first node in the second sub-pixel and a first node in the third sub-pixel are respectively disposed on the substrate. The orthographic projections on the board are respectively covered by at least 50% of the orthographic projections of the first anode of the first light-emitting element in the first sub-pixel, the second anode of the second light-emitting element in the second sub-pixel, and the third anode of the third light-emitting element in the third sub-pixel on the base substrate, and each first node in each sub-pixel includes the corresponding gate of the driving transistor and the corresponding node connection line in each sub-pixel; and the orthographic projections of the node connection line in the first sub-pixel, the node connection line in the second sub-pixel, and the node connection line in the third sub-pixel on the base substrate are respectively covered by at least 80% of the orthographic projections of the first anode of the first light-emitting element in the first sub-pixel, the second anode of the second light-emitting element in the second sub-pixel, and the third anode of the third light-emitting element in the third sub-pixel on the base substrate.

[0015] Optionally, the plurality of sub-pixels further include a fourth sub-pixel configured to emit light of the second color; wherein the orthographic projection of the first node in the second sub-pixel on the base substrate is covered by at least 60% of the orthographic projection of the second anode of the second light-emitting element in the second sub-pixel on the base substrate; the orthographic projection of the first node in the fourth sub-pixel on the base substrate is covered by at least 60% of the orthographic projection of the fourth anode of the fourth light-emitting element in the fourth sub-pixel on the base substrate; and the first area covered by the orthographic projection of the first node in the second sub-pixel on the base substrate by the orthographic projection of the second anode of the second light-emitting element in the second sub-pixel on the base substrate is greater than the second area covered by the orthographic projection of the first node in the fourth sub-pixel on the base substrate by the orthographic projection of the fourth anode of the fourth light-emitting element in the fourth sub-pixel on the base substrate.

[0016] Optionally, a fourth anode of the fourth light emitting element in the fourth sub-pixel has a first edge and a second edge on the substrate substrate, the first edge and the second edge are respectively located on two sides of a projection of a node connection line in the fourth sub-pixel on the substrate substrate along a first direction, the first direction is perpendicular to the projection of the node connection line in the fourth sub-pixel on the substrate substrate; the first edge is a non-straight line; and the second edge includes a straight line.

[0017] Optionally, the compensation transistor has a dual-gate structure; a part of a third anode of a third light emitting element in the third sub-pixel on the substrate substrate has at least partial overlap with a projection of a gate of the compensation transistor on the substrate substrate.

[0018] Optionally, the first anode of the first light emitting element in the first sub-pixel includes a first part, a second part and a third part of a hexagonal shape; the hexagonal shape has a first edge and a second edge directly connected to each other; the second part is adjacent to the first edge; the third part is adjacent to the second edge; the second part and the third part are adjacent to each other along a third edge; and the first edge, the second edge and the third edge are directly connected to each other at a corner of the hexagonal shape.

[0019] Optionally, the second part includes a first sub-part and a second sub-part; a projection of the first sub-part on the substrate substrate at least partially overlaps with a projection of a node connection line in the first sub-pixel on the substrate substrate, but does not overlap with a projection of a gate of the driving transistor in the first sub-pixel on the substrate substrate; a projection of the second sub-part on the substrate substrate at least partially overlaps with the projection of the node connection line in the first sub-pixel on the substrate substrate, and at least partially overlaps with the projection of the gate of the driving transistor in the first sub-pixel on the substrate substrate; the array substrate includes a gate line extending along a first direction; and a first width of the second sub-part along the first direction is greater than a second width of the first sub-part along the first direction.

[0020] Optionally, the anode is located on a side of the second planarization layer away from the first planarization layer; wherein, in the first sub-pixel, the first anode is connected to the first anode contact pad through a first through hole extending through the second planarization layer, and the first anode contact pad is connected to the first relay electrode through a second through hole extending through the first planarization layer; in the second sub-pixel, the second anode is connected to the second anode contact pad through a third through hole extending through the second planarization layer, and the second anode contact pad is connected to the second relay electrode through a fourth through hole extending through the first planarization layer; in the third sub-pixel, the third anode is connected to the third anode contact pad through a fifth through hole extending through the second planarization layer, and the third anode contact pad is connected to the third relay electrode through a sixth through hole extending through the first planarization layer; and a first distance between an orthographic projection of the first through hole on the base substrate and an orthographic projection of the second through hole on the base substrate is greater than a second distance between the third through hole and the fourth through hole; and a third distance between an orthographic projection of the fifth through hole and an orthographic projection of the sixth through hole is greater than the second distance between the third through hole and the fourth through hole.

[0021] Optionally, the first shortest distance between the orthographic projection of the first effective light-emitting area of ​​the first sub-pixel on the base substrate and the orthographic projection of the second through hole on the base substrate is greater than the second shortest distance between the orthographic projection of the second effective light-emitting area of ​​the second sub-pixel on the base substrate and the orthographic projection of the fourth through hole on the base substrate; and the third shortest distance between the orthographic projection of the third effective light-emitting area of ​​the third sub-pixel on the base substrate and the orthographic projection of the sixth through hole on the base substrate is greater than the second shortest distance.

[0022] Optionally, the first length of the first anode contact pad along the second direction and the second length of the second anode contact pad along the second direction are smaller than the third length of the third anode contact pad along the second direction; the fourth shortest distance between the orthographic projection of the second through hole on the base substrate and the orthographic projection of any anode adjacent to the first anode on the base substrate is greater than the fifth shortest distance between the orthographic projection of the sixth through hole on the base substrate and the orthographic projection of any anode adjacent to the third anode on the base substrate; and the sixth shortest distance between the orthographic projection of the fourth through hole on the base substrate and the orthographic projection of any anode adjacent to the second anode on the base substrate is greater than the fifth shortest distance.

[0023] Optionally, a third area covered by the orthographic projection of the first node in the first sub-pixel on the base substrate and the orthographic projection of the first anode of the first light-emitting element in the first sub-pixel on the base substrate is substantially the same as a fourth area covered by the orthographic projection of the first node in the third sub-pixel on the base substrate and the orthographic projection of the third anode of the third light-emitting element in the third sub-pixel on the base substrate; and the third area and the fourth area are smaller than the first area covered by the orthographic projection of the first node in the second sub-pixel on the base substrate and the orthographic projection of the second anode of the second light-emitting element in the second sub-pixel on the base substrate.

[0024] Optionally, the array substrate further comprises: a semiconductor material layer on the base substrate; and a gate line extending along a first direction; wherein each pixel driving circuit in the plurality of pixel driving circuits comprises a driving transistor, a data writing transistor and a compensation transistor, the driving transistor being configured to generate a driving current for driving the light-emitting element to emit light, and the data writing transistor being configured to write a voltage into the gate of the driving transistor; the gate line comprises a plurality of wide portions and a plurality of narrow portions respectively arranged along the first direction, a first dimension of the plurality of wide portions being larger than a second dimension of the plurality of narrow portions along a second direction, and the second direction is at an angle in a range of 80 degrees to 100 degrees relative to the first direction; a positive projection of a corresponding wide portion of the plurality of wide portions in a corresponding sub-pixel on the base substrate overlaps with a positive projection of a portion of the semiconductor material layer in the corresponding sub-pixel on the base substrate, thereby forming an active layer of the data writing transistor in the corresponding sub-pixel; and a ratio of a channel length to a channel width of the active layer of the data writing transistor is in a range of 1.5:1 to 3:1.

[0025] In another aspect, the present disclosure provides a display device including the array substrate described herein or manufactured by the method described herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The following drawings are examples for illustration purposes only, in accordance with various disclosed embodiments, and are not intended to limit the scope of the invention.

[0027] Figure 1 is a plan view of an array substrate according to some embodiments of the present disclosure.

[0028] Figure 2 is a circuit diagram illustrating a structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0029] Figure 3 is a diagram illustrating a structure of multiple sub-pixels of an array substrate according to some embodiments of the present disclosure.

[0030] Figure 4 It shows Figure 3 FIG. 1 is a diagram showing the structure of semiconductor material layers in multiple sub-pixels of an array substrate.

[0031] Figure 5 It shows Figure 3 FIG. 1 is a diagram showing the structure of the first conductive layer in multiple sub-pixels of an array substrate.

[0032] Figure 6 It shows Figure 3 FIG. 1 is a diagram showing the structure of the second conductive layer in multiple sub-pixels of an array substrate.

[0033] Figure 7 It shows Figure 3 FIG. 1 shows a diagram of the structure of the first signal line layer in multiple sub-pixels of an array substrate.

[0034] Figure 8 It shows Figure 3 FIG. 1 is a diagram showing the structure of the second signal line layer in multiple sub-pixels of an array substrate.

[0035] Figure 9 It shows Figure 3 FIG. 1 is a diagram showing the structure of the anode and pixel defining layer of the light-emitting element in multiple sub-pixels of the array substrate.

[0036] Figure 10 It is along Figure 3 Cross-sectional view along line AA'.

[0037] Figure 11 is a diagram illustrating a structure of multiple sub-pixels of an array substrate according to some embodiments of the present disclosure.

[0038] Figure 12 It shows Figure 11 FIG. 1 is a diagram showing the structure of the anode and pixel defining layer of the light-emitting element in multiple sub-pixels of the array substrate.

[0039] Figure 13 It is along Figure 11 Cross-sectional view along line BB'.

[0040] Figure 14A It shows Figure 3 The diagram shows the structure of the anode and the first signal line layer in the array substrate.

[0041] Figure 14B It shows Figure 3 FIG. 1 shows a diagram of the structure of the anode and the first conductive layer in the array substrate.

[0042] Figure 14C It shows Figure 3FIG. 1 is a diagram illustrating a structure of an anode and a second conductive layer in an array substrate.

[0043] Figure 14D FIG. 2 is a diagram illustrating a structure of an anode and a semiconductor material layer in an array substrate. Figure 3

[0044] Figure 14E FIG. 3 is a diagram illustrating a structure of an anode, a node connection line, and a first conductive layer in an array substrate. Figure 3

[0045] Figure 15A FIG. 4 is a diagram illustrating a structure of an anode and a first signal line layer in an array substrate. Figure 11

[0046] Figure 15B FIG. 5 is a diagram illustrating a structure of an anode and a first conductive layer in an array substrate. Figure 11

[0047] Figure 15C FIG. 6 is a diagram illustrating a structure of an anode and a second conductive layer in an array substrate. Figure 11

[0048] Figure 15D FIG. 7 is a diagram illustrating a structure of an anode and a semiconductor material layer in an array substrate. Figure 11

[0049] Figure 15E FIG. 8 is a diagram illustrating a structure of an anode, a node connection line, and a first conductive layer in an array substrate. Figure 11

[0050] Figure 16 FIG. 9 is a diagram illustrating a structure of a first conductive layer in a plurality of sub-pixels of an array substrate. Figure 3

[0051] Figure 17 FIG. 10 is a diagram illustrating a structure of a semiconductor material layer and a first conductive layer in a plurality of sub-pixels of an array substrate. Figure 3

[0052] FIG. 11 is an enlarged view according to a portion of a gate line in some embodiments of the present disclosure. Figure 18

[0053] Figure 19 FIG. 12 is a diagram illustrating a structure of a second conductive layer in a plurality of sub-pixels of an array substrate. Figure 3

[0054] Figure 20 FIG. 13 is a diagram illustrating a structure of a first conductive layer and a second conductive layer in a plurality of sub-pixels of an array substrate. Figure 3 ​​​​​​​​​​​

[0055] Figure 21 is a diagram illustrating a structure of a first conductive layer and a first signal line layer in a plurality of sub-pixels of the array substrate. Figure 3

[0056] Figure 22 is a diagram illustrating a structure of an anode, a node connection line, and a first conductive layer in the array substrate. Figure 3

[0057] Figure 23 is a partial enlarged view of Figure 22

[0058] Figure 24 is a diagram illustrating a structure of an anode and an anode contact pad in the array substrate. Figure 3

[0059] Figure 25 is a diagram illustrating a structure of an anode, a first conductive layer, and a second signal line layer in the array substrate. Figure 3

[0060] Figure 26 is a cross-sectional view along the line C-C' in Figure 11

[0061] Figure 27 is a cross-sectional view along the line D-D' in Figure 11 DETAILED DESCRIPTION

[0062] The present disclosure will now be described in greater particularity with reference to the following Examples. It should be noted that the following description of some examples presented herein is for illustrative purposes only. It is not intended to be exhaustive or to be limited to the precise form described.

[0063] ​​​​​​​The present disclosure particularly provides an array substrate and a display device, which substantially overcome one or more problems caused by the limitations and shortcomings of the prior art. In one aspect, the present disclosure provides an array substrate. In some embodiments, the array substrate includes a base substrate; a semiconductor material layer on the base substrate; a gate line extending along a first direction; a plurality of pixel driving circuits in a plurality of sub-pixels, the plurality of pixel driving circuits being configured to drive a plurality of light-emitting elements respectively. Optionally, each of the plurality of pixel driving circuits includes a driving transistor, a data writing transistor and a compensation transistor, the driving transistor being configured to generate a driving current for driving the light-emitting element to emit light, and the data writing transistor being configured to write a voltage to the gate of the driving transistor. Optionally, the gate line includes a plurality of wide portions and a plurality of narrow portions arranged along the first direction, respectively, and the first dimension of the plurality of wide portions along the second direction is greater than the second dimension of the plurality of narrow portions, and the second direction is at an angle in the range of 80 degrees to 100 degrees relative to the first direction. Optionally, an orthographic projection of a corresponding wide portion of the plurality of wide portions in a corresponding sub-pixel on the base substrate overlaps an orthographic projection of a portion of the semiconductor material layer in the corresponding sub-pixel on the base substrate, thereby forming an active layer of the data write transistor in the corresponding sub-pixel. Optionally, a ratio of a channel length to a channel width of the active layer of the data write transistor is in a range of 1.5:1 to 3:1.

[0064] In some embodiments, the array substrate includes a plurality of pixel driving circuits respectively in a plurality of sub-pixels, wherein the plurality of pixel driving circuits are configured to drive a plurality of light-emitting elements respectively. In some embodiments, each of the plurality of pixel driving circuits includes a plurality of transistors and a storage capacitor, the storage capacitor including a first capacitor electrode, a second capacitor electrode electrically connected to a corresponding voltage supply line, and an insulating layer between the first capacitor electrode and the second capacitor electrode. In some embodiments, the array substrate includes a semiconductor material layer on a base substrate; a node connection line, which is in the same layer as the corresponding voltage supply line and is connected to the first capacitor electrode through a first main through hole, and is connected to the semiconductor material layer through a second main through hole. Optionally, the plurality of sub-pixels include a first sub-pixel configured to emit light of a first color; a second sub-pixel configured to emit light of a second color; a third sub-pixel configured to emit light of a third color; and a fourth sub-pixel configured to emit light of a second color. Optionally, the percentages of the orthographic projections of the first corresponding node connection line in the first sub-pixel, the second corresponding node connection line in the second sub-pixel, the third corresponding node connection line in the third sub-pixel and the fourth corresponding node connection line in the fourth sub-pixel on the base substrate covered by the orthographic projections of the first anode of the first light-emitting element in the first sub-pixel, the second anode of the second light-emitting element in the second sub-pixel, the third anode of the third light-emitting element in the third sub-pixel and the fourth anode of the fourth light-emitting element in the fourth sub-pixel on the base substrate are within 20% of each other.

[0065] Figure 1 is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 1 , the array substrate includes an array of sub-pixels Sp. Each sub-pixel includes an electronic component, such as a light-emitting element. In one example, the light-emitting element is driven by a pixel driving circuit PDC. The array substrate includes a gate line GL, a data line DL, a voltage supply line Vdd (e.g., a high voltage supply line) and a second voltage supply line (e.g., a low voltage supply line Vss), each of which is electrically connected to the pixel driving circuit PDC. The light emission of each sub-pixel in the sub-pixel Sp is driven by the pixel driving circuit PDC. In one example, a high voltage signal (e.g., a VDD signal) is input to the pixel driving circuit PDC connected to the anode of the light-emitting element through the high voltage supply line Vdd; a low voltage signal (e.g., a VSS signal) is input to the cathode of the light-emitting element through the low voltage supply line. The voltage difference between the high voltage signal (e.g., VDD signal) and the low voltage signal (e.g., VSS signal) is a driving voltage ΔV, which drives the light-emitting element to emit light.

[0066] Various suitable pixel drive circuits can be used in this array substrate. Examples of suitable drive circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, and 8T2C. In some embodiments, each of the multiple pixel drive circuits is a 7T1C drive circuit. Various suitable light-emitting elements can be used in this array substrate. Examples of suitable light-emitting elements include organic light-emitting diodes, quantum dot light-emitting diodes, and micro light-emitting diodes. Optionally, the light-emitting element is a micro light-emitting diode. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0067] Figure 2 is a circuit diagram showing the structure of a pixel driving circuit in some embodiments of the present disclosure. Figure 2 In some embodiments, the pixel driving circuit includes a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first transistor T1 having a gate connected to a first reset control signal line rst1, a source connected to a first reset signal line Vint1, and a drain connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td; a second transistor T2 having a gate connected to a gate line GL, a source connected to a data line DL, and a drain connected to the source of the driving transistor Td; a third transistor T3 having a gate connected to the gate line GL, a source connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td. The transistor Td has a gate and a drain connected to the drain of the driving transistor Td; a fourth transistor T4 has a gate connected to the light emission control signal line em, a source connected to the voltage supply line Vdd, and a drain connected to the source of the driving transistor Td and the drain of the second transistor T2; a fifth transistor T5 has a gate connected to the light emission control signal line em, a source connected to the drain of the driving transistor Td and the drain of the third transistor T3, and a drain connected to the anode of the light emitting element LE; and a sixth transistor T6 has a gate connected to the second reset control signal line rst2, a source connected to the second reset signal line Vint2, and a drain connected to the drain of the fifth transistor and the anode of the light emitting element LE. A second capacitor electrode Ce2 is connected to the voltage supply line Vdd and the source of the fourth transistor T4.

[0068] The pixel driving circuit further includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the source of the third transistor T3. The second node N2 is connected to the drain of the fourth transistor T4, the drain of the second transistor T2, and the source of the driving transistor Td. The third node N3 is connected to the drain of the driving transistor Td, the drain of the third transistor T3, and the source of the fifth transistor T5. The fourth node N4 is connected to the drain of the fifth transistor T5, the drain of the sixth transistor T6, and the anode of the light-emitting element LE.

[0069] Figure 3 FIG is a diagram showing the structure of multiple sub-pixels of an array substrate according to some embodiments of the present disclosure. Figure 3 In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels include a first sub-pixel sp1, a second sub-pixel sp2, a third sub-pixel sp3, and a fourth sub-pixel sp4. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a repeating array of an S1-S2-S3-S4 format, where S1 represents the first sub-pixel sp1, S2 represents the second sub-pixel sp2, S3 represents the third sub-pixel sp3, and S4 represents the fourth sub-pixel sp4. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C2' format, where C1 represents the first sub-pixel sp1 of the first color, C2 represents the second sub-pixel sp2 of the second color, C3 represents the third sub-pixel sp3 of the third color, and C2' represents the fourth sub-pixel sp4 of the second color. In another embodiment, the C1-C2-C3-C2′ format is an RGBG format, wherein the first subpixel sp1 is a red subpixel, the second subpixel sp2 is a green subpixel, the third subpixel sp3 is a blue subpixel, and the fourth subpixel sp4 is a green subpixel.

[0070] Figure 4 It shows Figure 3 FIG. 1 is a diagram showing the structure of semiconductor material layers in multiple sub-pixels of an array substrate. Figure 5 It shows Figure 3 FIG. 1 is a diagram showing the structure of the first conductive layer in multiple sub-pixels of an array substrate. Figure 6 It shows Figure 3 FIG. 1 is a diagram showing the structure of the second conductive layer in multiple sub-pixels of an array substrate. Figure 7 It shows Figure 3 FIG. 1 shows a diagram of the structure of the first signal line layer in multiple sub-pixels of an array substrate. Figure 8 It shows Figure 3 FIG. 1 is a diagram showing the structure of the second signal line layer in multiple sub-pixels of an array substrate. Figure 9 It shows Figure 3 A diagram of a structure of an anode of a light emitting element and a pixel defining layer in a plurality of sub-pixels of the array substrate shown. Figure 10 is a cross-sectional view along Figure 3 line A-A' in FIG. 1B. Reference is made to Figures 3 to 10 In some embodiments, the array substrate includes a base substrate BS, a semiconductor material layer SML on the base substrate BS, a gate insulating layer GI on a side of the semiconductor material layer SML distal from the base substrate BS, a first conductive layer on a side of the gate insulating layer GI distal from the semiconductor material layer SML, an insulating layer IN on a side of the first conductive layer distal from the gate insulating layer GI, a second conductive layer on a side of the insulating layer IN distal from the first conductive layer, an interlayer dielectric layer ILD on a side of the second conductive layer distal from the insulating layer IN, a first signal line layer on a side of the interlayer dielectric layer ILD distal from the second conductive layer, a first planarization layer PLN1 on a side of the first signal line layer distal from the interlayer dielectric layer ILD, a second signal line layer on a side of the first planarization layer PLN1 distal from the interlayer dielectric layer ILD, a second planarization layer PLN2 on a side of the second signal line layer distal from the first planarization layer PLN1, and an anode on a side of the second planarization layer PLN2 distal from the first planarization layer PLN1.

[0071] Referring to Figure 3 , each of the first sub-pixel sp1, the second sub-pixel sp2, the third sub-pixel sp3, and the fourth sub-pixel sp4 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a driving transistor Td.

[0072] Referring to Figure 2 , Figure 3 and Figure 4 In some embodiments, in each sub-pixel, the semiconductor material layer has a unitary structure. In Figure 4 , the first sub-pixel Sp1 on the left is labeled with markers indicating regions corresponding to the plurality of transistors in the pixel driving circuit, including the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the driving transistor Td. In Figure 4, the fourth subpixel Sp4 on the right is marked with a mark indicating the components of each of the multiple transistors in the pixel drive circuit. For example, the first transistor T1 includes an active layer ACT1, a source S1, and a drain D1. The second transistor T2 includes an active layer ACT2, a source S2, and a drain D2. The third transistor T3 includes an active layer ACT3, a source S3, and a drain D3. The fourth transistor T4 includes an active layer ACT4, a source S4, and a drain D4. The fifth transistor T5 includes an active layer ACT5, a source S5, and a drain D5. The sixth transistor T6 includes an active layer ACT6, a source S6, and a drain D6. The drive transistor Td includes an active layer ACTd, a source Sd, and a drain Dd. In one example, the active layer (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), source (S1, S2, S3, S4, S5, S6, and Sd), and drain (D1, D2, D3, D4, D5, D6, and Dd) of the transistor (T1, T2, T3, T4, T5, T6, and Td) in each sub-pixel are part of an integral structure in each sub-pixel. In another example, the active layer (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), source (S1, S2, S3, S4, S5, S6, and Sd), and drain (D1, D2, D3, D4, D5, D6, and Dd) of the transistor (T1, T2, T3, T4, T5, T6, and Td) are in the same layer.

[0073] As used herein, an active layer refers to a component of a transistor comprising at least a portion of a semiconductor material layer, the orthographic projection of at least a portion of the semiconductor material layer on the base substrate overlapping with the orthographic projection of the gate on the base substrate. As used herein, a source electrode refers to a component of a transistor connected to one side of the active layer, and a drain electrode refers to a component of a transistor connected to the other side of the active layer. In the case of a dual-gate transistor (e.g., a third transistor T3), an active layer refers to a component of a transistor comprising a first portion of a semiconductor material layer, a second portion of a semiconductor material layer, and a third portion between the first portion and the second portion, the orthographic projection of the first portion of the semiconductor material layer on the base substrate overlapping with the orthographic projection of the first gate on the base substrate, and the orthographic projection of the second portion of the semiconductor material layer on the base substrate overlapping with the orthographic projection of the second gate on the base substrate. In the case of a dual-gate transistor, a source electrode refers to a component of the transistor connected to the first portion on a side away from the third portion, and a drain electrode refers to a component of the transistor connected to the second portion on a side away from the third portion.

[0074] Reference Figure 2 、 Figure 3 、 Figure 5 and Figure 10In some embodiments, the first conductive layer includes a gate line GL, a first reset control signal line rst1, a light emitting control signal line em, a second reset control signal line rst2, and a first capacitor electrode Ce1 of a storage capacitor Cst. Various appropriate electrode materials and various appropriate manufacturing methods can be used to manufacture the first conductive layer. For example, the conductive material can be deposited on a substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, and the like. Optionally, the gate line GL, the first reset control signal line rst1, the light emitting control signal line em, the second reset control signal line rst2, and the first capacitor electrode Ce1 are located in the same layer. As Figure 5 As shown, the gate line GL, the first reset control signal line rst1, the light emitting control signal line em and the second reset control signal line rst2 extend along the first direction DR1 respectively.

[0075] As used herein, the term "same layer" refers to the relationship between layers formed simultaneously in the same step. In one example, when the gate line GL and the first capacitor electrode Ce1 are formed by one or more steps of the same patterning process performed in the same material layer, the gate line GL and the first capacitor electrode Ce1 are located in the same layer. In another example, by performing the steps of forming the gate line GL and forming the first capacitor electrode Ce1 simultaneously, the gate line GL and the first capacitor electrode Ce1 can be formed in the same layer. The term "same layer" does not always mean that the thickness of the layer or the height of the layer in a cross-sectional view is the same.

[0076] Reference Figure 2 、 Figure 3 、 Figure 6 and Figure 10 In some embodiments, the second conductive layer includes a first reset signal line Vint1, a second capacitor electrode Ce2 of the storage capacitor Cst, and a second reset signal line Vint2. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second conductive layer. For example, the conductive material can be deposited on the substrate by a plasma enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for manufacturing the second conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the first reset signal line Vint1, the second reset signal line Vint2, and the second capacitor electrode Ce2 are located in the same layer.

[0077] Reference Figure 2 、 Figure 3 、 Figure 7and Figure 10 In some embodiments, the first signal line layer includes a voltage supply line Vdd, a data line DL, a node connection line Cl1, a second connection line Cl2, and a third connection line Cl3. The node connection line Cln connects the first capacitor electrode Ce1 and the source of the third transistor T3 in each subpixel. The second connection line Cl2 connects the second reset signal line Vint2 and the source of the sixth transistor T6 in each subpixel. The third connection line Cl3 connects the first reset signal line Vint1 and the source of the first transistor T1 in each subpixel. In some embodiments, the first signal line layer also includes a first relay electrode RE1 in the first subpixel sp1, a second relay electrode RE2 in the second subpixel sp2, a third relay electrode RE3 in the third subpixel sp3, and a fourth relay electrode RE4 in the fourth subpixel sp4. These relay electrodes connect the source of the fifth transistor in the first sub-pixel sp1, the second sub-pixel sp2, the third sub-pixel sp3 and the fourth sub-pixel sp4 to the anode contact pad in the first sub-pixel sp1, the anode contact pad in the second sub-pixel sp2, the anode contact pad in the third sub-pixel sp3 and the anode contact pad in the fourth sub-pixel sp4, respectively. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the first signal line layer. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first signal line layer include but are not limited to aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the voltage supply line Vdd, the data line DL, the node connection line Cl1, the second connection line Cl2 and the third connection line Cl3 are located on the same layer. As Figure 7 As shown, the voltage supply line Vdd and the data line DL extend along the second direction DR2 , respectively.

[0078] Reference Figure 2 、 Figure 3 、 Figure 8 and Figure 10 In some embodiments, the second signal line layer includes a first anode contact pad ACP1 in the first sub-pixel sp1, a second anode contact pad ACP2 in the second sub-pixel sp2, a third anode contact pad ACP3 in the third sub-pixel sp3, and a fourth anode contact pad ACP4 in the fourth sub-pixel sp4. These anode contact pads connect the relay electrodes (e.g. Figure 7The first relay electrode RE1, the second relay electrode RE2, the third relay electrode RE3, and the fourth relay electrode RE4 shown in the figure are respectively connected to the anode in the first sub-pixel sp1, the anode in the second sub-pixel sp2, the anode in the third sub-pixel sp3, and the anode in the fourth sub-pixel sp4. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second signal line layer. For example, the conductive material can be deposited on the substrate by a plasma enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for manufacturing the second signal line layer include but are not limited to aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the first anode contact pad ACP1, the second anode contact pad ACP2, the third anode contact pad ACP3 and the fourth anode contact pad ACP4 are in the same layer.

[0079] Reference Figure 2 、 Figure 3 、 Figure 9 and Figure 10 In some embodiments, the array substrate includes a first anode AD1 in the first subpixel sp1, a second anode AD2 in the second subpixel sp2, a third anode AD3 in the third subpixel sp3, and a fourth anode AD4 in the fourth subpixel sp4. The first anode AD1, the second anode AD2, the third anode AD3, and the fourth anode AD4 are respectively the anodes of the first light-emitting element in the first subpixel sp1, the second light-emitting element in the second subpixel sp2, the third light-emitting element in the third subpixel sp3, and the fourth light-emitting element in the fourth subpixel sp4. In some embodiments, the array substrate further includes a pixel defining layer (PDL) located on a side of the first anode AD1, the second anode AD2, the third anode AD3, and the fourth anode AD4 away from the second planarization layer PLN2. The array substrate further includes a first subpixel opening SA1, a second subpixel opening SA2, a third subpixel opening SA3, and a fourth subpixel opening SA4, respectively extending through the pixel defining layer PDL.

[0080] Reference Figure 2 、 Figure 3 、 Figure 5 、 Figure 6 and Figure 10 In some embodiments, except for the hole region H where a portion of the second capacitor electrode Ce2 does not exist, the orthographic projection of the second capacitor electrode Ce2 on the base substrate BS completely covers the orthographic projection of the first capacitor electrode Ce1 on the base substrate BS with a margin.

[0081] Figure 11is a diagram illustrating a structure of multiple sub-pixels of an array substrate according to some embodiments of the present disclosure. Figure 12 It shows Figure 11 FIG. 1 is a diagram showing the structure of the anode and pixel defining layer of the light-emitting element in multiple sub-pixels of the array substrate. Figure 13 It is along Figure 11 Compare to the cross-sectional view of the BB' line in Figure 11 The array substrate and Figure 3 The main difference between the two array substrates lies in the structure of the first anode of the first light-emitting element in the first sub-pixel sp1. Figure 12 The first anode AD1 is smaller than Figure 9 The first anode AD1 in the comparison Figure 10 The cross section and Figure 13 The cross section in Figure 10 The first anode AD1 in the embodiment covers the node connection line Cl1, and Figure 13 The first anode AD1 does not cover the node connection line Cl1.

[0082] Figure 14A It shows Figure 3 Figure 2 shows the structure of the anode and the first signal line layer in the array substrate. Figure 15A It shows Figure 11 The structure of the anode and the first signal line layer in the array substrate is shown in FIG. Figure 15A and Figure 11 The orthographic projection of the second anode AD2 on the base substrate substantially covers the orthographic projection of the second corresponding node connection line Cln2 on the base substrate; the orthographic projection of the third anode AD3 on the base substrate substantially covers the orthographic projection of the third corresponding node connection line Cln3 on the base substrate; and the orthographic projection of the fourth anode AD4 on the substrate substantially covers the orthographic projection of the fourth corresponding node connection line Cln4 on the substrate. As used herein, the term "substantially covers" means that one orthographic projection covers at least 70% (e.g., at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) of another orthographic projection.

[0083] However, reference Figure 11 and Figure 15A The orthographic projection of the first anode AD1 on the base substrate does not substantially overlap with the orthographic projection of the first corresponding node connection line Cln1 on the base substrate. As used herein, the term "substantially not overlapping" means that the two orthographic projections do not overlap by at least 70% (e.g., at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%).

[0084] The inventors of the present disclosure have discovered that there is a parasitic capacitance between the first node N1 and the fourth node N4 in the array substrate. The inventors of the present disclosure have discovered that when the orthographic projection of the first node N1 is covered by the orthographic projection of the anode, the parasitic capacitance between the first node N1 and the fourth node N4 is relatively large. When the orthographic projection of the first node N1 is not covered by the orthographic projection of any anode, the parasitic capacitance between the first node N1 and the fourth node N4 is relatively small. The inventors of the present disclosure have discovered that in the case of Figure 11 In the array substrate shown, the parasitic capacitance between the first node N1 and the fourth node N4 in the first subpixel sp1 is smaller than the parasitic capacitance between the first node N1 and the fourth node N4 in the second subpixel sp2, the third subpixel sp3, and the fourth subpixel sp4. Inconsistent parasitic capacitances in subpixels lead to inconsistent data loading in the subpixels, which in turn causes display defects in a display panel using this array substrate. This problem becomes particularly serious when considering line width fluctuations and alignment inaccuracies during the manufacturing process.

[0085] In one example, Figure 11 The parasitic capacitance between the first node N1 and the fourth node N4 in the array substrate shown can have a design value of 0.374fF; the current through the light-emitting element can have a design value of 15.416pA. Taking into account line width fluctuations and alignment inaccuracies during the manufacturing process, the parasitic capacitance between the first node N1 and the fourth node N4 can vary in the range of 0.244fF to 0.617fF; and the current through the light-emitting element can vary in the range of 15.113pA to 15.578pA. Therefore, the ratio of ΔI / I can vary in the range of -1.966% to 1.049%, where I represents the design value of the current through the light-emitting element and ΔI represents the current variation caused by line width fluctuations and alignment inaccuracies during the manufacturing process. The present disclosure has found that the current variation is more significant in areas with lower grayscale values, thereby adversely affecting the grayscale uniformity of the display panel.

[0086] The inventors of the present disclosure have found that by making the first anode AD1 in the first sub-pixel sp1 have Figure 3 and Figure 14A The enlarged area shown can unexpectedly and surprisingly improve or eliminate display defects caused by inconsistent parasitic capacitance between the first node N1 and the fourth node N4. In one example, Figure 3The parasitic capacitance between the first node N1 and the fourth node N4 in the illustrated array substrate may have a design value of 0.374 fF; the current through the light-emitting element may have a design value of 15.416 pA. Considering linewidth fluctuations and alignment inaccuracies during the manufacturing process, it is surprising that the parasitic capacitance between the first node N1 and the fourth node N4 can vary within a relatively small range of 0.372 fF to 0.376 fF; and the current through the light-emitting element can vary within a much smaller range of 15.415 pA to 15.417 pA. Consequently, the ratio ΔI / I can vary within a much smaller range of -0.0065% to 0.0065%, where I represents the design value of the current through the light-emitting element and ΔI represents the variation in current due to linewidth fluctuations and alignment inaccuracies during the manufacturing process.

[0087] Reference Figure 3 、 Figure 10 and Figure 14A In some embodiments, the orthographic projections of the first corresponding node connection line Cln1 in the first subpixel sp1, the second corresponding node connection line Cln2 in the second subpixel sp2, the third corresponding node connection line Cln3 in the third subpixel sp3, and the fourth corresponding node connection line Cln4 in the fourth subpixel sp4 on the base substrate BS are respectively covered by the orthographic projections of the first anode AD1 of the first light-emitting element in the first subpixel sp1, the second anode AD2 of the second light-emitting element in the second subpixel sp2, the third anode AD3 of the third light-emitting element in the third subpixel sp3, and the fourth anode AD4 of the fourth light-emitting element in the fourth subpixel sp4 on the base substrate BS, and the percentages are within 20% of each other, for example, within 18% of each other, within 16% of each other, within 14% of each other, within 12% of each other, within 10% of each other, within 8% of each other, within 6% of each other, within 4% of each other, within 2% of each other, or within 1% of each other.

[0088] As a comparison, Figure 11 、 Figure 13 and Figure 15AIn the array substrate shown, the percentage of the orthographic projection of the first corresponding node connection line Cln1 in the first sub-pixel sp1 covered by the orthographic projection of the first anode AD1 of the first light-emitting element in the first sub-pixel sp1 is much smaller than the percentage of the orthographic projection of the second corresponding node connection line Cln2 in the second sub-pixel sp2, the third corresponding node connection line Cln3 in the third sub-pixel sp3, and the fourth corresponding node connection line Cln4 in the fourth sub-pixel sp4 on the base substrate covered by the orthographic projection of the second anode AD2 of the second light-emitting element in the second sub-pixel sp2, the third anode AD3 of the third light-emitting element in the third sub-pixel sp3, and the fourth anode AD4 of the fourth light-emitting element in the fourth sub-pixel sp4 on the base substrate. In one example, Figure 11 and Figure 15A In the array substrate shown, the percentage of the orthographic projection of the first corresponding node connection line Cln1 in the first sub-pixel sp1 covered by the orthographic projection of the first anode AD1 of the first light-emitting element in the first sub-pixel sp1 is less than 20% (for example, less than 15%, less than 10% or less than 5%); and the percentage of the orthographic projection of the second corresponding node connection line Cln2 in the second sub-pixel sp2, the third corresponding node connection line Cln3 in the third sub-pixel sp3, and the fourth corresponding node connection line Cln4 in the fourth sub-pixel sp4 on the base substrate covered by the orthographic projections of the second anode AD2 of the second light-emitting element in the second sub-pixel sp2, the third anode AD3 of the third light-emitting element in the third sub-pixel sp3, and the fourth anode AD4 of the fourth light-emitting element in the fourth sub-pixel sp4 on the base substrate is greater than 80% (for example, greater than 85%, greater than 90% or greater than 95%).

[0089] Reference Figure 3 、 Figure 10 and Figure 14A In some embodiments, orthographic projections of the first corresponding node connection line Cln1 in the first subpixel sp1, the second corresponding node connection line Cln2 in the second subpixel sp2, the third corresponding node connection line Cln3 in the third subpixel sp3, and the fourth corresponding node connection line Cln4 in the fourth subpixel sp4 on the base substrate BS are substantially covered by orthographic projections of the first anode AD1 of the first light-emitting element in the first subpixel sp1, the second anode AD2 of the second light-emitting element in the second subpixel sp2, the third anode AD3 of the third light-emitting element in the third subpixel sp3, and the fourth anode AD4 of the fourth light-emitting element in the fourth subpixel sp4 on the base substrate BS, respectively. As used herein, the term "substantially covered" means that one orthographic projection is covered by another orthographic projection by at least 70% (e.g., at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%).

[0090] As a comparison, Figure 11 、 Figure 13 and Figure 15A In the array substrate shown, the orthographic projection of the first corresponding node connection line Cln1 in the first sub-pixel sp1 is substantially not covered by the orthographic projection of the first anode AD1 of the first light emitting element in the first sub-pixel sp1.

[0091] Figure 14B To show Figure 3 The structure of the anode and the first conductive layer in the array substrate is shown in FIG. Figure 3 、 Figure 10 and Figure 14B In some embodiments, the percentages of the orthographic projections of the first capacitor electrodes in the first subpixel sp1, the second subpixel sp2, the third subpixel sp3 and the fourth subpixel sp4 on the base substrate BS covered by the orthographic projections of the first anode AD1 of the first light-emitting element in the first subpixel sp1, the second anode AD2 of the second light-emitting element in the second subpixel sp2, the third anode AD3 of the third light-emitting element in the third subpixel sp3, and the fourth anode AD4 of the fourth light-emitting element in the fourth subpixel sp4 on the base substrate are within 20% of each other, for example, within 18% of each other, within 16% of each other, within 14% of each other, within 12% of each other, within 10% of each other, within 8% of each other, within 6% of each other, within 4% of each other, within 2% of each other, or within 1% of each other.

[0092] Figure 15B It shows Figure 11 FIG. 1 shows the structure of the anode and the first conductive layer in the array substrate. Figure 14B Compared to the array substrate shown in FIG. 1 , the percentage of the orthographic projection of the first capacitor electrode Ce1 in the first sub-pixel sp1 covered by the orthographic projection of the first anode AD1 of the first light-emitting element in the first sub-pixel sp1 is much smaller than the percentage of the orthographic projections of the first capacitor electrode Ce1 in the second sub-pixel sp2, the third corresponding node connection line Cln3 in the third sub-pixel sp3, and the fourth corresponding node connection line Cln4 in the fourth sub-pixel sp4 on the base substrate BS covered by the orthographic projections of the second anode AD2 of the second light-emitting element in the second sub-pixel sp2, the third anode AD3 of the third light-emitting element in the third sub-pixel sp3, and the fourth anode AD4 of the fourth light-emitting element in the fourth sub-pixel sp4 on the base substrate BS, respectively. In an example, in FIG. 1 , the orthographic projection of the first capacitor electrode Ce1 in the first sub-pixel sp1 is covered by the orthographic projection of the first anode AD1 of the first light-emitting element in the first sub-pixel sp1. Figure 11 、 Figure 13 and Figure 15AIn the array substrate shown, the percentage of the orthographic projection of the first capacitor electrode Ce1 in the first sub-pixel sp1 covered by the orthographic projection of the first anode AD1 of the first light-emitting element in the first sub-pixel sp1 is less than 40% (for example, less than 35%, less than 30% or less than 25%); and the percentage of the orthographic projections of the first capacitor electrodes in the second sub-pixel sp2, the third sub-pixel sp3 and the fourth sub-pixel sp4 on the base substrate BS covered by the orthographic projections of the second anode AD2 of the second light-emitting element in the second sub-pixel sp2, the third anode AD3 of the third light-emitting element in the third sub-pixel sp3 and the fourth anode AD4 of the fourth light-emitting element in the fourth sub-pixel sp4 on the base substrate BS is greater than 60% (for example, greater than 65%, greater than 70%, or greater than 75%).

[0093] Reference Figure 2 、 Figure 3 and Figure 10 In some embodiments, the signal line layer includes a node connection line Cln located on a side of the interlayer dielectric layer ILD away from the second capacitor electrode Ce2. The node connection line Cln is in the same layer as the voltage supply line Vdd and the data line DL. Optionally, the array substrate further includes a first main via v1 in the hole region H extending through the interlayer dielectric layer ILD and the insulating layer IN. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first main via v1.

[0094] In some embodiments, the first capacitor electrode Ce1 is located on a side of the gate insulating layer IN away from the base substrate BS. Optionally, the array substrate further includes a first main through hole v1 and a second main through hole v2. The first main through hole v1 is located in the hole area H and extends through the interlayer dielectric layer ILD and the insulating layer IN. The second main through hole v2 extends through the interlayer dielectric layer ILD, the insulating layer IN and the gate insulating layer GI. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first main through hole v1 and is connected to the semiconductor material layer SML through the second main through hole v2. Optionally, the node connection line Cln is connected to the source S3 of the third transistor, as shown in FIG. Figure 10 shown.

[0095] Figure 14C To show Figure 3 The structure of the anode and the second conductive layer in the array substrate is shown in FIG. Figure 3 、 Figure 10 and Figure 14CIn some embodiments, portions of the second capacitor electrodes in the first sub-pixel sp1, the second sub-pixel sp2, the third sub-pixel sp3, and the fourth sub-pixel sp4 are not located in the hole regions. The hole regions are surrounded by the second capacitor electrodes. In some embodiments, the percentages of the orthographic projections of the hole areas in the first subpixel sp1, the second subpixel sp2, the third subpixel sp3, and the fourth subpixel sp4 on the base substrate BS covered by the orthographic projections of the first anode AD1 of the first light-emitting element in the first subpixel sp1, the second anode AD2 of the second light-emitting element in the second subpixel sp2, the third anode AD3 of the third light-emitting element in the third subpixel sp3, and the fourth anode AD4 of the fourth light-emitting element in the fourth subpixel sp4 on the base substrate BS are within 20% of each other, for example, within 18% of each other, within 16% of each other, within 14% of each other, within 12% of each other, within 10% of each other, within 8% of each other, within 6% of each other, within 4% of each other, within 2% of each other, or within 1% of each other.

[0096] Reference Figure 3 、 Figure 10 and Figure 14C In some embodiments, the orthographic projections of the hole regions in the first subpixel sp1, the second subpixel sp2, the third subpixel sp3, and the fourth subpixel sp4, respectively, on the base substrate BS are substantially covered by the orthographic projections of the first anode AD1 of the first light-emitting element in the first subpixel sp1, the second anode AD2 of the second light-emitting element in the second subpixel sp2, the third anode AD3 of the third light-emitting element in the third subpixel sp3, and the fourth anode AD4 of the fourth light-emitting element in the fourth subpixel sp4, respectively, on the base substrate BS. Alternatively, the orthographic projections of the hole regions in the first subpixel sp1, the second subpixel sp2, the third subpixel sp3, and the fourth subpixel sp4, respectively, on the base substrate BS are completely covered by the orthographic projections of the first anode AD1 of the first light-emitting element in the first subpixel sp1, the second anode AD2 of the second light-emitting element in the second subpixel sp2, the third anode AD3 of the third light-emitting element in the third subpixel sp3, and the fourth anode AD4 of the fourth light-emitting element in the fourth subpixel sp4, respectively, on the base substrate BS.

[0097] Figure 15C It shows Figure 11 The structure of the anode and the second conductive layer in the array substrate is shown. Figure 14CCompared to the array substrate shown in FIG. 1 , the percentage of the orthographic projection of the hole area in the first sub-pixel sp1 covered by the orthographic projection of the first anode AD1 of the first light-emitting element in the first sub-pixel sp1 is much smaller than the percentage of the orthographic projection of the hole area in the second sub-pixel sp2, the third sub-pixel sp3, and the fourth sub-pixel sp4 on the base substrate BS covered by the orthographic projection of the second anode AD2 of the second light-emitting element in the second sub-pixel sp2, the third anode AD3 of the third light-emitting element in the third sub-pixel sp3, and the fourth anode AD4 of the fourth light-emitting element in the fourth sub-pixel sp4 on the base substrate BS, respectively. In an example, in FIG. Figure 11 、 Figure 13 and Figure 15C In the array substrate shown, the percentage of the orthographic projection of the hole area in the first sub-pixel sp1 covered by the orthographic projection of the first anode AD1 of the first light-emitting element in the first sub-pixel sp1 is less than 40% (for example, less than 35%, less than 30% or less than 25%); and the percentage of the orthographic projection of the hole area in the second sub-pixel sp2, the third sub-pixel sp3, and the fourth sub-pixel sp4 on the base substrate BS covered by the orthographic projection of the second anode AD2 of the second light-emitting element in the second sub-pixel sp2, the third anode AD3 of the third light-emitting element in the third sub-pixel sp3, and the fourth anode AD4 of the fourth light-emitting element in the fourth sub-pixel sp4 on the base substrate BS is greater than 60% (for example, 100%).

[0098] Figure 14D To show Figure 3 The structure of the anode and semiconductor material layer in the array substrate is shown. Figure 3 、 Figure 10 and Figure 14D In some embodiments, the percentages of the orthographic projections of the active layers of the driving transistors in the first subpixel, the second subpixel, the third subpixel, and the fourth subpixel on the base substrate covered by the orthographic projections of the first anode AD1 of the first light-emitting element in the first subpixel sp1, the second anode AD2 of the second light-emitting element in the second subpixel sp2, the third anode AD3 of the third light-emitting element in the third subpixel sp3, and the fourth anode AD4 of the fourth light-emitting element in the fourth subpixel sp4 on the base substrate BS are within 20% of each other, for example, within 18% of each other, within 16% of each other, within 14% of each other, within 12% of each other, within 10% of each other, within 8% of each other, within 6% of each other, within 4% of each other, within 2% of each other, or within 1% of each other.

[0099] Reference Figure 3 、 Figure 10 and Figure 14DIn some embodiments, the orthographic projections of the active layers of the driving transistors in the first sub-pixel sp1, the second sub-pixel sp2, the third sub-pixel sp3 and the fourth sub-pixel sp4 on the base substrate BS are substantially covered by the orthographic projections of the first anode AD1 of the first light emitting element in the first sub-pixel sp1, the second anode AD2 of the second light emitting element in the second sub-pixel sp2, the third anode AD3 of the third light emitting element in the third sub-pixel sp3 and the fourth anode AD4 of the fourth light emitting element in the fourth sub-pixel sp4 on the base substrate BS, respectively. Alternatively, the orthographic projections of the active layers of the driving transistors in the first sub-pixel sp1, the second sub-pixel sp2, the third sub-pixel sp3 and the fourth sub-pixel sp4 on the base substrate BS are fully covered by the orthographic projections of the first anode AD1 of the first light emitting element in the first sub-pixel sp1, the second anode AD2 of the second light emitting element in the second sub-pixel sp2, the third anode AD3 of the third light emitting element in the third sub-pixel sp3 and the fourth anode AD4 of the fourth light emitting element in the fourth sub-pixel sp4 on the base substrate BS, respectively.

[0100] Figure 15D is a diagram showing the structure of the anode and the semiconductor material layer in the array substrate shown in Figure 11 Figure 14D In the array substrate shown in FIG. 1, the percentage of the orthographic projection of the active layer ACTd of the driving transistor in the first sub-pixel sp1 covered by the orthographic projection of the first anode AD1 of the first light emitting element in the first sub-pixel sp1 is much smaller than the percentages of the orthographic projections of the active layers of the driving transistors in the second sub-pixel sp2, the third sub-pixel sp3 and the fourth sub-pixel sp4 on the base substrate BS covered by the orthographic projections of the second anode AD2 of the second light emitting element in the second sub-pixel sp2, the third anode AD3 of the third light emitting element in the third sub-pixel sp3 and the fourth anode AD4 of the fourth light emitting element in the fourth sub-pixel sp4 on the base substrate BS, respectively. In one example, in the array substrate shown in FIG. 1, the percentage of the orthographic projection of the active layer ACTd of the driving transistor in the first sub-pixel sp1 covered by the orthographic projection of the first anode AD1 of the first light emitting element in the first sub-pixel sp1 is less than 50%, while the percentages of the orthographic projections of the active layers of the driving transistors in the second sub-pixel sp2, the third sub-pixel sp3 and the fourth sub-pixel sp4 on the base substrate BS covered by the orthographic projections of the second anode AD2 of the second light emitting element in the second sub-pixel sp2, the third anode AD3 of the third light emitting element in the third sub-pixel sp3 and the fourth anode AD4 of the fourth light emitting element in the fourth sub-pixel sp4 on the base substrate BS are all greater than 50%. Figure 11 Figure 13 and Figure 15D ​​In the array substrate shown, the percentage of the orthographic projection of the active layer ACTd of the driving transistor in the first sub-pixel sp1 covered by the orthographic projection of the first anode AD1 of the first light-emitting element in the first sub-pixel sp1 is less than 40% (for example, less than 35%, less than 30% or less than 25%); and the percentage of the orthographic projections of the active layers of the driving transistors in the second sub-pixel sp2, the third sub-pixel sp3, and the fourth sub-pixel sp4 on the base substrate BS covered by the orthographic projections of the second anode AD2 of the second light-emitting element in the second sub-pixel sp2, the third anode AD3 of the third light-emitting element in the third sub-pixel sp3, and the fourth anode AD4 of the fourth light-emitting element in the fourth sub-pixel sp4 on the base substrate BS is greater than 60% (for example, 100%).

[0101] Figure 14E It shows Figure 3 The structure of the anode, node connection line and first conductive layer in the array substrate is shown. Figure 14E In some embodiments, the first anode AD1 of the first light-emitting element in the first subpixel sp1 includes a first portion Ph, a second portion Pr, and a third portion Pd. The first portion Ph is hexagonal in shape. Optionally, the hexagonal shape has a first side S1 and a second side S2 that are directly connected to each other. The second portion Pr is adjacent to the first side S1. The third portion Pd is adjacent to the second side S2. The second portion Pr and the third portion Pd are adjacent to each other along the third side S3. The first side S1, the second side S2, and the third side S3 are directly connected to each other at the corners of the hexagon.

[0102] like Figure 3 、 Figure 10 and Figure 14E As shown, in some embodiments, the orthographic projection of the first corresponding node connection line Cln1 in the first subpixel sp1 on the base substrate BS is substantially covered by the combination of the orthographic projections of the second portion Pr and the third portion Pd on the base substrate BS, and does not substantially overlap with the orthographic projection of the first portion Ph on the base substrate BS. The orthographic projection of a portion of the first corresponding node connection line Cln1 in the second main through-hole v2 on the base substrate BS is substantially covered by the orthographic projection of the second portion Pr on the base substrate BS. The orthographic projection of a portion of the first corresponding node connection line Cln1 in the first main through-hole v1 on the base substrate BS is substantially covered by the orthographic projection of the third portion Pd on the base substrate BS. The orthographic projection of the second portion Pr on the base substrate BS at least partially overlaps with the orthographic projection of the source electrode S3 of the third transistor T3 in the first subpixel sp1 on the base substrate BS. Optionally, the orthographic projection of at least one of the second portion Pr or the third portion Pd on the base substrate BS at least partially overlaps with the orthographic projection of the corresponding voltage supply line Vdd in the first subpixel sp1 on the base substrate BS.

[0103] Figure 15E is a diagram illustrating a structure of an anode, a node connection line, and a first conductive layer in an array substrate in Figure 11 . Compared with the array substrate illustrated in Figure 14E , Figure 15E the first anode AD1 in the array substrate illustrated in Figure 11 , Figure 13 and Figure 15E the array substrate illustrated in Figure 14E , a part of the third portion Pd and the second portion Pr in Figure 11 , Figure 13 and Figure 15E the array substrate illustrated in, a normal projection of a first respective node connection line Cln1 in the first sub-pixel sp1 on the base substrate BS is substantially not covered by the first anode AD1. A normal projection of a part of the first respective node connection line Cln1 in the second main via v2 on the base substrate BS is not covered by a normal projection of the second portion Pr on the base substrate BS. A normal projection of a part of the first respective node connection line Cln1 in the first main via v1 on the base substrate BS is substantially covered by a normal projection of the first anode AD1 on the base substrate BS. The normal projection of the first anode AD1 on the base substrate BS does not overlap with a normal projection of a source S3 of the third transistor T3 in the first sub-pixel sp1 on the base substrate BS. The normal projection of the first anode AD1 on the base substrate BS does not overlap with a normal projection of a respective voltage supply line Vdd in the first sub-pixel sp1 on the base substrate BS.

[0104] Referring to Figure 14E , in some embodiments, a second anode AD2 of a second light emitting element in the second sub-pixel sp2 comprises a fourth portion P4 of a rectangular shape and a fifth portion P5 of a trapezoidal shape. The fourth portion P4 and the fifth portion P5 abut each other along a fourth side S4.

[0105] Referring to Figure 14E , in some embodiments, a third anode AD3 of a third light emitting element in the third sub-pixel sp3 comprises a sixth portion P6 of a pentagonal shape, a seventh portion P7 of a rectangular shape, an eighth portion P8 of a quasi-rectangular shape, and a ninth portion P9 of a triangular shape. The sixth portion P6 and the seventh portion P7 abut each other along a fifth side S5. The seventh portion P7 abuts the eighth portion P8 and the ninth portion P9 along a sixth side S6, respectively. The eighth portion P8 and the ninth portion P9 abut each other along a seventh side S7.

[0106] Referring to Figure 14EIn some embodiments, the fourth anode AD4 of the fourth light-emitting element in the fourth subpixel SP4 includes a tenth portion P10 having a pentagonal shape, an eleventh portion P11 having a rectangular shape, and a twelfth portion P12 having a quasi-triangular shape. The tenth portion P10 is adjacent to the eleventh portion P11 and the twelfth portion P12 along the eighth side S8. The eleventh portion P11 and the twelfth portion P12 are adjacent to each other along the ninth side S9.

[0107] Reference Figure 3 、 Figure 5 as well as Figure 14E In some embodiments, the gate line GL extends through the first sub-pixel sp1, the second sub-pixel sp2, the third sub-pixel sp3, and the fourth sub-pixel sp4. The first corresponding node connection line Cln1, the second corresponding node connection line Cln2, the third corresponding node connection line Cln3, and the fourth corresponding node connection line Cln4 respectively pass through the gate line GL.

[0108] refer to Figure 3 、 Figure 5 and Figure 14E In some embodiments, the first anode AD1 passes through the first reset control signal line rst1 and the gate line GL; the second anode AD2 passes through the gate line GL and the emission control signal line em; the third anode AD3 passes through the first reset control signal line rst1 and the gate line GL; the fourth anode AD4 passes through the gate line GL, the emission control signal line em, and the second reset control signal line rst2.

[0109] In another aspect, the present disclosure provides a display panel comprising an array substrate as described herein or manufactured by the method described herein, and an opposing substrate facing the array substrate. Optionally, the display panel is an organic light-emitting diode (OLED) display panel. Optionally, the display panel is a micro-LED display panel.

[0110] Figure 16 To show Figure 3 The structure of the first conductive layer in the plurality of sub-pixels of the array substrate is shown. Figure 16 In some embodiments, the gate line GL extends along the first direction DR1. In some embodiments, the gate line GL includes a plurality of wide portions Wg, a plurality of narrow portions Ng, and a plurality of protrusions P alternately arranged along the first direction DR1. A first line width lw1 of the plurality of wide portions Wg is greater than a second line width lw2 of the plurality of narrow portions Ng. The plurality of wide portions Wg are respectively located in each sub-pixel along the first direction DR1. In some embodiments, each of the plurality of pixel driving circuits includes a driving transistor ( Figure 2 The driving transistor Td in the data writing transistor (eg, Figure 2 The second transistor T2 in the embodiment) and the compensation transistor (eg, Figure 2The third transistor T3 in FIG. This drive transistor is configured to generate a drive current for driving the light-emitting element to emit light. The data write transistor is configured to write the voltage of the data voltage signal and the threshold voltage of the drive transistor to the second capacitor electrode during a data write phase. By making the first line width lw1 greater than the second line width lw2, the active layer of the data write transistor can have an increased channel length, and data signals can be written in a more stable manner.

[0111] Optionally, a ratio of the first line width lw1 to the second line width lw2 is in a range of 1.1:1.0 to 3.0:1.0, for example, 1.1:1.0 to 1.5:1.0, 1.5:1.0 to 2.0:1.0, 2.0:1.0 to 2.5:1.0, or 2.5:1.0 to 3.0:1.0. Optionally, a ratio of the first line width lw1 to the second line width lw2 is 1.8:1.0. Optionally, the first line width lw1 is in a range of 3.5 μm to 4.5 μm. Optionally, the second line width lw2 is in a range of 2.5 μm to 3.5 μm.

[0112] In some embodiments, along the second direction Dr2, the first dimension of the plurality of wide portions Wg is greater than the second dimension of the plurality of narrow portions. Optionally, the second direction DR2 is at an angle in the range of 80 to 100 degrees relative to the first direction DR1. Optionally, the ratio of the first line width lw1 to the second line width lw2 is in the range of 1.1:1.0 to 3.0:1.0, for example, 1.1:1.0 to 1.5:1.0, 1.5:1.0 to 2.0:1.0, 2.0:1.0 to 2.5:1.0, or 2.5:1.0 to 3.0:1.0. Optionally, the ratio of the first dimension to the second dimension is 1.8:1.0. Optionally, the first dimension is in the range of 3.5 μm to 4.5 μm. Optionally, the second dimension is in the range of 2.5 μm to 3.5 μm. Optionally, each of the plurality of wide portions Wg has a first size greater than the second size by protruding toward both sides along the second direction DR2 relative to each of the plurality of narrow portions Ng.

[0113] In some embodiments, the plurality of wide portions Wg and the plurality of narrow portions Ng are alternately arranged along the first direction DR1 . Alternatively, the plurality of wide portions Wg are respectively located in each sub-pixel along the first direction DR1 .

[0114] Figure 17 It shows Figure 3 The structure of the semiconductor material layer and the first conductive layer in the plurality of sub-pixels of the array substrate is shown. Figure 17 In some embodiments, each of the plurality of protrusions P is a compensation transistor in each sub-pixel on the base substrate (eg, Figure 2The orthographic projection of each of the plurality of protrusions P in each sub-pixel on the base substrate is aligned with the gate of the compensation transistor (eg, Figure 2 In some embodiments, the orthographic projection of each of the plurality of wide portions Wg in each sub-pixel on the base substrate overlaps with the orthographic projection of a portion of the semiconductor material layer in each sub-pixel on the base substrate, thereby forming a data writing transistor (e.g., Figure 2 The positive projection of each of the plurality of wide portions Wg in each sub-pixel on the base substrate is aligned with the active layer of the data writing transistor (eg, Figure 2 The orthographic projection of the active layer of the second transistor T2 in the transistor overlaps with the base substrate.

[0115] In some embodiments, the aspect ratio of the active layer of the data write transistor is in the range of 1:1 to 3:1, for example, 1:1 to 1.5:1, 1.5:1 to 2:1, 2:1 to 2.5:1 or 2.5:1 to 3:1. The array substrate includes a gate line having a plurality of width portions Wg, thereby increasing the channel length of the active layer of the data write transistor. As used herein, the term aspect ratio of the active layer refers to the ratio of the channel length to the channel width of the active layer. Optionally, the channel length of the active layer of the data write transistor is in the range of 3.5 μm to 4.5 μm. Optionally, the channel width of the active layer of the data write transistor is in the range of 1.5 μm to 3.5 μm. Optionally, the active layer of the data write transistor (for example, a portion of the semiconductor material layer, the orthographic projection of which on the base substrate is covered by the orthographic projection of a corresponding one of the plurality of width portions Wg on the base substrate) is not processed to increase conductivity, for example, it is not doped.

[0116] Figure 18 FIG is an enlarged view of a portion of a grid line according to some embodiments of the present disclosure. Figure 18 In some embodiments, each of the plurality of wide portions Wg is wider than each of the plurality of narrow portions Ng by protruding toward both sides relative to each of the plurality of narrow portions Ng in a direction perpendicular to the first direction DR1. In one example, each of the plurality of wide portions Wg includes a body Mw having the same line width as each of the plurality of narrow portions Ng; and first and second protrusions Pw1 and Pw2, each protruding toward both sides relative to each of the plurality of narrow portions Ng in a direction perpendicular to the first direction DR1.

[0117] Figure 19 To show Figure 3The structure of the second conductive layer in the plurality of sub-pixels of the array substrate is shown. Figure 19 The second capacitor electrode Ce2 includes a main portion Mc and a connecting portion Cc that connects the main portions of the second capacitor electrodes of two adjacent sub-pixels along the first direction DR1. The main portion Mc has a wider portion Wc and a narrower portion Nc. The wider portion Wc has a width along a direction perpendicular to the first direction DR1 (e.g., along the second direction DR2) greater than a width of the narrower portion Nc along the direction perpendicular to the first direction DR1.

[0118] Figure 20 It shows Figure 3 The structure of the first conductive layer and the second conductive layer in the plurality of sub-pixels of the array substrate is shown. Figure 20 In some embodiments, the corresponding one of the plurality of wide portions Wg and the narrow portion Nc are arranged along the second direction DR2. Optionally, the orthographic projections of the corresponding one of the plurality of wide portions Wg and the narrow portion Nc on a plane containing a line along the first direction DR1 at least partially overlap with each other.

[0119] Optionally, the corresponding one of the plurality of wide portions Wg and the connecting portion Cc are arranged along the second direction DR2. Optionally, orthographic projections of the corresponding one of the plurality of wide portions Wg and the connecting portion Cc on a plane containing a line along the first direction at least partially overlap with each other.

[0120] In some embodiments, each column of pixel driving circuits corresponds to a data line DL. Optionally, the data line DL includes a main data line portion and a protruding data line portion. Optionally, the protruding data line portion is larger than the main data line portion in the first direction DR1.

[0121] Figure 21 It shows Figure 3 The structure of the first conductive layer and the first signal line layer in the plurality of sub-pixels of the array substrate shown in FIG. Figure 21 In some embodiments, an orthographic projection of each of the plurality of wide portions Wg on the base substrate only partially overlaps with an orthographic projection of the data line DL on the base substrate. Alternatively, an orthographic projection of each of the plurality of wide portions Wg on the base substrate partially overlaps with an orthographic projection of the data line DL on the base substrate, thereby forming an overlapping portion, and a ratio of a dimension of the overlapping portion along the first direction DR1 to a dimension of the main data line portion along the first direction DR1 is in a range of 10% to 100%.

[0122] The overlap between the orthographic projection of each of the plurality of wide portions Wg on the base substrate and the orthographic projection of the data line DL on the base substrate can be minimized. Alternatively, the orthographic projection of each of the plurality of wide portions Wg on the base substrate does not overlap with the orthographic projection of the data line DL on the base substrate. Alternatively, the orthographic projection of each of the plurality of wide portions Wg on the base substrate and the orthographic projection of the data line DL on the base substrate are arranged alternately.

[0123] refer to Figure 3 、 Figure 10 and Figure 14A In some embodiments, the orthographic projections of the first nodes in the first subpixel sp1, the second subpixel sp2, and the third subpixel sp3 on the base substrate are covered by at least 50% (e.g., at least 60%, at least 70%, at least 80%, at least 90%, or at least 95%) of the orthographic projections of the first anode AD1 of the first light-emitting element in the first subpixel sp1, the second anode AD2 of the second light-emitting element in the second subpixel sp2, and the third anode AD3 of the third light-emitting element in the third subpixel sp3 on the base substrate. As used herein, each first node N1 in each subpixel includes the corresponding gate electrode (e.g., the first capacitor electrode Ce1) of the drive transistor in each subpixel and the corresponding node connection line. Optionally, the orthographic projections of the node connection lines in the first subpixel sp1, the second subpixel sp2, and the third subpixel sp3 on the base substrate are covered by at least 80% of the orthographic projections of the first anode AD1 of the first light-emitting element in the first subpixel sp1, the second anode AD2 of the second light-emitting element in the second subpixel sp2, and the third anode AD3 of the third light-emitting element in the third subpixel sp3 on the base substrate. With this structure, the sub-pixels in the array substrate can emit light in a more uniform manner. In this array substrate, the orthographic projection of the anode covers the orthographic projection of the node connection line to a greater extent, and thus covers less of the orthographic projection of the capacitor electrode, thereby reducing the load on the storage capacitor.

[0124] In some embodiments, the orthographic projections of the first nodes in the first subpixel sp1, the second subpixel sp2, the third subpixel sp3, and the fourth subpixel sp4, respectively, on the base substrate are covered by at least 50% (e.g., at least 60%, at least 70%, at least 80%, at least 90%, or at least 95%) of the orthographic projections of the first anode AD1 of the first light-emitting element in the first subpixel sp1, the second anode AD2 of the second light-emitting element in the second subpixel sp2, the third anode AD3 of the third light-emitting element in the third subpixel sp3, and the fourth anode AD4 of the fourth light-emitting element in the fourth subpixel sp4, respectively, on the base substrate. Optionally, the orthographic projections of the node connection lines in the first subpixel sp1, the second subpixel sp2, the third subpixel sp3, and the fourth subpixel sp4, respectively, on the base substrate are covered by at least 80% of the orthographic projections of the first anode AD1 of the first light-emitting element in the first subpixel sp1, the second anode AD2 of the second light-emitting element in the second subpixel sp2, the third anode AD3 of the third light-emitting element in the third subpixel sp3, and the fourth anode AD4 of the fourth light-emitting element in the fourth subpixel sp4, respectively, on the base substrate.

[0125] In some embodiments, the orthographic projection of the first node N1 in the second sub-pixel sp2 on the base substrate is covered by at least 60% by the orthographic projection of the second anode AD2 of the second light-emitting element in the second sub-pixel sp2 on the base substrate; the orthographic projection of the first node N1 in the fourth sub-pixel sp4 on the base substrate is covered by at least 60% by the orthographic projection of the fourth anode AD4 of the fourth light-emitting element in the fourth sub-pixel sp4 on the base substrate; and the first area covered by the orthographic projection of the first node N1 in the second sub-pixel sp2 on the base substrate by the orthographic projection of the second anode AD2 of the second light-emitting element in the second sub-pixel sp2 on the base substrate is greater than the second area covered by the orthographic projection of the first node N1 in the fourth sub-pixel sp4 on the base substrate by the orthographic projection of the fourth anode AD4 of the fourth light-emitting element in the fourth sub-pixel sp4 on the base substrate.

[0126] Figure 22 It shows Figure 3 FIG. 1 shows the structure of the anode, node connection line, and first conductive layer in the array substrate. Figure 22 The orthographic projection of the fourth anode AD4 of the fourth light-emitting element in the fourth subpixel on the base substrate has a first edge E1 and a second edge E2, which are respectively located along a first direction on either side of the orthographic projection of the node connection line Cln4 in the fourth subpixel on the base substrate. Optionally, the first edge E1 is a non-straight line, and the second edge E2 comprises a straight line. Optionally, the first edge E1 is a curve, and the second edge E2 comprises one or more straight lines. The first direction DR1 is perpendicular to the orthographic projection of the node connection line Cln4 in the fourth subpixel on the base substrate.

[0127] refer to Figure 22 In some embodiments, the third anode AD3 of the third light emitting element in the third sub-pixel includes a main third anode portion Ph2 having a hexagonal shape, and an additional third anode portion Pe3. Figure 22 and Figure 16 The orthographic projection of a portion of the third anode AD3 of the third light emitting element in the third sub-pixel (eg, the additional third anode portion Pe3) on the base substrate is aligned with the gate of the third transistor (eg, Figure 16 The orthographic projections of a corresponding one of the plurality of protrusions P in the embodiment of the present invention on the base substrate at least partially overlap to stabilize the potential level of the third transistor.

[0128] Reference Figure 22 In some embodiments, the first anode AD1 of the first light-emitting element in the first subpixel sp1 includes a hexagonal shape comprising a first portion Ph, a second portion Pr, and a third portion Pd. Optionally, the hexagonal shape includes a first side S1 and a second side S2 that are directly connected to each other. The second portion Pr abuts the first side S1. The third portion Pd abuts the second side S2. The second portion Pr and the third portion Pd abut each other along a third side S3. The first side S1, the second side S2, and the third side S3 are directly connected to each other at the corners of the hexagonal shape.

[0129] In some embodiments, the second portion Pr includes a first sub-portion Pr1 and a second sub-portion Pr2. The orthographic projection of the first sub-portion Pr1 on the base substrate at least partially overlaps with the orthographic projection of the node connection line Cln1 in the first sub-pixel on the base substrate, but does not overlap with the orthographic projection of the gate of the driving transistor in the first sub-pixel (e.g., the first capacitor electrode Ce1) on the base substrate. The orthographic projection of the second sub-portion Pr2 on the base substrate at least partially overlaps with the orthographic projection of the node connection line Cln1 in the first sub-pixel on the base substrate, and at least partially overlaps with the orthographic projection of the gate of the driving transistor in the first sub-pixel on the base substrate.

[0130] Figure 23 for Figure 22 A magnified partial view of the . Figure 22 and Figure 23 , a first width wr1 of the second subportion Pr2 along the first direction DR1 is greater than a second width wr2 of the first subportion Pr1 along the first direction DR1.

[0131] Figure 24 It shows Figure 3 The structure of the anode and anode contact pad in the array substrate is shown in FIG. Figure 24 and Figures 7 to 9In some embodiments, in the first sub-pixel sp1, the first anode AD1 is connected to the first anode contact pad ACP1 through a first through-hole V1-1 extending through the second planarization layer, and the first anode contact pad ACP1 is connected to the first relay electrode RE1 through a second through-hole V1-2 extending through the first planarization layer; in the second sub-pixel sp2, the second anode AD2 is connected to the second anode contact pad ACP2 through a third through-hole V2-1 extending through the second planarization layer, and the second anode contact pad ACP2 is connected to the second relay electrode RE1 through a fourth through-hole V2-2 extending through the first planarization layer. In the third sub-pixel sp3, the third anode AD3 is connected to the third anode contact pad ACP3 through the fifth through hole V3-1 extending through the second planarization layer, and the third anode contact pad ACP3 is connected to the third relay electrode RE3 through the sixth through hole V3-2 extending through the first planarization layer; in the fourth sub-pixel sp4, the fourth anode AD4 is connected to the fourth anode contact pad ACP4 through the seventh through hole V4-1 extending through the second planarization layer, and the fourth anode contact pad ACP4 is connected to the fourth relay electrode RE4 through the eighth through hole V4-2 extending through the first planarization layer. Figure 24 As shown, the first distance between the first through hole V1-1 and the second through hole V1-2 is greater than the second distance between the third through hole V2-1 and the fourth through hole V2-2. The third distance between the fifth through hole V3-1 and the sixth through hole V3-2 is greater than the second distance between the third through hole V2-1 and the fourth through hole V2-2.

[0132] In this array substrate, the fourth through hole V2-2 can be spaced apart from the effective light-emitting area of ​​the second subpixel sp2 by making the second distance smaller than the first distance and smaller than the third distance. In some embodiments, the first shortest distance between the orthographic projection of the first effective light-emitting area of ​​the first subpixel sp1 and the orthographic projection of the second through hole V1-2 on the base substrate is greater than the second shortest distance between the orthographic projection of the second effective light-emitting area of ​​the second subpixel sp2 and the orthographic projection of the fourth through hole V2-2 on the base substrate. Optionally, the third shortest distance between the orthographic projection of the third effective light-emitting area of ​​the third subpixel sp3 on the base substrate and the orthographic projection of the sixth through hole V3-2 on the base substrate is greater than the second shortest distance.

[0133] In some embodiments, a fourth shortest distance between a footprint on the base substrate of the second via V1-2 and a footprint on the base substrate of any anode adjacent to the first anode AD1 is greater than a fifth shortest distance between a footprint on the base substrate of the sixth via V3-2 and a footprint on the base substrate of any anode adjacent to the third anode AD3. Optionally, a sixth shortest distance between a footprint on the base substrate of the fourth via V2-2 and a footprint on the base substrate of any anode adjacent to the second anode AD2 is greater than the fifth shortest distance.

[0134] In some embodiments, a first length of the first anode contact pad ACP1 along the second direction DR2 and a second length of the second anode contact pad ACP2 along the second direction DR2 are less than a third length of the third anode contact pad ACP3 along the second direction DR2. Optionally, a fourth length of the fourth anode contact pad ACP4 along the second direction DR2 is less than the third length of the third anode contact pad ACP3 along the second direction DR2.

[0135] By having the third length greater than the first length and the second length, the sixth via V3-2 can be spaced apart from the first anode of the first sub-pixel sp1 in the adjacent row. By having such a structure, the first anode can be disposed on a more planar surface. In some embodiments, a shortest distance between a footprint on the base substrate of the sixth via V3-2 and a footprint on the base substrate of an anode in the adjacent row is less than a shortest distance between a footprint on the base substrate of the second via V1-2 and a footprint on the base substrate of an anode in the adjacent row, and also less than a shortest distance between a footprint on the base substrate of the fourth via V2-2 and a footprint on the base substrate of an anode in the adjacent row.

[0136] Referring to Figure 3 , Figure 10 with Figure 14A In some embodiments, a third area in which a footprint on the base substrate of a first node N1 in the first sub-pixel sp1 is covered by a footprint on the base substrate of a first anode AD1 of the first light emitting element in the first sub-pixel sp1 is substantially the same as a fourth area in which a footprint on the base substrate of a first node N1 in the third sub-pixel sp3 is covered by a footprint on the base substrate of a third anode AD3 of the third light emitting element in the third sub-pixel sp3. Optionally, the third area and the fourth area are less than a first area in which a footprint on the base substrate of a first node N1 in the second sub-pixel sp1 is covered by a footprint on the base substrate of a second anode AD2 of the second light emitting element in the second sub-pixel sp2.

[0137] Figure 25 is shown Figure 3A diagram of the structure of the anode, the first conductive layer, and the second signal line layer in the array substrate shown. Figure 26 to avoid any overlap with the second voltage supply line Vdd2 on the base substrate. The orthogonal projection of the fourth anode AD4 on the base substrate does not overlap with the orthogonal projection of the second voltage supply line Vdd2 on the base substrate, which achieves a substantially planar surface of the second planarization layer PLN2 under the fourth anode AD4. As a result, the fourth anode AD4 is not tilted, thereby eliminating the color shift problem. Figure 11 Figure 25 Similarly, the orthogonal projection of the third anode AD3 on the base substrate does not overlap with the orthogonal projection of the branch line BRL in the second signal line layer on the base substrate to achieve a substantially planar surface of the second planarization layer PLN2 under the third anode AD3. Figure 26

[0138]

[0139] Figure 27 is a cross-sectional view along the line D-D' in Figure 11 Referring to Figure 27 A respective one of the plurality of wide portions Wg and the connection portion Cc are arranged along the second direction. Optionally, the orthogonal projection of the respective one of the plurality of wide portions Wg on a plane containing a line along the first direction at least partially overlaps with the orthogonal projection of the connection portion Cc on the plane containing a line along the first direction.

[0140] In another aspect, the present application provides a display device comprising an array substrate as described herein or manufactured by a method as described herein, and one or more integrated circuits connected to the array substrate.

[0141] In another aspect, the present application provides a method of manufacturing an array substrate. In some embodiments, the method comprises forming a plurality of light emitting elements, and forming a plurality of pixel drive circuits respectively in a plurality of sub-pixels and configured to respectively drive the plurality of light emitting elements. Optionally, forming each of the plurality of pixel drive circuits comprises forming a plurality of transistors, and forming a storage capacitor. Optionally, forming the storage capacitor comprises forming a first capacitor electrode, forming a second capacitor electrode electrically connected to a respective voltage supply line, and forming an insulating layer between the first capacitor electrode and the second capacitor electrode.

[0142] ​​​In some embodiments, the method includes: forming a semiconductor material layer on a base substrate; forming a node connection line that is in the same layer as each voltage supply line; forming a first main through hole and a second main through hole in the array substrate; connecting the node connection line to the first capacitor electrode through the first main through hole; and connecting the node connection line to the semiconductor material layer through the second main through hole.

[0143] In some embodiments, forming multiple sub-pixels includes: forming a first sub-pixel configured to emit light of a first color; forming a second sub-pixel configured to emit light of a second color; forming a third sub-pixel configured to emit light of a third color; and forming a fourth sub-pixel configured to emit light of the second color.

[0144] In some embodiments, the percentages of the orthographic projections of the first corresponding node connection line in the first sub-pixel, the second corresponding node connection line in the second sub-pixel, the third corresponding node connection line in the third sub-pixel, and the fourth corresponding node connection line in the fourth sub-pixel on the base substrate covered by the orthographic projections of the first anode of the first light-emitting element in the first sub-pixel, the second anode of the second light-emitting element in the second sub-pixel, the third anode of the third light-emitting element in the third sub-pixel, and the fourth anode of the fourth light-emitting element in the fourth sub-pixel on the base substrate are within 20% of each other.

[0145] In some embodiments, the orthographic projections of the first corresponding node connection line in the first subpixel, the second corresponding node connection line in the second subpixel, the third corresponding node connection line in the third subpixel, and the fourth corresponding node connection line in the fourth subpixel on the base substrate are respectively substantially covered by the orthographic projections of the first anode of the first light-emitting element in the first subpixel, the second anode of the second light-emitting element in the second subpixel, the third anode of the third light-emitting element in the third subpixel, and the fourth anode of the fourth light-emitting element in the fourth subpixel on the base substrate.

[0146] In some embodiments, the percentages of the orthographic projections of the first capacitor electrodes in the first subpixel, the second subpixel, the third subpixel, and the fourth subpixel on the base substrate covered by the orthographic projections of the first anode of the first light-emitting element in the first subpixel, the second anode of the second light-emitting element in the second subpixel, the third anode of the third light-emitting element in the third subpixel, and the fourth anode of the fourth light-emitting element in the fourth subpixel on the base substrate are within 20% of each other.

[0147] In some embodiments, the method further includes: forming a semiconductor material layer on a base substrate; forming a gate insulating layer on a side of the semiconductor material layer remote from the base substrate, the first capacitor electrode being located on the side of the gate insulating layer remote from the base substrate; and forming an interlayer dielectric layer on a side of the first capacitor electrode remote from the gate insulating layer, the node connection line being located on a side of the interlayer dielectric layer remote from the second capacitor electrode. Optionally, a first main via is formed in a hole region where a portion of the second capacitor electrode is not present, and is formed to extend through the interlayer dielectric layer and the insulating layer. Optionally, an orthographic projection of the second capacitor electrode on the base substrate completely covers an orthographic projection of the first capacitor electrode on the base substrate, leaving a margin, excluding the hole region. Optionally, the second main via is formed to extend through the interlayer dielectric layer, the insulating layer, and the gate insulating layer.

[0148] In some embodiments, the percentages of the orthographic projections of the aperture regions in the first, second, third, and fourth subpixels on the base substrate covered by the orthographic projections of the first anode of the first light-emitting element in the first subpixel, the second anode of the second light-emitting element in the second subpixel, the third anode of the third light-emitting element in the third subpixel, and the fourth anode of the fourth light-emitting element in the fourth subpixel on the base substrate are within 20% of each other. Optionally, portions of the second capacitor electrodes in the first, second, third, and fourth subpixels are not within the aperture regions. Optionally, the aperture regions are each surrounded by the second capacitor electrodes.

[0149] In some embodiments, the orthographic projections of the hole areas in the first subpixel, the second subpixel, the third subpixel, and the fourth subpixel, respectively, on the base substrate are substantially covered by the orthographic projections of the first anode of the first light-emitting element in the first subpixel, the second anode of the second light-emitting element in the second subpixel, the third anode of the third light-emitting element in the third subpixel, and the fourth anode of the fourth light-emitting element in the fourth subpixel on the base substrate.

[0150] In some embodiments, forming a plurality of transistors in each of the plurality of pixel drive circuits includes forming a drive transistor. The first capacitor electrode in each of the plurality of pixel drive circuits also serves as a gate of the drive transistor. Forming a semiconductor material layer includes forming an active layer of the drive transistor. Optionally, the percentages of the orthographic projections of the active layers of the drive transistors in the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel, respectively, on the base substrate covered by the orthographic projections of the first anode of the first light-emitting element in the first sub-pixel, the second anode of the second light-emitting element in the second sub-pixel, the third anode of the third light-emitting element in the third sub-pixel, and the fourth anode of the fourth light-emitting element in the fourth sub-pixel on the base substrate are within 20% of each other.

[0151] In some embodiments, the orthographic projections of the active layers of the driving transistors in the first subpixel, the second subpixel, the third subpixel, and the fourth subpixel, respectively, on the base substrate are substantially covered by the orthographic projections of the first anode of the first light-emitting element in the first subpixel, the second anode of the second light-emitting element in the second subpixel, the third anode of the third light-emitting element in the third subpixel, and the fourth anode of the fourth light-emitting element in the fourth subpixel on the base substrate.

[0152] In some embodiments, the first anode of the first light-emitting element in the first subpixel is formed to include a first portion, a second portion, and a third portion of a hexagonal shape. The hexagonal shape has a first side and a second side that are directly connected to each other. The second portion is adjacent to the first side. The third portion is adjacent to the second side. The second portion and the third portion are adjacent to each other along the third side. The first side, the second side, and the third side are directly connected to each other at the corners of the hexagonal shape.

[0153] In some embodiments, the orthographic projection of the first corresponding node connection line in the first sub-pixel on the base substrate is substantially covered by a combination of the orthographic projections of the second portion and the third portion on the base substrate, respectively, and substantially does not overlap with the orthographic projection of the first portion on the base substrate.

[0154] In some embodiments, the orthographic projection of the portion of the first corresponding node connection line in the second main through hole on the base substrate is substantially covered by the orthographic projection of the second portion on the base substrate; the orthographic projection of the portion of the first corresponding node connection line in the first main through hole on the base substrate is substantially covered by the orthographic projection of the third portion on the base substrate.

[0155] In some embodiments, the plurality of transistors formed in each of the plurality of pixel driving circuits include a third transistor. Optionally, the semiconductor material layer in the first sub-pixel is formed to include a source electrode of the third transistor in the first sub-pixel, and the source electrode of the third transistor in the first sub-pixel is electrically connected to the first capacitor electrode via a first corresponding node connection line in the first sub-pixel. Optionally, an orthographic projection of the second portion on the base substrate at least partially overlaps with an orthographic projection of the source electrode of the third transistor in the first sub-pixel on the base substrate.

[0156] In some embodiments, an orthographic projection of at least one of the second portion or the third portion on the base substrate at least partially overlaps with an orthographic projection of a corresponding voltage supply line in the first sub-pixel on the base substrate.

[0157] In some embodiments, the second anode of the second light-emitting element in the second subpixel is formed to include a fourth portion having a rectangular shape and a fifth portion having a trapezoidal shape, and the fourth portion and the fifth portion are adjacent to each other along the fourth side.

[0158] In some embodiments, the third anode of the third light-emitting element in the third subpixel is formed to include a pentagonal sixth portion, a rectangular seventh portion, a quasi-rectangular eighth portion, and a triangular ninth portion. The sixth and seventh portions are adjacent to each other along the fifth side. The seventh portion is adjacent to the eighth and ninth portions along the sixth side, respectively. The eighth and ninth portions are adjacent to each other along the seventh side.

[0159] In some embodiments, the fourth anode of the fourth light-emitting element in the fourth subpixel is formed to include a tenth portion having a pentagonal shape, an eleventh portion having a rectangular shape, and a twelfth portion having a quasi-triangular shape. The tenth portion is adjacent to the eleventh portion and the twelfth portion along the eighth side, respectively. The eleventh portion and the twelfth portion are adjacent to each other along the ninth side.

[0160] In some embodiments, the method further comprises: forming a gate line extending through the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel. Optionally, the first corresponding node connection line, the second corresponding node connection line, the third corresponding node connection line, and the fourth corresponding node connection line are formed to pass through the gate line respectively.

[0161] In some embodiments, forming a plurality of transistors includes: forming a driving transistor; forming a first transistor; forming a second transistor; forming a third transistor; forming a fourth transistor; forming a fifth transistor; and forming a sixth transistor. Optionally, the method further includes: forming a first reset control signal line connected to the gate of the first transistor; forming a gate line connected to the gates of the second and third transistors; forming a light emission control signal line connected to the gates of the fourth and fifth transistors; and forming a second reset control signal line connected to the gate of the sixth transistor.

[0162] In some embodiments, the first anode passes through the first reset control signal line and the gate line; the second anode passes through the gate line and the light-emitting control signal line; the third anode passes through the first reset control signal line and the gate line; the fourth anode passes through the gate line, the light-emitting control signal line and the second reset control signal line.

[0163] The foregoing description of the embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and various modifications as are suited to the particular use or implementation contemplated. The scope of the present invention is intended to be defined by the appended claims and their equivalents, in which all terms are to be used in their broadest reasonable sense unless otherwise indicated. Therefore, the terms "the invention," "the present invention," etc. do not necessarily limit the scope of the claims to specific embodiments, and reference to exemplary embodiments of the present invention is not intended to limit the invention, and no such limitation should be inferred. The present invention is limited solely by the spirit and scope of the appended claims. Furthermore, the claims may use the terms "first," "second," etc., followed by a noun or element. These terms should be understood as nomenclature and should not be construed as limiting the number of elements to which they refer unless a specific number is provided. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, no element or component in this disclosure is intended to be dedicated to the public, regardless of whether the element or component is explicitly stated in the appended claims.

Claims

1. An array substrate, comprising: base substrate; a semiconductor material layer located on the base substrate; a gate line extending along a first direction; a plurality of pixel driving circuits, each in a plurality of sub-pixels, each configured to drive a plurality of light-emitting elements; each pixel driving circuit in the plurality of pixel driving circuits includes a driving transistor, a data writing transistor, and a compensation transistor; the driving transistor is configured to generate a driving current for driving the light-emitting element to emit light; and the data writing transistor is configured to write a voltage into a gate of the driving transistor; a node connection line connecting the gate of the driving transistor and one of the source and the drain of the compensation transistor; in, The gate lines include a plurality of wide portions and a plurality of narrow portions respectively arranged along the first direction, a first dimension of the plurality of wide portions is greater than a second dimension of the plurality of narrow portions along a second direction, and the second direction forms an angle in a range of 80 degrees to 100 degrees relative to the first direction; An orthographic projection of a corresponding wide portion of the plurality of wide portions in a corresponding sub-pixel on the base substrate overlaps with an orthographic projection of a portion of the semiconductor material layer in the corresponding sub-pixel on the base substrate, thereby forming an active layer of the data writing transistor in the corresponding sub-pixel; and A ratio of a channel length to a channel width of an active layer of the data writing transistor is in a range of 1.5:1 to 3:1; The plurality of sub-pixels include a first sub-pixel configured to emit light of a first color; a second sub-pixel configured to emit light of a second color; and a third sub-pixel configured to emit light of a third color. orthographic projections of a first node in the first subpixel, a first node in the second subpixel, and a first node in the third subpixel on the base substrate are respectively covered by at least 50% of orthographic projections of a first anode of a first light-emitting element in the first subpixel, a second anode of a second light-emitting element in the second subpixel, and a third anode of a third light-emitting element in the third subpixel on the base substrate, each first node in each subpixel includes a corresponding gate of the driving transistor and a corresponding node connection line in each subpixel; and The orthographic projections of the node connection line in the first sub-pixel, the node connection line in the second sub-pixel, and the node connection line in the third sub-pixel on the base substrate are respectively covered by at least 80% of the orthographic projections of the first anode of the first light-emitting element in the first sub-pixel, the second anode of the second light-emitting element in the second sub-pixel, and the third anode of the third light-emitting element in the third sub-pixel on the base substrate.

2. The array substrate according to claim 1, wherein: A ratio of the channel length to the channel width of the active layer of the data write transistor is in a range of 2:1 to 3:

1.

3. The array substrate according to claim 1, wherein: The plurality of wide portions and the plurality of narrow portions are alternately arranged along the first direction; and The plurality of wide portions are respectively located in the sub-pixels along the first direction.

4. The array substrate according to claim 1, wherein: The plurality of wide portions have a first line width; The plurality of narrow portions have a second line width; and A ratio of the first line width to the second line width is in a range of 1.1:1 to 3:

1.

5. The array substrate according to claim 1, wherein: Each of the plurality of wide portions has the first size greater than the second size by protruding toward both sides along the second direction relative to each of the plurality of narrow portions.

6. The array substrate according to claim 1, wherein: Each of the plurality of pixel driving circuits further includes a storage capacitor, the storage capacitor including a first capacitor electrode, a second capacitor electrode, and an insulating layer between the first capacitor electrode and the second capacitor electrode; The second capacitor electrode includes a main portion and a connecting portion, wherein the connecting portion connects the main portions of the second capacitor electrodes from two adjacent sub-pixels along the first direction; The main body portion has a wider portion and a narrower portion, wherein a width of the wider portion along a second direction is greater than a width of the narrower portion along a direction perpendicular to the first direction; as well as Orthographic projections of corresponding wide portions of the plurality of wide portions and the narrower portion on a line arranged along the first direction at least partially overlap with each other.

7. The array substrate according to claim 1, wherein: Each of the plurality of pixel driving circuits further includes a storage capacitor, the storage capacitor including a first capacitor electrode, a second capacitor electrode, and an insulating layer between the first capacitor electrode and the second capacitor electrode; The second capacitor electrode includes a main portion and a connecting portion, wherein the connecting portion connects the main portions of the second capacitor electrodes from two adjacent sub-pixels along the first direction; as well as Orthographic projections of corresponding wide portions of the plurality of wide portions and the connecting portion on a line arranged along the first direction at least partially overlap with each other.

8. The array substrate according to claim 1, further comprising a data line extending along the second direction; Each column of pixel driving circuit corresponds to the data line; The data line includes a main data line portion and a protruding data line portion; The size of the protruding data line portion along the first direction is greater than the size of the main data line portion along the first direction; in, The orthographic projection of each of the multiple wide portions on the base substrate partially overlaps with the orthographic projection of the data line on the base substrate, thereby forming an overlapping portion, and the ratio of the size of the overlapping portion along the first direction to the size of the main data line portion along the first direction is in the range of 10% to 100%.

9. The array substrate according to claim 1, further comprising a data line extending along the second direction; Each column of pixel driving circuit corresponds to the data line; The data line includes a main data line portion and a protruding data line portion; The size of the protruding data line portion along the first direction is greater than the size of the main data line portion along the first direction; in, An orthographic projection of any one of the plurality of wide portions on the base substrate and an orthographic projection of the data line on the base substrate are spaced apart from each other. 10 . A display device comprising the array substrate according to claim 1 .

11. An array substrate comprising a plurality of pixel driving circuits respectively in a plurality of sub-pixels, wherein the plurality of pixel driving circuits are configured to respectively drive a plurality of light-emitting elements; in, Each pixel driving circuit of the plurality of pixel driving circuits includes a driving transistor and a compensation transistor; Wherein, the array substrate comprises: a node connection line connecting the gate of the driving transistor and one of the first electrode and the second electrode of the compensation transistor; The plurality of sub-pixels include a first sub-pixel configured to emit light of a first color; a second sub-pixel configured to emit light of a second color; and a third sub-pixel configured to emit light of a third color. orthographic projections of a first node in the first subpixel, a first node in the second subpixel, and a first node in the third subpixel on the base substrate are respectively covered by at least 50% of orthographic projections of a first anode of a first light-emitting element in the first subpixel, a second anode of a second light-emitting element in the second subpixel, and a third anode of a third light-emitting element in the third subpixel on the base substrate, each first node in each subpixel includes a corresponding gate of the driving transistor and a corresponding node connection line in each subpixel; and The orthographic projections of the node connection line in the first sub-pixel, the node connection line in the second sub-pixel, and the node connection line in the third sub-pixel on the base substrate are respectively covered by at least 80% of the orthographic projections of the first anode of the first light-emitting element in the first sub-pixel, the second anode of the second light-emitting element in the second sub-pixel, and the third anode of the third light-emitting element in the third sub-pixel on the base substrate.

12. The array substrate according to claim 11, wherein: The plurality of sub-pixels further include a fourth sub-pixel configured to emit light of the second color; wherein the orthographic projection of the first node in the second sub-pixel on the base substrate is covered by at least 60% of the orthographic projection of the second anode of the second light-emitting element in the second sub-pixel on the base substrate; The orthographic projection of the first node in the fourth subpixel on the base substrate is covered by at least 60% of the orthographic projection of the fourth anode of the fourth light-emitting element in the fourth subpixel on the base substrate; and A first area covered by the orthographic projection of the first node in the second sub-pixel on the base substrate and the second anode of the second light-emitting element in the second sub-pixel on the base substrate is greater than a second area covered by the orthographic projection of the first node in the fourth sub-pixel on the base substrate and the fourth anode of the fourth light-emitting element in the fourth sub-pixel on the base substrate.

13. The array substrate according to claim 12, wherein: An orthographic projection of a fourth anode of the fourth light-emitting element in the fourth sub-pixel on the base substrate has a first edge and a second edge, the first edge and the second edge are respectively located on either side of an orthographic projection of a node connection line in the fourth sub-pixel on the base substrate along a first direction, and the first direction is perpendicular to the orthographic projection of the node connection line in the fourth sub-pixel on the base substrate; The first edge is a non-straight line; as well as The second edge comprises a straight line.

14. The array substrate according to claim 11, wherein: The compensation transistor has a double-gate structure; An orthographic projection of a portion of a third anode of the third light-emitting element in the third sub-pixel on the base substrate at least partially overlaps with an orthographic projection of the gate of the compensation transistor on the base substrate.

15. The array substrate according to claim 11, wherein: The first anode of the first light-emitting element in the first sub-pixel includes a first portion, a second portion, and a third portion in a hexagonal shape; The hexagonal shape has a first side and a second side directly connected to each other; the second portion being adjacent to the first side; The third portion is adjacent to the second side; The second portion and the third portion are adjacent to each other along a third side; as well as The first side, the second side, and the third side are directly connected to each other at corners of the hexagonal shape.

16. The array substrate according to claim 15, wherein: The second portion includes a first sub-portion and a second sub-portion; An orthographic projection of the first sub-portion on the base substrate at least partially overlaps with an orthographic projection of a node connection line in the first sub-pixel on the base substrate, but does not overlap with an orthographic projection of a gate of the driving transistor in the first sub-pixel on the base substrate; An orthographic projection of the second sub-portion on the base substrate at least partially overlaps with an orthographic projection of the node connection line in the first sub-pixel on the base substrate, and at least partially overlaps with an orthographic projection of the gate of the driving transistor in the first sub-pixel on the base substrate; The array substrate includes gate lines extending along a first direction; as well as A first width of the second subsection along the first direction is greater than a second width of the first subsection along the first direction.

17. The array substrate according to claim 11, wherein: The anode is located on a side of the second planarization layer away from the first planarization layer; wherein, in the first sub-pixel, the first anode is connected to the first anode contact pad via a first through-hole extending through the second planarization layer, and the first anode contact pad is connected to the first relay electrode via a second through-hole extending through the first planarization layer; In the second subpixel, the second anode is connected to a second anode contact pad via a third through-hole extending through the second planarization layer, and the second anode contact pad is connected to a second relay electrode via a fourth through-hole extending through the first planarization layer; In the third subpixel, the third anode is connected to a third anode contact pad through a fifth through hole extending through the second planarization layer, and the third anode contact pad is connected to a third relay electrode through a sixth through hole extending through the first planarization layer; and a first distance between an orthographic projection of the first through hole on the base substrate and an orthographic projection of the second through hole on the base substrate is greater than a second distance between the third through hole and the fourth through hole; and A third distance between an orthographic projection of the fifth through hole and an orthographic projection of the sixth through hole is greater than the second distance between the third through hole and the fourth through hole.

18. The array substrate according to claim 17, wherein: a first shortest distance between an orthographic projection of a first effective light-emitting area of ​​the first subpixel on the base substrate and an orthographic projection of the second through hole on the base substrate, being greater than a second shortest distance between an orthographic projection of a second effective light-emitting area of ​​the second subpixel on the base substrate and an orthographic projection of the fourth through hole on the base substrate; as well as A third shortest distance between an orthographic projection of the third effective light emitting area of ​​the third sub-pixel on the base substrate and an orthographic projection of the sixth through hole on the base substrate is greater than the second shortest distance.

19. The array substrate according to claim 17 or 18, wherein: A first length of the first anode contact pad along the second direction and a second length of the second anode contact pad along the second direction are smaller than a third length of the third anode contact pad along the second direction; a fourth shortest distance between an orthographic projection of the second through hole on the base substrate and an orthographic projection of any anode adjacent to the first anode on the base substrate is greater than a fifth shortest distance between an orthographic projection of the sixth through hole on the base substrate and an orthographic projection of any anode adjacent to the third anode on the base substrate; as well as A sixth shortest distance between an orthographic projection of the fourth through hole on the base substrate and an orthographic projection of any anode adjacent to the second anode on the base substrate is greater than the fifth shortest distance.

20. The array substrate according to claim 11, wherein: a third area covered by the orthographic projection of the first node in the first subpixel on the base substrate and the orthographic projection of the first anode of the first light-emitting element in the first subpixel on the base substrate, and a fourth area covered by the orthographic projection of the first node in the third subpixel on the base substrate and the orthographic projection of the third anode of the third light-emitting element in the third subpixel on the base substrate, being substantially the same; as well as The third area and the fourth area are smaller than a first area where an orthographic projection of a first node in the second subpixel on the base substrate is covered by an orthographic projection of a second anode of a second light-emitting element in the second subpixel on the base substrate.

21. The array substrate according to claim 11, further comprising: a semiconductor material layer located on the base substrate; as well as a gate line extending along a first direction; Each pixel driving circuit in the plurality of pixel driving circuits includes a driving transistor, a data writing transistor, and a compensation transistor, wherein the driving transistor is configured to generate a driving current for driving the light-emitting element to emit light, and the data writing transistor is configured to write a voltage into a gate of the driving transistor; The gate lines include a plurality of wide portions and a plurality of narrow portions respectively arranged along the first direction, a first dimension of the plurality of wide portions is greater than a second dimension of the plurality of narrow portions along a second direction, and the second direction forms an angle in a range of 80 degrees to 100 degrees relative to the first direction; An orthographic projection of a corresponding wide portion of the plurality of wide portions in a corresponding sub-pixel on the base substrate overlaps with an orthographic projection of a portion of the semiconductor material layer in the corresponding sub-pixel on the base substrate, thereby forming an active layer of the data writing transistor in the corresponding sub-pixel; and A ratio of a channel length to a channel width of an active layer of the data write transistor is in a range of 1.5:1 to 3:

1.

22. A display device comprising the array substrate according to any one of claims 11 to 21.

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