Semiconductor package device and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor package device and a manufacturing method thereof, by tilting a photonic chip at a certain angle to realize direct alignment coupling with a fiber array unit. The use of a simpler coupling structure is realized to reduce optical coupling loss.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor packaging technology, and more specifically to semiconductor packaging apparatus and manufacturing methods thereof. Background Technology

[0002] Currently, in silicon photonic structures, such as Figure 1 As shown, a photonic integrated circuit (PIC) 12 is disposed on the substrate 11, and the photonic integrated circuit 12 is electrically connected to an electronic integrated circuit (EIC) 15. If the fiber array unit (FAU) and the photonic integrated circuit / photonic chip 12 are to be coupled using grating coupling, a prism 14 (mirror) is usually required to guide light into the waveguide (WG) in the photonic chip 12, and the photonic chip 12 then converts the light into an electrical signal and transmits it to the electronic chip 15. However, in such a silicon photonic structure, the bevel angle of the active surface (or light-receiving surface) of the prism 14 needs to be precisely controlled to avoid optical coupling loss. For example, optical coupling loss can be caused by light refraction loss or reflection loss due to an incorrect angle of reflected light. Summary of the Invention

[0003] This disclosure presents a semiconductor packaging apparatus and a method for manufacturing the same.

[0004] In a first aspect, this disclosure provides a semiconductor packaging apparatus, comprising:

[0005] Substrate;

[0006] A support member is disposed on the substrate;

[0007] A photonic chip, with its active side facing upward and at least partially disposed on the substrate, wherein the passive side of the photonic chip contacts the support member;

[0008] A fiber optic array unit is disposed on the substrate with the active surface of the photonic chip facing the fiber optic array unit.

[0009] In some optional embodiments, the semiconductor packaging device further includes:

[0010] The first wiring layer is disposed on the active surface of the photonic chip;

[0011] A second wiring layer is disposed on the upper surface of the substrate, and the photonic chip is electrically connected to the substrate through the first wiring layer and the second wiring layer; and

[0012] The optical array unit is disposed on the second rewiring layer.

[0013] In some alternative embodiments, the angle between the passive surface of the photonic chip and the projection of the passive surface onto the upper surface of the substrate is greater than or equal to 10° and less than or equal to 80°.

[0014] In some alternative embodiments, a cavity is provided on the upper part of the substrate, and the photonic chip is at least partially disposed within the cavity.

[0015] In some alternative embodiments, the support is an electronic chip electrically connected to the substrate.

[0016] In some optional embodiments, the semiconductor packaging device further includes:

[0017] An electrical connector is disposed on the lower surface of the substrate and is electrically connected to the substrate.

[0018] In some optional embodiments, the semiconductor packaging device further includes:

[0019] A first adhesive layer is disposed within the cavity, and the first adhesive layer covers a portion of the photonic chip.

[0020] In some optional embodiments, the semiconductor packaging device further includes:

[0021] A protective layer is disposed on the second wiring layer and covers the support and the portion of the photonic chip exposed from the second wiring layer.

[0022] In some alternative implementations, the protective layer is an adhesive or molding material.

[0023] In some alternative implementations, the active surface of the electronic chip faces the substrate and is electrically connected to the substrate via solder bumps.

[0024] In some alternative implementations, the active surface of the electronic chip is located away from the substrate and is electrically connected to the substrate via wire bonding.

[0025] In some alternative embodiments, at least two cavities are disposed on the upper portion of the substrate; and

[0026] The semiconductor packaging device includes at least two of the photonic chips.

[0027] In some optional embodiments, the semiconductor packaging device further includes:

[0028] A dielectric layer is disposed within the cavity.

[0029] In some alternative implementations, the photonic chip passively contacts the intersection edge between the upper surface of the substrate and the cavity.

[0030] In some optional embodiments, the semiconductor packaging device further includes:

[0031] A third wiring layer is disposed on the active surface of the electronic chip, and the active surface of the electronic chip faces the substrate and is electrically connected to the substrate through the third wiring layer.

[0032] In some alternative implementations, the third wiring layer is disposed within the cavity.

[0033] In some alternative implementations, the thickness of the photonic chip is between 20 micrometers and 100 micrometers.

[0034] In some alternative embodiments, the thickness of the support member is between 20 micrometers and 100 micrometers.

[0035] In some optional embodiments, the semiconductor packaging device further includes:

[0036] A second adhesive layer is disposed between the fiber array unit and the second rewiring layer.

[0037] In some alternative embodiments, the thickness of the second adhesive layer is between 10 micrometers and 50 micrometers.

[0038] In some alternative implementations, the second redistribution layer includes at least one second wiring layer with a thickness between 3 micrometers and 20 micrometers.

[0039] In some alternative embodiments, the substrate includes at least one substrate circuit layer with a thickness between 10 micrometers and 30 micrometers.

[0040] In some alternative embodiments, the solder bumps on the active surface of the electronic chip have a diameter between 10 micrometers and 30 micrometers and a spacing between 15 micrometers and 60 micrometers.

[0041] In some optional embodiments, the electrical connectors disposed on the lower surface of the substrate are solder balls, and the diameter of the solder balls disposed on the lower surface of the substrate is between 30 micrometers and 200 micrometers, and the spacing is between 50 micrometers and 400 micrometers.

[0042] In some alternative implementations, the linewidth of the first and second rewiring layers is between 1 micrometer and 10 micrometers, the line spacing is between 1 micrometer and 10 micrometers, and the pitch is between 2 micrometers and 20 micrometers.

[0043] In some alternative implementations, the maximum horizontal distance of the cavity is between 30 micrometers and 200 micrometers.

[0044] Secondly, this disclosure provides a method for manufacturing a semiconductor packaging device, comprising:

[0045] Provide substrates and supports;

[0046] The support member is disposed on the substrate;

[0047] A photonic chip is provided, wherein a first wiring layer is disposed on the active surface of the photonic chip;

[0048] The photonic chip is disposed on the substrate with its active surface facing upwards;

[0049] A second wiring layer is formed on the upper surface of the substrate so that the photonic chip is electrically connected to the substrate through the first wiring layer and the second wiring layer;

[0050] A fiber optic array unit is provided, and the fiber optic array unit is disposed on a second redistribution layer with the active surface of the photonic chip facing the fiber optic array unit.

[0051] In some alternative embodiments, a cavity is provided on the upper part of the substrate; and

[0052] The step of placing the photonic chip with its active surface facing upwards and partially disposed on the substrate includes:

[0053] The photonic chip is positioned with its active surface facing upwards and partially disposed within the cavity.

[0054] In some alternative embodiments, before the photonic chip is partially disposed within the cavity with its active surface facing upwards, the method further includes:

[0055] An adhesive is injected into the cavity to form a first adhesive layer; and

[0056] The step of placing the photonic chip with its active surface facing upwards and partially disposed within the cavity includes:

[0057] The first adhesive layer is partially disposed within the cavity with the active surface of the photonic chip facing upwards.

[0058] Heating is used to fix the photonic chip to the first adhesive layer.

[0059] In some alternative embodiments, after forming a second redistribution layer on the upper surface of the substrate, the method further includes:

[0060] The substrate is flipped over, and an electrical connection is formed on the surface of the substrate away from the support, so that the electrical connection is electrically connected to the substrate.

[0061] In some optional implementations, the method further includes:

[0062] A protective layer is provided on the second redistribution layer such that the protective layer covers the portion of the support and the photonic chip exposed from the second redistribution layer.

[0063] To address the stringent requirement for precise control of the prism's bevel angle in existing silicon photonic structures to reduce optical coupling losses, the semiconductor packaging device and method disclosed herein achieve direct alignment and optical coupling with the fiber optic array unit by tilting the photonic chip at a certain angle. This realizes a reduction in optical coupling losses using a simpler coupling structure. Attached Figure Description

[0064] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0065] Figure 1 This is a longitudinal cross-sectional structural schematic diagram of an embodiment of a semiconductor packaging device including a photonic chip in the prior art;

[0066] Figure 2A A longitudinal cross-sectional structural schematic diagram of an embodiment of the semiconductor packaging device 2a according to the present disclosure;

[0067] Figure 2B Based on this disclosure Figure 2A A magnified schematic diagram of the local longitudinal cross-sectional structure corresponding to the rectangular frame in the semiconductor packaging device shown.

[0068] Figure 2C Based on this disclosure Figure 2B A magnified schematic diagram of the local longitudinal cross-sectional structure corresponding to the larger rectangular frame in the semiconductor packaging device shown.

[0069] Figure 2D Based on this disclosure Figure 2A Dimensional diagram of semiconductor packaging device 2a shown;

[0070] Figure 2E , 2F 2e, 2f, 2g, 2h, 2i and 2j are schematic diagrams of longitudinal cross-sectional structures of one embodiment of the semiconductor packaging apparatus 2e, 2f, 2g, 2h, 2i and 2j according to the present disclosure;

[0071] Figure 3A , 3B3C, 3D, 3E, 3F, 3G, 3H and 3I are schematic diagrams of longitudinal cross-sectional structures of semiconductor packaging devices 3a, 3b, 3c, 3d, 3e, 3f, 3g, 3h and 3i manufactured at different stages according to the present disclosure;

[0072] Figure 3J This is a light path diagram of the operating state of the semiconductor packaging device 3a according to the present disclosure.

[0073] Symbol explanation:

[0074] 11-Substrate; 12-Photonic chip; 13-Fiber optic array unit; 14-Prism; 15-Electronic integrated circuit; 101-Substrate; 1011-Cavity; 1012-Substrate circuit layer; 102-Support component; 103-Photonic chip; 104-First redistribution layer; 105-Second redistribution layer; 1051-Second circuit layer; 106-Fiber optic array unit; 107-Electrical connector; 108-First adhesive layer; 109-Protective layer; 110-Solder bump; 111-Bump Line; 112 - Third wiring layer; 113 - Second adhesive layer; 115 - Metal pillar; θ - Angle between the passive surface of the photonic chip and the projection of the passive surface onto the upper surface of the substrate 11; TCT - Thickness of the photonic chip; PCT - Thickness of the support; FAT - Thickness of the second adhesive layer; FDT - Thickness of the second wiring layer; SDT - Thickness of the substrate wiring layer; DB - Diameter of the solder bumps; PB - Spacing of the solder bumps; DSB - Diameter of the solder balls; CS - Horizontal distance of the cavity. Detailed Implementation

[0075] The specific embodiments of the present invention will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by the present invention and the resulting technical effects from the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0076] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and to facilitate understanding and reading of the invention. They are not intended to limit the scope of the invention and therefore have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and objectives of the invention, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity and not intended to limit the scope of the invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the invention's implementation.

[0077] It should also be noted that the longitudinal section corresponding to the embodiments of this disclosure can be the section corresponding to the front view direction, the transverse section can be the section corresponding to the right view direction, and the horizontal section can be the section corresponding to the top view direction.

[0078] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0079] refer to Figure 2A , Figure 2B , Figure 2C and Figure 2D ,in, Figure 2A A longitudinal cross-sectional structural schematic diagram of an embodiment 2a of a semiconductor packaging device according to the present disclosure is shown. Figure 2B Based on this disclosure Figure 2A An enlarged schematic diagram of the local longitudinal cross-sectional structure corresponding to the middle rectangular frame of the semiconductor packaging device 2a shown. Figure 2C Based on this disclosure Figure 2B This is an enlarged schematic diagram of the local longitudinal cross-sectional structure corresponding to the larger rectangular frame in the semiconductor packaging device shown. Figure 2D Based on this disclosure Figure 2A The dimensions of the semiconductor packaging device 2a shown are marked.

[0080] like Figure 2A , Figure 2B , Figure 2C and Figure 2D As shown, the semiconductor packaging device 2a includes: a substrate 101, a support 102, a photonic chip 103, a first redistribution layer 104, a second redistribution layer 105, and a fiber optic array unit 106. Wherein:

[0081] Here, substrate 101 can be any type of substrate, and this disclosure does not specifically limit it.

[0082] The substrate 101 may include organic and / or inorganic materials, wherein the organic materials may be, for example, polyamide (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, also known as prepreg or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), etc., while the inorganic materials may be, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc.

[0083] The substrate 101 may also be, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate.

[0084] The substrate 101 may also include interconnect structures, such as conductive traces, conductive vias, etc. Here, the conductive vias can be through-holes, buried vias, or blind vias, and the through-holes, buried vias, or blind vias can be filled with conductive materials such as metals or metal alloys. Here, the metal can be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof.

[0085] A support member 102 is disposed on a substrate 101. Here, the support member 102 can be various supporting components. The support member 102 may simply serve a supporting function, such as a substrate. The support member 102 may also have a specific function. For example, the support member 102 may be a passive component or an electronic chip (also called an electronic integrated circuit, EIC).

[0086] The active surface of the photonic chip 103 faces upward and is at least partially disposed on the substrate 101. The angle θ between the passive surface of the photonic chip 103 (i.e., the back surface opposite to the active surface) and the projection of the passive surface of the photonic chip 103 onto the upper surface of the substrate 101 is greater than or equal to 10° and less than or equal to 80°. That is, the photonic chip 103 is disposed at an angle on the substrate 101.

[0087] The passive surface contact support 102 of the photonic chip 103, such as Figure 2B As shown in the dashed elliptical box.

[0088] The first wiring layer 104 is disposed on the active surface of the photonic chip 103 to realize the electrical connection between the photonic chip 103 and the outside.

[0089] The second wiring layer 105 is disposed on the upper surface of the substrate 101. The photonic chip 103 is electrically connected to the substrate 101 through the first wiring layer 104 and the second wiring layer 105.

[0090] The first redistribution layer 104 and the second redistribution layer 105 can be redistribution layers composed of conductive and dielectric materials. It should be noted that the fabrication process can employ currently known or future-developed redistribution layer formation technologies, and this disclosure does not specifically limit this. For example, redistribution layers can be formed using methods including, but not limited to, photolithography, electroplating, and electroless plating. Here, the dielectric material can include organic and / or inorganic materials. Organic materials can be, for example, polyamide (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, also known as prepreg or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), etc., while inorganic materials can be, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material may include a seed layer and a metal layer. Here, the seed layer may be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., while the metal layer may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof.

[0091] The fiber optic array unit 106 is disposed on the second wiring layer 105 and the active surface of the photonic chip 103 faces the fiber optic array unit 106.

[0092] When the aforementioned semiconductor packaging device 2a is in operation, the light emitted by the light array unit 106 can be as follows: Figure 2B As shown by the bold black dashed line, the light reaches the active surface of the photonic chip 103 and is converted into an electrical signal by the photonic chip 103. The prism is no longer needed, and there is no need to precisely control the angle of the prism's bevel. Compared with the existing silicon photonic structure, the structure is simple and can reduce optical coupling loss.

[0093] In some alternative implementations, such as Figure 2A As shown, a cavity 1011 may be disposed on the upper part of the substrate 101, and the photonic chip 103 may be disposed at least partially in the cavity 1011.

[0094] In some alternative implementations, such as Figure 2AAs shown, a dielectric layer may be disposed within the cavity 1011 of the semiconductor packaging device 2a. Here, the dielectric layer disposed within the cavity 1011 can be used to achieve the effect of isolating and insulating the back side of the photonic chip 103.

[0095] In some alternative implementations, such as Figure 2B As shown in the small rectangular dashed box, the passive surface of the photonic chip 103 can contact the intersection edge between the upper surface of the substrate 101 and the cavity 1011.

[0096] In some alternative implementations, the maximum horizontal distance CS of the cavity 1011 is between 30 micrometers and 200 micrometers.

[0097] In some alternative embodiments, the support 102 may be an electronic chip (or electronic integrated circuit), and the electronic chip 102 may be electrically connected to the substrate 101 in various ways.

[0098] In some alternative implementations, such as Figure 2A and 2D As shown, the semiconductor packaging device 2a may further include an electrical connector 107. The electrical connector 107 is disposed on the lower surface of the substrate 101 and is electrically connected to the substrate 101. The electrical connector 107 may be a solder pad or a solder bump. The electrical connector 107 is used to achieve electrical connection between the substrate 101 and the outside world, thereby achieving electrical connection between the semiconductor packaging device 2a and the outside world.

[0099] In some alternative implementations, such as Figure 2A and 2D As shown, the electrical connector 107 disposed on the lower surface of the substrate 101 can be a solder ball, and the diameter DSB (Diameter of Solder Ball) of the solder ball 107 disposed on the lower surface of the substrate 101 can be between 30 micrometers and 200 micrometers, and the spacing is between 50 micrometers and 400 micrometers.

[0100] In some alternative implementations, such as Figure 2A As shown, the semiconductor packaging device 2a may further include a first adhesive layer 108. The first adhesive layer 108 may be disposed within the cavity 1011, and the first adhesive layer 108 covers a portion of the photonic chip 103. Here, the first adhesive layer 108 is used to fix the photonic chip 103.

[0101] In some alternative implementations, such as Figure 2AAs shown, the semiconductor packaging device 2a may further include a protective layer 109. The protective layer 109 is disposed on the second wiring layer 105 and covers the portions of the support member 102 and the photonic chip 103 exposed from the second wiring layer 105. Here, the protective layer 109 is used to protect the support member 102 and the photonic chip 103. The protective layer 109 can be made of various materials that provide protection.

[0102] In some alternative embodiments, the protective layer 109 can be an adhesive (e.g., optical adhesive) or a molding compound with light-transmitting properties. For example, methylphenyl dichlorosilane (MePhSiCl2) is co-hydrolyzed with dimethyl dichlorosilane (Me2SiCl2), methyl vinyl dichlorosilane (MeViSiCl2), and phenyl trichlorosilane (PhSiCl3), and then co-condensed under potassium hydroxide (KOH) catalysis to prepare a methylphenyl vinyl silicone resin containing methylphenyl siloxane linkages using trimethylchlorosilane (Me3SiCl) as the end-capping agent. The product was characterized by FTIR, 1H NMR, and thermogravimetric analysis (TGA). The obtained methylphenyl vinyl silicone resin was mixed with methylphenyl hydrogen silicone oil in a certain ratio and vulcanized under platinum complex catalysis to prepare a molding compound with light-transmitting properties. The resulting molding compound with light-transmitting properties exhibits high light transmittance in the visible light range after curing. Figure 2A In the semiconductor packaging device 2a shown, the protective layer 109 is an adhesive.

[0103] In some alternative implementations, such as Figure 2A As shown, when the support 102 is an electronic chip, the active surface of the electronic chip 102 can face the substrate 101 and be electrically connected to the substrate 101 through the solder bump 110.

[0104] In some alternative implementations, such as Figure 2A and 2D As shown, the diameter DB of the solder bumps on the active surface of the electronic chip 102 is between 10 micrometers and 30 micrometers, and the spacing PB is between 15 micrometers and 60 micrometers.

[0105] In some alternative implementations, such as Figure 2D As shown, the thickness TCT of the photonic chip 103 can be between 20 micrometers and 100 micrometers.

[0106] In some alternative implementations, such as Figure 2D As shown, the thickness PCT of the support member 102 can be between 20 micrometers and 100 micrometers.

[0107] In some alternative implementations, such as Figure 2A and 2DAs shown, the semiconductor packaging device 2a may further include a second adhesive layer 113. The second adhesive layer 113 is disposed between the fiber array unit 106 and the second redistribution layer 105. The second adhesive layer 113 is used to bond the fiber array unit 106 to the second redistribution layer 105. The second adhesive layer can be various adhesives, such as die attach film.

[0108] In some alternative implementations, such as 2A and Figure 2D As shown, the thickness FAT of the second adhesive layer 113 can be between 10 micrometers and 50 micrometers.

[0109] In some alternative implementations, such as Figure 2A and Figure 2D As shown, the second redistribution layer 105 may include at least one second wiring layer 1051. The thickness FDT of the second wiring layer 1051 may be between 3 micrometers and 20 micrometers.

[0110] In some alternative implementations, such as Figure 2A and Figure 2D As shown, substrate 101 may include at least one substrate circuit layer 1012, and the thickness SDT of substrate circuit layer 1012 may be between 10 micrometers and 30 micrometers.

[0111] In some alternative implementations, the line width of the first wiring layer 104 and the second wiring layer 105 is between 1 micrometer and 10 micrometers, the line spacing is between 1 micrometer and 10 micrometers, and the pitch is between 2 micrometers and 20 micrometers.

[0112] The following is for reference. Figure 2E , Figure 2E This is a longitudinal cross-sectional structural schematic diagram of an embodiment 2e of the semiconductor packaging apparatus according to the present disclosure. Figure 2E The semiconductor packaging device 2e shown is similar to Figure 2A The semiconductor packaging device 2a shown is different in that the protective layer 109 is a molding material with light-transmitting properties.

[0113] The following is for reference. Figure 2F , Figure 2F This is a longitudinal cross-sectional structural schematic diagram of an embodiment 2f of the semiconductor packaging apparatus according to the present disclosure. Figure 2F The semiconductor packaging device 2f shown is similar to Figure 2A The semiconductor packaging device 2a shown is different in that the semiconductor packaging device 2f does not include the protective layer 109.

[0114] The following is for reference. Figure 2G , Figure 2G This is a longitudinal cross-sectional structural schematic diagram of an embodiment 2g of the semiconductor packaging device according to the present disclosure. Figure 2G The semiconductor packaging device 2g shown is similar to Figure 2A The semiconductor packaging device 2a shown is different in that when the support 102 is an electronic chip, the active surface of the electronic chip 102 is away from the substrate 101 and is electrically connected to the substrate 101 through wire bonding 111.

[0115] The following is for reference. Figure 2H , Figure 2H This is a longitudinal cross-sectional structural schematic diagram of an embodiment 2h of the semiconductor packaging apparatus according to the present disclosure. Figure 2H The semiconductor packaging device 2h shown is similar to Figure 2A The semiconductor packaging device 2a shown is different in that: at least two cavities 1011 are provided on the upper part of the substrate 101, and the semiconductor packaging device 2h includes at least two photonic chips 103.

[0116] The following is for reference. Figure 2I , Figure 2I This is a longitudinal cross-sectional structural schematic diagram of an embodiment 2i of the semiconductor packaging device according to the present disclosure. Figure 2I The semiconductor packaging device 2i shown is similar to Figure 2A The semiconductor packaging device 2a shown differs in that, when the support 102 is an electronic chip, the semiconductor packaging device 2i further includes a third wiring layer 112. The third wiring layer 112 is disposed on the active surface of the electronic chip 102, and the active surface of the electronic chip 102 faces the substrate 101 and is electrically connected to the substrate 101 through the third wiring layer 112.

[0117] In some alternative implementations, such as Figure 2I As shown, the third wiring layer 112 can be disposed inside the cavity 1011. That is, the back side of the photonic chip 103 contacts the support, but does not contact the intersection edge between the upper surface of the substrate 101 and the cavity 1011.

[0118] The following is for reference. Figure 2J , Figure 2J This is a longitudinal cross-sectional structural schematic diagram of an embodiment 2j of the semiconductor packaging apparatus according to the present disclosure. Figure 2J The semiconductor packaging device 2j shown is similar to Figure 2A The semiconductor packaging device 2a shown differs in that, when the support 102 is an electronic chip, the semiconductor packaging device 2j further includes a metal pillar 115. Solder bumps 110 and metal pillars 115 are sequentially disposed on the active surface of the electronic chip 102, and the active surface of the electronic chip 102 faces the substrate 101 and is electrically connected to the substrate 101 through the solder bumps 110 and metal pillars 115.

[0119] The following is for reference. Figures 3A-3I , Figure 3A ,3B Figures 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, and 3I are schematic longitudinal cross-sectional views of semiconductor packaging devices 3a, 3B, 3C, 3D, 3E, 3F, 3G, 3H, and 3I manufactured at different stages according to the present disclosure. The figures have been simplified for better understanding of various aspects of the present disclosure.

[0120] refer to Figure 3A A substrate 101 and a support 102 are provided.

[0121] refer to Figure 3B The support member 102 is placed on the substrate 101.

[0122] For example, when the support 102 is an electronic chip, techniques such as flip-chip bonding (FCB) or thermal compression bonding (TCB) can be used to place the support 102 on the substrate 101.

[0123] refer to Figure 3D Provides a photonic chip 103, and the active surface of the photonic chip 103 is facing upward and partially disposed on a substrate 101.

[0124] Here, the active surface of the photonic chip 103 is provided with a first wiring layer 104.

[0125] refer to Figure 3F A second redistribution layer 105 is formed on the upper surface of the substrate 101 so that the photonic chip 103 is electrically connected to the substrate 101 through the first redistribution layer 104 and the second redistribution layer 105.

[0126] The redistribution layer formation technology currently known or developed in the future can be used in the manufacturing process. This disclosure does not make specific limitations on this. For example, the second redistribution layer 105 can be formed by methods including but not limited to photolithography, electroplating, and electroless plating.

[0127] refer to Figure 3H The optical fiber array unit 106 is provided, and the optical fiber array unit 106 is disposed on the second wiring layer 105, with the active surface of the photonic chip 103 facing the optical fiber array unit 106.

[0128] In some alternative embodiments, a cavity 1011 may be provided on the upper part of the substrate 101. Based on this, Figure 3D The active surface of the photonic chip is facing upward and partially disposed on the substrate 101, which can be: the active surface of the photonic chip 103 is facing upward and partially disposed inside the cavity 1011.

[0129] In some alternative implementations, based on the above alternative implementations, in Figure 3D Before placing the photonic chip 103 with its active surface facing upwards and partially within the cavity 1011, one can also refer to... Figure 3C Adhesive is injected into the cavity 1011 to form a first adhesive layer 108. Furthermore, Figure 3D The photonic chip 103 is partially disposed within the cavity 1011 with its active surface facing upwards. This can be achieved by placing a first adhesive layer 108 within the cavity 1011 with the active surface of the photonic chip 103 facing upwards and partially disposed within the cavity 1011. And in... Figure 3D Afterwards, you can also refer to Figure 3E Heating is performed to fix the photonic chip 103 to the first adhesive layer 108. At the same time, when the support 102 is an electronic chip and the active surface of the electronic chip 102 is provided with solder bumps 110, this heating process can also allow the electronic chip 102 to be bonded to the substrate 101 through the solder bumps 110.

[0130] In some alternative implementations, in Figure 3F After the second redistribution layer 105 is formed on the upper surface of the substrate 101, reference can also be made to Figure 3G The substrate is flipped over, and an electrical connector 107 is formed on the surface of the substrate 101 away from the support 102, so that the electrical connector 107 is electrically connected to the substrate 101.

[0131] In some alternative implementations, it is also possible to... Figure 3H Afterwards, refer to Figure 3I A protective layer 109 is provided on the second wiring layer 105 so that the protective layer 109 covers the portion of the support member 102 and the photonic chip 103 exposed from the second wiring layer 105.

[0132] The following is for reference. Figure 3J , Figure 3J This is a light path diagram of the operating state of the semiconductor packaging device 2a according to this disclosure. For example... Figure 3J As shown, when the semiconductor packaging device 2a is working, the light emitted by the fiber array unit 106 directly illuminates the active surface of the photonic chip 103, and can then be directly converted into an electrical signal and transmitted to the electronic chip 102 through the first wiring layer 104, the second wiring layer 104, and the substrate 101.

[0133] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual implementation due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and illustrations should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit this disclosure.

Claims

1. A semiconductor packaging device, comprising: Substrate; A support member is disposed on the substrate; A photonic chip, with its active surface facing upward and at least partially disposed on the substrate, and its passive surface in contact with the support member, wherein the photonic chip is tilted on the substrate, and a cavity is provided on the upper part of the substrate, and the photonic chip is at least partially disposed in the cavity; An optical fiber array unit is disposed on the substrate, with the active surface of the photonic chip facing the optical fiber array unit.

2. The semiconductor packaging apparatus according to claim 1, wherein, The semiconductor packaging apparatus further includes: The first wiring layer is disposed on the active surface of the photonic chip; A second wiring layer is disposed on the upper surface of the substrate, and the photonic chip is electrically connected to the substrate through the first wiring layer and the second wiring layer; and The fiber optic array unit is disposed on the second rewiring layer.

3. The semiconductor packaging apparatus according to claim 1, wherein, The support is an electronic chip, which is electrically connected to the substrate.

4. The semiconductor packaging apparatus according to claim 1, wherein, The semiconductor packaging apparatus further includes: A first adhesive layer is disposed within the cavity, and the first adhesive layer covers a portion of the photonic chip.

5. The semiconductor packaging apparatus according to claim 2, wherein, The semiconductor packaging apparatus further includes: A protective layer is disposed on the second wiring layer and covers the support and the portion of the photonic chip exposed from the second wiring layer.

6. The semiconductor packaging apparatus according to claim 3, wherein, The active surface of the electronic chip is away from the substrate and is electrically connected to the substrate via wire bonding.

7. The semiconductor packaging apparatus according to claim 1, wherein, At least two cavities are provided on the upper part of the substrate; and The semiconductor packaging device includes at least two of the photonic chips.

8. The semiconductor packaging apparatus according to claim 3, wherein, The semiconductor packaging apparatus further includes: A third wiring layer is disposed on the active surface of the electronic chip, and the active surface of the electronic chip faces the substrate and is electrically connected to the substrate through the third wiring layer.

9. The semiconductor packaging apparatus according to claim 8, wherein, The third wiring layer is disposed within the cavity.

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