Photonic chip including electrical interconnects with bipolar ports

Abstract

The invention relates to photonic chips including electrical interconnects with bilobed pillars. Structures for photonic chips and related methods are provided. The structure includes a photonic chip including a bond pad, and an electrical interconnect including a pillar disposed on the bond pad. The post includes a first valvular section, a second valvular section spaced from the first valvular section by a gap, and a connection section extending across a portion of the gap to connect the first valvular section with the second valvular section.

Description

Technical Field

[0001] This invention generally relates to the manufacture of semiconductor devices and integrated circuits, and more particularly to structures and methods for use in photonic chips. Background Technology

[0002] Photonic chips are used in many applications and systems, including but not limited to data communication systems and data computing systems. Photonic chips include photonic integrated circuits, which consist of photonic elements (such as modulators, polarizers, and optical couplers) used to manipulate light received from a light source (such as an optical fiber or laser).

[0003] Photonic chips can be mounted on a laminated substrate to form a packaged assembly. Copper pillars or bumps can provide electrical interconnection between the laminated substrate and the photonic chip. However, due to strain transmitted from the stressed copper bumps to the interlayer dielectric layer of the back-end-of-line stack, the copper bumps may cause failures in the lower portion of the back-end-of-line stack of the photonic chip.

[0004] The need for improvements in the structure and related methods for photonic chips. Summary of the Invention

[0005] In one embodiment, a structure includes a photonic chip and an electrical interconnect. The photonic chip includes a bonding pad, and the electrical interconnect includes a pillar disposed on the bonding pad. The pillar includes a first lobe-shaped segment, a second lobe-shaped segment spaced apart from the first lobe-shaped segment by a gap, and a connection segment extending across the gap to connect the first lobe-shaped segment and the second lobe-shaped segment.

[0006] In one embodiment, a method includes forming a photonic chip including a bonding pad and forming an electrical interconnect including a pillar disposed on the bonding pad. The pillar includes a first lobe-shaped segment, a second lobe-shaped segment spaced apart from the first lobe-shaped segment by a gap, and a connection segment extending across the gap to connect the first lobe-shaped segment and the second lobe-shaped segment. Attached Figure Description

[0007] The accompanying drawings, which are included and constitute a part of this specification, illustrate various embodiments of the invention and, together with the foregoing general description of the invention and the following detailed description of these embodiments, serve to explain these embodiments of the invention. In these drawings, similar reference numerals are used to indicate similar features in different views.

[0008] Figure 1 A cross-sectional view of a packaging component according to an embodiment of the present invention is shown.

[0009] Figure 2 show Figure 1 A magnified view of the portion.

[0010] Figure 3 This shows that before attaching the laminated substrate to the photonic chip, Figure 1 A top view of the portion of the packaged component where the photonic chip and the laminated substrate are electrically interconnected.

[0011] Figure 4 Showing the general outline Figure 3 The sectional view made along line 4-4 in the diagram.

[0012] Figure 5 This shows a top view of the electrical interconnection between the photonic chip and the laminated substrate of the package assembly according to an alternative embodiment of the present invention.

[0013] Figure 5A Showing the general outline Figure 5 The sectional view is drawn along line 5A-5A.

[0014] Figure 6 This shows a top view of the electrical interconnection between the photonic chip and the laminated substrate of the package assembly according to an alternative embodiment of the present invention.

[0015] Figure 7 This shows a cross-sectional view of the electrical interconnection between the photonic chip and the laminated substrate of the package assembly according to an alternative embodiment of the present invention.

[0016] Figure 8 This shows a cross-sectional view of the electrical interconnection between the photonic chip and the laminated substrate of the package assembly according to an alternative embodiment of the present invention. Detailed Implementation

[0017] Please refer to Figure 1 , Figure 2 , Figure 3 , Figure 4 According to an embodiment of the present invention, the structure 10 for a capped packaging assembly includes a photonic chip 12, a laminated substrate 14 (providing a representative packaging substrate), and a cap 16. The photonic chip 12 is disposed between the laminated substrate 14 and the cap 16. The laminated substrate 14 may include an epoxy-glass cloth core and alternating layers of metal and electrical insulators laminated thereon. In one embodiment, the laminated substrate 14 may include copper film layers alternating with insulating resin layers (e.g., Ajinomoto Build-up Film (ABF)). The cumulative alternating layers of the laminated substrate 14 may be disposed adjacent to the photonic chip 12.

[0018] The photonic chip 12 includes photonic elements (e.g., modulators, polarizers, and optical couplers) disposed within a functional photonic integrated circuit configured to manipulate light received from a light source (e.g., an optical fiber or laser). The photonic chip 12 includes a substrate 31 on which the photonic integrated circuit is disposed and a back-end process stack 25 disposed on the substrate 31. The substrate 31 may be made of, for example, silicon. The back-end process stack 25 may be disposed adjacent to a laminated substrate 14 and may include bonding pads 34, a set of interlayer dielectric layers, and interconnects located within the interlayer dielectric layers. Each interlayer dielectric layer may be made of a dielectric material (e.g., a low-k dielectric, silicon nitride, or silicon dioxide), and the interconnects may be made of a metal (e.g., aluminum or copper).

[0019] A dielectric layer 36 composed of an inorganic dielectric material (e.g., silicon dioxide formed from tetraethyl orthosilicate) may be formed as a passivation layer on the surface of the back-end process stack 25 of the exposed bonding pad 34. In one embodiment, the dielectric layer 36 may have a thickness on the order of six (6) micrometers. The inorganic dielectric material constituting the dielectric layer 36 may be characterized by high stiffness and low coefficient of thermal expansion, especially compared to organic materials (e.g., polyimide).

[0020] The laminate substrate 14 includes bonding pads 27 coupled to the metal layers in the uplayer via vias. The surface 32 of the laminate substrate 14 (adjacent to the top surface 28 of the back-end process stack 25 of the photonic chip 12) may be coated with a solder mask layer 30, which is adjacent to the edge 15 of the laminate substrate 14. Electrical interconnects 17 and 18 couple the bonding pads 34 of the photonic chip 12 to the bonding pads 27 of the laminate substrate 14. Electrical interconnects 17 and 18 are disposed in a gap G1 between the top surface 28 of the back-end process stack 25 and the surface 32 of the laminate substrate 14. One of the electrical interconnects 18 may be adjacent to the entrance of the gap G1 closest to the side surface 13 of the photonic chip 12. The other electrical interconnect 18 may be adjacent to the entrance of the gap G1 closest to the side surface 11 of the photonic chip 12. All electrical interconnects 17 may be disposed between the electrical interconnects 18 located at the entrances on opposite sides of the gap G1.

[0021] The photonic chip 12 also includes a bottom surface 20 opposite to the top surface 28, a side surface 11, and a side surface 13 opposite to the side surface 11. The side surfaces 11 and 13 are connected via the bottom surface 20 and the top surface 28. Due to lateral offset in the attachment of the photonic chip 12 to the laminated substrate 14, the photonic chip 12 includes a portion disposed between the side surface 13 and the edge 15 of the laminated substrate 14. The side surface 11 overlaps with the laminated substrate 14, while the side surface 13 does not overlap with the laminated substrate 14.

[0022] The cover 16 (which may be composed of a conductive and thermally conductive material (e.g., nickel-plated copper)) is attached to the same side of the laminated substrate 14 as the photonic chip 12. The photonic chip 12 partially overlaps with the cover 16. A thermal interface material layer 19 may be provided between the overlapping portion of the photonic chip 12 and the cover 16. The thermal interface material in layer 19 may be composed of, for example, thermally conductive adhesive or thermally conductive paste, to improve heat flow between the overlapping portion of the photonic chip 12 and the cover 16.

[0023] Another portion of the cover 16 can be attached to a portion of the surface 32 of the laminated substrate 14 via the adhesive layer 23. An open space 21 is provided between the side 11 of the photonic chip 12, the cover 16, and a portion of the surface 32 of the laminated substrate 14. The different portions of the cover 16 are characterized by vertical offset to accommodate the placement of the photonic chip 12 between the laminated substrate 14 and the cover 16. The attachment of a portion of the cover 16 to the laminated substrate 14 increases the mechanical strength of the structure 10, and if the adhesive constituting the adhesive layer 23 is conductive, it can provide a conductive path from the cover 16 to the laminated substrate 14.

[0024] A layer 22 composed of an underfill material may be disposed in the gap G1 between the photonic chip 12, which includes electrical interconnects 17 and 18, and the laminated substrate 14. The layer 22 may have a thickness substantially equal to the height dimension of the gap G1. The layer 22 protects the electrical interconnects 17 and 18 from various adverse environmental factors, redistributes mechanical stress caused by impact, and prevents the electrical interconnects 17 and 18 from moving under strain during thermal cycling when the photonic chip 12 is in operation.

[0025] A fillet 24, consisting of an underfill material, is provided on a portion of the top surface 28 of the photonic chip 12 adjacent to the edge 15 of the laminated substrate 14 and the gap G1. A fillet 26, consisting of an underfill material, is provided on a portion of the side surface 11 of the photonic chip 12 adjacent to the surface 32 of the laminated substrate 14 and the gap G1.

[0026] Each electrical interconnect 18 may include a pillar 38 disposed on one of the bonding pads 34 of the photonic chip 12. In one embodiment, the pillar 38 may be disposed directly on the central portion of the top surface 35 of the bonding pad 34. In one embodiment, the top surface 35 of the bonding pad 34 may be flat. The pillar 38 may be made of metal (e.g., copper) and may be covered by one or more capping layers made of solder or a barrier layer made of nickel or another metal. The pillar 38 may be formed by a plating process.

[0027] Viewed from a vertical angle, the column 38 may have a bilobed shape, comprising a petal segment 40, a petal segment 42 separated from the petal segment 40 by a gap G2, a connecting segment 44 connecting portions of the petal segment 40 and the petal segment 42, and an outer wall 46 extending along the outer boundary contours of the petal segments 40, 42 and the connecting segment 44. In one embodiment, the petal segment 40 includes a curved edge that is part of the outer wall 46, the petal segment 42 includes a curved edge that is part of the outer wall 46, and the connecting segment 44 connects to portions of the petal segment 42 and the petal segment 40 that are opposite each other across a gap G2.

[0028] Connecting section 44 provides a bridge extending across the gap G2 between petal sections 40 and 42. Column 38 includes a recess 48 in its outer side wall 46 that extends along the entire height of column 38 to the underlying mating pad 34. The recess 48 (located between petal sections 40 and 42) represents portions of the gap G2 separated from each other by connecting section 44. Connecting section 44 is laterally disposed between the recesses 48.

[0029] The petal segments 40 and 42 may have different sizes to make the pillar 38 asymmetrical. In one embodiment, the petal segment 40 may be smaller than the petal segment 42. In one embodiment, the pillar 38 may be rotated so that the petal segment 40 is closer to the side surface 13 of the photonic chip 12 than the petal segment 42, or closer to the side surface 11 of the photonic chip 12 than the petal segment 42.

[0030] The dielectric layer 36 includes an opening 50 having a sidewall 51 surrounding the pillar 38. A portion 33 of the dielectric layer 36 overlaps with a portion 33 of a bonding pad 34 adjacent to the sidewall 51 of the opening 50. The opening 50 may have a bilobed shape that matches and is slightly larger than the bilobed shape of the bilobed pillar 38, thereby creating a gap G3 between the outer sidewall 46 of the pillar 38 and the sidewall 51 of the opening 50 located in the dielectric layer 36. More specifically, the inner periphery of the outer sidewall 46 may extend along the contour of the outer sidewall 46 of the bilobed pillar 38, defining the gap G3 in the open space therebetween. The opening 50 may have a petal-shaped segment along its inner periphery that coincides in position with the petal-shaped segment 40, and the opening 50 may have a petal-shaped segment along its inner periphery that coincides in position with the petal-shaped segment 42. The gap G3 extends downward along the height H of the opening 50 between the sidewall 51 of the opening 50 and the outer sidewall 46 of the pillar 38 to the top surface 35 of the bonding pad 34, so that the dielectric layer 36 and the pillar 38 have a non-contact and spaced relationship. In one embodiment, the opening 50 may have a section along its sidewall 51 that coincides in position with the connection section 44 along the outer sidewall 46 of the pillar 38. In one embodiment, the sidewall 51 of the opening 50 may be oriented perpendicular to the horizontal plane established by the top surface 35 of the bonding pad 34, so that the opening 50 is a straight cylinder. In one embodiment, the gap G3 may have a constant average width dimension along the height H of the pillar 38. In one embodiment, the average width dimension of the gap G3 may be selected to optimize the relevant benefits by reducing the strain transmitted from the pillar 38 to the interlayer dielectric layer of the back-end process stack 25. In one embodiment, the average width dimension of the gap G3 may be less than about 1 micrometer.

[0031] The bilobed shape of pillar 38, combined with the shape of the opening 50 in dielectric layer 36 (which may also be bilobed), can significantly reduce strain transmitted from pillar 38 to the back-end process stack 25 of photonic chip 12, thereby reducing or eliminating the incidence of chip-package interaction failures in adjacent portions of the back-end process stack 25. The shape of pillar 38 (which may also be bilobed) reduces tensile stress without increasing the area of ​​pillar 38 in contact with bonding pad 34. In particular, it reduces tensile stress on the contact area between the petal segment 40 of pillar 38 and bonding pad 34. Rotational orientation of pillar 38 (positioning the smaller petal segment 40 closer to the adjacent side surface 11 of photonic chip 12 compared to the larger petal segment 42, or closer to the adjacent side surface 13 of photonic chip 12 compared to the larger petal segment 42) can further reduce tensile stress.

[0032] Please refer to Figure 5 , Figure 5A According to an alternative embodiment, each electrical interconnect 18 may include a base or pedestal 52 disposed between the mating pad 34 and the pillar 38. Figure 5In one embodiment shown, the base 52 may be a cylinder with a circular cross-sectional profile, different from the bilobed shape of the column 38. A notch 48 located in the sidewall of the column 38 may extend along the entire height of the column 38 to the base 52. The opening 50 may be modified to be a cylinder with a circular cross-sectional profile, rather than bilobed, so that the opening 50 has the same diameter D as the base 52. A gap G3 between the outer wall 46 of the column 38 and the sidewall 51 of the opening 50 may be maintained at least on those portions of the sidewall 51 of the opening 50 adjacent to the curved portions of the bilobed segments 40, 42 of the column 38. In one embodiment, the base 52 may completely overlap the mating pad 34 along the entire gap G3.

[0033] In one embodiment, the base 52 and the pillar 38 may be made of the same metal. In one embodiment, the base 52 may be made of a different metal than the pillar 38. In one embodiment, the base 52 may be made of a different metal than the mating pad 34. The presence of the base 52 filling the gap G3 can at least replace a portion of the bottom filler material that would normally fill the gap G3.

[0034] Please refer to Figure 6 According to an alternative embodiment, the base 52 may have a double-lobed shape, mirroring the double-lobed shape of the pillar 38 and the double-lobed shape of the opening 50 located in the dielectric layer 36. Specifically, the base 52 may have a lobe-shaped segment that coincides in position with the lobe-shaped segment 40 of the pillar 38, a lobe-shaped segment that coincides in position with the lobe-shaped segment 42 of the pillar 38, and a segment that coincides in position with the connecting segment 44 of the pillar 38.

[0035] Please refer to Figure 7 According to an alternative embodiment, the sidewall 51 of the opening 50 in the dielectric layer 36 may be inclined outward at an acute angle, which is the complementary angle of angle θ. Angle θ can be evaluated relative to the surface normal perpendicular to the horizontal plane established by the top surface 35 of the bonding pad 34. In one embodiment, the sidewall 51 of the opening 50 (adjacent to the outer sidewall 46 of the pillar 38) may be inclined relative to the horizontal plane established by the top surface 35 of the bonding pad 34 in the range of about 75° to less than 90°. The width of the gap G3 may increase along the height H of the opening 50 with increasing distance from the bonding pad 34.

[0036] The tilt of the sidewall 51 of the opening 50 in the dielectric layer 36 (particularly in the range of about 75° to less than 90°) can help to further reduce the strain transferred from the pillar 38 to the back-end process stack 25 of the photonic chip 12. This further reduction in strain can further help to reduce or eliminate the incidence of chip-package interaction failures in adjacent portions of the back-end process stack 25.

[0037] Please refer to Figure 8 According to an alternative embodiment, the connecting section 44 of the column 38 can connect at least a portion of the petal-shaped section 40 of the column 38 to at least a portion of the petal-shaped section 42 of the column 38. The connecting section 44 of the column 38 can be bent so that its width dimension W increases with the distance from the petal-shaped section 42. The portion of the opening 50 adjoining the connecting section 44 can also be bent to match the curvature of the connecting section 44 and maintain the width dimension of the gap G3 between the sidewall 51 and the outer sidewall 46.

[0038] The method described above is used for the manufacture of integrated circuit chips. Manufacturers can distribute the resulting integrated circuit chips in raw wafer form (e.g., as a single wafer with multiple unpackaged chips), as bare dies, or in packaged form. The chip can be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of an intermediate or final product. The final product can be any product including the integrated circuit chip, such as a computer product with a central processing unit or a smartphone.

[0039] The terms used herein, modified by approximate language such as “approximately,” “roughly,” and “substantially,” are not limited to the specified exact values ​​or conditions. In embodiments, approximate language may represent a range of + / -10% of the one or more values ​​or conditions.

[0040] The terms "vertical" and "horizontal" are used in this document as examples to establish a reference frame and are not intended to be limiting. The term "horizontal" as used herein is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "orthogonal" refer to directions within the reference frame that are perpendicular to the horizontal plane as defined above. The term "lateral" refers to a direction within the reference frame that lies within the horizontal plane.

[0041] A feature "connected" or "coupled" to another feature may be directly connected or coupled to that other feature, or one or more intermediate features may exist. If no intermediate features exist, the feature may be "directly connected" or "directly coupled" to the other feature. If at least one intermediate feature exists, the feature may be "indirectly connected" or "indirectly coupled" to the other feature. A feature "on" or "in contact" with another feature may be directly on or in contact with that other feature, or one or more intermediate features may exist. If no intermediate features exist, the feature may be directly "on" or in contact with that other feature. If at least one intermediate feature exists, the feature may not be "directly" on or in contact with that other feature. If one feature extends over and covers a portion of another feature, the different features may "overlap".

[0042] The descriptions of various embodiments of the invention are for illustrative purposes only and are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or improvements upon technical techniques known in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A structure, characterized in that, include: Photonic chips, including bonding pads; and Electrical interconnection includes a post disposed on a portion of the bonding pad, the post including a first petal segment, a second petal segment separated from the first petal segment by a first gap, and a connecting segment extending across the first gap to connect the first petal segment and the second petal segment.

2. The structure as described in claim 1, characterized in that, The first petal-shaped section of the column is smaller than the second petal-shaped section of the column.

3. The structure as described in claim 1, characterized in that, Also includes: Dielectric layer with openings The column is disposed inside the opening, the column has a sidewall, and the opening has a sidewall that is separated from the sidewall of the column by a second gap.

4. The structure as described in claim 3, characterized in that, The dielectric layer partially overlaps with the bonding pad on the sidewall adjacent to the opening.

5. The structure as described in claim 3, characterized in that, The opening has a height relative to the mating pad, and the second gap has a width dimension that is constant along the height of the opening.

6. The structure as described in claim 3, characterized in that, The second gap has an average width dimension of less than about 1 micrometer.

7. The structure as described in claim 3, characterized in that, The second gap has a width dimension that increases along the height of the opening as the distance from the mating pad increases.

8. The structure as described in claim 3, characterized in that, The bonding pad has a flat top surface, and the sidewall of the opening is inclined at an angle relative to the flat top surface of the bonding pad in the range of about 75° to less than 90°.

9. The structure as described in claim 3, characterized in that, The electrical interconnect includes a base disposed between the bonding pad and the pillar.

10. The structure as described in claim 9, characterized in that, The base is a cylinder with a circular cross-sectional profile.

11. The structure as described in claim 9, characterized in that, The base has a first petal-shaped section that coincides with the first petal-shaped section of the column, a second petal-shaped section that coincides with the second petal-shaped section of the column in position, and a section that coincides with the connecting section of the column.

12. The structure as described in claim 3, characterized in that, The opening has a first petal-shaped section that coincides with the first petal-shaped section of the pillar, a second petal-shaped section that coincides with the second petal-shaped section of the pillar in position, and a section that coincides with the connecting section of the pillar.

13. The structure as described in claim 12, characterized in that, The second gap has a constant width dimension between the opening and the column.

14. The structure as described in claim 3, characterized in that, The dielectric layer comprises inorganic dielectric materials.

15. The structure as described in claim 14, characterized in that, The dielectric layer has a thickness of approximately 6 micrometers.

16. The structure as described in claim 3, characterized in that, The sidewall of the opening completely surrounds the sidewall of the column.

17. The structure as described in claim 1, characterized in that, Also includes: The laminated substrate is separated from the photonic chip by a second gap. The bonding pad and the electrical interconnect are disposed in the second gap.

18. The structure as described in claim 1, characterized in that, The photonic chip has a side surface, the first lobe segment is disposed closer to the side surface of the photonic chip than the second lobe segment, and the first lobe segment of the pillar is smaller than the second lobe segment of the pillar.

19. The structure as described in claim 1, characterized in that, The first petal-shaped section of the column is smaller than the second petal-shaped section of the column, and the connecting section has a width dimension that increases with the distance from the second petal-shaped section of the column.

20. A method, characterized in that, include: Forming a photonic chip including a bonding pad; as well as An electrical interconnect is formed, the electrical interconnect including a pillar disposed on a portion of the bonding pad, wherein the pillar includes a first petal-shaped segment, a second petal-shaped segment separated from the first petal-shaped segment by a gap, and a connecting segment extending across the gap to connect the first petal-shaped segment and the second petal-shaped segment.

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