A trimming circuit applied to a low-power chip

Abstract

The present invention discloses a trimming circuit applied to a low-power chip, comprising: a power-on reset circuit, a first delay circuit, a second delay circuit, a third delay circuit, a trimming unit, a logic circuit, and a control circuit; the input end of the power-on reset circuit is connected to a power supply, and the output end of the power-on reset circuit is respectively connected to the input end of the first delay circuit, the input end of the second delay circuit, and the input end of the third delay circuit; the output end of the first delay circuit is connected to the input end of the logic circuit, the output end of the second delay circuit is connected to the input end of the trimming unit, and the output end of the third delay circuit is connected to the input end of the control circuit; the output end of the trimming unit is connected to the input end of the logic circuit, and the output end of the logic circuit is connected to the input end of the control circuit. The trimming circuit provided by the present invention can complete the selection of the trimming state and the logic control after the chip is powered on, and hardly consumes power, which is an ideal choice for low-power chips.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and particularly to a trimming circuit applied to a low-power chip. Background Art

[0002] In the design of integrated circuits, due to the deviation of the design process, the parameter accuracy is often insufficient or even exceeds the range of the specification, which requires trimming of the parameters. In measuring the performance of a chip, power consumption is a very important indicator. However, the trimming circuit of the parameters requires a certain working current, and this current will exist as long as the chip is not powered off. Usually, a chip needs to trim multiple parameters, so multiple trimming units must be provided, which increases the power consumption of the entire chip. For a low-power chip, this is unacceptable. Summary of the Invention

[0003] In order to solve the problems existing in the prior art, the present invention provides a trimming circuit applied to a low-power chip.

[0004] To achieve the above object, the present invention provides the following solution:

[0005] A trimming circuit applied to a low-power chip includes: a power-on reset circuit, a first delay circuit, a second delay circuit, a third delay circuit, a trimming unit, a logic circuit, and a control circuit;

[0006] The input end of the power-on reset circuit is connected to a power supply, and the output end of the power-on reset circuit is respectively connected to the input ends of the first delay circuit, the second delay circuit, and the third delay circuit; the output end of the first delay circuit is connected to the input end of the logic circuit, the output end of the second delay circuit is connected to the input end of the trimming unit, and the output end of the third delay circuit is connected to the input end of the control circuit; the output end of the trimming unit is connected to the input end of the logic circuit, and the output end of the logic circuit is connected to the input end of the control circuit.

[0007] Optionally, the trimming unit includes: a first inverter, a second inverter, a third inverter, a fourth inverter, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a bias current source, and a fuse;

[0008] The input terminal of the first inverter is connected to the output terminal of the second delay circuit. The output terminal of the first inverter is respectively connected to the input terminal of the second inverter and the gate of the second PMOS transistor. The power supply terminal of the first inverter is connected to the power supply, and the ground terminal of the first inverter is grounded. The output terminal of the second inverter is respectively connected to the gates of the first PMOS transistor, the first NMOS transistor, the fourth NMOS transistor, and the seventh NMOS transistor. The power supply terminal of the second inverter is connected to the power supply, and the ground terminal of the second inverter is grounded. The input terminal of the bias current source is connected to the power supply, and the output terminal of the bias current source is connected to the source of the first PMOS transistor. The drain of the first PMOS transistor is respectively connected to the drains of the first NMOS transistor, the second NMOS transistor, the gate of the second NMOS transistor, and the gate of the third NMOS transistor. The source of the first NMOS transistor is grounded. The source of the second NMOS transistor is grounded. The drain of the third NMOS transistor is respectively connected to the drains of the second PMOS transistor, the third PMOS transistor, the gate of the third PMOS transistor, the gate of the fourth PMOS transistor, and the gate of the fifth PMOS transistor. The source of the third NMOS transistor is grounded. The source of the second PMOS transistor is connected to the power supply. The source of the third PMOS transistor is connected to the power supply. The drain of the fourth PMOS transistor is respectively connected to the drains of the fourth NMOS transistor, the fifth NMOS transistor, the gate of the fifth NMOS transistor, and the gate of the sixth NMOS transistor. The source of the fourth PMOS transistor is connected to the power supply. The drain of the fifth PMOS transistor is respectively connected to the drains of the sixth NMOS transistor, the seventh NMOS transistor, and the input terminal of the third inverter. The source of the fifth PMOS transistor is connected to the power supply. The source of the fourth NMOS transistor is grounded. The source of the fifth NMOS transistor is grounded. The source of the sixth NMOS transistor is connected to the first input terminal of the fuse, and the second input terminal of the fuse is grounded. The source of the seventh NMOS transistor is grounded. The output terminal of the third inverter is connected to the input terminal of the fourth inverter. The power supply terminal of the third inverter is connected to the power supply, and the ground terminal of the third inverter is grounded. The output terminal of the fourth inverter is connected to the input terminal of the logic circuit. The power supply terminal of the fourth inverter is connected to the power supply, and the ground terminal of the fourth inverter is grounded.

[0009] Optionally, the W / L ratios of the third PMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor are 2:1:1. The W / L ratios of the second NMOS transistor and the third NMOS transistor are 1:1. The W / L ratios of the fifth NMOS transistor and the sixth NMOS transistor are 1:2.

[0010] Optionally, when the output of the second delay circuit is at a low level, the trimming unit is in a normal working state; if no trimming is performed, the fuse is not blown, and the output terminal of the fourth inverter outputs a low level; if trimming is performed, the fuse is blown, and the output terminal of the fourth inverter outputs a high level.

[0011] Optionally, the logic circuit includes: a NOR gate, a fifth inverter, a sixth inverter, and a NAND gate;

[0012] The first input terminal of the NOR gate is connected to the output terminal of the sixth inverter, the second input terminal of the NOR gate is connected to the output terminal of the fourth inverter, and the output terminal of the NOR gate is connected to the input terminal of the fifth inverter; the output terminal of the fifth inverter is connected to the first input terminal of the NAND gate; the second input terminal of the NAND gate is connected to the output terminal of the first delay circuit, and the output terminal of the NAND gate is connected to the input terminal of the sixth inverter; the output terminal of the sixth inverter is further connected to the input terminal of the control circuit.

[0013] According to the specific embodiments provided by the present invention, the following technical effects are disclosed by the present invention:

[0014] The trimming circuit provided by the present invention can be applied to a trimming circuit (general type) for blowing a fuse. After the chip powers on, it can not only complete the selection of the trimming state and logical control, but also consume almost no power, which is an ideal choice for low-power chips. Description of the Drawings

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0016] Figure 1 It is a schematic structural diagram of a trimming circuit applied to a low-power chip provided by the present invention;

[0017] Figure 2 It is a schematic structural diagram of a trimming unit provided by the present invention;

[0018] Figure 3 It is a schematic structural diagram of a logic circuit provided by the present invention

[0019] Figure 4 It is a schematic diagram of the working curves of each point in the trimming circuit applied to a low-power chip provided by the present invention. Detailed Embodiments

[0020] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0021] To make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] As Figure 1 shown, the trimming circuit applied to a low-power chip provided by the present invention includes: a power-on reset circuit I1, a first delay circuit I2, a second delay circuit I3, a third delay circuit I7, a trimming unit I4, a logic circuit I5, and a control circuit I6.

[0023] The input end of the power-on reset circuit I1 is connected to the power supply VCC, and the output end of the power-on reset circuit I1 is respectively connected to the input ends of the first delay circuit I2, the second delay circuit I3, and the third delay circuit I7. The output end of the first delay circuit I2 is connected to the input end of the logic circuit I5, the output end of the second delay circuit I3 is connected to the input end of the trimming unit I4, and the output end of the third delay circuit I7 is connected to the input end of the control circuit I6; the output end of the trimming unit I4 is connected to the input end of the logic circuit I5, and the output end of the logic circuit I5 is connected to the input end of the control circuit I6.

[0024] The power-on reset circuit I1 generates a logic signal POR during the rising process of VCC, which is used to reset or enable control of other modules. After VCC rises to a certain threshold, POR changes from low to high. The first delay circuit I2 and the second delay circuit I3 are controlled to start timing by the signal POR.

[0025] The second delay circuit I3 delays the signal POR output by the power-on reset circuit I1 (using an inverter and an RC), and after the delay ends, turns off the branch currents in the trimming unit I4.

[0026] The trimming unit I4 determines whether the fuse FUSE is blown to decide whether the output TRIM_DATA is high or low. If trimming is required, that is, the fuse is blown, then TRIM_DATA is high; if no trimming is required, then TRIM_DATA is low.

[0027] The logic circuit I5 uses the output TRIM_CTL of the first delay circuit I2 to set TRIM_OK and latch the state of the output TRIM_DATA of the trimming unit I4. When VCC does not lose power, TRIM_OK always remains high or low. TRIM_OK is the finally output latched signal, and its high or low state represents trimming or non-trimming.

[0028] Based on the output signal POR of the power-on reset circuit I1, the third delay circuit I7 generates a delay time TDC and outputs a POR_END signal to determine the working state of the control circuit I6. The control circuit I6 determines whether to transmit the TRIM_OK signal to the subsequent circuit according to the POR_END signal.

[0029] The working principle of the trimming circuit applied to the low-power chip provided by the present invention is as follows:

[0030] During the power-on process of VCC, if VCC > VPOR, the output POR of the power-on reset circuit I1 changes from low to high. At the same time, the first delay circuit I2, the second delay circuit I3, and the third delay circuit I7 start timing. Within the T DA time, the output TRIM_CTL of the first delay circuit I2 is low. Within the T DB time, the output TRIM_RST of the second delay circuit I3 is low. Within the T DC time, the output POR_END of the third delay circuit I7 is low. If trimming is performed, the fuse is blown. Within the T DB time, the output TRIM_DATA of the trimming unit I4 remains high. Within the T DA time, the output TRIM_OK of the logic circuit I5 remains low. Within the T DC time, the output CTL of the control circuit I6 remains low. Once the T DA time ends, the output TRIM_CTL of the first delay circuit I2 changes from low to high, sets the output TRIM_OK of the logic circuit I5 to high, and keeps it high. As long as VCC does not lose power, TRIM_OK always remains high. Once the T DB time ends, the output TRIM_RST of the second delay circuit I3 changes from low to high, the output TRIM_DATA of the trimming unit I4 changes from high to low, and at the same time, the currents of each branch in the trimming unit I4 are turned off. If no trimming is performed, the fuse is not blown, and the output TRIM_OK of the logic circuit I5 is always low. Similarly, after the T DB time ends, the output TRIM_RST of the second delay circuit I3 changes from low to high, and the currents of each branch in the trimming unit I4 are also turned off. Once the T DCWhen the time ends, the output signal POR_END of the third delay circuit I7 goes high, allowing the control circuit I6 to transmit the TRIM_OK signal to CTL, that is, CTL is in the same direction as TRIM_OK. The working curves of each point in the trimming circuit are as Figure 4 shown.

[0031] As Figure 2 shown, the trimming unit includes: a first inverter I8, a second inverter I9, a third inverter (Schmitt inverter) I10, a fourth inverter I11, a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, a bias current source I BIAS and a fuse FUSE.

[0032] The input terminal of the first inverter I8 is connected to the output terminal of the second delay circuit I3. The output terminal of the first inverter I8 is respectively connected to the input terminal of the second inverter I9 and the gate of the second PMOS transistor P2. The power supply terminal of the first inverter I8 is connected to the power supply VCC, and the ground terminal of the first inverter I8 is grounded to GND. The output terminal of the second inverter I9 is respectively connected to the gates of the first PMOS transistor P1, the first NMOS transistor N1, the fourth NMOS transistor N4, and the seventh NMOS transistor N7. The power supply terminal of the second inverter I9 is connected to the power supply VCC, and the ground terminal of the second inverter I9 is grounded to GND. The input terminal of the bias current source is connected to the power supply VCC, and the output terminal of the bias current source is connected to the source of the first PMOS transistor P1. The drain of the first PMOS transistor P1 is respectively connected to the drains of the first NMOS transistor N1, the second NMOS transistor N2, the gate of the second NMOS transistor N2, and the gate of the third NMOS transistor N3. The source of the first NMOS transistor N1 is grounded to GND. The source of the second NMOS transistor N2 is grounded to GND. The drain of the third NMOS transistor N3 is respectively connected to the drains of the second PMOS transistor P2, the third PMOS transistor P3, the gate of the third PMOS transistor P3, the gate of the fourth PMOS transistor P4, and the gate of the fifth PMOS transistor P5. The source of the third NMOS transistor N3 is grounded to GND. The source of the second PMOS transistor P2 is connected to the power supply VCC. The source of the third PMOS transistor P3 is connected to the power supply VCC. The drain of the fourth PMOS transistor P4 is respectively connected to the drains of the fourth NMOS transistor N4, the fifth NMOS transistor N5, the gate of the fifth NMOS transistor N5, and the gate of the sixth NMOS transistor N6. The source of the fourth PMOS transistor P4 is connected to the power supply VCC. The drain of the fifth PMOS transistor P5 is respectively connected to the drains of the sixth NMOS transistor N6, the seventh NMOS transistor N7, and the input terminal of the third inverter I10. The source of the fifth PMOS transistor P5 is connected to the power supply VCC. The source of the fourth NMOS transistor N4 is grounded to GND. The source of the fifth NMOS transistor N5 is grounded to GND. The source of the sixth NMOS transistor N6 is connected to the first input terminal of the fuse, and the second input terminal of the fuse is grounded to GND. The source of the seventh NMOS transistor N7 is grounded to GND. The output terminal of the third inverter I10 is connected to the input terminal of the fourth inverter I11. The power supply terminal of the third inverter I10 is connected to the power supply VCC, and the ground terminal of the third inverter I10 is grounded to GND. The output terminal of the fourth inverter I11 is connected to the input terminal of the logic circuit I5. The power supply terminal of the fourth inverter I11 is connected to the power supply VCC, and the ground terminal of the fourth inverter I11 is grounded to GND.

[0033] The W / L ratios of the third PMOS transistor P3, the fourth PMOS transistor P4, and the fifth PMOS transistor P5 are 2:1:1; the W / L ratios of the second NMOS transistor N2 and the third NMOS transistor N3 are 1:1; the W / L ratios of the fifth NMOS transistor N5 and the sixth NMOS transistor N6 are 1:2.

[0034] The working principle of the trimming unit I4 is as follows:

[0035] When TRIM_RST is high, the trimming unit I4 does not consume power and is in the off state; the output terminal of the first inverter I8 is low, and the output terminal of the second inverter I9 is high; the gate of the second PMOS transistor P2 is set low; the gates of the first PMOS transistor P1, the first NMOS transistor N1, the fourth NMOS transistor N4, and the seventh NMOS transistor N7 are all set high; the gates and drains of the second NMOS transistor N2, and the gate of the third NMOS transistor N3 are all set low; the gates and drains of the fifth NMOS transistor N5, and the gates and drains of the sixth NMOS transistor N6 are all set low; the gates and drains of the third PMOS transistor P3, the gate of the fourth PMOS transistor P4, and the gate of the fifth PMOS transistor P5 are all set high; the input terminal of the third inverter I10 is set low, and its output terminal is high; the input terminal of the fourth inverter I11 is high, and its output terminal TRIM_DATA is low. When TRIM_RST is low, the trimming unit I4 is in the normal working state; if no trimming is performed, the fuse FUSE is not blown, the drain of the sixth NMOS transistor N6 is low, and the output terminal TRIM_DATA of the fourth inverter I11 is low; if trimming is performed, the fuse FUSE is blown, the drain of the sixth NMOS transistor N6 is high, and the output terminal TRIM_DATA of the fourth inverter I11 is high. At time DB During T, TRIM_RST is low. Whether trimming is performed or not, the state of TRIM_DATA has been determined, and this TRIM_DATA state is passed to the logic circuit I5, and the logic circuit I5 latches the state of TRIM_DATA; at the end of time DB T, TRIM_RST changes from low to high, and the branch currents in the trimming unit I4 will be turned off.

[0036] As Figure 3 shown, the logic circuit I5 includes: a NOR gate I12, a fifth inverter I13, a sixth inverter I15, and a NAND gate I14.

[0037] The first input terminal of the NOR gate I12 is connected to the output terminal of the sixth inverter I15, the second input terminal of the NOR gate I12 is connected to the output terminal of the fourth inverter I11, and the output terminal of the NOR gate I12 is connected to the input terminal of the fifth inverter I13; the output terminal of the fifth inverter I13 is connected to the first input terminal of the NAND gate I14; the second input terminal of the NAND gate I14 is connected to the output terminal of the first delay circuit I12, and the output terminal of the NAND gate I14 is connected to the input terminal of the sixth inverter I15; the output terminal of the sixth inverter I15 is also connected to the input terminal of the control circuit I16.

[0038] The working principle of the logic circuit I5 is as follows:

[0039] If the second input terminal TRIM_CTL of the NAND gate I14 is low, the output terminal TRIM_OK of the sixth inverter I15 is low. Regardless of whether the state of the second input terminal of the NOR gate I12 is high or low, the output terminal TRIM_OK of the sixth inverter I15 is always low. If during the time when the second input terminal TRIM_CTL of the NAND gate I14 is low, the second input terminal TRIM_DATA of the NOR gate I12 is low, then the output terminal of the fifth inverter I13 is low. Once the second input terminal TRIM_CTL of the NAND gate I14 changes from low to high, the output terminal TRIM_OK of the sixth inverter I15 is latched low. If during the time when the second input terminal TRIM_CTL of the NAND gate I14 is low, the second input terminal TRIM_DATA of the NOR gate I12 is high, then the output terminal of the fifth inverter I13 is high. Once the second input terminal TRIM_CTL of the NAND gate I14 changes from low to high, the output terminal TRIM_OK of the sixth inverter I15 is latched high.

[0040] The present invention is applicable to a trimming circuit (general type) for blowing fuses. After the chip powers on and ends, it not only completes the selection and logic control of the trimming state, but also consumes almost no power, which is an ideal choice for low-power chips.

[0041] In this specification, each embodiment is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0042] In this article, specific examples are used to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A trimming circuit applied to a low-power chip, characterized in that, it includes: a power-on reset circuit, a first delay circuit, a second delay circuit, a third delay circuit, a trimming unit, a logic circuit, and a control circuit; the input end of the power-on reset circuit is connected to a power supply, and the output end of the power-on reset circuit is respectively connected to the input end of the first delay circuit, the input end of the second delay circuit, and the input end of the third delay circuit; the output end of the first delay circuit is connected to the input end of the logic circuit, the output end of the second delay circuit is connected to the input end of the trimming unit, and the output end of the third delay circuit is connected to the input end of the control circuit; the output end of the trimming unit is connected to the input end of the logic circuit, and the output end of the logic circuit is connected to the input end of the control circuit; the trimming unit includes: a first inverter, a second inverter, a third inverter, a fourth inverter, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a bias current source, and a fuse; The input terminal of the first inverter is connected to the output terminal of the second delay circuit. The output terminal of the first inverter is respectively connected to the input terminal of the second inverter and the gate of the second PMOS transistor. The power supply terminal of the first inverter is connected to the power supply, and the ground terminal of the first inverter is grounded. The output terminal of the second inverter is respectively connected to the gates of the first PMOS transistor, the first NMOS transistor, the fourth NMOS transistor, and the seventh NMOS transistor. The power supply terminal of the second inverter is connected to the power supply, and the ground terminal of the second inverter is grounded. The input terminal of the bias current source is connected to the power supply, and the output terminal of the bias current source is connected to the source of the first PMOS transistor. The drain of the first PMOS transistor is respectively connected to the drains of the first NMOS transistor, the second NMOS transistor, the gate of the second NMOS transistor, and the gate of the third NMOS transistor. The source of the first NMOS transistor is grounded. The source of the second NMOS transistor is grounded. The drain of the third NMOS transistor is respectively connected to the drains of the second PMOS transistor, the third PMOS transistor, the gate of the third PMOS transistor, the gate of the fourth PMOS transistor, and the gate of the fifth PMOS transistor. The source of the third NMOS transistor is grounded. The source of the second PMOS transistor is connected to the power supply. The source of the third PMOS transistor is connected to the power supply. The drain of the fourth PMOS transistor is respectively connected to the drains of the fourth NMOS transistor, the fifth NMOS transistor, the gate of the fifth NMOS transistor, and the gate of the sixth NMOS transistor. The source of the fourth PMOS transistor is connected to the power supply. The drain of the fifth PMOS transistor is respectively connected to the drains of the sixth NMOS transistor, the seventh NMOS transistor, and the input terminal of the third inverter. The source of the fifth PMOS transistor is connected to the power supply. The source of the fourth NMOS transistor is grounded. The source of the fifth NMOS transistor is grounded. The source of the sixth NMOS transistor is connected to the first input terminal of the fuse, and the second input terminal of the fuse is grounded. The source of the seventh NMOS transistor is grounded. The output terminal of the third inverter is connected to the input terminal of the fourth inverter. The power supply terminal of the third inverter is connected to the power supply, and the ground terminal of the third inverter is grounded. The output terminal of the fourth inverter is connected to the input terminal of the logic circuit. The power supply terminal of the fourth inverter is connected to the power supply, and the ground terminal of the fourth inverter is grounded.

2. The trimming circuit applied to a low-power chip according to claim 1, characterized in that, the W / L ratios of the third PMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor are 2:1:1; the W / L ratios of the second NMOS transistor and the third NMOS transistor are 1:1; the W / L ratios of the fifth NMOS transistor and the sixth NMOS transistor are 1:

2.

3. The trimming circuit applied to the low-power chip according to claim 1, characterized in that, when the output of the second delay circuit is at a low level, the trimming unit is in a normal working state; if there is no trimming, the fuse is not blown, and the output end of the fourth inverter outputs a low level; if there is trimming, the fuse is blown, and the output end of the fourth inverter outputs a high level.

4. The trimming circuit applied to the low-power chip according to claim 1, characterized in that, the logic circuit includes: a NOR gate, a fifth inverter, a sixth inverter, and a NAND gate; the first input end of the NOR gate is connected to the output end of the sixth inverter, the second input end of the NOR gate is connected to the output end of the fourth inverter, and the output end of the NOR gate is connected to the input end of the fifth inverter; the output end of the fifth inverter is connected to the first input end of the NAND gate; the second input end of the NAND gate is connected to the output end of the first delay circuit, and the output end of the NAND gate is connected to the input end of the sixth inverter; the output end of the sixth inverter is further connected to the input end of the control circuit.

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