Video data processing debugging system and method based on FPGA prototype verification

Abstract

The application relates to the field of chip design, in particular to a video data processing debugging system and method based on FPGA prototype verification. The system comprises a DDR memory for storing data; a data generation module for generating original video data to be tested; a compression module for compressing the original video data to be tested to generate compressed data, and for providing an internal bus interface for accessing the DDR memory; a bus interface debugging module for providing an external bus interface for accessing the DDR memory; when the compression module generates the compressed data, a bus arbitration module is enabled to connect the internal bus interface with the DDR memory to store the compressed data into the DDR memory; when it is needed to verify the video data processing function, the bus arbitration module is enabled to connect the external bus interface to enable an external device to read the compressed data from the DDR memory. The scheme of the application avoids wasting internal RAM resources and realizes convenient and fast acquisition of debugging data.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip design, and particularly relates to a video data processing debugging system and method based on FPGA prototype verification, a computer device and a computer readable storage medium. BACKGROUND

[0002] With the increase of chip complexity and performance, more and more IP (Intellectual Property core) is integrated in the chip, which brings more challenges to the chip verification. Unlike logic simulation verification, FPGA (Field-Programmable Gate Array) prototype verification restores the real use scene of the chip as much as possible, and has become the mainstream and mature verification method in the current chip design. The RTL (Register Transfer Level) code is transplanted to the FPGA for function verification using the FPGA prototype verification platform. In addition, FPGA verification can reduce the cost, and can be repeatedly verified many times in the prototype verification stage. FPGA prototype verification can accelerate the simulation speed and realize the soft and hardware collaborative development verification before the chip is taped out. The BMC (Baseboard Management Controller) chip is used for management and control in the server system, such as monitoring and controlling the system hardware. The VGA interface in the BMC chip is used to realize the display function of the server host. In order to facilitate the debugging of the server system, the video data is compressed and sent to the remote end through the network to realize the function of remote monitoring and management. If the remote display function has a problem, it will directly affect the effect of remote monitoring. Therefore, during the FPGA prototype verification, the video image compression function of the BMC chip needs to be verified as much as possible.

[0003] In order to verify the video image compression function as much as possible, the module is verified separately to ensure the correctness of the video compression. The test data is provided in the form of internally self-built video image data in the module level verification, and then the compressed image data is obtained. The obtained data is compared with the correct compressed data. At present, the compressed video image data is generally obtained by using the online debugging IP core method. Please refer to Figure 1As shown, in the FPGA prototype verification project, data signals to be observed are added, which are stored in internal RAM (Random Access Memory) and different storage depths can be set. A data stream file is generated using FPGA software, the data stream file is downloaded into the FPGA device through a downloader, and real-time captured data in the storage RAM is read on the PC through the downloader. The BMC chip is a SoC (System on Chip) chip, which has its own CPU, bus arbitration module and DDR (Double Data Rate) memory on the chip. The internally self-built test data is transmitted to the compression module for video image data compression, and in order to prevent data processing from being lost in time, the video data needs to be written into the DDR memory for caching. In the SoC, the bus arbitration module is used to realize the arbitration operation of the bus. However, the online debugging IP mode needs to use internal RAM to store data signals. The more data signals to be observed, the larger the bit width, the larger the depth to be set, and the more RAM resources are consumed. Therefore, the display data obtained each time through this way is limited. If all the data of the corresponding resolution is to be obtained, multiple batches of reading are required. In addition, this way increases the difficulty of software layout and wiring, increases the time of generating the data stream file, and may also cause project timing violation and other problems. SUMMARY

[0004] Therefore, in view of the problem that the existing online debugging IP core mode greatly wastes RAM resources and the project timing is complex, the present application provides a video data processing debugging system based on FPGA prototype verification, a video data processing debugging method based on FPGA prototype verification, a computer device and a computer readable storage medium.

[0005] According to a first aspect of the present application, a video data processing debugging system based on FPGA prototype verification is provided, and the system comprises:

[0006] a DDR memory for storing data;

[0007] a data generation module for generating original video data to be tested;

[0008] a compression module for compressing the original video data to be tested to generate compressed data, and for providing an internal bus interface for accessing the DDR memory;

[0009] a bus interface debugging module for providing an external bus interface for accessing the DDR memory;

[0010] a bus arbitration module for selecting the internal bus interface or the external bus interface to communicate with the DDR memory, wherein when the compression module generates compressed data, the internal bus interface is selected to connect with the DDR memory to store the compressed data into the DDR memory, and when it is needed to verify the video data processing function, the external bus interface is selected to enable an external device to read the compressed data from the DDR memory.

[0011] In some embodiments, the system further comprises a CPU module for configuring registers of the compression module by configuring a bus based on a resolution of the raw video data to be tested.

[0012] In some embodiments, the data generation module provides a built-in digital VGA interface to generate RGB format data.

[0013] In some embodiments, the compression module is further configured to:

[0014] convert the raw video data to be tested in RGB format to YUV format data, and compress the YUV format data in blocks to generate compressed data.

[0015] According to a second aspect of the present application, there is provided a video data processing debugging method based on FPGA prototype verification, the method comprising:

[0016] using DDR memory to store data;

[0017] using a data generation module to generate raw video data to be tested;

[0018] using a compression module to compress the raw video data to be tested to generate compressed data, and providing an internal bus interface to access the DDR memory;

[0019] using a bus interface debugging module to provide an external bus interface to access the DDR memory;

[0020] using a bus arbitration module to select the internal bus interface or the external bus interface to communicate with the DDR memory, wherein when the compression module generates compressed data, the internal bus interface is selected to connect with the DDR memory to store the compressed data into the DDR memory, and when it is needed to verify the video data processing function, the external bus interface is selected to enable an external device to read the compressed data from the DDR memory.

[0021] In some embodiments, the method further comprises:

[0022] The CPU module configures the registers of the compression module through a configuration bus based on the resolution of the original video data to be tested.

[0023] In some embodiments, the original video data to be tested is generated by a data generation module, including:

[0024] A built-in digital VGA interface is provided to generate RGB format data.

[0025] In some embodiments, the original video data to be tested is compressed by a compression module to generate compressed data, including:

[0026] The original video data to be tested in RGB format is converted to YUV format data, and the YUV format data is compressed in blocks to generate compressed data.

[0027] According to a third aspect of the present application, there is also provided a computer device, comprising:

[0028] at least one processor; and

[0029] a memory storing a computer program capable of running on the processor, the processor executing the program to perform the aforementioned FPGA prototype verification based video data processing debugging method, the method comprising performing the following steps:

[0030] DDR memory is used to store data;

[0031] A data generation module is used to generate original video data to be tested;

[0032] A compression module is used to compress the original video data to be tested to generate compressed data, and an internal bus interface is provided to access the DDR memory;

[0033] An external bus interface is provided by a bus interface debugging module to access the DDR memory;

[0034] The internal bus interface or the external bus interface is selected to be connected to the DDR memory by a bus arbitration module, wherein when the compression module generates compressed data, the internal bus interface is selected to be connected to the DDR memory to store the compressed data in the DDR memory, and when it is necessary to verify the video data processing function, the external bus interface is selected to enable an external device to read the compressed data from the DDR memory.

[0035] According to the fourth aspect of the present application, there is also provided a computer readable storage medium storing a computer program which, when executed by a processor, performs the aforementioned FPGA prototype verification based video data processing debugging method, the method comprising performing the following steps:

[0036] using the DDR memory for storing data;

[0037] generating the original video data to be tested using a data generation module;

[0038] compressing the original video data to be tested using a compression module to generate compressed data, and providing an internal bus interface for accessing the DDR memory;

[0039] providing an external bus interface for accessing the DDR memory using a bus interface debugging module;

[0040] selecting the internal bus interface or the external bus interface to be connected to the DDR memory using a bus arbitration module, wherein when the compression module generates compressed data, the internal bus interface is selected to be connected to the DDR memory to store the compressed data in the DDR memory, and when it is necessary to verify the video data processing function, the external bus interface is selected to enable an external device to read the compressed data from the DDR memory.

[0041] The aforementioned FPGA prototype verification based video data processing debugging system adds a bus interface debugging module to provide an external bus interface for accessing the DDR memory, and uses a bus arbitration module to select the internal bus interface or the external bus interface to be connected to the DDR memory, thereby realizing that when the compression module generates compressed data, the internal bus interface is selected to be connected to the DDR memory to store the compressed data in the DDR memory, and when it is necessary to verify the video data processing function, the external bus interface is selected to enable an external device to read the compressed data from the DDR memory, thus providing a simple and convenient way to obtain video compressed data, which does not deteriorate the timing of the project, thereby avoiding waste of internal RAM resources and realizing convenient and fast access to debugging data.

[0042] In addition, the present application also provides an FPGA prototype verification based video data processing debugging method, a computer device and a computer readable storage medium, which can also achieve the aforementioned technical effects, and thus will not be described here. BRIEF DESCRIPTION OF DRAWINGS

[0043] In order to make the technical solutions in the embodiments of the present application or the prior art clearer, the accompanying drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description only only some embodiments of the present application, and for those skilled in the art, other embodiments can be obtained from these drawings without creative labor.

[0044] Figure 1 A schematic diagram of a video data processing debugging system for traditional FPGA prototype verification;

[0045] Figure 2 A structural schematic diagram of a video data processing debugging system based on FPGA prototype verification provided by an embodiment of the present application;

[0046] Figure 3 A flow schematic diagram of a video data processing debugging method based on FPGA prototype verification provided by another embodiment of the present application;

[0047] Figure 4 A video compression function verification flow schematic diagram provided by an embodiment of the present application;

[0048] Figure 5 An internal structure diagram of a computer device in another embodiment of the present application. DETAILED DESCRIPTION

[0049] In order to make the technical solutions in the embodiments of the present application or the prior art clearer, the accompanying drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description only only some embodiments of the present application, and for those skilled in the art, other embodiments can be obtained from these drawings without creative labor.

[0050] It should be noted that all the expressions of "first" and "second" in the embodiments of the present application are used to distinguish two same name different entities or different parameters. It can be seen that "first" and "second" are only for the convenience of description, and should not be understood as a limitation of the embodiments of the present application. The subsequent embodiments will not be described one by one.

[0051] In an embodiment, referring to Figure 2 The present application provides a video data processing debugging system 100 based on FPGA prototype verification, specifically, the system comprises:

[0052] DDR memory 101, the DDR memory 101 is used for storing data;

[0053] Data generation module 102, the data generation module 102 is used for generating original video data to be tested;

[0054] a compression module 103 for compressing the raw video data to be tested to generate compressed data, and for providing an internal bus interface to access the DDR memory 101;

[0055] a bus interface debug module 104 for providing an external bus interface to access the DDR memory 101;

[0056] a bus arbitration module 105 for selecting the internal bus interface or the external bus interface to communicate with the DDR memory 101, wherein when the compression module 103 generates compressed data, the internal bus interface is selected to connect with the DDR memory 101 to store the compressed data into the DDR memory 101, and when it is needed to verify the video data processing function, the external bus interface is selected to enable an external device to read the compressed data from the DDR memory 101.

[0057] The above-mentioned video data processing debug system based on FPGA prototype verification adds the bus interface debug module to provide the external bus interface to access the DDR memory, and uses the bus arbitration module to select the internal bus interface or the external bus interface to communicate with the DDR memory, so as to realize that when the compression module generates compressed data, the internal bus interface is selected to connect with the DDR memory to store the compressed data into the DDR memory, and when it is needed to verify the video data processing function, the external bus interface is selected to enable an external device to read the compressed data from the DDR memory, thereby providing a simple and convenient way to obtain video compressed data, which will not deteriorate the timing of the project, thereby avoiding wasting the internal RAM resources and realizing convenient and fast access to debug data.

[0058] In some embodiments, please continue to refer to Figure 2 The system further includes a CPU module 106 for configuring registers of the compression module 103 by configuring a bus based on a resolution of the raw video data to be tested.

[0059] In some embodiments, the data generation module 102 provides a built-in digital VGA (Video Graphics Array) interface to generate RGB format data.

[0060] In some embodiments, the compression module 103 is further used for:

[0061] performing format conversion on the raw video data to be tested in RGB format to generate YUV format data, and performing block compression on the YUV format data to generate compressed data.

[0062] In yet another embodiment, please refer toFigure 2 and Figure 3 As shown in FIG. 1, FIG. 2, and FIG. 3, the present application also provides a video data processing debugging method 200 based on FPGA prototype verification, the method comprising:

[0063] Step 201, using DDR memory for storing data;

[0064] Step 202, using a data generation module to generate original video data to be tested;

[0065] Step 203, using a compression module to compress the original video data to be tested to generate compressed data, and providing an internal bus interface for accessing the DDR memory;

[0066] Step 204, using a bus interface debugging module to provide an external bus interface for accessing the DDR memory;

[0067] Step 205, using a bus arbitration module to select the internal bus interface or the external bus interface to be connected with the DDR memory, wherein when the compression module generates compressed data, the internal bus interface is selected to be connected with the DDR memory to store the compressed data into the DDR memory, and when it is needed to verify the video data processing function, the external bus interface is selected to enable an external device to read the compressed data from the DDR memory.

[0068] The above-mentioned video data processing debugging method based on FPGA prototype verification uses an added bus interface debugging module to provide an external bus interface for accessing the DDR memory, and uses a bus arbitration module to select the internal bus interface or the external bus interface to be connected with the DDR memory, thereby realizing that when the compression module generates compressed data, the internal bus interface is selected to be connected with the DDR memory to store the compressed data into the DDR memory, and when it is needed to verify the video data processing function, the external bus interface is selected to enable an external device to read the compressed data from the DDR memory, which provides a simple and convenient way to obtain video compressed data, does not deteriorate the timing of the project, thereby avoiding wasting internal RAM resources, and realizing simple and convenient access to debugging data.

[0069] In some embodiments, the method further comprises:

[0070] Using a CPU module to configure the register of the compression module based on the resolution of the original video data to be tested.

[0071] In some embodiments, step 202 of using a data generation module to generate original video data to be tested comprises:

[0072] Providing a built-in digital VGA interface to generate RGB format data.

[0073] In some embodiments, step 203, compressing the original video data to be tested using a compression module to generate compressed data, includes:

[0074] The original video data to be tested in RGB format is converted to generate YUV format data, and the YUV format data is compressed in blocks to generate compressed data.

[0075] In yet another embodiment, to facilitate understanding of the present invention, please refer to the following... Figure 2 The system shown in the illustration details the video data processing and debugging system based on FPGA prototype verification provided by this invention and its working principle: This invention utilizes the characteristics of the SoC chip architecture to directly read video image compression data from DDR memory using a bus interface debugging module. All necessary memory data can be read at once through a script file. The specific functions of each part are as follows:

[0076] The data generation module provides built-in digital VGA interface data, such as RGB data.

[0077] The CPU module configures the registers of the compression module, such as resolution, through the configuration bus;

[0078] The compression module compresses the video data. First, it converts the RGB data to YUV format data, and then compresses it in blocks to generate compressed data.

[0079] The bus arbitration module is responsible for arbitrating different types of buses, as well as arbitrating the read and write operations of DDR memory.

[0080] DDR memory caches compressed video image data and stores multiple frames of image data as needed.

[0081] The bus interface debugging module is an internal IP of the FPGA. It can be instantiated and used, and it supports the bus interface.

[0082] Please combine Figure 4 As shown, the process of an external PC reading data from DDR memory is as follows:

[0083] Step 1: Download the FPGA project data stream file;

[0084] Step two: Prepare the script file, set the address to be read from DDR memory (i.e., the location to store the compressed data); set the amount of data to be read (either read the entire DDR memory or read as needed); and set the data to be stored in a file.

[0085] Step 3: Run the script file on the PC software to read data from DDR memory through the bus interface debugging module;

[0086] Step 4: Prepare the Golden video compression file on the PC for comparison using the compression module to process the generated compressed data file;

[0087] Step 5: Compare the files to determine if the compression function is working properly and if DDR read / write is working properly.

[0088] The video data processing and debugging system for FPGA prototype verification of the present invention simplifies the video data compression and debugging process, optimizes the project timing, supports higher resolution video compression and debugging, and enables convenient and quick acquisition of debugging data.

[0089] According to another aspect of the present invention, a computer device is provided, which may be a server, and its internal structure diagram is shown below. Figure 5 As shown. The computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database stores data. The network interface communicates with external terminals via a network connection. When the computer program is executed by the processor, it implements the above-described FPGA-based prototype verification video data processing and debugging method. Specifically, the method includes the following steps:

[0090] DDR memory is used for data storage;

[0091] Use the data generation module to generate the original video data to be tested;

[0092] The original video data to be tested is compressed using a compression module to generate compressed data, and an internal bus interface for accessing the DDR memory is provided.

[0093] The bus interface debugging module provides an external bus interface for accessing the DDR memory;

[0094] The bus arbitration module is used to select either the internal bus interface or the external bus interface to connect to the DDR memory. When the compression module generates compressed data, the internal bus interface is selected to connect to the DDR memory so that the compressed data is stored in the DDR memory. When it is necessary to verify the video data processing function, the external bus interface is selected so that the external device can read the compressed data from the DDR memory.

[0095] The aforementioned computer device executes a program that implements a video data processing debugging method based on FPGA prototype verification. It adds a bus interface debugging module to provide an external bus interface for accessing DDR memory. A bus arbitration module selects either the internal or external bus interface to connect to the DDR memory. This allows the internal bus interface to be connected to the DDR memory when the compression module generates compressed data, and the external bus interface to be selected when verifying video data processing functionality, enabling external devices to read compressed data from the DDR memory. This provides a simple and quick way to obtain compressed video data without compromising project timing or wasting internal RAM resources, thus enabling convenient and rapid acquisition of debugging data.

[0096] In some embodiments, the method further includes:

[0097] The CPU module configures the registers of the compression module via the configuration bus based on the resolution of the original video data to be tested.

[0098] In some embodiments, the data generation module generates raw video data to be tested, including:

[0099] It provides a built-in digital VGA interface to generate RGB format data.

[0100] In some embodiments, the original video data to be tested is compressed using a compression module to generate compressed data, including:

[0101] The original video data to be tested in RGB format is converted to generate YUV format data, and the YUV format data is compressed in blocks to generate compressed data.

[0102] According to another aspect of the present invention, a computer-readable storage medium is provided, on which a computer program is stored, wherein when the computer program is executed by a processor, it implements the above-described video data processing and debugging method based on FPGA prototype verification, specifically including the following steps:

[0103] DDR memory is used for data storage;

[0104] Use the data generation module to generate the original video data to be tested;

[0105] The original video data to be tested is compressed using a compression module to generate compressed data, and an internal bus interface for accessing the DDR memory is provided.

[0106] The bus interface debugging module provides an external bus interface for accessing the DDR memory;

[0107] The bus arbitration module is used to select either the internal bus interface or the external bus interface to connect to the DDR memory. When the compression module generates compressed data, the internal bus interface is selected to connect to the DDR memory so that the compressed data is stored in the DDR memory. When it is necessary to verify the video data processing function, the external bus interface is selected so that the external device can read the compressed data from the DDR memory.

[0108] The aforementioned computer-readable storage medium stores a computer program that implements a video data processing debugging method based on FPGA prototype verification. It adds a bus interface debugging module to provide an external bus interface for accessing DDR memory. A bus arbitration module selects either the internal or external bus interface to connect to the DDR memory. This allows the internal bus interface to be connected to the DDR memory when the compression module generates compressed data, and the external bus interface to be selected when verifying video data processing functionality, enabling external devices to read compressed data from the DDR memory. This provides a simple and quick way to obtain compressed video data without compromising project timing or wasting internal RAM resources, thus enabling convenient and fast data acquisition for debugging.

[0109] In some embodiments, the method further includes:

[0110] The CPU module configures the registers of the compression module via the configuration bus based on the resolution of the original video data to be tested.

[0111] In some embodiments, the data generation module generates raw video data to be tested, including:

[0112] It provides a built-in digital VGA interface to generate RGB format data.

[0113] In some embodiments, the original video data to be tested is compressed using a compression module to generate compressed data, including:

[0114] The original video data to be tested in RGB format is converted to generate YUV format data, and the YUV format data is compressed in blocks to generate compressed data.

[0115] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0116] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0117] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A video data processing and debugging system based on FPGA prototype verification, characterized in that, The system includes: DDR memory, the DDR memory being used to store data; A data generation module, which is used to generate the original video data to be tested; A compression module is used to compress the raw video data to be tested to generate compressed data, and to provide an internal bus interface for accessing the DDR memory; A bus interface debugging module, which provides an external bus interface for accessing the DDR memory; A bus arbitration module is provided, which is used to select the internal bus interface or the external bus interface to connect with the DDR memory. When the compression module generates compressed data, the internal bus interface is selected to connect with the DDR memory so that the compressed data is stored in the DDR memory. When it is necessary to verify the video data processing function, the external bus interface is selected so that the external device can read the compressed data from the DDR memory.

2. The video data processing and debugging system based on FPGA prototype verification according to claim 1, characterized in that, The system also includes a CPU module, which is used to configure the registers of the compression module via a configuration bus based on the resolution of the raw video data to be tested.

3. The video data processing and debugging system based on FPGA prototype verification according to claim 1, characterized in that, The data generation module provides a built-in digital VGA interface to generate RGB format data.

4. The video data processing and debugging system based on FPGA prototype verification according to claim 3, characterized in that, The compression module is further used for: The original video data to be tested in RGB format is converted to generate YUV format data, and the YUV format data is compressed in blocks to generate compressed data.

5. A video data processing and debugging method based on FPGA prototype verification, characterized in that, The method includes: DDR memory is used for data storage; Use the data generation module to generate the original video data to be tested; The original video data to be tested is compressed using a compression module to generate compressed data, and an internal bus interface for accessing the DDR memory is provided. The bus interface debugging module provides an external bus interface for accessing the DDR memory; The bus arbitration module is used to select either the internal bus interface or the external bus interface to connect to the DDR memory. When the compression module generates compressed data, the internal bus interface is selected to connect to the DDR memory so that the compressed data is stored in the DDR memory. When it is necessary to verify the video data processing function, the external bus interface is selected so that the external device can read the compressed data from the DDR memory.

6. The video data processing and debugging method based on FPGA prototype verification according to claim 5, characterized in that, The method further includes: The CPU module configures the registers of the compression module via the configuration bus based on the resolution of the original video data to be tested.

7. The video data processing and debugging method based on FPGA prototype verification according to claim 5, characterized in that, The data generation module generates the original video data to be tested, including: It provides a built-in digital VGA interface to generate RGB format data.

8. The video data processing and debugging method based on FPGA prototype verification according to claim 7, characterized in that, The original video data to be tested is compressed using a compression module to generate compressed data, including: The original video data to be tested in RGB format is converted to generate YUV format data, and the YUV format data is compressed in blocks to generate compressed data.

9. A computer device, characterized in that, include: At least one processor; as well as A memory storing a computer program executable in the processor, wherein the processor executes the program to perform the video data processing and debugging method based on FPGA prototyping as described in any one of claims 5-8.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it performs the video data processing and debugging method based on FPGA prototype verification as described in any one of claims 5-8.

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