Optimize garbage collection using logical to physical table seeks

Abstract

The present application relates to optimizing garbage collection using logical-to-physical table searches. A method is described that includes determining, by a memory subsystem, that a garbage collection process is to be performed on a memory device, and in response to determining that the garbage collection process is to be performed, selecting a first candidate stripe for folding into a first target stripe. The method further includes: determining, by the memory subsystem, that a physical-to-logical table stored in the first candidate stripe is unavailable; in response to determining that the physical-to-logical table stored in the first candidate stripe is unavailable, reducing a write command rate that controls a rate at which writes are implemented by the memory subsystem; and performing folding of the first candidate stripe into the first target stripe using a logical-to-physical table.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to International Application No. PCT / CN2021 / 105996 filed on July 13, 2021, which is hereby incorporated by reference. Technical Field

[0003] The present disclosure relates generally to garbage collection, and more particularly to optimizing garbage collection using logical-to-physical (L2P) table searches. Background Art

[0004] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0005] One aspect of the present disclosure provides a method, comprising: determining, by a memory subsystem, that a garbage collection process will be performed on a memory device; in response to determining that the garbage collection process will be performed, selecting, by the memory subsystem, a first candidate block stripe for folding into a first target block stripe; determining, by the memory subsystem, that a physical-to-logical table stored in the first candidate block stripe is unavailable; in response to determining that the physical-to-logical table stored in the first candidate block stripe is unavailable, reducing, by the memory subsystem, a write command rate, the write command rate controlling a rate at which writes are implemented by the memory subsystem; and executing, by the memory subsystem, folding the first candidate block stripe into the first target block stripe using the logical-to-physical table.

[0006] Another aspect of the present disclosure provides a non-transitory computer-readable storage medium, comprising instructions that, when executed by a processing device, cause the processing device to: determine that a garbage collection process is to be performed on a memory device of a memory subsystem; in response to determining that the garbage collection process is to be performed, select a first candidate block stripe for folding into a first target block stripe; determine that a physical-to-logical table stored in the first candidate block stripe is unavailable; in response to determining that the physical-to-logical table stored in the first candidate block stripe is unavailable, reduce a write command rate, the write command rate controlling a rate at which writes are implemented by the memory subsystem; and perform folding the first candidate block stripe into the first target block stripe using the logical-to-physical table.

[0007] Another aspect of the present disclosure provides a system comprising: a memory device; and a processing device operatively coupled to the memory device to: determine that a physical-to-logical table stored in a first candidate stripe is unavailable, wherein the first candidate stripe is to be folded into a first target stripe; in response to determining that the physical-to-logical table stored in the first candidate stripe is unavailable, reduce a write command rate, the write command rate controlling a rate at which writes are implemented by the memory subsystem; and perform folding the first candidate stripe into the first target stripe using the logical-to-physical table. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure will be more fully understood from the detailed description provided below and the accompanying drawings of various embodiments of the present disclosure. However, the drawings should not be considered to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0009] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is described.

[0010] Figure 2 A flowchart of an example method for performing an optimized garbage collection process using a logical-to-physical (L2P) table and / or a physical-to-logical (P2L) table according to some embodiments of the present disclosure is provided.

[0011] Figure 3A An example L2P table including a set of L2P entries and a current position / location during an L2P search is shown according to some embodiments of the present disclosure.

[0012] Figure 3B An example L2P table and updated location / position during L2P search according to some embodiments of the present disclosure are shown.

[0013] Figure 4 Alternating processing of an L2P candidate slice and several P2L candidate slices according to some embodiments of the present disclosure is shown.

[0014] Figure 5 Flowchart of another example method for performing an optimized garbage collection process using an L2P table and / or a P2L table according to some embodiments of the present disclosure.

[0015] Figure 6 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0016] Aspects of the present disclosure relate to optimizing garbage collection using logical-to-physical (L2P) table searches in a memory subsystem. The memory subsystem may be a storage device, a memory module, or a mixture of a storage device and a memory module. Figure 1 Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more components, such as memory devices that store data. The host system may provide data to be stored at the memory subsystem and may request data to be retrieved from the memory subsystem.

[0017] The memory device may be a non-volatile memory device. A non-volatile memory device is a package of one or more dies. An example of a non-volatile memory device is a NAND memory device. Figure 1 Other examples of non-volatile memory devices are described. The die in a package may be assigned to one or more channels for communicating with a memory subsystem controller. Each die may be composed of one or more planes. Planes may be grouped into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND memory devices), each plane is composed of a set of physical blocks, which are groups of memory cells used to store data. A cell is an electronic circuit that stores information.

[0018] Depending on the cell type, a cell can store one or more bits of binary information and have various logical states related to the number of bits being stored. The logical states can be represented by binary values ​​such as "0" and "1" or a combination of these values. There are various types of cells such as single-level cells (SLC), multi-level cells (MLC), triple-level cells (TLC), and quad-level cells (QLC). For example, an SLC can store one bit of information and have two logical states.

[0019] The memory subsystem may be composed of various layers / tiers, including an operating system layer, a file system layer, a flash translation layer (FTL), and a NAND flash layer. The FTL is a software layer between the file system layer and the NAND flash layer, allowing the operating system layer to read and write to the NAND flash layer in the same manner as a disk drive. In particular, the FTL provides virtual to physical address translation, wear leveling, and garbage collection for the management of the NAND flash layer. The proper operation of the memory subsystem depends on these services. For example, each write or rewrite performed by the FTL associated with the NAND flash layer requires a free conversion unit. In particular, even if the FTL is trying to rewrite data currently stored in a specific conversion unit of the NAND flash layer, the FTL will not write / rewrite the data to this specific conversion unit, but will use the free conversion unit to store the data. This configuration requires free conversion units to be available at any time in the NAND flash layer. Garbage collection helps make free conversion units available in the NAND flash layer by identifying invalid conversion units in blocks / block stripes.

[0020] For example, the garbage collector may use a valid page (VP) bitmap that records / tracks valid translation units for each stripe and is stored outside the corresponding stripe (e.g., a die may include 500 stripes and 485 stripes are dedicated to user data, while the 15 remaining stripes are dedicated to the VP bitmap of the 485 user data stripes). The garbage collector identifies all valid translation units in the corresponding stripe through the VP bitmap and folds / copies these valid translation units into the target stripe. Thus, the previous stripe no longer has valid translation units and can be completely erased and used for future program / write operations.

[0021] In another example, the garbage collector may use a physical to logical (P2L) table that records / tracks the logical address of each translation unit of the corresponding stripe and is stored within the corresponding stripe. Specifically, the garbage collector determines the logical address of each translation unit of the stripe through the P2L table and uses the logical address to obtain the physical address from the L2P table. The physical address retrieved from the L2P table is compared to the original physical address used with the P2L table to determine a match. When a match is identified, the known translation unit is valid and is folded / copied to another / target stripe.

[0022] If the memory subsystem uses a P2L table for garbage collection and the memory subsystem also uses a multi-cursor strategy that separates host data (e.g., user data from the host system), garbage collection data (e.g., user data being folded / copied into the target stripe), and system data (e.g., L2P table) into different stripes, then there is a non-negligible possibility of a deadlock situation. In particular, since the multi-cursor strategy separates host data, garbage collection data, and system data into different stripes, there may be three stripes being written / programmed at any given time, and each will require free conversion units to perform these write / program operations. In this case, due to physical problems with the NAND flash layer, the P2L table may not be correctly read from the NAND flash layer (e.g., uncorrectable even with error correction code (ECC)), which will prevent garbage collection from supplying more free conversion units. This may occur because the P2L table (possibly together with metadata) is stored in a TLC block along with the user data, which has much lower stability than an SLC block and may result in data corruption.

[0023] In order to solve the P2L damage, a search based on the L2P table can be used. Each entry in the L2P table contains or otherwise references a physical address, including one or more of a block number / identifier, a page number / identifier, a conversion unit number / identifier, and a plane number / identifier. In the search based on the L2P table, the block, page, and conversion unit number of each entry in the L2P table are compared with the block, page, and conversion unit number of the conversion unit in the candidate block stripe to determine whether there is a match. If the block, page, and conversion unit number of the entry in the L2P table match the block, page, and conversion unit number of the conversion unit of the candidate block stripe, then this identifies the valid conversion unit that should be folded / copied to the block stripe of the target block stripe before the candidate block stripe can be erased. Although this technology can accurately identify valid and invalid conversion units in the candidate block stripe, this process requires a large amount of resources (e.g., time and processing power) because the L2P table must be repeatedly parsed by the corresponding address / number comparison. Specifically, for a gigabyte (GB) drive, a search based on the L2P table may require more than 512 seconds to complete the folding of a single block stripe. In contrast, garbage collection using the P2L table (when the P2L table is not corrupted) for a 2GB drive will take approximately 5 seconds to complete the collapse of a single block stripe. This extreme delay using L2P table-based searches can result in command timeouts (i.e., host commands are not implemented during the timeout period), blue or black screen events, or another serious error.

[0024] Aspects of the present disclosure address the above and other deficiencies by performing one or more of the following operations: (1) limiting write speed to TLC stripes, including potentially suspending write requests when the number of free stripes is below a threshold, so that free space will be consumed less quickly while waiting for more space to be freed using garbage collection; (2) modifying garbage collection strategies to potentially free up space more quickly, so that write speeds can be increased; and (3) periodically recording the current position / entry in the L2P table while performing an L2P table-based search for a particular stripe, so that the L2P table-based search for this stripe can be intermittently paused and later resumed to split the heavy L2P table-based search cost over time while using other stripes to perform more resource-efficient P2L-based garbage collection. Thus, the above adjustments to the memory subsystem allow the use of L2P table-based searches in garbage collection of stripes when the P2L table is corrupted for these stripes, while avoiding possible error conditions.

[0025] Figure 1 An example computing system 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0026] The memory subsystem 110 may be a storage device, a memory module, or a mixture of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controllers (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0027] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, automobile, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0028] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0029] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, writing data to the memory subsystem 110 and reading data from the memory subsystem 110.

[0030] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Small Computer System Interface (SCSI), a Double Data Rate (DDR) memory bus, a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface may provide an interface for transferring control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1 Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0031] The memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0032] Some examples of non-volatile memory devices (e.g., memory device 130) include non-and (NAND) type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in body resistance. In addition, compared to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0033] Although nonvolatile memory devices such as NAND-type memory (e.g., 2D NAND, 3D NAND) and 3D cross-point nonvolatile memory cell arrays are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selected memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), non-OR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0034] The memory subsystem controller 115 (or, for simplicity, the controller 115) may communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data and other such operations at the memory device 130 (e.g., in response to commands dispatched by the controller 115 on a command bus). The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

[0035] The memory subsystem controller 115 may include a processing device 117 (processor) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0036] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been illustrated as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host, or by a processor or controller separate from the memory subsystem 110).

[0037] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130 and / or the memory device 140. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address conversion between logical addresses (e.g., logical block addresses (LBA), name space) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130 and / or the memory device 140, and convert responses associated with the memory device 130 and / or the memory device 140 into information for the host system 120.

[0038] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0039] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) can externally manage the memory device 130 (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., the local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0040] The memory subsystem 110 includes a garbage collection manager 113 that can adjust one or more parameters of the memory subsystem 110 to optimize garbage collection using logical to physical (L2P) table searches. In some embodiments, the controller 115 includes at least a portion of the garbage collection manager 113. For example, the controller 115 may include a processor 117 (processing device) configured to execute instructions stored in a local memory 119 for performing the operations described herein. In some embodiments, the garbage collection manager 113 is part of the host system 110, an application, or an operating system. Additional details regarding the operation of the garbage collection manager 113 are described below.

[0041] Figure 2 Flowchart of an example method 200 for performing an optimized garbage collection process using an L2P table and / or a P2L table according to some embodiments of the present disclosure. The method 200 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 200 is performed by Figure 1 The garbage collection manager 113 of the embodiment of the present invention is executed. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0042] like Figure 2As shown in FIG. 2 , method 200 begins at operation 202, where a processing device determines whether a garbage collection process will be performed in memory subsystem 110 to free one or more stripes in memory subsystem 110. As described above, memory subsystem 110 may perform write / program operations only on idle stripes (e.g., stripes that are erased and do not store data). Therefore, memory subsystem 110 should ensure that idle stripes are available at any time to accommodate programming operations (e.g., programming operations corresponding to write requests from host system 120 or programming operations corresponding to internally generated write requests). In one embodiment, the processing device determines whether a garbage collection process will be performed based on a plurality of idle stripes in memory subsystem 110 (e.g., stripes that do not have any conversion units that are being used to store data). For example, the processing device may compare the number of idle stripes in memory device 130 / 140 with a garbage collection threshold. The garbage collection threshold may be a static value (e.g., fifteen stripes or five percent of the total number of stripes in memory device 130 / 140) or may be dynamically adjusted. When the processing device determines that the number of idle stripes in the memory subsystem 110 meets the garbage collection threshold (e.g., the number of idle stripes in the memory subsystem 110 is greater than or equal to the garbage collection threshold), the processing device determines that there is no need to perform a garbage collection process because there are enough idle stripes to meet the write request requirements. In this case, the method 200 remains at operation 202 to continue to determine whether a garbage collection process will be performed. When the processing device determines that the number of idle stripes in the memory subsystem 110 does not meet the garbage collection threshold (e.g., the number of idle stripes in the memory subsystem 110 is less than the garbage collection threshold), the processing device determines that a garbage collection process will be performed and the method 200 moves to operation 204. As described above, the garbage collection process locates candidate stripes to be released / erased and checks the candidate stripes for folding / copying valid conversion units to the target stripes. The candidate stripes may be selected based on a garbage collection policy. For example, the garbage collection policy may cause the processing device to select a candidate stripe based in part or in whole on a valid conversion unit count (VTC), which indicates how many valid conversion units are present in the stripe. In this example, the processing device selects the stripe as the candidate stripe with the highest VTC or a VTC that satisfies a threshold. As will be described below, the processing device may use other garbage collection strategies.

[0043] At operation 204, the processing device determines whether an L2P table-based search (sometimes referred to as an L2P search mode) is required to perform garbage collection on the candidate stripe. In particular, the memory subsystem 110 may ideally utilize a P2L table for determining valid conversion units in the candidate stripe so that folding / duplication can be performed. However, the P2L table may be damaged while being stored in the candidate stripe (e.g., stored in a TLC block of the memory device 130 / 140 along with user data). Upon determining that the P2L table of the candidate stripe is damaged and unusable, the processing device determines that an L2P search mode is required for performing a garbage collection process associated with the candidate stripe. Therefore, when a P2L table-based search is not available for the candidate stripe, an L2P table-based search utilizing an L2P table shared across all stripes of the memory device 130 / 140 is a backup search procedure. In some cases, the P2L table is stored with an error correction code (ECC) so that a defined number of bit errors can be corrected in the P2L table while stored in the memory device 130 / 140. Once the number of bit errors for the P2L table exceeds the correction capability of the ECC, the processing device may determine that the P2L table is unusable / corrupted, such that an L2P table-based search is required. In response to determining that performing a garbage collection process on the candidate stripe does not require an L2P table-based search (e.g., the P2L table of the candidate stripe is not corrupted and can be read correctly), the method 200 moves to operation 206.

[0044] At operation 206, the processing device performs garbage collection on the candidate stripe using the P2L table of the candidate stripe. Specifically, for each conversion unit in the candidate stripe, the processing device uses the physical address of the conversion unit to locate the logical address using the P2L table. Thereafter, the processing device uses the determined logical address to locate the physical address using the L2P table. If the physical address determined using the L2P table matches the physical address of the conversion unit, the processing device determines that the data of the conversion unit is valid and is folded into another / target stripe before erasing / releasing the candidate stripe. Otherwise, if the physical address determined using the L2P table does not match the physical address of the conversion unit, the processing device determines that the data in the conversion unit is invalid and is not folded into another / target stripe. Therefore, during the garbage collection process, the processing device identifies all valid conversion units in the candidate stripe and folds / copies these valid conversion units into the target stripe. Therefore, the processing device can now erase the entire candidate stripe because all the data of the valid conversion units have been moved / copied to the target stripe. This erased candidate stripe is now free for subsequent write / rewrite operations. After completing the folding of the candidate stripes using the P2L table based search, the method 200 returns to operation 202 to determine whether a garbage collection process is still needed. If garbage collection is to be performed continuously, a new candidate stripe is selected according to the garbage collection policy.

[0045] Although described above as a P2L table-based search and an L2P table-based search, the P2L table-based search still relies on the use of the L2P table. Therefore, the P2L table-based search is a page validity search that relies on the P2L table and other tables (e.g., the L2P table), while the L2P table-based search is a page validity search that relies on the L2P table but does not involve or otherwise rely on any other mapping or validity table (including the P2L table or the VP bitmap).

[0046] Returning to operation 204, in response to determining that performing a garbage collection process on the candidate stripe does not require an L2P table-based search (e.g., the P2L table of the candidate stripe is corrupted / unavailable and cannot be correctly read), the method 200 moves to operation 208. At operation 208, the processing device determines whether the number of idle stripes in the memory subsystem 110 meets a minimum threshold. The minimum threshold is less than the garbage collection threshold described above in connection with operation 202. In particular, the garbage collection threshold indicates when the number of idle stripes is low enough to warrant performing a garbage collection process, and the minimum threshold indicates when the number of idle stripes is low enough that other possible corrective actions should be performed in addition to garbage collection, as will be described in more detail below. In response to determining that the number of idle stripes in the memory subsystem 110 does not meet the minimum threshold (e.g., the number of idle stripes in the memory subsystem 110 is less than the minimum threshold), the method 200 moves to operation 210.

[0047] At operation 210, the processing device reduces the write command rate in the memory subsystem 110. In particular, the memory subsystem 110 may be configured in conjunction with the host system 120 to detect a timeout when a confirmation of completing a host write request is not received by the host system 120 within a timeout period. For example, the timeout period may be eight seconds. In this configuration, the processing device may reduce the write command rate by delaying the completion / implementation of the host write request / command by a delay period that is less than the timeout period. For example, the processing device may artificially delay the implementation of the write request from the host system 120 by five seconds (i.e., the delay period is five seconds). This restriction on the implementation of write memory requests allows more time to release additional blocks to meet the minimum threshold via the garbage collection process. In some embodiments, host write requests / commands and internally generated write requests / commands are processed separately. For example, the processing device may limit / delay host write requests by a host delay period and limit / delay internally generated write requests by an internal delay period. In this example, the host delay period and the internal delay period are independently set (i.e., the host delay period and the internal delay period may not be equal). In one embodiment, the processing device may abort all internally generated write requests while still implementing host write requests (although possibly based on host latency cycles). In some embodiments, the processing device aborts all write requests until the number of idle stripes in the memory subsystem 110 meets a minimum threshold (e.g., when there are no idle stripes in the memory subsystem 110, the processing device does not implement any write requests, regardless of their source / association). Although the processing device may adjust the processing of write requests, this adjustment does not change the processing of read requests and the memory subsystem 110 still implements read requests because the implementation of these requests is not affected by the number of idle stripes in the memory subsystem 110.

[0048] In some embodiments, in response to determining that the write command rate is already at a sufficiently low level (e.g., the delay period is almost equal to or otherwise almost corresponds to the timeout period based on the previous iteration of operation 210), the processing device may determine not to further reduce the write command rate at operation 210. Specifically, at operation 210, the processing device first determines the current delay period and compares it to the timeout period or another threshold to determine whether the write command rate needs to be further reduced or can otherwise be further reduced.

[0049] Returning to operation 208, in response to determining that the number of idle stripes in the memory subsystem 110 meets the minimum threshold (e.g., the number of idle stripes in the memory subsystem 110 is greater than or equal to the minimum threshold), the method 200 moves to operation 212. At operation 212, the processing device increases the write command rate in the memory subsystem 110. In particular, the processing device may reduce the latency period while ensuring that the latency period is greater than or equal to zero. For example, when the memory subsystem 110 is new, the latency period is set to zero because little or no data is written to the memory device 130 / 140, so that there are sufficient idle stripes. However, as time passes and the stripes are used to store data, the processing device may reduce the write command rate by increasing the latency period at operation 210. As the garbage collection process continues to be performed, the processing device may determine that the latency period can be relaxed / reduced so that the write command rate can be increased. Therefore, the processing device may increase the write command rate to possibly return the latency period and the subsequent write command rate to their original settings (e.g., a latency period of zero and a maximum write command rate). In some embodiments, the extent to which the delay period is increased at operation 210 and / or decreased at operation 212 may be related to the number of idle stripes. As described above, the adjustment delay period may be related to each of a host delay period (corresponding to a realization / processing delay of a host write request / command) and an internal delay period (corresponding to a realization / processing delay of an internally generated write request / command).

[0050] In some embodiments, in response to determining that the write command rate is already at a sufficiently high level (e.g., the delay period is zero), the processing device may determine not to further increase the write command rate by further reducing the delay period at operation 210. Specifically, at operation 210, the processing device first determines the current delay period and compares it to a threshold to determine whether the write command rate needs to be further reduced or can otherwise be further reduced.

[0051] After operation 210 or operation 212, method 200 moves to operation 214. At operation 214, the processing device determines whether to use an aggressive garbage collection strategy to govern the operation of the garbage collection process. In particular, the garbage collection process selects candidate stripes for processing and folding into target stripes. When the P2L table of the candidate stripe is corrupted, the processing device employs an L2P table-based search to identify valid translation units for folding. However, as described above, a pure L2P table-based search for identifying valid translation units may require a large amount of resources (e.g., consume a large amount of processing resources and time). A conservative garbage collection strategy may require that the processing device complete the processing of the current candidate stripe before a new candidate stripe can be selected for processing. In contrast, an aggressive garbage collection strategy may allow the processing device to pause or completely abandon / suspend the processing of the current candidate stripe in order to process a new candidate stripe when (1) an L2P table-based search is required and (2) the number of idle stripes is below a minimum threshold. Therefore, these factors can be used to determine whether to use an aggressive garbage collection strategy. For example, using an aggressive garbage collection strategy, when the current candidate stripe requires the use of an L2P table-based search and the number of idle stripes is below a minimum threshold, the processing device may temporarily suspend processing of the current candidate stripe in order to process a new candidate stripe. In some cases, the processing device may select a new candidate stripe using the same criteria and / or process used to select a previous candidate stripe with a corrupted P2L table. Because P2L corruption is not a likely event, it is unlikely that another candidate stripe with a corrupted P2L table will be selected. However, the processing device may select an aggressive garbage collection strategy that considers additional factors when selecting a new candidate stripe, including (1) a number of program and erase cycles for the stripe, (2) a total read count for the stripe, and (3) the most recently programmed stripe. For example, a large number of program and erase cycles for a stripe may indicate that the stripe is old (i.e., has been written and read for a long time relative to other stripes), which may indicate that the stripe may contain more errors, or be susceptible to more errors, than stripes with a smaller number of program and erase cycles. Relative to a high total read count for the stripe, this may indicate high read disturb for the stripe, which may indicate that the stripe may contain more errors, or be susceptible to more errors, than a stripe with a lower total read count for the stripe. In some embodiments, the total read count for the stripe is the number of read operations on the stripe since the previous write operation, which may clear any disturb effects. Relative to the newest recently programmed stripe, this may indicate that low slow charge loss effects are lower than older programmed stripes indicating a lower number of errors. The garbage collection process may use these updated / additional factors to improve the chances of selecting a new candidate stripe that does not require a search based on the L2P table to perform a fold. Therefore, at operation 214, the processing device determines whether an aggressive garbage collection strategy is warranted.When the processing device determines the need to perform an L2P table based search on the current candidate stripe and / or the number of free stripes is below a minimum threshold, the processing device may determine to use an aggressive garbage collection strategy and the method 200 moves to operation 218. Otherwise, the method 200 moves to operation 216.

[0052] At operation 216, the processing device performs a garbage collection process on the candidate stripes using an L2P table-based search to fold the candidate stripes into a target stripe. Specifically, each entry in the L2P table includes a physical address or otherwise references a physical address, including one or more of a block number / identifier, a page number / identifier, a conversion unit number / identifier, and a plane number / identifier. In the L2P table-based search, the block, page, and conversion unit number of each entry in the L2P table are compared with the block, page, and conversion unit number of the conversion unit in the candidate stripe to determine whether there is a match. If the block, page, and conversion unit number of the entry in the L2P table matches the block, page, and conversion unit number of the conversion unit of the candidate stripe, then this identifies the valid conversion unit within the stripe that should be folded / copied before the candidate stripe can be erased. This process continues until each conversion unit is identified as being either valid or invalid, so that the valid conversion unit can be folded / copied into the target stripe. After folding the valid conversion units of the candidate stripe into the target stripe, the processing device erases the candidate stripe to free up the stripe for write / rewrite operations.

[0053] As discussed above, when the processing device determines to use an aggressive garbage collection strategy at operation 214, method 200 moves to operation 218. At operation 218, the processing device performs garbage collection on the candidate stripes using the aggressive garbage collection strategy. In particular, the aggressive garbage collection strategy may allow the processing device to (1) suspend or abandon the L2P table-based search for the current candidate stripe, (2) select a new candidate stripe for the garbage collection process, and / or (3) change the method of selecting a new candidate stripe. That is, as described above, the L2P table-based search includes traversing each entry in the L2P table to determine a match with a conversion unit in the candidate stripe. However, since this L2P table-based search may take a long time to complete, the processing device may periodically save an identifier of the current entry in the L2P table (for example, save the logical address of the current entry or save the time that has passed since the start of the L2P table-based search, which can be used to derive the current entry in the L2P table), so that the processing device can suspend folding the current candidate block strip into the target block strip through the L2P table search and instead select a new candidate block strip for folding. Figure 3A The example L2P table 300 is shown, including a set of L2P entries 3021 to 302 X and the current location / position 304 during the search process based on the L2P table. L2P entries 3021 to 302 XEach of the L2P entry 3021 corresponds to a logical address (e.g., L2P entry 3022 corresponds to logical address 0000 0000, L2P entry 3023 corresponds to logical address 0000 0001, L2P entry 3024 corresponds to logical address 0000 0010, etc.), and includes a physical address or otherwise references a physical address, including one or more of a block number / identifier, a page number / identifier, a translation unit number / identifier, and a plane number / identifier. Figure 3A The current position / location 304 in the L2P search process is shown when the L2P search process is started. In this case, the current position / location 304 is the L2P entry 3021 in the L2P table 300 because the L2P table-based search iteratively moves through the L2P entries 302 in the L2P table 300 and the L2P search process has just begun. Figure 3B Shows the L2P search process after some time period. Figure 3B As shown in FIG. 1 , the current location / position 304 is now the L2P entry 302 in the L2P table 300. N Specifically, the L2P table-based search progresses during the time period and the L2P table-based search is now checking L2P entry 302. N . The processing device may store the current position / location 304 according to different storage strategies. For example, the processing device may store the current position / location 304 after each movement through the L2P entry 302 (that is, the processing device saves (1) the logical address / index of each L2P entry 302 when it is being processed or has completed processing, or (2) the elapsed time corresponding to when the new L2P entry 302 is being processed or has completed processing). In another example, the processing device may store the current position / location 304 at a specified interval (for example, the processing device saves (1) the logical address / index of the L2P entry 302 after ten L2P entries 302 have completed processing or (2) the elapsed time corresponding to when ten L2P entries 302 have completed processing). In yet another example, in response to determining to suspend garbage collection of the current candidate block strip and instead select a new candidate block strip for performing garbage collection, the processing device stores / records the current position / location 304. In some embodiments, the processing device stores not only the location / position within the L2P table 300 but also the current location / position of the conversion unit processed by the L2P table based search.

[0054] As described above, the processing device may save the current L2P entry 302 in the L2P table 300 or the current elapsed time of the L2P table-based search. In either case, the processing device may accurately determine the amount of resources (e.g., time) dedicated to performing garbage collection on the current candidate stripe. In addition, these two indicators (e.g., location and time) will allow the processing device to continue the L2P table-based search even during interruption events where progress of the L2P table-based search would be lost. These interruption events include power cycling of the memory subsystem 110, which would otherwise cause the L2P table-based search to be completely restarted from the beginning.

[0055] At operation 220 , the processing device determines whether the L2P table-based search is complete for the candidate stripe (sometimes referred to as the L2P candidate stripe). In response to the processing device determining that the L2P table-based search is complete for the candidate stripe, method 200 moves to operation 224 .

[0056] At operation 224, the processing device determines whether garbage collection of the L2P candidate stripe is suspended and remains incomplete. Specifically, if the processing device determines that there is no L2P candidate stripe for which garbage collection has been started but has not yet been completed, the method 200 moves to operation 202. In contrast, if the L2P table-based search is suspended for the previous candidate stripe and remains incomplete (e.g., the saved current position of the L2P table-based search is not the last entry in the L2P table), the method 200 moves to operation 226.

[0057] At operation 226, the processing device sets the paused / incomplete L2P candidate stripe as the current candidate stripe. Specifically, the processing device selects the paused / incomplete L2P candidate stripe as the current candidate stripe so that garbage collection using L2P table-based search can be started / resume. After operation 226, the method 200 moves to operation 218 to resume garbage collection for the paused / incomplete L2P candidate stripe. In this manner, the method 200 continues to process the L2P candidate stripe until garbage collection using L2P table-based search is completed, while still allowing P2L table-based search of other stripes to intervene.

[0058] Returning to operation 220, when the processing device determines that the L2P table-based search for the candidate stripe is incomplete, method 200 moves to operation 222. At operation 222, the processing device selects a new candidate stripe and performs garbage collection on the new candidate stripe. In particular, the processing device pauses the processing of the L2P candidate stripe and uses the aggressive garbage collection strategy described above to select a new candidate stripe. In particular, the aggressive garbage collection strategy allows for pausing and / or suspending the processing of the L2P candidate stripe, which requires an L2P table-based search, and optionally considers several factors when selecting a new candidate stripe, including (1) a number of program and erase cycles for the stripe, (2) a total read count for the stripe, and (3) the latest most recently programmed stripe. The garbage collection process can use these updated / additional factors to increase the chances of selecting a new candidate stripe that does not require an L2P table-based search to perform a fold. When the selected new candidate stripe allows the use of a P2L-based search, the processing device completes garbage collection / folding operations associated with the new candidate stripe (e.g., in a manner similar to or identical to operation 206) before returning to operation 218 to continue processing the suspended L2P candidate stripe. In some embodiments, operation 222 may operate in a manner similar to or identical to operations 204 through 226. In particular, when the new candidate stripe requires an L2P table-based search, the processing device may recursively perform operations 204 through 226 on the new candidate stripe. In this manner, the processing device may fold several stripes based on a P2L table-based search while still acting to complete a garbage collection / folding process associated with one or more L2P candidate stripes.

[0059] Figure 4The alternating processing of the L2P candidate stripe 402 is shown along with several P2L candidate stripes 4041 to 4043. In particular, the memory subsystem 110 processes the L2P candidate stripe 402 during garbage collection time period 1 using an L2P table-based search. However, before the memory subsystem 110 can complete the L2P table-based search, the memory subsystem 110 processes the P2L candidate stripe 4041 during garbage collection time period 2 using a P2L table-based search. After completing the folding / garbage collection associated with the P2L candidate stripe 4041, the memory subsystem 110 resumes processing the L2P candidate stripe 402 during garbage collection time period 3 using an L2P table-based search. In particular, the memory subsystem 110 resumes the L2P table-based search from the previous location / entry saved during garbage collection time period 1. Before the memory subsystem 110 can complete the L2P table-based search, the memory subsystem 110 processes the P2L candidate stripe 4042 during garbage collection time period 4 using the P2L table-based search. After completing garbage collection associated with the P2L candidate stripe 4042, the memory subsystem 110 resumes processing the L2P candidate stripe 402 during garbage collection time period 5 using the L2P table-based search. Again, the memory subsystem 110 resumes the L2P table-based search from the previous location / entry saved during garbage collection time period 3. Before the memory subsystem 110 can complete the L2P table-based search, the memory subsystem 110 processes the P2L candidate stripe 4043 during garbage collection time period 6 using the P2L table-based search. After completing garbage collection associated with the P2L candidate stripe 4043, the memory subsystem 110 resumes processing the L2P candidate stripe 402 during garbage collection time period 7 using the L2P table-based search. After garbage collection time period 7, the memory subsystem 110 completes garbage collection associated with the L2P candidate stripe 402. Therefore, the memory subsystem 110 processes the L2P candidate stripe 402 and several P2L candidate stripes 404 intermittently to avoid deadlock when performing only L2P table-based garbage collection. Therefore, as shown and described, the processing device can avoid serious errors (e.g., serious delays in the memory subsystem 110 caused by L2P table-based searches) while still processing stripes that are unavailable for time / resource intensive search modes (e.g., P2L table-based searches).

[0060] Although the adjustment of the write command rate and the garbage collection policy is described in a particular order, in some embodiments, the adjustment may be performed in a different order, or only one of the adjustments may be performed. For example, in some embodiments, the memory subsystem 110 may only adjust the garbage collection policy in response to a low number of idle stripes, or the memory subsystem 110 may adjust the garbage collection policy before adjusting the write command rate in response to a low number of idle stripes. Therefore, the adjustment of the write command rate and the garbage collection policy are two options that can be used separately or in conjunction.

[0061] Figure 5 Flowchart of another example method 500 for performing an optimized garbage collection process using an L2P table and / or a P2L table according to some embodiments of the present disclosure. The method 500 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 500 is performed by Figure 1 The garbage collection manager 113 of the embodiment of the present invention is executed. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0062] like Figure 5 , method 500 begins at operation 502, with a processing device determining whether a garbage collection process is to be performed on a memory device 130 / 140 to free one or more stripes in a memory subsystem 110. In one embodiment, the processing device determines whether a garbage collection process is to be performed based on a number of idle stripes (e.g., stripes that do not have any conversion units being used to store data) in the memory subsystem 110 (e.g., in the memory device 130 / 140). For example, the processing device may compare the number of idle stripes in the memory device 130 / 140 to a garbage collection threshold.

[0063] At operation 504, in response to determining that a garbage collection process is to be performed, the processing device selects a candidate stripe for folding into a target stripe. In particular, the processing device may utilize a garbage collection policy to determine the candidate stripes for the garbage collection process. Folding the candidate stripes into the target stripe includes copying valid pages from the candidate stripe into pages of the target stripe.

[0064] At operation 506, the processing device determines whether the P2L table stored in the candidate stripe is available. In particular, the memory subsystem 110 may ideally utilize the P2L table for determining valid conversion units in the candidate stripe so that folding / duplication can be performed. However, the P2L table may be corrupted while being stored in the candidate stripe (e.g., stored in a TLC block of the memory device 130 / 140 with user data). Upon determining that the P2L table of the candidate stripe is corrupted and unusable, the processing device determines that the P2L table is unusable and that an L2P search mode is required for performing a garbage collection process associated with the candidate stripe.

[0065] At operation 508, in response to determining that the P2L table stored in the candidate stripe is unavailable, the processing device reduces the write command rate, which controls the rate at which writes are implemented by the memory subsystem 110. In one embodiment, the processing device may reduce the write command rate by delaying the completion / implementation of host write requests / commands by a delay period that is less than the timeout period of the memory subsystem 110. For example, the processing device may artificially delay the implementation of write requests from the host system 120 by five seconds (i.e., the delay period is five seconds). This restriction on the implementation of write memory requests allows more time to free up additional stripes to meet the minimum threshold via the garbage collection process.

[0066] At operation 510, the processing device performs folding the candidate stripes into the target stripe using the L2P table. Specifically, each entry in the L2P table includes a physical address or otherwise references a physical address, including one or more of a block number / identifier, a page number / identifier, a conversion unit number / identifier, and a plane number / identifier. In a search based on the L2P table, the block, page, and conversion unit number of each entry in the L2P table are compared with the block, page, and conversion unit number of the conversion unit in the candidate stripe to determine whether there is a match. If the block, page, and conversion unit number of the entry in the L2P table matches the block, page, and conversion unit number of the conversion unit of the candidate stripe, then this identifies the valid conversion unit within the stripe that should be folded / copied before the candidate stripe can be erased. This process continues until each conversion unit is identified as being either valid or invalid, so that the valid conversion unit can be folded / copied into the target stripe. After folding the valid conversion units of the candidate stripe into the target stripe, the processing device erases the candidate stripe to release this stripe for write / rewrite operations.

[0067] Figure 6 An example machine illustrating a computer system 600 within which a set of instructions may be executed for causing the machine to perform any one or more of the methodologies discussed herein. In some embodiments, the computer system 600 may correspond to a computer system that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1A host system (eg, a memory subsystem 110) of Figure 1 host system 120), or can be used to perform operations of the controller (e.g., execute an operating system to perform operations corresponding to Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or in the capacity of a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0068] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Furthermore, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or collectively execute a set (or multiple sets of instructions) to perform any one or more of the methodologies discussed herein.

[0069] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0070] The processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets or a processor that implements a combination of instruction sets. The processing device 602 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. The computer system 600 may further include a network interface device 608 to communicate on a network 620.

[0071] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 626 or software embodying any one or more of the methodologies or functions described herein. The instructions 626 may also reside, completely or at least partially, within the main memory 604 and / or within the processing device 602 during execution thereof by the computer system 600, the main memory 604 and the processing device 602 also constituting machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may correspond to Figure 1 Memory subsystem 110.

[0072] In one embodiment, instructions 626 include instructions for implementing a method corresponding to a garbage collection manager (e.g., Figure 1 113) of the garbage collection manager 113). Although the machine-readable storage medium 624 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executed by a machine and causing the machine to perform any one or more of the methods of the present disclosure. The term "machine-readable storage medium" should therefore be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0073] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are a means for those skilled in the art of data processing to most effectively convey the substance of their work to others skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations that lead to a desired result. The operations are those that require physical manipulation of physical quantities. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. At times, it has proven convenient, primarily for general reasons, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0074] It should be borne in mind, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within a computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0075] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for a given purpose, or it may include a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. For example, a computer system or other data processing system (e.g., controller 115) may perform computer-implemented methods 200 and 500 in response to its processor executing a computer program (e.g., a sequence of instructions) contained in a memory or other non-transitory machine-readable storage medium. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magnetic optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each of which is connected to a computer system bus.

[0076] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. The structures of a variety of these systems will be presented as set forth in the description below. In addition, the present disclosure is described without reference to any particular programming language. It should be appreciated that the teachings of the present disclosure described herein may be implemented using a variety of programming languages.

[0077] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0078] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the present description and drawings should be viewed in an illustrative sense rather than a restrictive sense.

Claims

1. A method comprising: determining, by the memory subsystem, that a garbage collection process will be performed on the memory device; In response to determining that the garbage collection process is to be performed, selecting, by the memory subsystem, a first candidate stripe for folding into a first target stripe; determining, by the memory subsystem, that the physical-to-logical table stored in the first candidate stripe is unavailable; In response to determining that the physical-to-logical table stored in the first candidate stripe is unavailable, reducing, by the memory subsystem, a write command rate, the write command rate controlling a rate at which the memory subsystem implements writes; and Collapsing the first candidate stripe into the first target stripe using a logical-to-physical table is performed by the memory subsystem.

2. The method of claim 1 , wherein determining that the garbage collection process is to be performed on the memory device is based on a number of free blocks in the memory device failing to satisfy a garbage collection threshold; wherein reducing the write command rate is further performed based on the number of idle stripes in the memory device failing to meet a minimum threshold; and The minimum threshold is smaller than the garbage collection threshold.

3. The method according to claim 2, further comprising: selecting, by the memory subsystem, a first garbage collection strategy for the garbage collection process from a set of garbage collection strategies, the set of garbage collection strategies including the first garbage collection strategy and a second garbage collection strategy, The first garbage collection strategy includes a first write delay time for delaying processing of a write command in the memory subsystem. 4 . The method of claim 3 , wherein the first garbage collection policy is selected for the garbage collection process in response to the number of free stripes in the memory device failing to satisfy the minimum threshold.

5. The method according to claim 3, further comprising: recording, by the memory subsystem in response to selecting the first garbage collection policy, a current position in the logical-to-physical table during a fold performed using the logical-to-physical table; and Collapsing the first candidate stripe into the first target stripe is performed by the memory subsystem suspending use of the logical-to-physical table.

6. The method according to claim 5, further comprising: In response to selecting the first garbage collection policy, selecting, by the memory subsystem, a second candidate stripe for folding into a second target stripe; After pausing the execution of folding the first candidate stripe, executing, by the memory subsystem, folding the second candidate stripe into the second target stripe using the physical-to-logical table stored in the second candidate stripe; and After completing folding the second candidate stripe into the second target stripe, the memory subsystem resumes folding the first candidate stripe into the first target stripe using the logical-to-physical table.

7. The method of claim 1, wherein collapsing the first candidate stripe into the first target stripe comprises copying valid pages from the first candidate stripe into pages of the first target stripe.

8. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: determining that a garbage collection process is to be performed on a memory device of the memory subsystem; In response to determining that the garbage collection process is to be performed, selecting a first candidate stripe for folding into a first target stripe; determining that the physical-to-logical table stored in the first candidate stripe is unavailable; In response to determining that the physical-to-logical table stored in the first candidate stripe is unavailable, reducing a write command rate that controls a rate at which the memory subsystem implements writes; and Collapsing the first candidate stripe into the first target stripe is performed using a logical-to-physical table.

9. The non-transitory computer-readable storage medium of claim 8, wherein determining that the garbage collection process is to be performed on the memory device is based on a number of free blocks in the memory device failing to satisfy a garbage collection threshold; wherein reducing the write command rate is further performed based on the number of idle stripes in the memory device failing to meet a minimum threshold; and The minimum threshold is smaller than the garbage collection threshold.

10. The non-transitory computer-readable storage medium of claim 9, wherein the processing device further: selecting a first garbage collection strategy for the garbage collection process from a set of garbage collection strategies, the set of garbage collection strategies including the first garbage collection strategy and a second garbage collection strategy, The first garbage collection strategy includes a first write delay time for delaying processing of a write command in the memory subsystem.

11. The non-transitory computer-readable storage medium of claim 10, wherein the first garbage collection policy is selected for the garbage collection process in response to the number of free stripes in the memory device failing to satisfy the minimum threshold.

12. The non-transitory computer-readable storage medium of claim 10, wherein the processing device further: responsive to selecting the first garbage collection strategy, recording a current position in the logical-to-physical table during a fold performed using the logical-to-physical table; and Performing the folding of the first candidate stripe into the first target stripe using the logical-to-physical table is suspended.

13. The non-transitory computer-readable storage medium of claim 12, wherein the processing device further: In response to selecting the first garbage collection strategy, selecting a second candidate stripe for folding into a second target stripe; After pausing the execution of folding the first candidate block stripe, using the physical-to-logical table stored in the second candidate block stripe to execute folding the second candidate block stripe into the second target block stripe; and After completing folding the second candidate stripe into the second target stripe, resuming folding the first candidate stripe into the first target stripe using the logical-to-physical table.

14. The non-transitory computer-readable storage medium of claim 8, wherein collapsing the first candidate stripe into the first target stripe comprises copying valid pages from the first candidate stripe into pages of the first target stripe.

15. A system comprising: Memory device; and a processing device operatively coupled to the memory device to: determining that a physical-to-logical table stored in a first candidate stripe is unavailable, wherein the first candidate stripe is to be collapsed into a first target stripe; In response to determining that the physical-to-logical table stored in the first candidate stripe is unavailable, reducing a write command rate that controls a rate at which a memory subsystem implements writes; and Collapsing the first candidate stripe into the first target stripe is performed using a logical-to-physical table.

16. The system of claim 15, wherein reducing the write command rate is performed based on a number of idle stripes in the memory device failing to satisfy a minimum threshold.

17. The system of claim 16, wherein the processing device further: selecting a first garbage collection strategy for a garbage collection process from a set of garbage collection strategies, the set of garbage collection strategies including the first garbage collection strategy and a second garbage collection strategy, The first garbage collection strategy includes a first write delay time for delaying processing of a write command in the memory subsystem.

18. The system of claim 17, wherein the first garbage collection policy is selected for the garbage collection process in response to the number of free stripes in the memory device failing to satisfy the minimum threshold.

19. The system of claim 17, wherein the processing device further: responsive to selecting the first garbage collection strategy, recording, during a fold performed using the logical-to-physical table, a current position in the logical-to-physical table; suspending the use of the logical-to-physical table to perform folding the first candidate block stripe into the first target block stripe; In response to selecting the first garbage collection strategy, selecting a second candidate stripe for folding into a second target stripe; After pausing the execution of folding the first candidate block stripe, using the physical-to-logical table stored in the second candidate block stripe to execute folding the second candidate block stripe into the second target block stripe; and After completing folding the second candidate stripe into the second target stripe, resuming folding the first candidate stripe into the first target stripe using the logical-to-physical table.

20. The system of claim 15, wherein collapsing the first candidate stripe into the first target stripe comprises copying valid pages from the first candidate stripe into pages of the first target stripe.

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