Semiconductor structure and memory

Abstract

The embodiment of the present disclosure provides a semiconductor structure and a memory, the semiconductor structure comprises: a storage cell array comprising a first storage cell subarray and a second storage cell subarray arranged along a first direction; a first data line group comprising a plurality of first data lines connected to the first storage cell subarray; a second data line group comprising a plurality of second data lines connected to the second storage cell subarray; and a plurality of read-write control circuits comprising a plurality of odd read-write control circuits and a plurality of even read-write control circuits, the odd read-write control circuits and the even read-write control circuits are arranged alternately in sequence; wherein the odd read-write control circuits are connected to first odd data lines in the first data lines and second odd data lines in the second data lines in a one-to-one correspondence respectively, and the even read-write control circuits are connected to first even data lines in the first data lines and second even data lines in the second data lines in a one-to-one correspondence respectively.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and in particular, to a semiconductor structure and a memory. BACKGROUND

[0002] Dynamic random access memory (DRAM) is widely used in modern electronic systems due to its high storage density and fast transmission speed. Dynamic random access memory usually includes a core storage area and a peripheral circuit area. The core storage area is used to set a plurality of storage units for storing data information. The peripheral circuit area is electrically connected to the storage units through data lines to enable the storage units to store or read data information.

[0003] With the development of semiconductor technology, the integration of storage units is becoming higher and higher, and the connection lines between the peripheral circuit and the storage units are becoming more and more complex, which increases the difficulty of the preparation process of the memory and also increases the power consumption of the memory, thereby reducing the performance of the memory. SUMMARY

[0004] Therefore, the embodiments of the present disclosure provide a semiconductor structure and a memory.

[0005] In a first aspect, the embodiments of the present disclosure provide a semiconductor structure, comprising:

[0006] a storage unit array comprising a first storage unit sub-array and a second storage unit sub-array arranged along a first direction;

[0007] a first data line group comprising a plurality of first data lines, the first data lines being connected to the first storage unit sub-array;

[0008] a second data line group comprising a plurality of second data lines, the second data lines being connected to the second storage unit sub-array, and the first data lines and the second data lines being arranged at intervals;

[0009] a plurality of read-write control circuits comprising a plurality of odd read-write control circuits and a plurality of even read-write control circuits, the odd read-write control circuits and the even read-write control circuits being arranged alternately in sequence; wherein

[0010] the odd read-write control circuits are connected one by one to first odd data lines in the first data lines and second odd data lines in the second data lines, respectively, and the even read-write control circuits are connected one by one to first even data lines in the first data lines and second even data lines in the second data lines, respectively.

[0011] In some embodiments, the semiconductor structure further comprises:

[0012] The buffer circuit comprises a plurality of buffer sub-circuits, each of which is connected to one of the read-write control circuits, and each of the buffer sub-circuits is configured to transmit a control signal to the read-write control circuit.

[0013] In some embodiments, the plurality of buffer sub-circuits comprises a plurality of odd buffer sub-circuits and a plurality of even buffer sub-circuits; wherein,

[0014] The odd buffer sub-circuits are connected to the odd read-write control circuits; and the even buffer sub-circuits are connected to the even read-write control circuits.

[0015] In some embodiments, the number of odd buffer sub-circuits is equal to the number of even buffer sub-circuits.

[0016] The number of odd read-write control circuits is equal to the number of even read-write control circuits.

[0017] In some embodiments, the semiconductor structure further comprises:

[0018] A first control signal line is connected to the plurality of odd buffer sub-circuits and configured to transmit a control signal to the odd read-write control circuits.

[0019] A second control signal line is connected to the plurality of even buffer sub-circuits and configured to transmit a control signal to the even read-write control circuits.

[0020] In some embodiments, the read-write control circuits are located on one side of the array of memory cells in a second direction; and the second direction is perpendicular to the first direction.

[0021] In some embodiments, the buffer circuit is located on a side of the read-write control circuits away from the array of memory cells in the second direction.

[0022] In some embodiments, the plurality of buffer sub-circuits are arranged at intervals along the first direction.

[0023] In some embodiments, the semiconductor structure further comprises:

[0024] A control line is connected between the plurality of read-write control circuits.

[0025] In a second aspect, the embodiments of the present disclosure further provide a memory, comprising:

[0026] A plurality of semiconductor structures according to any one of the above embodiments.

[0027] In the semiconductor structure provided by the embodiments of the present disclosure, the first memory cell sub-array and the second memory cell sub-array arranged along the first direction are respectively connected with the first data line in the first data line group and the second data line in the second data line group; the read-write control circuit corresponding to each memory cell sub-array is arranged alternately in odd and even manners, and is connected with the first data line and the second data line one by one in odd and even manners. In this way, each memory cell sub-array is connected with the read-write control circuit one by one through the data line, which can reduce the jumper in the wiring, simplify the circuit layout design, and reduce the power loss caused by a large number of data lines. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 Basic architecture of the read-write control circuit layout of the DRAM in an embodiment;

[0029] Figure 2 Layout of a circuit layout in an embodiment;

[0030] Figure 3 Schematic diagram of the distribution of a read-write control circuit and the connection relationship with data lines in an embodiment;

[0031] Figure 4 Schematic diagram of the distribution of a read-write control circuit and the connection relationship with data lines in an embodiment;

[0032] Figure 5 Schematic diagram of the distribution of a read-write control circuit and the connection relationship with data lines in an embodiment;

[0033] Figure 6 Schematic diagram of a circuit layout in an embodiment;

[0034] Figure 7 Schematic diagram of a circuit layout in an embodiment;

[0035] Figure 8 Schematic diagram of a circuit layout in an embodiment; DETAILED DESCRIPTION

[0036] In order to facilitate the understanding of the present disclosure, the exemplary embodiments disclosed by the present disclosure will be described in more detail below with reference to the relevant drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms, and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood, and the scope of the present disclosure disclosed can be fully conveyed to those skilled in the art.

[0037] In the following description, numerous specific details are set forth to provide a more thorough understanding of the present disclosure. However, it will be apparent to one of skill in the art upon

[0038] Generally, the terminology can be understood at least in part from usage in context. For example, the term "one or more," as used herein, can be taken to describe any feature, structure, or characteristic in the singular or can be taken to describe a combination of features, structures or characteristics, in the plural, depending at least in part on the context in which such a term is used. Similarly, as used herein, the terminology "at least one," "one or more," and "and / or," can be taken to express the possibility of zero, one, or more instances of the feature, structure or characteristic. Also, the term "based on" can be taken to mean "based, at least in part, on," that is, one or more factors, which can be explicitly stated or not explicitly stated.

[0039] Unless otherwise defined, the terms (used herein are intended to be interpreted as being limited only by specific embodiments described in the written description and are not intended to be limited by the terms shown in the appended claims. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0040] For a thorough understanding of the present disclosure, reference should be made to the following detailed description together with the accompanying drawings, in which:

[0041] A semiconductor memory is a memory that uses a semiconductor circuit for access, and DRAM is widely used in various fields due to its fast storage speed and high integration. Embodiments of the present disclosure are described with reference to the circuit layout of DRAM.

[0042] In some embodiments, Figure 1For the basic architecture of the read-write control circuit layout (RWBnk), each read-write control circuit RW2B (e.g. RW2B_0, RW2B_1,... RW2B_15) is connected to the memory cell array (Array) through a data signal line YIO* respectively.

[0043] In the layout of the circuit layout, as shown in Figure 2 The first memory cell sub-array corresponding read-write control circuit (odd read-write control circuit 11) and the second memory cell sub-array corresponding read-write control circuit (even read-write control circuit 12) are arranged in two regions: the first region 21 and the second region 22 respectively. Here, the first memory cell sub-array and the second memory cell sub-array are arranged alternately, and the corresponding connected data lines YIO* are also arranged alternately, that is, according to the odd-even alternation arrangement, Yio<0>, Yio<1>, Yio<2> and Yio<3> are connected to the odd bit memory cells in the first memory cell sub-array 111, Yio<4>, Yio<5>, Yio<6> and Yio<7> are connected to the even bit memory cells in the first memory cell sub-array 111, Yio<8>, Yio<9>, Yio<10> and Yio<11> are connected to the odd bit memory cells in the second memory cell sub-array 112, Yio<12>, Yio<13>, Yio<14> and Yio<15> are connected to the even bit memory cells in the second memory cell sub-array 112. However, since the odd read-write control circuit 11 and the even read-write control circuit 12 are arranged separately in two adjacent regions, that is, a plurality of odd read-write control circuits 11 are arranged in sequence in the first region 21, and a plurality of even read-write control circuits 12 are arranged in sequence in the second region 22, therefore, the read-write control circuit and the memory cell sub-array are not arranged in a one-to-one corresponding position relationship.

[0044] Exemplarily, as shown in Figure 3 The odd read-write control circuit 11 includes 8 circuit units arranged side by side, W_bit0 to W_bit7, and the even read-write control circuit 12 also includes 8 circuit units arranged side by side, E_bit0 to E_bit7. These circuit units need to be alternately connected to the data lines Yio <x>Connect (here x represents the number of data lines), so it needs a large number of X direction jumper ( Figure 3 The part of the connection line is only schematically marked). That is, the connection between the read-write control circuit and the data line of the storage unit sub-array not only needs a large number of metal wires extending along the Y direction, but also needs to be connected by the X direction jumper connected to the other metal layer through the via. For example, the metal line extending in the Y direction is located in the first metal layer M1, and the metal line extending in the X direction is located in the second metal layer M2. The above connection mode will cause the second metal layer M2 to contain a large number of metal line segments, thereby increasing the complexity of the circuit layout, increasing the power consumption of the circuit, and the too long data wire is also prone to cause data transmission errors.

[0045] The embodiment of the present disclosure provides a semiconductor structure 100, as shown in the figure, comprising: Figure 4

[0046] The storage unit array 110 comprises a first storage unit sub-array 111 and a second storage unit sub-array 112 arranged along a first direction;

[0047] The first data line group 120 comprises a plurality of first data lines 121, and the first data lines 121 are connected to the first storage unit sub-array 111;

[0048] The second data line group 130 comprises a plurality of second data lines 131, and the second data lines 131 are connected to the second storage unit sub-array 112, and the first data lines 121 and the second data lines 131 are arranged at intervals;

[0049] The plurality of read-write control circuits 140 comprises a plurality of odd read-write control circuits 141 and a plurality of even read-write control circuits 142, and the odd read-write control circuits 141 and the even read-write control circuits 142 are alternately arranged in sequence; wherein,

[0050] The odd read-write control circuit 141 is connected to the first odd data line 121a in the first data line 121 and the second odd data line 131a in the second data line 131 in one-to-one correspondence, respectively, and the even read-write control circuit 142 is connected to the first even data line 121b in the first data line 121 and the second even data line 131b in the second data line 131 in one-to-one correspondence.

[0051] It can be understood that the first storage unit sub-array 111 and the second storage unit sub-array 112 are arranged side by side, and the data lines connected thereto are arranged in sequence along the first direction, such as Figure 4 The X direction as shown, and the data lines connected to each storage unit sub-array are also arranged at intervals in the X direction.

[0052] ​The first odd data line 121a in the first data line 121 and the second odd data line 131a in the second data line 131, i.e. the data line in odd position in all sequentially arranged data lines, and the first odd data line 121a in the first data line 121 receives data of odd bit storage units of the first storage unit subarray 111, and the second odd data line 131a in the second data line 131 receives data of odd bit storage units of the second storage unit subarray 112; similarly, the first even data line 121b in the first data line 121 and the second even data line 131b in the second data line 131, i.e. the data line in even position in all sequentially arranged data lines, and the first even data line 121b in the first data line 121 receives data of even bit storage units of the first storage unit subarray 111, and the second even data line 131b in the second data line 131 receives data of even bit storage units of the second storage unit subarray 112.

[0053] In the embodiments of the present disclosure, the read-write control circuit 140 is sequentially and alternately arranged as the odd read-write control circuit 141 and the even read-write control circuit 142, and is connected with the data line one by one. In this way, the connection relationship as shown in FIG. 4 can be formed: the odd read-write control circuit W_bit0-7 (141) and the even read-write control circuit E_bit0-7 (142) are sequentially and alternately arranged, and are connected with the data line Yio_0-7. Figure 5 <x>is a one-to-one connection. As can be seen, since the positional relationship between the read / write control circuit 140 and the sub-array of memory cells is one-to-one, a large number of circuit traces extending in the X direction can be reduced. Exemplarily, in the structure shown in Figure 5 each memory cell array and the read / write control circuit are connected only by data lines Yio extending in the Y direction. <x>Is ready to connect. Note that, Figure 5 Yio <x>The order of the numbers is only an example, and the odd data lines and even data lines above only represent the odd and even distribution of the positions of the data lines, and are irrelevant to the numbers above. Specifically, Yio<0>, Yio<1>, Yio<2> and Yio<3> receive data of odd bit storage units in the first storage unit subarray 111, Yio<4>, Yio<5>, Yio<6> and Yio<7> receive data of even bit storage units in the first storage unit subarray 111, Yio<8>, Yio<9>, Yio<10> and Yio<11> receive data of odd bit storage units in the second storage unit subarray 112, and Yio<12>, Yio<13>, Yio<14> and Yio<15> receive data of even bit storage units in the second storage unit subarray 112. In actual application, the numbers of the data lines can be set according to specific conditions.

[0054] If the data lines Yio <x>The partial layout along the Y direction is in the first metal layer M1, and the partial layout along the X direction is in the second metal layer M2. In this way, the number of wirings in the second metal layer M2 can be reduced, so as to reduce the complexity of the whole circuit and save the layout space. Moreover, the data line Yio <x>In this way, the power consumption can be effectively saved and the probability of data transmission error can be reduced.

[0055] In some embodiments, as shown in Figure 6 the semiconductor structure 100 further comprises:

[0056] The buffer circuit 210 comprises a plurality of buffer sub-circuits, each of which is connected to one of the read-write control circuits 140, and is configured to transmit a control signal to the read-write control circuit 140.

[0057] In some embodiments, the plurality of buffer sub-circuits are arranged at intervals along the first direction.

[0058] Here, the first direction is the X direction as shown in Figure 6 .

[0059] In some embodiments, the plurality of buffer sub-circuits comprise a plurality of odd buffer sub-circuits 211 and a plurality of even buffer sub-circuits 212; the odd buffer sub-circuits 211 are connected to the odd read-write control circuits 141; and the even buffer sub-circuits 212 are connected to the even read-write control circuits 142.

[0060] In comparison with the arrangement of the odd buffer sub-circuits 211 and the even buffer sub-circuits 212 in two areas as shown in Figure 3 , the embodiments of the present disclosure adopt an alternative arrangement as shown in Figure 6 .

[0061] Since the plurality of odd buffer sub-circuits 211 are connected to each other, and the plurality of even buffer sub-circuits 212 are connected to each other, this arrangement may cause a small increase in the number of lines. However, considering that this arrangement is more convenient for connecting the read-write control circuits 140, this small increase in the number of lines is acceptable.

[0062] It should be noted that the connection lines of the circuits as shown in Figure 6 are only schematic lines representing the interaction between the circuits, and do not represent the structure of the actual circuit traces. The actual circuit may include more traces, and may include bent parts or additional devices or circuits, etc.

[0063] In some embodiments, the number of odd buffer sub-circuits 211 is equal to the number of even buffer sub-circuits 212; and the number of odd read-write control circuits 141 is equal to the number of even read-write control circuits 141.

[0064] In this way, each read-write control circuit is connected to one buffer sub-circuit one-to-one. In addition, each odd buffer sub-circuit 211 can be connected to one odd read-write control circuit 141; and each even buffer sub-circuit 212 can be connected to one even read-write control circuit 142.

[0065] In some embodiments, the semiconductor structure further comprises:

[0066] A first control signal line 221 is connected to the plurality of odd buffer sub-circuits 211, and is used to transmit control signals to the odd read-write control circuits 141.

[0067] A second control signal line 222 is connected to the plurality of even buffer sub-circuits 212, and is used to transmit control signals to the even read-write control circuits 142.

[0068] The first control signal line 221 is connected to the plurality of odd buffer sub-circuits 211 and can transmit control signals to the plurality of odd read-write control circuits 141 through the plurality of odd buffer sub-circuits 211, thereby achieving control of the odd read-write control circuits 141. That is, the first control signal line 221 is used to connect the plurality of odd buffer sub-circuits 211 together and transmit control signals corresponding to the plurality of odd buffer sub-circuits 211. Similarly, the second control signal line 222 is connected to the plurality of even buffer sub-circuits 212 and transmits control signals to the plurality of even read-write control circuits 142 through the plurality of even buffer sub-circuits 212, thereby achieving control of the even read-write control circuits 142. Exemplarily, the control signals can include enable signals, read / write state switching signals, etc. of the odd read-write control circuits 141 or the even read-write control circuits 142.

[0069] In some embodiments, the read-write control circuit 140 is located on one side of the memory cell array 110 in a second direction; and the second direction is perpendicular to the first direction.

[0070] In some embodiments, the buffer circuit 210 is located on a side of the read-write control circuit 140 away from the memory cell array 110 in the second direction.

[0071] Here, the second direction is the Y direction as shown in the above figures, and the first direction is the X direction as shown in the above figures.

[0072] The above arrangement is shown in the layout structure of Figure 6 The first memory cell sub-arrays 111 and the second memory cell sub-arrays 112 in the memory cell array 110 are arranged at the bottom of the layout structure. The read-write control circuit 140 and the buffer circuit 210 are located on one side of the memory cell array 110 in the Y direction and are connected in sequence.

[0073] In some embodiments, the semiconductor structure further includes:

[0074] Control lines connected between the plurality of read / write control circuits 140.

[0075] Since some control signals need to be transmitted between the multiple read / write control circuits 140, control lines are also provided between each read / write control circuit 140. For example, read / write command signals and data read / write enable signals are transmitted between different read / write control circuits.

[0076] Since there are control lines connecting the odd-numbered read / write control circuit 141 and the even-numbered read / write control circuit 142, the layout provided in this embodiment of the present disclosure allows the odd-numbered read / write control circuit 141 and the even-numbered read / write control circuit 142 to be arranged alternately, which can reduce the number and length of control lines and thus simplify the circuit layout.

[0077] like Figure 7 The diagram shows some circuit traces (extending along the X direction) on the second metal layer M2 in a conventional design, including the address bus Abus*, some control signal lines DrC* in the read / write control circuit, and the data line YIO*, etc. It can be seen that in a conventional design, these circuit traces occupy a large number of traces on the second metal layer M2, resulting in a large layout area and complex wiring.

[0078] Based on the improvements made to the above embodiments, the circuit traces (extending along the X direction) of the second metal layer M2 are as follows: Figure 8 As shown, the number of traces in the second metal layer M2 is significantly reduced, which can effectively save layout area and reduce circuit complexity.

[0079] Furthermore, this disclosure also provides a memory comprising: a plurality of semiconductor structures as described in any of the above embodiments.

[0080] It should be noted that the features disclosed in the various embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0081] It should be understood that every feature, structure, or characteristic described herein is within a single embodiment and is included in at least one embodiment of the present disclosure. Therefore, repeated description of the same feature, structure, or characteristic in the description is not unnecessary. In addition, many of the features, structures, or characteristics described herein can be combined in any suitable manner in one or more embodiments. It should be understood that the sequence of the processes described above does not mean the order of execution, and the execution order of the processes should be determined according to their functions and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The sequence of the above embodiments of the present disclosure is only for description, and does not represent the advantages or disadvantages of the embodiments.

[0082] It should be noted that the terms "comprising", "containing", or any other similar term as used herein are intended to encompass the inclusion of a feature, structure, or characteristic, but do not exclude the presence of other features, structures, or characteristics. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or device including the element.

[0083] In several embodiments provided by the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The above-described device embodiments are only illustrative, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed components can be through some interface, indirect coupling or communication connection between devices or units, which can be electrical, mechanical or other forms.

[0084] The units described above as separate components can or can not be physically separated, and the components displayed as units can or can not be physical units; they can be located in one place or distributed on multiple network units; some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0085] In addition, each functional unit in each embodiment of the present disclosure can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be realized in the form of hardware or hardware plus software functional unit.

[0086] The above embodiments are only illustrative of the principles of the present disclosure and its effects, and are not intended to limit the present disclosure. Any modification or change made by anyone skilled in the art based on the above embodiments without departing from the spirit and scope of the present disclosure shall be covered by the claims of the present disclosure.< / x> < / x> < / x> < / x> < / x> ​< / x>

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a memory cell array comprising a first memory cell sub-array and a second memory cell sub-array arranged along a first direction; a first data line group comprising a plurality of first data lines, the first data lines being connected to the first memory cell sub-array; a second data line group comprising a plurality of second data lines, the second data lines being connected to the second memory cell sub-array, the first data lines and the second data lines being arranged alternately; wherein the first data lines and the second data lines are data lines Yio, and the data lines Yio are arranged alternately according to odd and even; a plurality of read-write control circuits comprising a plurality of odd read-write control circuits and a plurality of even read-write control circuits, the odd read-write control circuits and the even read-write control circuits being arranged alternately in sequence; wherein the odd read-write control circuits are connected to first odd data lines in the first data lines and second odd data lines in the second data lines in one-to-one correspondence respectively, and the even read-write control circuits are connected to first even data lines in the first data lines and second even data lines in the second data lines in one-to-one correspondence respectively.

2. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises: a buffer circuit, the buffer circuit comprising a plurality of buffer sub-circuits, each buffer sub-circuit being connected to a read-write control circuit, and the buffer sub-circuits being configured to transmit control signals to the read-write control circuits.

3. The semiconductor structure of claim 2, wherein, The plurality of buffer sub-circuits comprise a plurality of odd buffer sub-circuits and a plurality of even buffer sub-circuits; wherein the odd buffer sub-circuits are connected to the odd read-write control circuits, and the even buffer sub-circuits are connected to the even read-write control circuits.

4. The semiconductor structure of claim 3, wherein, The number of the odd buffer sub-circuits is equal to the number of the even buffer sub-circuits. The number of the odd read-write control circuits is equal to the number of the even read-write control circuits.

5. The semiconductor structure of claim 3, wherein, The semiconductor structure further comprises: a first control signal line connected to the plurality of odd buffer sub-circuits and configured to transmit control signals to the odd read-write control circuits; a second control signal line connected to the plurality of even buffer sub-circuits and configured to transmit control signals to the even read-write control circuits.

6. The semiconductor structure of any of claims 2 to 4, wherein the semiconductor structure is a vertical semiconductor structure. The read-write control circuits are located on one side of the memory cell array in a second direction; and the second direction is perpendicular to the first direction.

7. The semiconductor structure of claim 5, wherein, The buffer circuit is located on a side of the read-write control circuits away from the memory cell array in the second direction; and the second direction is perpendicular to the first direction.

8. The semiconductor structure of claim 7, wherein, The plurality of buffer sub-circuits are arranged alternately along the first direction.

9. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises: a control line connected between the plurality of read-write control circuits.

10. A memory, comprising: The semiconductor structure comprises: a plurality of semiconductor structures according to any one of claims 1 to 9.

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