Flash controller configuration method and apparatus for solid state drive, device, and medium

Abstract

The application relates to the technical field of storage, in particular to a flash memory controller configuration method and device for a solid state disk, equipment and a medium. The method comprises the following steps: according to the use information of the solid state disk, a target stage in which the solid state disk currently belongs in a life cycle is matched from a starting stage, an intermediate stage and an ending stage; in response to the target stage being the starting stage, the interleaving function of the flash memory controller is closed; in response to the target stage being the intermediate stage, the bit error rate of the solid state disk is periodically acquired, and the bit error rate is compared with a preset bit error rate to determine whether to open the interleaving function of the flash memory controller; and in response to the target stage being the ending stage, the interleaving function of the flash memory controller is opened. The application scheme flexibly opens or closes the interleaving function according to the stage of the solid state disk in the life cycle, improves the decoding success probability, and significantly improves the reliability of the solid state disk.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage, and in particular to a flash memory controller configuration method and device for a solid state disk, an equipment and a medium. BACKGROUND

[0002] The basic unit for storing data in a flash memory (Nand Flash) is called a Cell, and each Cell records different data by injecting and releasing electrons. The entry and exit of electrons in the Cell causes wear to the Cell, and as the degree of wear increases, the probability of escape of electrons in the Cell increases, thereby causing the data stored in the Cell to jump.

[0003] In view of this, the flash memory needs to cooperate with the ECC algorithm in the host to perform data error detection and correction. When writing data, an error correcting code (ECC) engine calculates redundant data based on the original data and stores the original data and the redundant data at the same time. When reading data, the original data and the redundant data are read out together, and the ECC engine checks and corrects errors to obtain the correct original data. However, with the widespread application of TLC flash memory particles and 3D NAND, and the increase in flash memory Program / Erase (PE), or the influence of factors such as temperature, it is more likely to occur that data determination errors occur when reading Nand, or errors occur due to interference. SUMMARY

[0004] Therefore, it is necessary to provide a flash memory controller configuration method and device for a solid state disk, an equipment and a medium to solve the above technical problems.

[0005] According to a first aspect of the present application, a flash memory controller configuration method for a solid state disk is provided, the method comprising:

[0006] According to the use information of the solid state disk, a target stage is matched from a start stage, an intermediate stage and an end stage, which belongs to the current time in the life cycle of the solid state disk;

[0007] In response to the target stage being the start stage, the interleaving function of the flash memory controller is closed;

[0008] In response to the target stage being the intermediate stage, the bit error rate of the solid state disk is periodically obtained, and the bit error rate is compared with a preset bit error rate to determine whether to start the interleaving function of the flash memory controller;

[0009] In response to the target stage being the end stage, the interleaving function of the flash memory controller is started.

[0010] In some embodiments, the method comprises:

[0011] acquiring a current cumulative usage duration of the SSD;

[0012] matching the current cumulative usage duration with a preset usage duration and a corresponding relationship among the beginning stage, the intermediate stage and the end stage to obtain the target stage.

[0013] In some embodiments, the method further comprises:

[0014] acquiring a current bit error rate of the SSD at intervals of a first preset time;

[0015] comparing each acquired bit error rate with the preset bit error rate;

[0016] in response to a certain acquired bit error rate exceeding the preset bit error rate, turning on the interleaving function of the flash controller;

[0017] in response to a certain acquired bit error rate not exceeding the preset bit error rate, turning off the interleaving function of the flash controller.

[0018] In some embodiments, the method further comprises:

[0019] returning to execute the step of matching the target stage from the beginning stage, the intermediate stage and the end stage according to the usage information of the SSD at intervals of a second preset time, wherein the second preset time is much greater than the first preset time.

[0020] In some embodiments, the method further comprises:

[0021] in response to the flash controller turning on the interleaving function, starting multiple threads according to the actual performance of the SSD to perform parallel grouping interleaving.

[0022] According to a second aspect of the present application, a flash controller configuration device for an SSD is provided, which comprises:

[0023] a matching module configured to match a target stage from a beginning stage, an intermediate stage and an end stage according to the usage information of the SSD, wherein the target stage belongs to a life cycle of the SSD at a current time.

[0024] a first judging module, configured to close the interleaving function of the flash memory controller in response to the target stage being the start stage;

[0025] a second judging module, configured to periodically acquire a bit error rate of the solid state disk and compare the bit error rate with a preset bit error rate to determine whether to open the interleaving function of the flash memory controller in response to the target stage being the intermediate stage;

[0026] a third judging module, configured to open the interleaving function of the flash memory controller in response to the target stage being the end stage.

[0027] In some embodiments, the matching module is further configured to:

[0028] acquire a current cumulative usage duration of the solid state disk;

[0029] match the current cumulative usage duration with a preset usage duration and a start stage, an intermediate stage and an end stage correspondence to obtain the target stage.

[0030] In some embodiments, the second judging module is further configured to:

[0031] acquire the current bit error rate of the solid state disk at intervals of a first preset time;

[0032] respectively compare each acquired bit error rate with the preset bit error rate;

[0033] open the interleaving function of the current flash memory controller in response to a certain acquired bit error rate exceeding the preset bit error rate;

[0034] close the interleaving function of the current flash memory controller in response to a certain acquired bit error rate not exceeding the preset bit error rate.

[0035] According to a third aspect of the present application, a computer device is also provided, which comprises:

[0036] at least one processor; and

[0037] a memory storing a computer program capable of running on the processor, and the processor executes the program to perform the aforementioned flash memory controller configuration method for a solid state disk.

[0038] According to a fourth aspect of the present application, a computer readable storage medium is also provided, which stores a computer program, and the computer program is executed by a processor to perform the aforementioned flash memory controller configuration method for a solid state disk.

[0039] The flash memory controller configuration method for the solid state disk can improve the reliability of the solid state disk.

[0040] In addition, the application further provides a flash memory controller configuration device for a solid state disk, a computer device and a computer readable storage medium, which can also achieve the above technical effects, and details are not described herein. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced as follows. Obviously, the drawings in the following description only represent some embodiments of the present application, and for those skilled in the art, other embodiments can be obtained from these drawings without creative labor.

[0042] Figure 1 A flow chart of a flash memory controller configuration method for a solid state disk is provided for an embodiment of the present application;

[0043] Figure 2 A data processing flow diagram using packet interleaving is provided for an embodiment of the present application;

[0044] Figure 3 An implementation flow diagram of a group of data writing is provided for another embodiment of the present application;

[0045] Figure 4 A structure diagram of a flash memory controller configuration device for a solid state disk is provided for another embodiment of the present application;

[0046] Figure 5 An internal structure diagram of a computer device in another embodiment of the present application. DETAILED DESCRIPTION

[0047] In order to make the objects, technical solutions and advantages of the present application clearer, the following further describes the embodiments of the present application in detail with reference to the specific embodiments and the accompanying drawings.

[0048] It should be noted that all the expressions of "first" and "second" in the embodiments of the present application are used to distinguish two same name non-same entities or non-same parameters. It can be seen that "first" and "second" are only for the convenience of description, and should not be understood as a limitation on the embodiments of the present application. The subsequent embodiments will not be described one by one.

[0049] In one embodiment, referring to Figure 1 The present application provides a flash memory controller configuration method 100 for a solid state disk, specifically, the method comprises the following steps:

[0050] Step 101, according to the use information of the solid state disk (SSD), a target stage to which the solid state disk belongs at the current time in the life cycle is matched from the start stage, the middle stage and the end stage;

[0051] In the embodiment, the start stage represented as BOL (Begin of Life) refers to the start stage of the life cycle, for example, the start stage can be between 0 to 200 hours of the use duration of the solid state disk, the middle stage represented as MOL (Middle of Life) can be the time period of 201 to 500 hours of the use duration of the solid state disk, and the end stage represented as EOL (End of Life) can be above 501 hours of the use duration of the solid state disk. It should be noted that in the specific implementation process, the above three stages can also be determined according to the use frequency and the actual business mark of the hard disk. The embodiment does not limit the specific determination method of the three stages, and the specific actual value is only for reference, and should not be understood as a specific limitation on the present application.

[0052] Step 102, in response to the target stage being the start stage, the interleaving function of the flash memory controller is closed;

[0053] Step 103, in response to the target stage being the middle stage, the bit error rate of the solid state disk is periodically acquired, and the bit error rate is compared with the preset bit error rate to determine whether to start the interleaving function of the flash memory controller;

[0054] Step 104, in response to the target stage being the end stage, the interleaving function of the flash memory controller is started.

[0055] It should be noted that the interleaving function can adopt any existing interleaving process. For ease of understanding, it is better to take the group interleaving data processing process as an example. Figure 2 As shown, the SSD's interleaving function is enabled or disabled based on the SSD lifecycle stage. At the beginning of the SSD's lifecycle, raw bit errors are low, so interleaving is not necessary. In the middle of the Nand Flash's lifecycle, as the number of P / E cycles increases, the raw bit error rate increases, so interleaving can be enabled based on a threshold. At the end of the Nand Flash's lifecycle, the raw bit error rate is even higher, so enabling interleaving can further improve SSD reliability. The data group "data_group_in" transmitted by the host typically contains host data, FTL meta, scramble seed, and CRC data. Under the control of the Nand Flash controller, data_group_in undergoes scrambling, cyclic redundancy check (CRC), and low-density parity check (LDPC) encoding before undergoing interleaving and finally being written to the Nand Flash. When the firmware (FW) issues a command to read the Nand Flash, the data read from the Nand Flash first undergoes a deinterleaving operation, then passes through low-density parity check code encoding and decoding (LDPC decoding), cyclic redundancy check, and descrambling processing, and finally the data group data_group_out is fed back to the host.

[0056] The above-mentioned flash memory controller configuration method for a solid-state drive has a low original bit error rate at the beginning of the solid-state drive's life cycle, and the LDPC encoding and decoding function can meet the system reliability requirements, so there is no need to enable the above-mentioned interleaving function. In the middle stage of the solid-state drive's life cycle, the bit error rate increases with the increase of erase / write cycles. At this time, the interleaving function can be selected to be turned on according to the preset bit error rate to disperse continuous error bits and enhance decoding performance. At the end node stage of the solid-state drive's life cycle, the bit error rate of the flash memory is further increased due to various factors. Sometimes the LDPC encoding and decoding function cannot fully meet the system bit error rate requirements. Turning on the interleaving function can maximize the dispersion of error bits in the flash memory read data. Flexibly turning on or off the interleaving function based on the stage of the solid-state drive's life cycle helps to increase the probability of subsequent decoding success and significantly improve the reliability of the solid-state drive.

[0057] In some embodiments, the step 101 of matching a target stage from the start stage, the intermediate stage and the end stage according to the usage information of the solid state disk comprises:

[0058] acquiring a current usage cumulative duration of the solid state disk;

[0059] matching the current usage cumulative duration with a preset usage duration and a corresponding relationship among the start stage, the intermediate stage and the end stage to obtain the target stage.

[0060] In some embodiments, the step 103 of periodically acquiring the bit error rate of the solid state disk and comparing the bit error rate with a preset bit error rate to determine whether to start the interleaving function of the flash memory controller comprises:

[0061] acquiring the current bit error rate of the solid state disk at intervals of a first preset time;

[0062] comparing the bit error rate acquired each time with the preset bit error rate respectively;

[0063] in response to the bit error rate acquired at a certain time exceeding the preset bit error rate, starting the interleaving function of the current flash memory controller;

[0064] in response to the bit error rate acquired at a certain time not exceeding the preset bit error rate, stopping the interleaving function of the current flash memory controller.

[0065] In some embodiments, the method further comprises:

[0066] returning to execute the step of matching a target stage from the start stage, the intermediate stage and the end stage according to the usage information of the solid state disk at intervals of a second preset time, wherein the second preset time is much larger than the first preset time.

[0067] It should be noted that much larger generally means a difference of two orders of magnitude, for example, the second preset time is 100 times the first preset time, and in the specific implementation process, the multiple value of the two can be reasonably set according to the user's demand and the performance of the solid state disk.

[0068] In some embodiments, the method further comprises:

[0069] in response to the flash memory controller starting the interleaving function, starting multi-threading according to the actual performance of the solid state disk to perform grouped interleaving in parallel.

[0070] In another embodiment, in order to facilitate the understanding of the scheme of the present application, this embodiment takes a solid state disk using packet interleaving as an example to explain the implementation process of the flash memory controller configuration method of the present application in detail. The principle is that at the beginning stage (BOL) of the life cycle of the solid state disk, the interleaving function does not need to be started; at the middle stage (MOL) of the life cycle of the solid state disk, the interleaving function can be started according to the preset bit error rate; at the end stage (EOL) of the life cycle of the solid state disk, the bit error rate of the Nand Flash is larger, and the interleaving function can be started to maximize the dispersion of the error bits in the read data of the Nand Flash, thereby improving the probability of subsequent decoding success.

[0071] The process of scramble, crc, ldpc encode and interleaving processing on the data_group_in data group is shown in Figure 3 The processing process of the data_group_in data is briefly described as follows:

[0072] Step one, the first data_group_in data group is written into sram0 in sequence address, the second data_group_in data group is written into sram1 in sequence address, and according to the actual performance requirement of the SSD, N sram can be set, so that multiple data groups can be processed in parallel.

[0073] Step two, when the scramble operation is performed on the first data_group_in to make the 0 and 1 in the data uniform, sram0 is read in sequence and the read data is scrambled, and then the scrambled data is written back to sram0.

[0074] Step three, after the scramble of the first data_group_in is completed, the crc process is started, and the scramble processing of the second data_group_in data group can be performed at the same time. When the crc encoding is performed, the data in sram0 is read in sequence and the data is encoded, and then the crc processed data is written back to sram0.

[0075] Step four, after the crc of the first data_group_in is completed, the LDPC encode process is started, and the scramble or crc processing of other data groups can be performed at the same time. When the LDPC encoding is performed, the data in sram0 is read in sequence and the data is encoded, and then the LDPC encoded data is written back to sram0.

[0076] Step five, according to the stage of SSD life cycle and the preset bit error rate, when the interleaving function is needed, after the LDPC encoding of the first data_group_in is completed, start reading sram0 and perform interleaving processing on the read data using the memory: the data read from the sram is written into an array memory by row to form an interleaving matrix of M rows and N columns. Then read the data from the memory by column, the values of M and N can be selected in combination with the interleaving delay and system performance.

[0077] It should be noted that when the interleaving function is enabled, the data read from the Nand Flash should be de-interleaved first: the read data is written into an M*N array memory by column, and then read by row and written into sram, and then the ldpc decoding, crc and scramble operations are completed by sharing the sram resource. The processing of data_group_out data is opposite to the above process, and the specific implementation is referred to the processing process of data_group_in data.

[0078] The flash memory controller configuration method of the solid state disk of the embodiment combines grouping interleaving and the life cycle stage of the SSD, and flexibly starts or closes the grouping interleaving function. Specifically, in the SOF stage of the SSD life cycle, the original bit error rate is low, and the LDPC encoding and decoding function can meet the requirements of system reliability, and the interleaving function does not need to be enabled; in the MOL stage of the SSD, as the P / E cycle increases, the bit error rate increases, at this time, the interleaving function can be selected to be started according to the preset bit error rate, to disperse the continuous error bits and enhance the decoding performance; in the EOL stage of the SSD, the Nand Flash is affected by various factors to further increase the bit error rate, and sometimes the LDPC encoding and decoding function cannot fully meet the requirements of system error rate, so the use of the interleaving function can maximize the dispersion of error bits in the Nand Flash read data, improve the probability of subsequent decoding success, and further improve the reliability of the system.

[0079] In some embodiments, referring to Figure 4 The application further provides a flash memory controller configuration device 200 for a solid state disk, the device comprising:

[0080] A matching module 201 configured to match a target stage from a start stage, an intermediate stage and an end stage according to the use information of the solid state disk, the target stage being the current stage of the solid state disk in the life cycle;

[0081] A first judging module 202 configured to close the interleaving function of the flash memory controller in response to the target stage being the start stage;

[0082] a second determining module 203 configured to, in response to the target stage being the intermediate stage, periodically obtain a bit error rate of the solid-state drive, and compare the bit error rate with a preset bit error rate to determine whether to enable the interleaving function of the flash memory controller;

[0083] The third judgment module 204 is configured to enable the interleaving function of the flash memory controller in response to the target phase being the end phase.

[0084] The above-mentioned flash memory controller configuration device for a solid-state drive has a low original bit error rate at the beginning of the solid-state drive's life cycle, and the LDPC encoding and decoding function can meet the system reliability requirements, so there is no need to enable the above-mentioned interleaving function. In the middle stage of the solid-state drive's life cycle, the bit error rate increases with the increase of erase / write cycles. At this time, the interleaving function can be selected to be turned on according to the preset bit error rate to disperse continuous error bits and enhance decoding performance. At the end node stage of the solid-state drive's life cycle, the bit error rate of the flash memory is further increased due to various factors. Sometimes the LDPC encoding and decoding function cannot fully meet the system bit error rate requirements. Turning on the interleaving function can maximize the dispersion of error bits in the flash memory read data. Flexibly turning on or off the interleaving function in combination with the stage of the solid-state drive in its life cycle helps to increase the probability of subsequent decoding success and significantly improve the reliability of the solid-state drive.

[0085] In some embodiments, the matching module 201 is further configured to:

[0086] Get the current cumulative usage time of the solid-state drive;

[0087] The current accumulated usage duration is matched with the preset usage duration and the corresponding relationship between the start stage, the middle stage and the end stage to obtain the target stage.

[0088] In some embodiments, the second determining module 203 is further configured to:

[0089] Obtaining a current bit error rate of the solid state drive at first preset time intervals;

[0090] Comparing the bit error rate obtained each time with the preset bit error rate;

[0091] In response to a bit error rate obtained at a certain time exceeding the preset bit error rate, enabling an interleaving function of the current flash memory controller;

[0092] In response to a bit error rate obtained at a certain time not exceeding the preset bit error rate, the interleaving function of the current flash memory controller is disabled.

[0093] In some embodiments, the apparatus further comprises a returning module, configured to:

[0094] returning to execute the step of matching one of the start stage, the intermediate stage and the end stage as a target stage to which the solid state disk currently belongs in the life cycle according to the usage information of the solid state disk at intervals of a second preset time, wherein the second preset time is much greater than the first preset time.

[0095] In some embodiments, the apparatus further comprises a parallel execution module, configured to:

[0096] in response to the flash controller opening the interleaving function, starting multi-threading according to the actual performance of the solid state disk to execute the group interleaving in parallel.

[0097] It should be noted that the specific limitations of the flash controller configuration apparatus for the solid state disk can refer to the limitations of the flash controller configuration method for the solid state disk described above, which will not be repeated here. Each module in the above flash controller configuration apparatus for the solid state disk can be realized by software, hardware and their combinations. The above modules can be embedded in or independent of the processor in the computer device in hardware form, or can be stored in the memory in the computer device in software form, so as to call and execute the operations corresponding to each module by the processor.

[0098] According to another aspect of the present application, a computer device, which can be a server, is provided, and its internal structure diagram is shown in Figure 5 The computer device comprises a processor, a memory, a network interface and a database connected by a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device comprises a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with external terminals through network connection. The computer program is executed by the processor to implement the above-mentioned flash controller configuration method for the solid state disk. Specifically, the method comprises the following steps:

[0099] matching one of the start stage, the intermediate stage and the end stage as a target stage to which the solid state disk currently belongs in the life cycle according to the usage information of the solid state disk;

[0100] in response to the target stage being the start stage, closing the interleaving function of the flash controller;

[0101] in response to the target stage being the intermediate stage, periodically acquiring a bit error rate of the solid state disk, and comparing the bit error rate with a preset bit error rate to determine whether to turn on an interleaving function of the flash controller;

[0102] in response to the target stage being the end stage, turning on the interleaving function of the flash controller.

[0103] In some embodiments, a target stage is matched from the start stage, the intermediate stage and the end stage according to usage information of the solid state disk, so as to belong to a current time of the solid state disk in a life cycle, comprising:

[0104] acquiring a current usage cumulative duration of the solid state disk;

[0105] matching the current usage cumulative duration with a preset usage duration and a corresponding relationship of the start stage, the intermediate stage and the end stage to obtain the target stage.

[0106] In some embodiments, the bit error rate of the solid state disk is periodically acquired, and the bit error rate is compared with a preset bit error rate to determine whether to turn on the interleaving function of the flash controller, comprising:

[0107] acquiring the current bit error rate of the solid state disk at intervals of a first preset time;

[0108] respectively comparing the bit error rate acquired each time with the preset bit error rate in size;

[0109] in response to the bit error rate acquired at a certain time exceeding the preset bit error rate, turning on the interleaving function of the current flash controller;

[0110] in response to the bit error rate acquired at a certain time not exceeding the preset bit error rate, turning off the interleaving function of the current flash controller.

[0111] In some embodiments, the method further comprises:

[0112] returning to execute the step of matching a target stage from the start stage, the intermediate stage and the end stage according to the usage information of the solid state disk, so as to belong to a current time of the solid state disk in a life cycle, at intervals of a second preset time, wherein the second preset time is much greater than the first preset time.

[0113] In some embodiments, the method further comprises:

[0114] in response to the flash controller turning on the interleaving function, starting multi-thread according to the actual performance of the solid state disk to perform parallel grouping interleaving.

[0115] According to another aspect of the present application, there is provided a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the above-mentioned method for configuring a flash memory controller of a solid state disk, in particular comprising the following steps:

[0116] determining a target stage from the start stage, the intermediate stage and the end stage according to the usage information of the solid state disk, the target stage being a stage to which the solid state disk currently belongs in a life cycle;

[0117] in response to the target stage being the start stage, closing the interleaving function of the flash memory controller;

[0118] in response to the target stage being the intermediate stage, periodically acquiring a bit error rate of the solid state disk, and comparing the bit error rate with a preset bit error rate to determine whether to open the interleaving function of the flash memory controller;

[0119] in response to the target stage being the end stage, opening the interleaving function of the flash memory controller.

[0120] In some embodiments, the target stage is determined from the start stage, the intermediate stage and the end stage according to the usage information of the solid state disk, the target stage being a stage to which the solid state disk currently belongs in a life cycle, comprising:

[0121] acquiring a current cumulative usage duration of the solid state disk;

[0122] matching the current cumulative usage duration with a preset usage duration and a correspondence relationship between the start stage, the intermediate stage and the end stage to obtain the target stage.

[0123] In some embodiments, the bit error rate of the solid state disk is periodically acquired, and the bit error rate is compared with a preset bit error rate to determine whether to open the interleaving function of the flash memory controller, comprising:

[0124] acquiring the current bit error rate of the solid state disk at intervals of a first preset time;

[0125] respectively comparing the bit error rate acquired each time with the preset bit error rate in size;

[0126] in response to the bit error rate acquired at a certain time exceeding the preset bit error rate, opening the interleaving function of the current flash memory controller;

[0127] in response to the bit error rate acquired at a certain time not exceeding the preset bit error rate, closing the interleaving function of the current flash memory controller.

[0128] In some embodiments, the method further comprises:

[0129] Return to execute the step of matching one of the start stage, the intermediate stage and the end stage as the target stage to which the solid state disk currently belongs in the life cycle according to the use information of the solid state disk at intervals of a second preset time, wherein the second preset time is much larger than the first preset time.

[0130] In some embodiments, the method further comprises:

[0131] In response to the flash controller starting the interleaving function, starting multi-threading according to the actual performance of the solid state disk to perform the group interleaving in parallel.

[0132] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer readable storage medium, and when executed, can include the processes of the above-mentioned embodiments. Any reference to memory, storage, database or other medium used in the embodiments provided by the present application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0133] Any combination of the above technical features of the above embodiments can be combined. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combination of the technical features does not exist, it should be considered as the scope of the present application.

[0134] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, some modifications and improvements can be made, which are within the scope of the present application. Therefore, the scope of the patent of the present application should be subject to the appended claims.

Claims

1. A flash controller configuration method for a solid state drive, characterized by, The method comprises: According to the use information of the solid state disk, a target stage is matched from the start stage, the intermediate stage and the end stage, which belongs to the life cycle of the solid state disk at the current time; In response to the target stage being the start stage, the interleaving function of the flash memory controller is closed; In response to the target stage being the intermediate stage, the bit error rate of the solid state disk is periodically obtained, and the bit error rate is compared with the preset bit error rate to determine whether to open the interleaving function of the flash memory controller; In response to the target stage being the end stage, the interleaving function of the flash memory controller is opened; Periodically obtaining the bit error rate of the solid state disk and comparing the bit error rate with the preset bit error rate to determine whether to open the interleaving function of the flash memory controller comprises: The current bit error rate of the solid state disk is obtained at intervals of a first preset time; Each obtained bit error rate is compared with the preset bit error rate in size respectively; In response to the bit error rate obtained at a certain time exceeding the preset bit error rate, the interleaving function of the current flash memory controller is opened; In response to the bit error rate obtained at a certain time not exceeding the preset bit error rate, the interleaving function of the current flash memory controller is closed.

2. The method of claim 1, wherein, According to the use information of the solid state disk, a target stage is matched from the start stage, the intermediate stage and the end stage, which belongs to the life cycle of the solid state disk at the current time, comprising: The current use cumulative duration of the solid state disk is obtained; The current use cumulative duration is matched with the preset use duration and the corresponding relationship of the start stage, the intermediate stage and the end stage to obtain the target stage.

3. The method of claim 1, wherein, The method further comprises: The step of matching a target stage from the start stage, the intermediate stage and the end stage according to the use information of the solid state disk, which belongs to the life cycle of the solid state disk at the current time, is returned to be executed at intervals of a second preset time, wherein the second preset time is much larger than the first preset time.

4. The method of claim 1, wherein, The method further comprises: In response to the flash memory controller opening the interleaving function, multi-threading is started according to the actual performance of the solid state disk to perform grouping interleaving in parallel.

5. A flash memory controller configuration device for a solid state drive, characterized in that: The device comprises: A matching module is configured to match a target stage from the start stage, the intermediate stage and the end stage according to the use information of the solid state disk, which belongs to the life cycle of the solid state disk at the current time; A first judgment module is configured to close the interleaving function of the flash memory controller in response to the target stage being the start stage; A second judgment module is configured to periodically obtain the bit error rate of the solid state disk and compare the bit error rate with the preset bit error rate to determine whether to open the interleaving function of the flash memory controller in response to the target stage being the intermediate stage; A third judgment module is configured to open the interleaving function of the flash memory controller in response to the target stage being the end stage; The second judgment module is further configured to: The current bit error rate of the solid state disk is obtained at intervals of a first preset time; respectively, the bit error rate of each acquisition is compared with the preset bit error rate; in response to the bit error rate of a certain acquisition exceeding the preset bit error rate, the interleaving function of the current flash memory controller is turned on; in response to the bit error rate of a certain acquisition not exceeding the preset bit error rate, the interleaving function of the current flash memory controller is turned off.

6. The flash controller configuration apparatus for solid state hard drives of claim 5, wherein, The matching module is further configured to: acquire the current cumulative usage duration of the solid state disk; match the current cumulative usage duration with the preset usage duration and the corresponding relationship of the start stage, the intermediate stage and the end stage to obtain the target stage.

7. A computer device, characterized by comprise: at least one processor; and a memory, the memory storing a computer program executable in the processor, the processor executing the program to execute the flash memory controller configuration method for the solid state disk of any one of claims 1-4.

8. A computer-readable storage medium storing a computer program, the computer-readable storage medium comprising instructions that, when executed by a computer, cause the computer to perform the method of any one of claims 1 to 7. The computer program is executed by the processor to execute the flash memory controller configuration method for the solid state disk of any one of claims 1-4.

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