Apparatus and method for erasing data in a non-volatile memory device.

Abstract

This disclosure relates to an apparatus and method for erasing data in a non-volatile memory device. The memory device includes a plurality of non-volatile memory cells and control circuitry. The plurality of non-volatile memory cells can store data and are arranged in series between bit lines and source lines. During an erase operation for erasing data stored in the plurality of non-volatile memory cells, the control circuitry synchronizes the discharge of charge accumulated in the channel formed by the plurality of non-volatile memory cells through the bit lines and source lines.

Description

Technical Field

[0001] One or more embodiments described herein relate to a memory device, and more specifically, to an apparatus and method for erasing data stored in a non-volatile memory device. Background Technology

[0002] Recently, the paradigm of computing environments has shifted to ubiquitous computing, enabling access to computer systems virtually anytime, anywhere. Consequently, the use of portable electronic devices (e.g., mobile phones, digital cameras, laptops, etc.) has increased rapidly. Each of these devices can use or include a memory system having at least one memory device. The memory system can be a data storage device, for example, that can be used as a primary or secondary storage device.

[0003] Such data storage devices may include one or more non-volatile semiconductor memories that exhibit improved stability and durability, lack mechanically driven components (e.g., robotic arms), and therefore provide high data access speeds and relatively low power consumption. Examples of these types of data storage devices include, but are not limited to, Universal Serial Bus (USB) memory devices, memory cards with various interfaces, and solid-state drives (SSDs). Summary of the Invention

[0004] Embodiments of this disclosure may provide an apparatus and method for erasing data stored in a non-volatile memory device.

[0005] According to embodiments of this disclosure, when a high-level voltage is applied to a block containing multiple non-volatile memory cells during an erase operation for erasing data stored in a memory block in a non-volatile memory device, the high-level voltage applied to the block causes charge accumulation at the channels in the string. Because accumulated charge can have adverse effects, embodiments can provide apparatus and methods capable of synchronizing charge discharge in the channels via bit lines and common source lines.

[0006] Furthermore, according to embodiments of this disclosure, when the non-volatile memory device performs an erase operation, charge can be discharged from the serial channel through the bit line and common source line at the same speed or within a preset time difference. When the discharge rate on one side is faster than the discharge rate on the other side, a negative boost or undercoupling may occur where the word line is downwardly coupled to a negative voltage. Additionally, when the discharge rate on one side is slower than the other side, the data stored in the non-volatile memory cell may not be properly erased.

[0007] Furthermore, according to embodiments of this disclosure, when the charge in the channel of the string is discharged at the same speed or within a preset time difference through the bit line and the common source line during an erase operation performed in the non-volatile memory device, the memory device can uniformly control the characteristics of the non-volatile memory cells (which may vary depending on the location of the non-volatile memory cells (e.g., closer to the bit line or closer to the common source line)), thereby improving the operational reliability of the non-volatile memory cells.

[0008] In one embodiment, the memory device may include: a plurality of non-volatile memory cells capable of storing data and arranged in series between a bit line and a source line; and control circuitry configured to synchronize the discharge of charge accumulated in the channel formed by the plurality of non-volatile memory cells through the bit line and the source line during an erase operation for erasing data stored in the plurality of non-volatile memory cells.

[0009] The control circuit can be configured to control the voltage level applied to the transistor included in the channel or the amount of current flowing through the channel so that the discharge of charge in the channel through the bit line and the common source line is synchronized at the same speed or within a preset time difference.

[0010] The control circuit can be configured to adjust the second speed of discharge of charge through the bit line in response to the first speed of discharge of charge through the source line so as to synchronize the discharge of charge in the channel through the bit line and the source line.

[0011] The control circuit can be configured to change the voltage level applied to the gate of the second discharge transistor to adjust the second speed, the second discharge transistor being configured to apply a ground voltage to the bit line.

[0012] The control circuit can be configured to change the voltage level applied to the gate of the second discharge transistor to change the resistance of the second discharge transistor.

[0013] The memory device may further include a plurality of first discharge transistors, the plurality of first discharge transistors being independently configured to apply a ground voltage to the source line. Control circuitry may be configured to selectively turn on the plurality of first discharge transistors to control a first rate of discharge of charge through the source line, so as to synchronize the discharge of charge in the channel through the bit line and the source line.

[0014] The memory device may further include at least one second discharge transistor configured to apply a ground voltage to the bit line. Control circuitry may be configured to change the voltage level applied to the gate of the second discharge transistor in response to the conduction of a plurality of first discharge transistors, so as to synchronize the discharge of charge in the channel through the bit line and source line.

[0015] The memory device may further include: a plurality of first discharge transistors, the plurality of first discharge transistors being independently configured to apply a ground voltage to the source line; and a plurality of second discharge transistors, the plurality of second discharge transistors being independently configured to apply a ground voltage to the bit line. Control circuitry may be configured to selectively turn on the plurality of first discharge transistors and the plurality of second discharge transistors to synchronize the discharge of charge in the channel through the bit line and the source line.

[0016] The control circuit can be configured to turn on a larger number of the first discharge transistors than the number of the second discharge transistors that are turned on among the plurality of first discharge transistors.

[0017] The memory device may further include: a first discharge transistor configured to apply a ground voltage to a source line; and a second discharge transistor configured to apply a ground voltage to a bit line. Control circuitry may be configured to adjust the levels of a first voltage and a second voltage applied to the gates of the first and second discharge transistors to control a first rate of discharge of charge through the source line and a second rate of discharge of charge through the bit line, so as to synchronize the discharge of charge in the channel through the bit line and the source line.

[0018] A first voltage and a second voltage can be applied simultaneously. The first voltage can have a higher level than the second voltage.

[0019] In another embodiment, the memory system may include: a memory device configured to store data; and a controller coupled to the memory device and configured to send read commands, write commands, or erase commands regarding the data. The memory device may include: a plurality of non-volatile memory cells arranged in series between a bit line and a source line; and control circuitry configured to synchronize the discharge of charge accumulated in the channel formed by the plurality of non-volatile memory cells through the bit line and source line in response to an erase command.

[0020] The control circuit can be configured to control the voltage level applied to the transistor included in the channel or the amount of current flowing through the channel so that the discharge of charge in the channel through the bit line and the source line is synchronized at the same speed or within a preset time difference.

[0021] The control circuit can be configured to adjust the second speed of discharge of charge through the bit line in response to the first speed of discharge of charge through the source line so as to synchronize the discharge of charge in the channel through the bit line and the source line.

[0022] The control circuit can be configured to change the voltage level applied to the gate of the second discharge transistor to adjust the second speed, the second discharge transistor being configured to apply a ground voltage to the bit line.

[0023] The memory device may also include a plurality of first discharge transistors, which are independently configured to apply a ground voltage to the source line. Control circuitry may be configured to selectively turn on the plurality of first discharge transistors to control a first rate of charge discharge through the source line, so as to synchronize the discharge of charge in the channel through the bit line and the source line.

[0024] The memory device may further include at least one second discharge transistor configured to apply a ground voltage to the bit line. Control circuitry may be configured to change the voltage level applied to the gate of the second discharge transistor in response to the conduction of a plurality of first discharge transistors, so as to synchronize the discharge of charge in the channel through the bit line and source line.

[0025] The memory device may further include: a plurality of first discharge transistors, each independently configured to apply a ground voltage to a source line; and a plurality of second discharge transistors, each independently configured to apply a ground voltage to a bit line. Control circuitry may be configured to selectively turn on the plurality of first discharge transistors and the plurality of second discharge transistors to synchronize the discharge of charge in the channel through the bit line and the source line. The control circuitry is configured to turn on a greater number of the first discharge transistors than the number of the second discharge transistors that are turned on.

[0026] The memory device may further include: a first discharge transistor configured to apply a ground voltage to a source line; and a second discharge transistor configured to apply a ground voltage to a bit line. Control circuitry may be configured to adjust the levels of a first voltage and a second voltage applied to the gates of the first and second discharge transistors to control a first rate of discharge of charge through the source line and a second rate of discharge of charge through the bit line, so that the discharge of charge in the channel through the bit line and the source line is synchronized. The first voltage and the second voltage may be applied simultaneously. The first voltage may have a higher level than the second voltage.

[0027] In an implementation, a method for operating a memory system may include the following steps: in response to an erase command, determining the levels of an erase voltage and a gate voltage for erasing data stored in a plurality of non-volatile memory cells; applying an erase voltage to the block containing the plurality of non-volatile memory cells and applying a negative voltage or a 0V ground voltage to word lines connected to the plurality of non-volatile memory cells; controlling the path for discharging charge accumulated in a channel formed by the plurality of non-volatile memory cells through bit lines and source lines to synchronize the discharge rate or time through the bit lines and source lines; and verifying whether the data has been erased.

[0028] In another embodiment, a memory device may include: a string of non-volatile memory cells arranged in series between a bit line and a source line; a first discharge circuit configured to discharge the source line with a first discharge amount for a first discharge time length at a first time point by referring to a register configured to store information about a first time point, a first discharge amount, and a first discharge time length therein; a second discharge circuit configured to discharge the bit line with a second discharge amount for a second discharge time length at a second time point; and a control circuit configured to control the first and second discharge circuits to operate during an erase operation on the string by determining the second time point, the second discharge amount, and the second discharge time length based on the information. Attached Figure Description

[0029] The description herein refers to the accompanying drawings, in which the same reference numerals refer to the same parts throughout the drawings.

[0030] Figure 1 An example of a memory device according to an embodiment of the present disclosure is shown.

[0031] Figure 2 An example of a data processing system according to an embodiment of the present disclosure is provided.

[0032] Figure 3 An example is given of the phenomenon of charge generation in the channel during an erase operation performed in a memory device according to an embodiment of the present disclosure.

[0033] Figure 4 An example of a method for erasing data stored in a non-volatile memory cell according to an embodiment of the present disclosure is provided.

[0034] Figure 5 An example is shown of a circuit for controlling bit lines of a memory device according to an embodiment of the present disclosure.

[0035] Figure 6 An example of a circuit for controlling a common source line of a memory device according to an embodiment of the present disclosure is shown.

[0036] Figure 7 An example of channel discharge during an erase operation performed in a memory device according to an embodiment of the present disclosure.

[0037] Figure 8 An example is given of an operation in which charge is discharged in the channel of a string through the bit line and the common source line during an erase operation performed in a memory device according to an embodiment of the present disclosure.

[0038] Figure 9 An example is provided of a method for synchronizing discharges in a memory device via bit lines and a common source line, according to an embodiment of the present disclosure.

[0039] Figure 10 A first example of synchronizing discharges according to an embodiment of the present disclosure is shown.

[0040] Figure 11 A second example of synchronizing discharges according to an embodiment of the present disclosure is shown.

[0041] Figure 12 A third example of synchronizing discharges according to an embodiment of the present disclosure is shown. Detailed Implementation

[0042] Various embodiments of the present disclosure are described below with reference to the accompanying drawings. However, the elements and features of the present disclosure may be configured or arranged differently to form other embodiments, which may be variations of any of the disclosed embodiments.

[0043] In this disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment,” “example embodiment,” “implementation,” “another embodiment,” “some embodiments,” “various embodiments,” “other embodiments,” “alternative embodiments,” etc., are intended to indicate that any such feature is included in one or more embodiments of this disclosure, but may or may not be combined in the same embodiments.

[0044] In this disclosure, the terms “comprising,” “including,” “having,” and “containing” are open-ended. As used in the appended claims, these terms specify the presence of the stated element and do not exclude the presence or addition of one or more other elements. These terms in the claims do not exclude the inclusion of additional components (e.g., interface units, circuitry, etc.).

[0045] In this disclosure, various units, circuits, or other components may be described or claimed as being "configured to" perform one or more tasks. In such a context, "configured to" is used to imply a structure by indicating that a block / unit / circuit / component includes a structure (e.g., a circuit) that performs one or more tasks during operation. Thus, a block / unit / circuit / component may be referred to as being configured to perform a task even when the specified block / unit / circuit / component is not currently in operation (e.g., not turned on or activated). Blocks / units / circuits / components used with the language "configured to" include hardware (e.g., circuits, memory storing program instructions executable to perform operations, etc.). Additionally, "configured to" may include general structures (e.g., general-purpose circuits) manipulated by software and / or firmware (e.g., a general-purpose processor or FPGA executing software) to operate in a manner capable of performing the tasks in question. "Configured to" may also include adapting a manufacturing process (e.g., a semiconductor manufacturing facility) to manufacture means (e.g., integrated circuits) suitable for implementing or performing one or more tasks.

[0046] As used in this disclosure, the terms “circuit” or “logic” refer to all of the following: (a) a hardware circuit implementation only (such as an implementation only in analog and / or digital circuitry) and (b) a combination of circuitry and software (and / or firmware), such as (if applicable): (i) a combination of processors, or (ii) portions of processors / software (including digital signal processors), software, and memory that work together to enable a device (e.g., a mobile phone or server) to perform various functions, and (c) a circuit that requires software or firmware to operate (e.g., a microprocessor or a portion of a microprocessor), even if the software or firmware is not physically present. This definition of “circuit” or “logic” applies to all use cases of the term included in any claim in this application. As yet another example, as used in this application, the terms “circuit” or “logic” also cover only an implementation of a processor (or processors) or a portion of a processor and its accompanying software and / or firmware. The terms “circuit” or “logic” also cover (e.g., and if applicable to a particular claim element) integrated circuits for storage devices.

[0047] As used herein, the terms “first,” “second,” “third,” etc., are used as labels for the nouns that follow them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). The terms “first” and “second” do not necessarily imply that the first value must be written before the second value. Furthermore, while these terms may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element that would otherwise have the same or similar name. For example, a first circuit can be distinguished from a second circuit.

[0048] Furthermore, the term "based on" is used to describe one or more factors influencing a determination. This term does not exclude additional factors influencing the determination. That is, a determination may be based solely on these factors or at least partially on them. Consider the phrase "A is determined based on B." While B is a factor influencing the determination of A in this case, the phrase does not exclude the possibility that A is also determined based on C. In other cases, A may be determined solely based on B.

[0049] In this document, a data item, data entry, or data term can be a bit sequence. For example, a data item may include the contents of a file, a portion of a file, a page in memory, an object in an object-oriented program, a digital message, a digitally scanned image, a portion of a video or audio signal, metadata, or any other entity that can be represented by a bit sequence. According to one embodiment, a data item may include discrete objects. According to another embodiment, a data item may include information units within a transmission packet between two different components.

[0050] The embodiments described herein provide a data processing system and a method for operating the data processing system. The data processing system includes components and resources such as a memory system and a host, and is capable of dynamically allocating multiple data paths for data communication between components based on the use of components and resources.

[0051] Embodiments will now be described with reference to the accompanying drawings, wherein similar reference numerals denote similar elements.

[0052] Figure 1 An example of a memory device 150 according to an embodiment of the present disclosure includes a memory cell array circuit formed in a memory die.

[0053] Reference Figure 1 The memory device 150 may include at least one memory bank 330 having a plurality of cell strings 340. Each cell string 340 may include a plurality of non-volatile memory cells MC0 to MCn-1 connected to a corresponding one of a plurality of bit lines BL0 to BLm-1. The cell strings 340 are arranged in corresponding columns of the memory bank 330, and each cell string 340 may include at least one drain select transistor (DST) and at least one source select transistor (SST). The non-volatile memory cells MC0 to MCn-1 of each cell string 340 may be connected in series between the drain select transistor (DST) and the source select transistor (SST). Each of the non-volatile memory cells MC0 to MCn-1 may be configured as a multi-level cell (MLC), with each cell storing a data item having a plurality of bits. The cell strings 340 may be electrically connected to the corresponding bit lines BL0 to BLm-1.

[0054] In one embodiment, memory group 330 may include NAND flash memory cells MC0 to MCn-1. In another embodiment, memory group 330 may be implemented as a NOR flash memory, a hybrid flash memory in which at least two different types of memory cells are mixed or combined, or a monolithic NAND flash memory in which the controller is embedded in a single memory chip. In one embodiment, memory group 330 may include flash memory cells including a charge-trapped flash (CTF) layer having a conductive floating gate or insulating layer.

[0055] Figure 2 An example of a memory system 110 according to an embodiment of the present disclosure may include a memory device 150. In this embodiment, the memory group 330 in the memory device 150 may include one or more memory blocks 152, 154, 156. According to the embodiment, the memory device 150 may have a two-dimensional (2D) structure or a three-dimensional (3D) structure. For example, each of the memory blocks 152, 154, 156 in the memory device 150 may be implemented as a 3D structure (i.e., a vertical structure). Each of the memory blocks 152, 154, 156 may have a three-dimensional structure extending along a first direction to a third direction (e.g., the X-axis direction, the Y-axis direction, and the Z-axis direction).

[0056] Memory bank 330, comprising multiple memory blocks 152, 154, and 156, can be connected to multiple bit lines BL, multiple source select lines or string select lines SSL, multiple drain select lines DSL, multiple word lines WL, multiple dummy word lines DWL, and multiple common source lines CSL. In an embodiment, memory bank 330 may include, for example, multiple NAND strings NS that may correspond to cell strings 340 respectively. Each NAND string NS may include multiple memory cells MC and may be connected to corresponding bit lines in the bit lines BL. Additionally, the string select transistor SST of each NAND string NS may be connected to the common source line CSL, and the drain select transistor DST of each NAND string NS may be connected to the corresponding bit line BL. In each NAND string NS, the memory cells MC may be arranged between the string select transistor SST and the drain select transistor DST.

[0057] Reference Figure 1 and Figure 2The memory device 150 may include a voltage supply circuit 170, which can supply word line voltages (e.g., one or more predetermined voltages such as programming voltage, read voltage, and pass voltage) for corresponding word lines according to an operating mode, or can supply voltage to a bulk (e.g., a well region) in which each memory block comprising a memory cell MC is formed. In this case, the voltage generation operation of the voltage supply circuit 170 can be performed under the control of the control circuit 180. Furthermore, the voltage supply circuit 170 can generate multiple variable read voltages to distinguish multiple data items from each other.

[0058] In response to control by the control circuitry, one memory block or sector of the memory cell array can be selected, and one word line of the selected memory block can be selected. Word line voltages can be supplied independently to the selected word line and the unselected word line. The voltage supply circuitry 170 may include a voltage generating circuit for generating target voltages with various levels (e.g., see reference 170). Figures 4 to 8 ).

[0059] In one embodiment, the voltage supply circuit 170 may be connected to a first pin or pad that receives a first power supply voltage VCC applied from an external source (e.g., an external device), and a second pin or pad that receives a second power supply voltage VPP applied from an external device. The second power supply voltage VPP may have a higher voltage level than the first power supply voltage VCC (e.g., twice or more the voltage level of the first power supply voltage VCC). For example, the first power supply voltage VCC may have a voltage level of 2.0V to 5.5V, while the second power supply voltage may have a voltage level of 9V to 13V.

[0060] According to one embodiment, the voltage supply circuit 170 may include a voltage generating circuit for more quickly generating target voltages of various levels used in the memory bank 330. The voltage generating circuit may use a second supply voltage VPP to generate the target voltage, which may have a higher voltage level than the second supply voltage VPP.

[0061] The memory device 150 may further include a read / write circuit 320 controlled by the control circuit 180. The read / write circuit 320 may function as a sense amplifier or a write driver depending on the operating mode. For example, in verification and read operations, the read / write circuit 320 may function as a sense amplifier for reading data items from the memory cell array. In programming operations, the read / write circuit 320 may function as a write driver for controlling the potential of bit lines based on the data items to be stored in the memory cell array. The read / write circuit 320 may receive data items to be programmed into the cell array from a page buffer during programming operations. The read / write circuit 320 may drive bit lines based on the input data items. For this purpose, the read / write circuit 320 may include a plurality of page buffers (PB) 322, 324, 326, wherein each page buffer corresponds to each column or bit line, or to each column pair or bit line pair. According to embodiments, a plurality of latches may be included in each of the page buffers 322, 324, 326.

[0062] Page buffers 322, 324, and 326 can be connected to data input / output devices (e.g., serialization circuits or serializers) via multiple buses. When each of page buffers 322, 324, and 326 is connected to a data input / output device via a different bus, potential latency in data transmission from page buffers 322, 324, and 326 can be reduced. For example, each page buffer 322, 324, and 326 can perform data transmission without waiting time.

[0063] According to an embodiment, the memory device 150 may receive a write command, write data, and information about the location where the write data will be stored (e.g., a physical address). The control circuit 180 causes the voltage supply circuit 170 to generate programming pulses, pass voltages, etc., for a programming operation performed in response to the write command, and to generate one or more voltages for a verification operation performed after the programming operation.

[0064] When multi-bit data items are programmed into non-volatile memory cells included in memory bank 330, the error rate may be higher than when single-bit data items are stored in non-volatile memory cells. For example, errors in non-volatile memory cells may be induced due to cell-to-cell interference (CCI). To reduce errors in non-volatile memory cells, the width (deviation) of the threshold voltage distribution (corresponding to the stored data items) between non-volatile memory cells should be reduced.

[0065] To this end, the memory device 150 can perform incremental step pulse programming (ISPP) operations to effectively obtain a narrow threshold voltage distribution for the non-volatile memory cells. In an embodiment, the memory device 150 can use ISPP operations to perform multi-step programming operations. For example, the memory device 150 can divide the programming operation into least significant bit (LSB) programming operations and most significant bit (MSB) operations in a predetermined order between non-volatile memory cells or pages.

[0066] According to embodiments, an apparatus and method can be provided that can reduce the time for discharging bit lines or channels between programming pulse applications during data programming operations performed by applying multiple programming pulses to memory cells in a memory device. When the discharge time can be reduced, the speed of programming operations on the memory device can be increased. For example, to discharge bit lines or channels in the memory device, the memory device can control or adjust the voltage level of the bit line select line or drain select line (DSL) to prevent transistors from being in a floating state when controlled by the bit line select line or drain select line (DSL). This is because when transistors are in a floating state, the bit lines or channels may not be properly discharged.

[0067] In an embodiment, the memory device can adjust and change the set time for adjusting the potential of the bit line after the programming pulse is applied during a unit program operation of a non-volatile memory cell in the memory device. Therefore, apparatus and methods capable of increasing the speed and / or improving the efficiency of programming operations can be provided.

[0068] For example, during the operation of applying multiple programming pulses to a non-volatile memory cell in a memory device to program the non-volatile memory cell using multi-bit data, the memory device can perform a unit programming operation in one of a variety of modes, wherein a second programming pulse is applied after a first programming pulse has been applied.

[0069] The programming operation modes can include a first programming mode, a second programming mode, and a third programming mode. In the first programming mode, the degree to which data is programmed in response to a second programming pulse (e.g., a change or transition in the threshold voltage of the non-volatile memory cell when the second programming pulse is applied) can be similar to or greater than the degree to which data is programmed in response to a first programming pulse. In the second programming mode, the degree to which data is programmed in response to a second programming pulse is less than the degree to which data is programmed in response to a first programming pulse. In the third programming mode, there is no degree to which data is programmed in response to a second programming pulse (e.g., no change or transition in the threshold voltage of the non-volatile memory cell even when the second programming pulse is applied). The modes can be implemented based on the potential of the bit line connected to the target memory cell when the programming pulse is applied. If the discharge time can be reduced, the memory device can improve the efficiency or speed of the data programming operation by adjusting and changing the set time used to change or discharge the bit line potential.

[0070] According to an implementation, the memory device can change or adjust the control voltage applied via the bit line select line or drain select line (DSL) in response to the programming operating environment (e.g., temperature) and regarding the level (or magnitude) or number of programming pulses applied to the non-volatile memory cells during data programming operations. Therefore, the memory device can reduce the operating margin corresponding to each programming pulse during data programming operations by applying multiple programming pulses to the non-volatile memory cells. This can reduce the time spent performing data programming operations.

[0071] Refer again Figure 2 The memory device 150 is shown as being included in the data processing system 100. According to an embodiment, the data processing system 100 may include a host 102 that is coupled to or connected to a memory system (e.g., memory system 110). For example, the host 102 and the memory system 110 may be connected to each other via a data bus, host cable, etc., to perform data communication.

[0072] Memory system 110 may include memory device 150 and controller 130. Memory device 150 and controller 130 in memory system 110 may be considered as physically separate components or elements. Memory device 150 and controller 130 may be connected via at least one data path. For example, a data path may include a channel and / or a way.

[0073] According to embodiments, the memory device 150 and the controller 130 may be functionally separated components or elements. Furthermore, according to embodiments, the memory device 150 and the controller 130 may be implemented in a single chip or multiple chips. The controller 130 may perform data input / output operations in response to requests input from external devices. For example, when the controller 130 performs a read operation in response to a read request input from an external device, data stored in a plurality of non-volatile memory cells included in the memory device 150 is transferred to the controller 130.

[0074] exist Figure 2 In this configuration, memory device 150 may include one or more memory blocks 152, 154, and 156. Each of memory blocks 152, 154, and 156 can be understood as a group of non-volatile memory cells whose data is removed together by a single erase operation. Memory blocks 152, 154, and 156 may include at least one page (e.g., a group of non-volatile memory cells that store data together during a single programming operation and / or output data together during a single read operation). For example, a memory block may include multiple pages.

[0075] In one embodiment, the memory device 150 may include a plurality of memory planes or one or more memory dies. According to one embodiment, a memory plane may be considered a logical partition or a physical partition, which includes at least one memory block, drive circuitry capable of controlling an array of multiple non-volatile memory cells, and a buffer capable of temporarily storing data input to or output from the non-volatile memory cells.

[0076] According to an implementation, each memory die may include at least one memory plane and can be understood as a collection of components implemented on a physically distinguishable substrate. Each memory die may be connected to the controller 130 via a data path and may include an interface for exchanging data items and signals with the controller 130.

[0077] According to an embodiment, the memory device 150 may include at least one memory block 152, 154, 156, at least one memory plane, or at least one memory die. The internal configuration of the memory device 150 (e.g., Figure 1 (As shown) may vary depending on the performance of the memory system 110. Embodiments of this disclosure are not limited to... Figure 2 The internal configuration shown.

[0078] exist Figure 2In this context, memory device 150 includes a voltage supply circuit 170 capable of supplying one or more voltages to memory blocks 152, 154, and 156. The voltage supply circuit 170 may include methods for generating target voltages for memory blocks 152, 154, and 156 (e.g., as shown in reference 150). Figures 4 to 8 The voltage generating circuit described.

[0079] In this implementation, the voltage supply circuit 170 can provide a read voltage Vrd, a programming voltage Vprog, a pass voltage Vpass, or an erase voltage Vers to the non-volatile memory cells included in the memory blocks. For example, during a read operation for reading data stored in the non-volatile memory cells of memory blocks 152, 154, and 156, the voltage supply circuit 170 can provide the read voltage Vrd to the selected non-volatile memory cell. During a programming operation for storing data in the non-volatile memory cells of memory blocks 152, 154, and 156, the voltage supply circuit 170 can provide the programming voltage Vprog to the selected non-volatile memory cell. During a read or programming operation performed on a selected non-volatile memory cell, the voltage supply circuit 170 can provide the pass voltage Vpass to an unselected non-volatile memory cell. During an erase operation for erasing data stored in the non-volatile memory cells of memory blocks 152, 154, and 156, the voltage supply circuit 170 can provide the erase voltage Vers to the memory block.

[0080] The memory device 150 can store information about various voltages supplied to memory blocks 152, 154, and 156 based on which operation is being performed. For example, when the non-volatile memory cells in memory blocks 152, 154, and 156 can store multi-bit data, multiple levels of the read voltage Vrd can be used to identify or read multi-bit data items. The memory device 150 may include a table having information indicating multiple levels of the read voltage Vrd corresponding to multi-bit data items. For example, the table may include bias values ​​stored in a register, where each bias value corresponds to a specific level of the read voltage Vrd. The number of bias values ​​of the read voltage Vrd used for read operations can be limited to a preset range. Furthermore, in one embodiment, the bias values ​​can be quantized.

[0081] The host 102 may include a portable electronic device (e.g., a mobile phone, MP3 player, laptop computer, etc.) or a non-portable electronic device (e.g., a desktop computer, game console, television, projector, etc.). According to an embodiment, the host 102 may include a central processing unit (CPU) included in both portable and non-portable electronic devices.

[0082] Host 102 may include at least one operating system (OS) capable of controlling the functions and operations performed within host 102. The OS can provide interoperability between host 102, which is operationally coupled to memory system 110, and users who intend to store data in memory system 110. The OS can support functions and operations corresponding to user requests. By way of example and not limitation, the OS can be classified into general-purpose operating systems and mobile operating systems based on the mobility of host 102. General-purpose operating systems can be further divided into personal operating systems and enterprise operating systems based on system requirements or user environment. Compared to personal operating systems, enterprise operating systems can be specifically designed to ensure and support high-performance computing.

[0083] The mobile operating system may support services or functions for mobility (e.g., power-saving features). Host 102 may include multiple operating systems. Host 102 may execute multiple operating systems interlocked with memory system 110 corresponding to user requests. Host 102 may send multiple commands corresponding to user requests to memory system 110, thereby executing operations corresponding to the multiple commands within memory system 110.

[0084] The controller 130 can control the memory device 150 in response to requests or commands from the host 102. For example, the controller 130 can perform a read operation to provide data read from the memory device 150 to the host 102 and can perform a write operation (or programming operation) to store data input from the host 102 into the memory device 150. In order to perform data input / output (I / O) operations, the controller 130 can control and manage internal operations such as reading data, programming data, erasing data, etc.

[0085] According to an implementation, the controller 130 may include a host interface (I / F) 132, a processor 134, an error correction circuit (ECC) 138, a power management unit (PMU) 140, a memory interface (I / F) 142, and a memory 144. For example... Figure 2 The components in the controller 130 shown can vary depending on the structure, function, and operational performance of the memory system 110.

[0086] For example, memory system 110 can be implemented using any of a variety of storage devices electrically connected to host 102 according to a host interface protocol. Non-limiting examples of suitable storage devices include solid-state drives (SSDs), multimedia cards (MMCs), embedded MMCs (eMMCs), size-reduced MMCs (RS-MMCs), micro MMCs, secure digital cards (SDs), mini SDs, micro SDs, universal serial bus (USB) storage devices, universal flash memory (UFS) devices, compact flash memory (CF) cards, smart media (SM) cards, memory sticks, etc. Components may be added to or omitted from controller 130 depending on the implementation of memory system 110.

[0087] Each of the host 102 and the memory system 110 may include a controller or interface for sending and receiving signals, data, etc., according to one or more predetermined protocols. For example, the host interface 132 in the memory system 110 may include devices capable of sending signals, data, etc. to or receiving signals, data, etc. from the host 102.

[0088] Host interface 132 can receive signals, commands (or requests), and / or data input from host 102. For example, host 102 and memory system 110 can send and receive data between them using predetermined protocols. Examples of communication standards or interfaces for sending and receiving data supported by host 102 and memory system 110 include Universal Serial Bus (USB), Multimedia Card (MMC), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Peripheral Component Interconnect Express (PCIe or PCI-e), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Mobile Industry Processor Interface (MIPI), etc. Depending on the implementation, host interface 132 is a type of layer used for exchanging data with host 102 and implemented or driven using firmware called the Host Interface Layer (HIL).

[0089] Integrated Drive Electronics (IDE) or Advanced Technology Accessory (ATA) can be used as one of the interfaces for sending and receiving data, and a cable including 40 wires connected in parallel can be used, for example, to support data transmission and reception between host 102 and memory system 110. When multiple memory systems 110 are connected to a single host 102, the multiple memory systems 110 can be divided into master and slave devices using the positions or DIP switches to which they are connected. The memory system 110 set as the master device can be used as the primary memory device. IDE (ATA) can include, for example, Fast ATA, ATAPI, or Enhanced IDE (EIDE).

[0090] The Serial Advanced Technology Attachment (SATA) interface is a serial data communication interface compatible with various ATA standards for parallel data communication interfaces used by Integrated Drive Electronics (IDE). The 40 wires in an IDE interface can be reduced to six wires in a SATA interface. For example, 40 parallel signals for IDE can be converted to 6 serial signals for SATA. Due to its faster data transmission and reception rates and lower resource consumption, the SATA interface has been widely used in host 102 for data transmission and reception. The SATA interface can connect up to 30 external devices to a single transceiver included in host 102. Furthermore, the SATA interface supports hot-plugging, allowing external devices to be attached to or detached from host 102 even while data communication between host 102 and another device is in progress. Therefore, the memory system 110 can be connected or disconnected as an attachment device, similar to devices supported by Universal Serial Bus (USB), even when host 102 is powered on. For example, in a host 102 with an eSATA port, the storage system 110 can be freely attached to or removed from the host 102, similar to an external hard drive.

[0091] Small Computer System Interface (SCSI) is a serial data communication interface used to connect a computer or server to other peripheral devices. Compared to other interfaces such as IDE and SATA, SCSI offers high transmission speeds. In SCSI, the host 102 and at least one peripheral device (e.g., memory system 110) are connected in series, but data transmission and reception between the host 102 and each peripheral device can be performed through parallel data communication. With SCSI, devices such as memory system 110 can be easily connected to or disconnected from the host 102. SCSI can support connections of up to 15 other devices to a single transceiver included in the host 102.

[0092] Serial Attached SCSI (SAS) can be understood as a serial data communication version of SCSI. In SAS, the host 102 and multiple peripheral devices are connected in series, and data transmission and reception between the host 102 and each peripheral device can be performed using a serial data communication scheme. Furthermore, SAS can support the connection between the host 102 and peripheral devices via serial cables instead of parallel cables, making it easier to manage devices and enhance operational reliability and communication performance. In addition, SAS can support connections from up to eight external devices to a single transceiver included in the host 102.

[0093] Non-volatile memory Express (NVMe) is an interface based at least on Peripheral Component Interconnect Express (PCIe) designed to increase the performance and design flexibility of a host 102, server, computing device, etc., equipped with a non-volatile memory system 110. PCIe can use slots or specific cables for connecting computing devices (e.g., host 102) and peripheral devices (e.g., memory system 110). For example, PCIe can use multiple pins (e.g., 18 pins, 32 pins, 49 pins, or 82 pins) and at least one wire (e.g., x1, x4, x8, or x16) to achieve high-speed data communication of several hundred MB per second (e.g., 250 MB / s, 500 MB / s, 984.6250 MB / s, or 1969 MB / s). Depending on the implementation, PCIe schemes can achieve bandwidths from tens of gigabits per second to hundreds of gigabits per second. NVMe can support operating speeds of non-volatile memory systems 110 (e.g., SSDs) that are faster than hard drives.

[0094] According to one implementation, host 102 and memory system 110 can be connected via Universal Serial Bus (USB). Universal Serial Bus (USB) is a scalable, hot-pluggable, plug-and-play serial interface that provides a cost-effective standard connection between host 102 and peripheral devices such as keyboards, mice, joysticks, printers, scanners, storage devices, modems, video cameras, etc. Multiple peripheral devices, such as memory system 110, can be coupled to a single transceiver included in host 102.

[0095] Error correction circuit 138 can correct erroneous bits in data read from memory device 150 and may include an error correction code (ECC) encoder and an ECC decoder. The ECC encoder performs error correction encoding on the data to be programmed into memory device 150 to generate encoded data with parity bits added. The encoded data can be stored in memory device 150. When controller 130 reads data stored in memory device 150, ECC decoder can detect and correct erroneous bits contained in the data read from memory device 150. For example, after performing error correction decoding on data read from memory device 150, error correction circuit 138 determines whether error correction decoding was successful based on the result of the error correction decoding and outputs a command signal (e.g., a correction success signal or a correction failure signal). Error correction circuit 138 can use parity bits generated for the data stored in memory device 150 during the ECC encoding process to correct erroneous bits in the read data. When the number of error bits is greater than or equal to the number of correctable error bits, the error correction circuit 138 may not correct the error bits, but may instead output a correction failure signal indicating the failure to correct the error bits.

[0096] According to an implementation, the error correction circuit 138 can perform error correction operations based on coded modulation. Examples include low-density parity-check (LDPC) codes, Bosch-Chaudhuri-Hocquenghem (BCH) codes, turbo codes, Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), block-coded modulation (BCM), etc. The error correction circuit 138 may include all circuits, modules, systems, and / or devices for performing error correction operations based on at least one of the above-described codes. In one implementation, the error correction circuit 138 may include... Figure 1 At least some of the components in the controller 130 shown.

[0097] The ECC decoder can perform either hard decision decoding or soft decision decoding on data sent from memory device 150. Hard decision decoding can be understood as one of two methods broadly classified for error correction. Hard decision decoding may include, for example, correcting erroneous bits by reading '0' or '1' digital data from non-volatile memory cells in memory device 150. Because hard decision decoding processes binary logic signals, the circuit / algorithm design or configuration can be simpler and the processing speed can be faster compared to soft decision decoding.

[0098] Soft-decision decoding can quantize the threshold voltage of a non-volatile memory cell in memory device 150 using two or more quantization values ​​(e.g., multi-bit data, approximations, analog values, etc.) to facilitate the correction of erroneous bits based on the two or more quantization values. Controller 130 can receive two or more alphabetic or quantization values ​​from multiple non-volatile memory cells in memory device 150 and then perform decoding based on information generated by characterizing the quantization values ​​as a combination of information such as conditional probabilities or possibilities.

[0099] According to the implementation, the ECC decoder can use Low-Density Parity-Generator Matrix (LDPC-GM) codes from a method designed for soft-decision decoding. The LDPC code uses an algorithm that reads data values ​​in bits from memory device 150 based on reliability (instead of simply reading 1 or 0 data as in hard-decision decoding), and iteratively repeats this process through message exchange to improve the reliability of the values. These values ​​are then ultimately determined as 1 or 0 data. For example, the decoding algorithm using LDPC codes can be understood as probabilistic decoding. In hard-decision decoding, the values ​​output from non-volatile memory cells can be encoded as 0 or 1.

[0100] Compared to hard-decision decoding, soft-decision decoding can determine the value stored in a non-volatile memory cell based on random information. Regarding bit-flipping, which can be considered an error that may occur in memory device 150, soft-decision decoding can provide improved error correction and data recovery probability, as well as providing the reliability and stability of the corrected data. LDPC-GM codes can have schemes where the internal low-density generator matrix (LDGM) code can be cascaded with high-speed LDPC codes.

[0101] According to the implementation, the ECC decoder can use, for example, low-density parity-check convolutional codes (LDPC-CC) for soft-decision decoding. LDPC-CC can correspond to schemes using pipelined decoding and linear-time coding based on variable block length and shift registers.

[0102] According to the implementation, the ECC decoder can use, for example, a log-likelihood ratio Turbo code (LLR-TC) for soft-decision decoding. The log-likelihood ratio (LLR) can be calculated as a non-linear function of the distance between the sampled value and the ideal value. Alternatively, the Turbo code (TC) can include simple codes in two or three dimensions (e.g., Hamming codes), and the decoding is repeated in both the row and column directions to improve the reliability of the values.

[0103] The power management unit (PMU) 140 can control the power supplied to the controller 130. The PMU 140 can monitor the power supplied to the memory system 110 (e.g., the voltage supplied to the controller 130) and supply power to the components included in the controller 130. The PMU 140 can not only detect power on or off, but also generate a trigger signal to enable the memory system 110 to urgently back up its current state when the power supplied to the memory system 110 is unstable. According to embodiments, the PMU 140 may include means or components capable of accumulating power that can be used in emergency situations.

[0104] The memory interface 142 can be used as an interface for processing commands and data transferred between the controller 130 and the memory device 150, so as to allow the controller 130 to control the memory device 150 in response to commands or requests input from the host 102. When the memory device 150 is a flash memory, the memory interface 142 can generate control signals for the memory device 150 under the control of the processor 134, and can process data input to or output from the memory device 150.

[0105] For example, when the memory device 150 includes NAND flash memory, the memory interface 142 includes a NAND flash controller (NFC). The memory interface 142 provides an interface for processing commands and data transferred between the controller 130 and the memory device 150. According to an embodiment, the memory interface 142 may be implemented or driven by firmware called a flash interface layer (FIL) for exchanging data with the memory device 150.

[0106] According to the implementation, the memory interface 142 may support an Open NAND Flash Interface (ONFi) for data input / output with the memory device 150, switching modes, etc. For example, ONFi may use a data path (e.g., channel, path, etc.) including at least one signal line capable of supporting bidirectional transmission and reception in units of 8 bits or 16 bits of data. Data communication between the controller 130 and the memory device 150 may be implemented through at least one interface relating to Asynchronous Single Data Rate (SDR), Synchronous Double Data Rate (DDR), Toggle Double Data Rate (DDR), etc.

[0107] Memory 144 can be used as working memory for either memory system 110 or controller 130 while temporarily storing transactional data for operations performed in memory system 110 and controller 130. For example, memory 144 can temporarily store read data output from memory device 150 in response to a read request from host 102 before the read data is output to host 102.

[0108] Furthermore, the controller 130 can temporarily store write data input from the host 102 in the memory 144 before programming the write data into the memory device 150. When the controller 130 controls the operation of the memory device 150 (e.g., data read operation, data write or programming operation, data erase operation, etc.), data transmitted between the controller 130 and the memory device 150 of the memory system 110 can be temporarily stored in the memory 144.

[0109] In addition to reading or writing data, memory 144 may also store information (e.g., mapped data, read requests, programming requests, etc.) for inputting or outputting data between host 102 and memory device 150. According to embodiments, memory 144 may include one or more of a command queue, program memory, data memory, write buffer / cache, read buffer / cache, data buffer / cache, mapping buffer / cache, etc. Controller 130 may allocate some storage space in memory 144 for components established to perform data input / output operations. For example, a write buffer established in memory 144 may be used to temporarily store target data for programming operations.

[0110] In one implementation, memory 144 can be implemented using volatile memory. For example, memory 144 can be implemented using static random access memory (SRAM), dynamic random access memory (DRAM), or both. Although Figure 2 An example of a memory 144 disposed within the controller 130 is illustrated, but the implementation is not limited thereto. The memory 144 may be located within or outside the controller 130. For example, the memory 144 may be implemented by an external volatile memory having a memory interface for transferring data and / or signals between the memory 144 and the controller 130.

[0111] Processor 134 can control the overall operation of memory system 110. For example, processor 134 can control programming or reading operations of memory device 150 in response to a write or read request input from host 102. According to embodiments, processor 134 can execute firmware to control programming or reading operations in memory system 110. The firmware may be, for example, a flash translation layer (FTL). According to embodiments, processor 134 can be implemented using a microprocessor, a central processing unit (CPU), or another processing device.

[0112] According to one implementation, the memory system 110 may be implemented using at least one multi-core processor. A multi-core processor is a circuit or chip in which two or more cores, considered as different processing regions, are integrated. For example, when multiple cores in a multi-core processor independently drive or execute multiple flash translation layers (FTLs), the data input / output speed (or performance) of the memory system 110 can be improved. According to one implementation, data input / output (I / O) operations in the memory system 110 can be performed independently by different cores in the multi-core processor.

[0113] The processor 134 in the controller 130 can perform operations corresponding to requests or commands input from the host 102. Furthermore, the memory system 110 can perform operations independently of commands or requests input from the host 102. In one case, operations performed by the controller 130 in response to requests or commands input from the host 102 can be considered foreground operations, while operations performed by the controller 130 independently of requests or commands input from the host 102 can be considered background operations. The controller 130 can perform foreground or background operations to read, write, or erase data in the memory device 150. Additionally, parameter setting operations corresponding to setting feature commands or setting parameter commands sent from the host 102 can be considered foreground operations. As an example of a background operation that can be performed without commands sent from the host 102, the controller 130 can perform garbage collection (GC), wear leveling (WL), bad block management for identifying and handling bad blocks, etc.

[0114] According to the implementation, substantially similar operations can be performed as both foreground and background operations. For example, garbage collection can be considered a foreground operation when the memory system 110 performs garbage collection (e.g., manual GC) in response to a request or command input from the host 102. Garbage collection can be considered a background operation when the memory system 110 performs garbage collection independently of the host 102 (e.g., automatic GC).

[0115] When the memory device 150 includes multiple dies (or chips), each containing multiple non-volatile memory cells, the controller 130 can perform parallel processing on multiple requests or commands input from the host 102 to improve the performance of the memory system 110. For example, the sent requests or commands can be divided into multiple groups comprising at least some of the multiple planes, dies, or chips contained in the memory device 150, and the requests or commands in each group can be processed independently or in parallel in each plane, each die, or each chip.

[0116] The memory interface 142 in controller 130 can be connected to multiple dies or chips in memory device 150 via at least one channel and at least one path. When controller 130 allocates and stores data in multiple dies via each channel or path in response to a request or command associated with multiple pages including non-volatile memory cells, multiple operations corresponding to the request or command can be performed simultaneously or in parallel in multiple dies or planes. Such a processing method or scheme can be considered an interleaving method. Because the data input / output speed of memory system 110 is increased by utilizing the interleaving method, the data I / O performance of memory system 110 can be improved.

[0117] As an example and not a limitation, controller 130 can identify the status of multiple channels (or multiple paths) associated with multiple dies included in memory device 150. Controller 130 can determine the status of each channel or path as one of busy, ready, active, idle, normal, and abnormal states. The determination by controller 130 of which channel (and / or path) to pass instructions (and / or data) can be associated with a physical block address. Controller 130 can reference descriptors passed from memory device 150. Descriptors can include blocks or pages of parameters describing certain matters concerning memory device 150. Descriptors can have a predetermined format or structure. For example, descriptors can include device descriptors, configuration descriptors, unit descriptors, etc. Controller 130 can refer to or use descriptors to determine which channel(s)(s) is used to exchange instructions or data.

[0118] As described above, the memory device 150 in the memory system 110 may include one or more memory blocks 152, 154, and 156. Each of the memory blocks 152, 154, and 156 includes a plurality of non-volatile memory cells. According to an embodiment, each of the memory blocks 152, 154, and 156 may be a group of non-volatile memory cells that are erased together. The memory blocks 152, 154, and 156 may include a plurality of pages of a group of non-volatile memory cells that are read or programmed together.

[0119] In this implementation, each of the memory blocks 152, 154, and 156 may have a three-dimensional stacked structure for high integration. Furthermore, the memory device 150 may include multiple dies, each die including multiple planes, and each plane including memory blocks 152, 154, and 156. The configuration of the memory device 150 may be varied depending on the performance of the memory system 110.

[0120] exist Figure 2 In this embodiment, memory device 150 includes memory blocks 152, 154, and 156, which can be any of a single-level cell (SLC) memory block, a multi-level cell (MLC) memory block, etc., depending on the number of bits that can be stored in a single memory cell. An SLC memory block comprises multiple pages implemented from memory cells, with each memory cell storing one bit of data. SLC memory blocks can have higher data I / O performance and greater endurance than MLC memory blocks. An MLC memory block comprises multiple pages implemented from memory cells, with each memory cell storing multiple bits of data (e.g., two or more bits of data). Compared to SLC memory blocks, MLC memory blocks can have a larger storage capacity for the same space. MLC memory blocks can be highly integrated in terms of storage capacity.

[0121] In one embodiment, the memory device 150 may be implemented using MLC memory blocks (e.g., two-level cell (DLC) memory blocks, three-level cell (TLC) memory blocks, four-level cell (QLC) memory blocks, and combinations thereof). A DLC memory block may include multiple pages implemented from memory cells, where each memory cell is capable of storing 2 bits of data. A TLC memory block may include multiple pages implemented from memory cells, where each memory cell is capable of storing 3 bits of data. A QLC memory block may include multiple pages implemented from memory cells, where each memory cell is capable of storing 4 bits of data. In another embodiment, the memory device 150 may be implemented using blocks comprising multiple pages implemented from memory cells, where each memory cell is capable of storing five or more bits of data.

[0122] According to one implementation, the controller 130 can use an MLC (Multi-Level Cell) memory block included in the memory device 150 as an SLC (Simplified Level Cell) memory block to store one bit of data in a memory cell. The data input / output speed of a Multi-Level Cell (MLC) memory block can be slower than that of an SLC memory block. For example, when an MLC memory block is used as an SLC memory block, the margin for read or programmable operations can be reduced. For example, when an MLC memory block is used as an SLC memory block, the controller 130 can perform data input / output operations at a higher speed. Therefore, the controller 130 can use the MLC memory block as an SLC buffer to temporarily store data, since a buffer may require a high data input / output speed to improve the performance of the memory system 110.

[0123] According to one implementation, the controller 130 can program data into the MLC multiple times without performing an erase operation on a specific MLC memory block included in the memory device 150. Typically, non-volatile memory cells do not support data rewriting. However, the controller 130 can use the feature of the MLC being able to store multiple bits of data to program 1 bit of data into the MLC multiple times. For an MLC rewrite operation, when programming 1 bit of data into the MLC, the controller 130 can store the number of programming times as separate operation information. According to one implementation, an operation to uniformly equalize the threshold voltage of the MLCs (each MLC has one stored bit of data) can be performed before programming another 1 bit of data into the same MLC.

[0124] In one embodiment, the memory device 150 is implemented as a non-volatile memory such as flash memory, for example, NAND flash memory, NOR flash memory, etc. In another embodiment, the memory device 150 may be implemented by at least one of phase-change random access memory (PCRAM), ferroelectric random access memory (FRAM), spin-transfer torque random access memory (STT-RAM), and spin-transfer torque magnetic random access memory (STT-MRAM).

[0125] Figure 3 An example is given of the phenomenon of charge generation in the channel during an erase operation performed in a memory device according to an embodiment of the present disclosure. Specifically, Figure 3 As described in the example Figure 1 The cross-section of string 340 is described in the figure. The shape or thickness of the layers in the cross-section of string 340 can vary depending on the manufacturing process of memory device 150 and the characteristics of the (2D or 3D) structure of string 340.

[0126] Reference Figure 3The semiconductor substrate (P-sub) can be a P-type silicon semiconductor. A pouch-shaped P-type well region (Pp well) can be formed at a predetermined depth from the surface of the semiconductor substrate (P-sub). The pouch-shaped P-type well region (Pp well) can be surrounded by an N-type well region. Within the pouch-shaped P-type well region (Pp well), n+ doped regions doped with N-type impurities can be isolated from each other using channel regions interposed therebetween. The control gate of the non-volatile memory cell can be formed between the n+ doped regions.

[0127] During an erase operation, an erase voltage Vers, significantly higher than the supply voltage, can be applied to a block (Pp well) containing multiple non-volatile memory cells. When applying a high-level voltage to the block, the high voltage can also be applied to the bit line BL or the common source line CSL via a forward bias of the PN junction. Furthermore, the high-level voltage applied to the block can affect the n+ doped regions disposed between the control gates of the non-volatile memory cells. For example, the erase voltage Vers can have a level higher than 15V, while the supply voltage has a level lower than 3V to 5V. The transistor connecting the multiple non-volatile memory cells and the bit line BL or the common source line CSL can be a high-voltage transistor that is durable and operable under the applied high-level voltage. Additionally, the high-level voltage should not be applied directly to low-voltage circuitry (e.g., page buffers or bit line drivers operating with low supply voltages).

[0128] Reference Figure 1 and Figure 3 Due to the structure of memory device 150, when a high-level erase voltage Vers is applied to the block (Pp well) during an erase operation, charge can accumulate in the channel of series 340. Because the charge accumulated in the channel of series 340 may interfere with the erase operation, memory device 150 can apply a ground voltage to the bit line BL and the common source line CSL to discharge the charge accumulated in the channel through the bit line BL and the common source line CSL.

[0129] exist Figure 3 In the previous example, the erasure voltage Vers was applied to the block (Pp well). However, according to the implementation, the erasure voltage Vers can be applied to the bit line BL and the common source line CSL to erase data stored in multiple non-volatile memory cells.

[0130] Figure 4 An example of a method for erasing data stored in a non-volatile memory cell according to an embodiment of the present disclosure is provided.

[0131] Reference Figure 4 ,when Figure 2When the controller 130 sends an erase command to the memory device 150, the memory device 150 can begin an erase operation (operation 220). According to an embodiment, the controller 130 can send an address indicating at least one memory block along with the erase command to the memory device 150. The memory device 150 can determine the range from which the erase operation will be performed based on the address sent from the controller 130.

[0132] The memory device 150 can be configured to set the level of the erase voltage Vers to be applied to the well region corresponding to the memory block for an erase operation (operation 222). According to an embodiment, the level of the erase voltage Vers can be determined based on the operating characteristics of the non-volatile memory cell. Furthermore, the level of the erase voltage Vers can be adjusted according to the operating state of the memory device 150 (e.g., wear level) or operating conditions (e.g., temperature, etc.).

[0133] The memory device 150 can establish a gate voltage applied to each string in the memory block for an erase operation (operation 224). In this case, the gate voltage may include voltages applied to word lines connected to non-volatile memory cells and voltages applied through drain select line DSL and source select line SSL. Furthermore, the gate voltage may include control signals for determining whether a ground voltage is applied to the common source line CSL and bit line BL.

[0134] Once the levels of the erase voltage Vers and the gate voltage for the erase operation are determined, the determined voltage levels can be applied to the memory block (operation 226). When the erase voltage Vers is applied to the well region where the memory block resides and the gate voltage is applied via the word line connected to the memory block, the data stored in the non-volatile memory cells within the memory block can be erased.

[0135] Reference Figure 1 and Figures 3 to 4When the memory device 150 applies an erase voltage Vers to the well region where the memory block resides, charge accumulates in the channel of string 340. The memory device 150 can discharge the charge in the channel of string 340 (operation 228). According to an embodiment, in order to control the speed or time for discharging the charge in the channel of string 340, the memory device 150 can control the transistors configured to apply a ground voltage to bit line BL or common source line CSL. For example, the memory device 150 can adjust the level of the gate voltage applied to the gate of the transistor that applies a ground voltage to bit line BL or common source line CSL, or adjust the number of conducting transistors that apply a ground voltage to bit line BL or common source line CSL. The memory device 150 can control or change the path through which charge is discharged from the channel of string 340 to synchronize the speed or time of discharging the charge accumulated in the channel through bit line BL and common source line CSL.

[0136] The memory device 150 can verify whether the data stored in the memory block has been erased (operation 230). When data is erased from the memory block (operation 230 passed), the memory device 150 can terminate the erase operation (operation 234). On the other hand, when not all data in the memory block is erased (operation 230 fails), the memory device 150 can adjust or change the voltage level established for the erase operation (operation 232). For example, when data has not been erased, the level of the erase voltage Vers can be increased for the erase operation. Furthermore, according to an embodiment, the memory device 150 can determine that the gate voltage is not applied to the word line connected to the non-volatile memory cell in which data has not been erased. When the voltage applied for the erase operation is adjusted or changed (operation 232), the memory device 150 can apply a voltage with the adjusted level to the memory block (operation 226).

[0137] Figure 5 An example is shown of a circuit for controlling bit lines of a memory device according to an embodiment of the present disclosure.

[0138] Reference Figure 5 String 340 can be connected to the source line SL and the bit line BL. In this paper, the source line SL can be connected to the reference line. Figure 1 The description corresponds to the common source line CSL.

[0139] Bit line BL can be connected to page buffers 322, 324, and 326 (see reference) via the page buffer control signal PBSENSE. Figure 1 During a read or verification operation, the sensed data SO can be output via the bit line BL.

[0140] Bit line BL can be controlled by the bit line select signal SEL_BL. For example, the bit line select signal SEL_BL can output the data sent through bit line BL during a read operation, or apply a ground voltage VSSI to bit line BL during an erase operation.

[0141] In one implementation, the erase voltage Vers can be applied to bit line BL based on the erase voltage application signal VERASETOBL. Because the erase voltage Vers has a high voltage level, the erase voltage application signal VERASETOBL can be applied to a transistor designed to avoid operational problems even when a high voltage level is applied.

[0142] For example, when the erase voltage application signal VERASETOBL goes high (H) during the erase operation, the erase voltage Vers can be applied to bit line BL, and the bit line select signal SEL_BL can be low (L). When the time or operation interval for erasing data from the non-volatile memory cell has elapsed, the erase voltage application signal VERASETOBL can go low (L). Additionally, to discharge the charge accumulated in the channel of string 340, the bit line select signal SEL_BL and the bit line discharge signal BLDIS can be high (H). Through these methods, the charge accumulated in the channel of string 340 can be discharged, causing the channel potential to become 0V.

[0143] During the erase operation, a ground voltage VSSI can be applied to bit line BL to discharge the charge accumulated in the channel of series 340. The ground voltage VSSI can be applied to bit line BL when the bit line discharge signal BLDIS is activated. By adjusting the voltage level of the bit line discharge signal BLDIS, the speed or time of discharging the charge accumulated in the channel of series 340 through bit line BL can be adjusted or changed.

[0144] Figure 6 An example of a circuit for controlling a common source line of a memory device according to an embodiment of the present disclosure is shown.

[0145] Reference Figure 6 Multiple transistors are connected in parallel to the source line SL. The source line SL can be connected to a reference. Figure 1 The description corresponds to the common source line CSL. During the erase operation, an erase voltage Vers can be applied to the source line SL in response to the erase voltage application signal VERASETOSL. It can be applied to different locations. Figure 6 The described erase voltage application signal VERASETOSL and Figure 5The erase voltage application signal VERASETOBL described can be activated or deactivated simultaneously. Because the erase voltage Vers is high, the erase voltage application signal VERASETOSL can be applied to a transistor designed to avoid operational problems even when a high voltage is applied.

[0146] For example, when the erase voltage application signal VERASETOSL goes high (H) during the erase operation, the erase voltage Vers can be applied to the source line SL. When the time or operation interval for erasing data from the non-volatile memory cell has elapsed, the erase voltage application signal VERASETOSL can go low (L). Additionally, to discharge the charge accumulated in the channel of string 340, the source line discharge signals SLTOGND and SLTOGND_SLOW<0:2> can be high (H). This method discharges the charge accumulated in the channel of string 340, causing the channel potential to become 0V.

[0147] According to the implementation, all source line discharge signals SLTOGND and SLTOGND_SLOW<0:2> can be activated to rapidly discharge the charge accumulated in the channel of series 340. Alternatively, a portion of the source line discharge signals SLTOGND and SLTOGND_SLOW<0:2> can be activated to slowly discharge the charge accumulated in the channel of series 340. The number of transistors turned on to apply the ground voltage VSSI to the channel can vary based on how many source line discharge signals SLTOGND and SLTOGND_SLOW<0:2> are activated. This method allows adjustment or variation of the speed or time of discharging the charge accumulated in the channel of series 340 through the source line SL.

[0148] Reference Figure 5 and Figure 6 Because the components connected to bit line BL (e.g., page buffers, etc.) are included in memory device 150, it may be difficult to increase the number of transistors connected to bit line BL to discharge the charge accumulated in the channel of string 340 through bit line BL. However, a configuration that increases the number of transistors applying ground voltage to source line SL can be implemented more simply than a configuration that increases the number of transistors applying ground voltage to bit line BL.

[0149] Reference Figure 1Multiple non-volatile memory cells are connected to the page buffer via a single bit line BL. On the other hand, similar to the common source line CSL, the source line SL can be connected to multiple strings 340. Due to this structural difference, the parasitic capacitances present in the bit line BL and the common source line CSL can be different. For example, the parasitic capacitance of the common source line CSL can be greater than that of the bit line BL. Therefore, the rate or time at which the charge accumulated in the channel of the string 340 is discharged through the common source line CSL and the bit line BL can be different.

[0150] Figure 7 An example of channel discharge during an erase operation performed in a memory device according to an embodiment of the present disclosure.

[0151] Reference Figure 7 The memory device 150 can use erase voltage application signals VERASETOBL and VERASETOSL to apply an erase voltage Vers to the bit line BL and source line SL connected to the series 340 during an erase operation. When the erase voltage application signals VERASETOBL and VERASETOSL are applied, the potentials of the bit line BL and source line SL can continue to rise.

[0152] After the time or operation interval used to erase data from multiple non-volatile memory cells, the erase voltage application signals VERASETOBL and VERASETOSL are deactivated, and the charge accumulated in the channel of series 340 can be discharged through the bit line BL and the source line SL.

[0153] Reference Figure 7 The charge accumulated in the channel of series 340 discharges at different rates through the bit line BL and the source line SL, resulting in different slopes at which the potentials of the bit line BL and the source line SL drop to 0V. As described above, when the bit line discharge signal BLDIS is activated, the charge discharges rapidly through the bit line BL. However, the rate at which the charge is discharged through the source line SL can be controlled differently based on whether the source line discharge signals SLTOGND and SLTOGND_SLOW<0:2> are activated.

[0154] According to an embodiment, in order to synchronize the rate or time of discharging the charge accumulated in the channel in the string 340 through the bit line BL and the source line SL, the memory device 150 may use the source line discharge signals SLTOGND and SLTOGND_SLOW<0:2> to increase the rate of discharging the charge through the source line SL, or use the bit line discharge signal BLDIS to decrease the rate of discharging the charge through the bit line BL.

[0155] Figure 8An example is given of an operation in which charge is discharged in the channel of a string through the bit line and the common source line during an erase operation performed in a memory device according to an embodiment of the present disclosure.

[0156] Reference Figure 8 The charge accumulated in the channel of string 340 can be discharged through the bit line BL and the source line SL. When the charge accumulated in the channel is discharged after the erase voltage Vers or erase pulse is applied to string 340, a coupling capacitance can be formed between the channel and the word line. The coupling capacitance formed between the channel and the word line may cause the word line WL to be negatively down-coupled, resulting in a negative boost or undercoupling. In this case, the characteristics of the non-volatile memory cells may change depending on the location of the non-volatile memory cells in string 340. When the characteristics of the non-volatile memory cells differ, the operational reliability of memory device 150 may deteriorate. To avoid this problem, memory device 150 may slow down the discharge rate through the bit line BL and the source line SL. However, when the rate is slowed down, the performance of the erase operation may deteriorate.

[0157] In embodiments of this disclosure, when the charge in the channel of the series discharges through the bit line and the common source line, the first discharge rate of the charge through the bit line can be changed or adjusted in response to the second discharge rate of the charge through the source line, so that the first discharge rate and the second discharge rate (or the two discharge times) can be synchronized.

[0158] Figure 9 An example of a method for synchronizing discharges in a memory device via bit lines and a common source line, according to an embodiment of the present disclosure.

[0159] Reference Figure 9 This can increase (SL fast discharge) or decrease (SL slow discharge) the rate at which charge is discharged through the source line SL. For example, as Figure 6 As described, the rate at which charge is discharged through the source line SL in the channel of string 340 can be adjusted or changed based on the number of activation signals in the source line discharge signals SLTOGND and SLTOGND_SLOW<0:2>. In response to the rate at which charge is discharged through the source line SL, the memory device 150 applies a bit line discharge signal BLDIS having various levels of VREF1, VREF2, VREF3, and VREF4 during different time periods. This method allows for the adjustment or change of the rate at which charge is discharged through the bit line BL in the channel of string 340.

[0160] To synchronize the speed or timing of discharging accumulated charge in the channel of string 340 through bit line BL and source line SL, memory device 150 can store control information in a register. The control information for controlling the speed of charge discharge through source line SL may include how much the source line discharge signal SLTOGND is active and for how long SLTOGND_SLOW<0:2> is active. Based on the control information, memory device 150 can adjust or change the level of the bit line discharge signal BLDIS to control the speed of charge discharge through bit line BL. (Refer to...) Figure 9 When the estimated rate of charge discharge through the source line SL is fast (SL fast discharge), the memory device 150 can apply a first level VREF1 and a second level VREF2 to rapidly increase the level of the bit line discharge signal BLDIS. When the estimated rate of charge discharge through the source line SL is slow (SL slow discharge), the memory device 150 can apply a third level VREF3 and a fourth level VREF4 to slowly increase the level of the bit line discharge signal BLDIS. Depending on the applied voltage levels VREF1, VREF2, VREF3, and VREF4 to the bit line discharge signal BLDIS, the rate (or time) of charge discharge through the bit line BL can be increased or decreased (shortened or lengthened).

[0161] Reference Figures 10 to 12 The following describes an implementation for synchronizing the rate or time of discharging the charge accumulated in the channel of string 340 through bit line BL and source line SL.

[0162] Figure 10 A first example of synchronizing discharges according to an embodiment of the present disclosure is shown.

[0163] Reference Figure 10 To synchronize the speed or time of discharging the charge accumulated in the channel of series 340 through bit line BL and source line SL, the memory device 150 can increase the voltage level of the bit line discharge signal BLDIS as the number of transistors activated for discharging charge through source line SL increases. Here, the number of activated transistors can correspond to the number of activated signals in the source line discharge signals SLTOGND and SLTOGND_SLOW<0:2>.

[0164] For reference Figure 9 As described, the memory device 150 can identify the number of active signals in the source line discharge signals SLTOGND and SLTOGND_SLOW<0:2> by the values ​​stored in the register, and then control or adjust the level of the bit line discharge signal BLDIS based on the identified number.

[0165] Figure 11 A second example of synchronizing discharges according to an embodiment of the present disclosure is illustrated.

[0166] Reference Figure 11 To synchronize the speed or time of discharging the charge accumulated in the channel of series 340 through bit line BL and source line SL, memory device 150 can reduce the time for discharging charge through bit line BL as the number of transistors activated for discharging charge through source line SL increases. For example, memory device 150 can increase the voltage level (VREF level) of the bit line discharge signal BLDIS to reduce the time for discharging charge through bit line BL.

[0167] Figure 12 A third example of a method for synchronizing discharges according to an embodiment of the present disclosure is illustrated.

[0168] Reference Figure 12 The memory device 150 can synchronize the speed or time of discharging the charge accumulated in the channel of the series 340 through the bit line BL and source line SL based on the discharge current generated in the source line SL and bit line BL. (Refer to reference) Figure 10 The implementation methods for adjusting and changing the voltage level of the bit line discharge signal BLDIS described differ, according to the reference. Figure 12 The memory device 150 of the described embodiment can generate a control current or a reference current (current Ref) and apply the control current or reference current (current Ref) to a transistor for discharging charge through the source line SL and a transistor for discharging charge through the bit line BL. When the amount of the control current or reference current (current Ref) applied by the memory device 150 increases, the discharge rate can increase. When the amount of the control current or reference current (current Ref) decreases, the discharge rate can decrease. In the memory device 150, the control current or reference current (current Ref) applied to the transistor for discharging charge through the source line SL can be different from the control current or reference current (current Ref) applied to the transistor for discharging charge through the bit line BL. Even if these currents are different, they may have similar trends (e.g., both currents may increase or decrease together). That is, the memory device 150 can determine changes in the control current or reference current (current Ref) in the same direction of decrease or increase.

[0169] Reference Figures 10 to 12 According to an embodiment, in order to synchronize the speed or time of discharging the charge accumulated in the channel of the series 340 through the bit line BL and the source line SL, the memory device 150 may adjust or change the voltage level, current and / or discharge time.

[0170] As described above, when the memory device performs an erase operation, the memory device according to the embodiments of the present disclosure can discharge the charge already present in the channel of the string at the same rate through the bit line and the common source line, so that data can be erased more efficiently during the erase operation regardless of the location of the non-volatile memory cell.

[0171] Furthermore, the memory device according to the embodiments of the present disclosure can reduce the characteristic differences that may occur depending on the location of the non-volatile memory cell during the erase operation for erasing data stored in the non-volatile memory cell, thereby improving the operational reliability of the non-volatile memory cell.

[0172] The methods, processes, and / or operations described herein can be performed by code or instructions executed by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device can be those described herein or other than those described herein. Because the algorithms underlying the methods (or the operation of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the methods can transform the computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods herein.

[0173] In addition, another embodiment may include a computer-readable medium (e.g., a non-transitory computer-readable medium) for storing the aforementioned code or instructions. The computer-readable medium may be volatile or non-volatile memory or other storage devices that may be removably or permanently coupled to a computer, processor, controller or other signal processing device that is to execute the code or instructions for performing the operation or method implementation of the device implementation described herein.

[0174] The controllers, processors, control circuits, devices, modules, units, multiplexers, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features disclosed herein can be implemented, for example, in non-transitory logic that may include hardware, software, or both. When implemented at least partially in hardware, the controllers, processors, control circuits, devices, modules, units, multiplexers, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features can be, for example, any of a variety of integrated circuits, including but not limited to application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), combinations of logic gates, systems-on-a-chip (SoCs), microprocessors, or other types of processing or control circuitry.

[0175] When implemented at least partially in software, controllers, processors, control circuits, devices, modules, units, multiplexers, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features may include, for example, memory or other storage devices for storing code or instructions to be executed by, for example, a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be those described herein or other elements besides those described herein.

[0176] While this teaching has been illustrated and described with respect to specific embodiments, it will be apparent to those skilled in the art, based on this disclosure, that various changes and modifications can be made without departing from the spirit and scope of this disclosure as defined by the appended claims. Furthermore, embodiments may be combined to form other embodiments.

[0177] Cross-reference to related applications

[0178] This patent application claims the benefit of Korean Patent Application No. 10-2021-0093236, filed on July 16, 2021, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device, the memory device comprising: A cell string, comprising a plurality of non-volatile memory cells capable of storing data and arranged in series between a bit line and a source line; A plurality of first discharge transistors are connected in parallel to the source line to provide a first current path for discharging charge; At least one second discharge transistor, the at least one second discharge transistor being coupled to the bit line, is used to provide a second current path for discharging the charge accumulated in the channel formed through the cell string; as well as A control circuit that controls the plurality of first discharge transistors and the at least one second discharge transistor during an erase operation for erasing data stored in the plurality of nonvolatile memory cells to synchronize the discharge of the charge through the first current path, the second current path, the bit line, and the source line.

2. The memory device according to claim 1, wherein, The control circuit controls the voltage level applied to the plurality of first discharge transistors or the at least one second discharge transistor so that the discharge of the charge in the channel through the bit line and the source line is synchronized at the same speed or within a preset time difference.

3. The memory device according to claim 1, wherein, The control circuit adjusts a second discharge speed through the bit line in response to a first discharge speed through the source line, so that the discharge of the charge in the channel through the bit line and the source line is synchronized.

4. The memory device according to claim 3, wherein, The control circuit changes the voltage level applied to the gate of the at least one second discharge transistor to adjust the second speed, the second discharge transistor applying a ground voltage to the bit line.

5. The memory device according to claim 4, wherein, The control circuit changes the voltage level applied to the gate of the at least one second discharge transistor to change the resistance of the at least one second discharge transistor.

6. The memory device according to claim 1, in, The plurality of first discharge transistors independently apply a ground voltage to the source line. The control circuit selectively turns on the plurality of first discharge transistors to control the first speed at which the charge is discharged through the source line, so that the discharge of the charge in the channel through the bit line and the source line is synchronized.

7. The memory device according to claim 6, in, The at least one second discharge transistor applies the ground voltage to the bit line. The control circuit changes the voltage level applied to the gate of the at least one second discharge transistor in response to the conduction of the plurality of first discharge transistors, so as to synchronize the discharge of the charge in the channel through the bit line and the source line.

8. The memory device according to claim 1, wherein, The control circuit turns on a greater number of the first discharge transistors than the number of the at least one second discharge transistor turns on.

9. The memory device according to claim 1, in, The control circuit adjusts the levels of a first voltage and a second voltage applied to the gates of the plurality of first discharge transistors and the at least one second discharge transistor to control a first discharge rate of the charge through the source line and a second discharge rate of the charge through the bit line, so as to synchronize the discharge of the charge in the channel through the bit line and the source line.

10. The memory device according to claim 9, wherein, The first voltage and the second voltage are applied simultaneously, and the first voltage has a higher level than the second voltage.

11. A memory system, the memory system comprising: A memory device that stores data; as well as A controller, connected to the memory device, sends erase commands regarding the data. The memory device includes: A cell string, comprising a plurality of non-volatile memory cells, the plurality of non-volatile memory cells being arranged in series between a bit line and a source line; A plurality of first discharge transistors are connected in parallel to the source line to provide a first current path for discharging charge; At least one second discharge transistor, the at least one second discharge transistor being coupled to the bit line, is configured to provide a second current path for discharging charge accumulated in the channel formed through the cell string; and A control circuit that, in response to the erase command, controls the plurality of first discharge transistors and the at least one second discharge transistor to synchronize the discharge of the charge through the first current path, the second current path, the bit line, and the source line.

12. The memory system according to claim 11, wherein, The control circuit controls the voltage level applied to the plurality of first discharge transistors or the at least one second discharge transistor so that the discharge of the charge in the channel through the bit line and the source line is synchronized at the same speed or within a preset time difference.

13. The memory system according to claim 11, wherein, The control circuit adjusts a second discharge speed through the bit line in response to a first discharge speed through the source line, so that the discharge of the charge in the channel through the bit line and the source line is synchronized.

14. The memory system according to claim 13, wherein, The control circuit changes the voltage level applied to the gate of the at least one second discharge transistor to adjust the second speed, and the at least one second discharge transistor applies a ground voltage to the bit line.

15. The memory system according to claim 11, in, The plurality of first discharge transistors independently apply a ground voltage to the source line. The control circuit selectively turns on the plurality of first discharge transistors to control the first speed at which the charge is discharged through the source line, so that the discharge of the charge in the channel through the bit line and the source line is synchronized.

16. The memory system according to claim 15, in, The at least one second discharge transistor applies the ground voltage to the bit line. The control circuit changes the voltage level applied to the gate of the at least one second discharge transistor in response to the conduction of the plurality of first discharge transistors, so as to synchronize the discharge of the charge in the channel through the bit line and the source line.

17. The memory system according to claim 15, in, The control circuit adjusts the levels of a first voltage and a second voltage applied to the gates of the plurality of first discharge transistors and the at least one second discharge transistor to control a first discharge rate of the charge through the source line and a second discharge rate of the charge through the bit line, so that the discharge of the charge in the channel through the bit line and the source line is synchronized. In this case, the first voltage and the second voltage are applied simultaneously, and the first voltage has a higher level than the second voltage.

18. A method for operating a memory system, the method comprising the steps of: In response to an erase command, the levels of erase voltage and gate voltage for erasing data stored in a plurality of non-volatile memory cells are determined, the plurality of non-volatile memory cells being arranged in series between a bit line and a source line; An erase voltage is applied to the block containing the plurality of non-volatile memory cells, and a negative voltage or a 0 V ground voltage is applied to the word lines connected to the plurality of non-volatile memory cells; Controlling a plurality of first discharge transistors connected in parallel to the source line to provide a first current path and at least one second discharge transistor connected to the bit line to provide a second current path, for controlling the first current path and the second current path that discharge charge accumulated in the channel formed by the plurality of nonvolatile memory cells through the bit line and the source line, so as to synchronize the discharge rate or time through the bit line and the source line; as well as Verify whether the data has been erased.

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