Method for improving high resistance stability of polysilicon gate
By implementing a low-temperature alloying process in semiconductor manufacturing, phosphorus in the polycrystalline silicon gate is accelerated to escape, thus solving the problem of high resistance instability of the polycrystalline silicon gate and improving the stability and uniformity of the high resistance value.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUA HONG SEMICON WUXI LTD
- Filing Date
- 2022-11-10
- Publication Date
- 2026-06-02
AI Technical Summary
In the semiconductor large linewidth aluminum metal process, the high resistance of polysilicon gates is unstable. In particular, the high resistance of N-type polysilicon gates implanted with low dose of phosphorus is affected by the introduction of boron/phosphorus, resulting in high resistance with low uniformity.
A low-temperature alloying process is used to accelerate the escape of phosphorus from the first interlayer dielectric layer. By performing the low-temperature alloying process before the formation of the passivation layer, the phosphorus in the first interlayer dielectric layer is accelerated to escape into the external environment. Combined with the use of boron phosphorus tetraethyl orthosilicate and plasma-enhanced tetraethyl orthosilicate layers stacked from bottom to top, a multilayer dielectric structure is formed.
It significantly improves the high resistance stability and uniformity of polysilicon gates, ensuring that the high resistance value reaches the target value and reducing the fluctuation range.
Smart Images
Figure CN115621196B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and specifically to a method for improving the high-resistivity stability of polysilicon gates. Background Technology
[0002] In existing semiconductor large-linewidth aluminum metal process, when forming the interlayer dielectric layer on the substrate, the process of depositing boron phosphide tetraethyl orthosilicate (BPTEOS) and reflow is usually used to fill the gap between polysilicon gates. However, the introduction of boron / phosphorus affects the doping elements in the polysilicon gate, resulting in high resistance and instability of the polysilicon gate. In particular, the high resistance of the high-resistivity N-type polysilicon gate with low-dose phosphorus implantation is often lower than the target value and has poor uniformity due to the above process. Summary of the Invention
[0003] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a method to improve the high resistance stability of polysilicon gates, in order to solve the problem of high resistance instability of polysilicon gates when forming an interlayer dielectric layer on a substrate in the large linewidth aluminum metal process of the prior art.
[0004] To achieve the above and other related objectives, this application provides a method for improving the high-resistivity stability of polysilicon gates, comprising:
[0005] A substrate is provided on which multiple gate structures are formed;
[0006] A first interlayer dielectric layer is formed on the substrate, the first interlayer dielectric layer covers the gate structure and the substrate, and a metal interconnect structure is formed in the first interlayer dielectric layer;
[0007] Multiple top metal layers are formed on the first interlayer dielectric layer, and the top metal layers are electrically connected to the metal interconnect structure in the first interlayer dielectric layer.
[0008] A second interlayer dielectric layer is formed on the first interlayer dielectric layer, and the second interlayer dielectric layer completely covers the top surface and sidewalls of the top metal layer;
[0009] Implementing a low-temperature alloying process accelerates the escape of phosphorus from the first interlayer dielectric layer into the external environment;
[0010] A passivation layer is formed on the second interlayer dielectric layer.
[0011] Preferably, the first interlayer dielectric layer is composed of a boron phosphide tetraethyl orthosilicate layer and a plasma-enhanced tetraethyl orthosilicate layer stacked from bottom to top.
[0012] Preferably, the boron phosphide orthosilicate layer is formed using a deposition + reflow process.
[0013] Preferably, a plasma-enhanced tetraethyl orthosilicate layer is formed using a plasma-enhanced chemical vapor deposition process.
[0014] Preferably, the temperature for the low-temperature alloying process is 200℃~400℃.
[0015] Preferably, the second interlayer dielectric layer is composed of another plasma-enhanced tetraethyl orthosilicate layer.
[0016] Preferably, the passivation layer is composed of a silicon nitride layer.
[0017] Preferably, after forming the passivation layer, the method further includes etching the passivation layer on the top metal layer and the second interlayer dielectric layer to form a through opening on the top metal layer.
[0018] Preferably, after forming the opening, the process further includes filling the opening with metal to complete the fabrication of the pressure weld joint.
[0019] Preferably, after the pressure weld joint is made, another low-temperature alloying process is also performed.
[0020] As described above, the method for improving the high resistance stability of polysilicon gates provided in this application has the following beneficial effects: by performing a low-temperature alloying process before forming the passivation layer, the phosphorus in the first interlayer dielectric layer can be accelerated to escape into the external environment, which can significantly improve the stability of polysilicon high resistance. Attached Figure Description
[0021] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0022] Figure 1 The flowchart shown is a method for improving the high resistance stability of polysilicon gates according to an embodiment of this application.
[0023] Figures 2-6 The diagram shows a cross-sectional structure of the device formed after each step in the method for improving the high resistance stability of polysilicon gates provided in the embodiments of this application.
[0024] Figure 7 The figure shown is a data analysis diagram illustrating the improvement in the stability of high-resistivity polysilicon gates provided in this application embodiment compared to the prior art. Detailed Implementation
[0025] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this invention.
[0026] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0027] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," indicating orientation or positional relationships, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0028] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0029] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0030] In existing large-linewidth aluminum semiconductor manufacturing processes, the interlayer dielectric layer is typically formed on the substrate using a process of depositing tetraethyl orthosilicate borophosphide followed by reflow to fill the gaps between polysilicon gates. After forming the metal interconnect structure in the interlayer dielectric layer, a passivation layer (composed of silicon nitride) is formed on the interlayer dielectric layer to protect the semiconductor device from moisture, scratches, and contamination. Then, a cryogenic alloying process is performed to improve the electrical performance and reliability of the semiconductor device. Simultaneously, the heating process in the cryogenic alloying process can repair the gate oxide layer that has suffered plasma damage.
[0031] In order to improve the structural density of the deposited thin film, when forming an interlayer dielectric layer on a substrate, plasma processing and chemical vapor deposition processes are usually combined, such as plasma-enhanced chemical vapor deposition (PECVD) or high-density plasma chemical vapor deposition (HDPCVD) for thin film deposition.
[0032] Existing thin-film deposition techniques include the following steps: placing a substrate on an electrostatic chuck in a deposition chamber; introducing a reactive gas into the deposition chamber, turning on an RF source, and heating the reactive gas with low RF power; finally, ionizing the reactive gas with high RF power to form plasma, and depositing a thin film on the substrate. This process generates a large amount of free charge on the substrate surface. During the formation of the metal interconnect structure, the metal interconnect structure collects this free charge and transfers a large amount of charge to the gate structure, creating leakage current in the gate oxide layer below the gate structure. When the accumulated free charge reaches a certain amount, it discharges, causing plasma damage to the gate oxide layer and the interlayer dielectric layer, thereby reducing the breakdown performance of the semiconductor device. Therefore, after forming a passivation layer on the interlayer dielectric layer, a low-temperature alloying process is essential.
[0033] However, the boron / phosphorus introduced by the boron-phosphorus tetraethyl orthosilicate deposited during the formation of the interlayer dielectric layer can affect the doping elements in the polysilicon gate, leading to instability and high resistance of the polysilicon gate.
[0034] Taking a high-resistivity N-type polysilicon gate with low-dose phosphorus implantation as an example, the equilibrium concentration of phosphorus impurities in the polysilicon gate is greater than that in the interlayer dielectric layer. The implemented low-temperature alloying process redistributes the impurity concentration. The constituent materials of the interlayer dielectric layer (mainly silicon dioxide) repel impurities. Under the obstruction of the passivation layer formed on the interlayer dielectric layer, phosphorus cannot escape into the gaseous environment and accumulates on the surface of the polysilicon gate, making the high resistance of the phosphorus-doped polysilicon gate lower and unstable.
[0035] To address the aforementioned issues, this application provides a method for improving the high-resistivity stability of polysilicon gates.
[0036] Please see Figure 1 The document illustrates a flowchart of a method for improving the high-resistivity stability of polysilicon gates provided in an embodiment of this application.
[0037] In step S1, a substrate is provided on which a plurality of gate structures are formed.
[0038] like Figure 2As shown, a substrate 100 is provided. Optionally, the substrate 100 is a silicon substrate, a germanium substrate, or a silicon-on-insulator substrate, etc.; or the material of the substrate 100 may also include other materials, such as gallium arsenide or other III-V compounds. Those skilled in the art can select the constituent material of the substrate 100 according to the type of device structure formed on the substrate 100, therefore the type of substrate 100 should not limit the scope of protection of this invention.
[0039] A plurality of gate structures 101 are formed on the substrate 100. Exemplarily, each gate structure 101 includes a gate oxide layer and a gate material layer stacked from bottom to top, the gate material layer being polysilicon. Sidewall structures are formed on the sidewalls of the gate structures 101; for simplicity, they are not shown in the illustrations. Exemplarily, the sidewall structures can be one of silicon oxide, silicon nitride, and silicon oxynitride, or a combination thereof.
[0040] Multiple isolation components are formed on the substrate 100, dividing the substrate 100 into multiple regions, which are not shown in the illustrations for simplicity. The isolation components may be composed of any insulating material such as silicon dioxide (SiO2) or a "high-k" dielectric with a high dielectric constant, for example, greater than 3.9. In some cases, the isolation components may be composed of oxide materials. Suitable materials for constituting the isolation components include, for example, silicon dioxide (SiO2), hafnium oxide (HfO2), bauxite (Al2O3), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), titanium dioxide (TiO2), praseodymium oxide (Pr2O3), zirconium oxide (ZrO2), erbium oxide (ErOx), and other materials with similar properties, either currently known or developed later.
[0041] For example, the isolation component is formed by a shallow trench isolation process (STI), which includes, but is not limited to, shallow trench etching, oxide filling, and oxide planarization.
[0042] Shallow trench etching includes, but is not limited to, isolating oxide layers, nitride deposition, shallow trench isolation using masks, and STI shallow trench etching. STI oxide filling includes, but is not limited to, trench liner silicon oxide, trench CVD (chemical vapor deposition) oxide filling, or PVD (physical vapor deposition) oxide filling. Silicon wafer surface planarization can be achieved through various methods. Planarization can be achieved by using SOG (spin-on-glass) to fill the gaps. SOG can be composed of 80% solvent and 20% silicon dioxide. After deposition, the SOG is baked to evaporate the solvent, leaving the silicon dioxide in the gaps. Alternatively, the entire surface can be reverse-etched to reduce the overall wafer thickness. Planarization can also be effectively achieved through CMP (chemical mechanical polishing) processes, including but not limited to polishing the trench oxides (using chemical mechanical polishing) and nitride removal.
[0043] In areas of substrate 100 where silicide formation is not required, a silicide barrier layer is formed, which is not shown in the illustration for simplicity. For example, to improve device performance, a low-pressure chemical vapor deposition (LPTEOS) layer of tetraethyl orthosilicate is used as the silicide barrier layer.
[0044] Silicides, such as nickel-platinum alloys, are formed on the substrate 100 in regions such as the top of the gate structure 101, the source regions on both sides of the gate structure 101, and the drain regions. For simplicity, they are not shown in the illustration.
[0045] In step S2, a first interlayer dielectric layer is formed on the substrate. The first interlayer dielectric layer covers the gate structure and the substrate, and a metal interconnect structure is formed in the first interlayer dielectric layer.
[0046] like Figure 3 As shown, a first interlayer dielectric layer 102 is formed on a substrate 100. Exemplarily, the first interlayer dielectric layer 102 is formed on the substrate 100 by a deposition process.
[0047] The first interlayer dielectric layer 102 is formed in steps: First, a boron phosphide orthosilicate layer 102a is formed on the substrate 100 using a deposition + reflow process to fill the gaps between the gate structures 101; then, a plasma-enhanced orthosilicate (PETEOS) layer 102b is formed on the substrate 100 using a deposition process to cover the boron phosphide orthosilicate layer 102a; finally, a planarization process is performed to make the surface of the PETEOS layer 102b flat, for example, the planarization process is a chemical mechanical polishing process.
[0048] Next, a metal interconnect structure is formed in the first interlayer dielectric layer 102, which is not shown in the illustration for simplicity. Exemplarily, the metal interconnect structure includes several stacked metal interconnect layers, which can make electrical connections with the gate structure 101, the source region and the drain region on both sides of the gate structure 101 through contact with the silicide on the substrate 100 via structures such as plugs.
[0049] In step S3, a plurality of top metal layers are formed on the first interlayer dielectric layer, and the top metal layers are electrically connected to the metal interconnect structure in the first interlayer dielectric layer.
[0050] like Figure 4 As shown, a plurality of top metal layers 103 are formed on the first interlayer dielectric layer 102, and the top metal layers 103 are electrically connected to the metal interconnect structure in the first interlayer dielectric layer 102. For example, a metal layer is deposited on the first interlayer dielectric layer 102 and the metal layer is etched to form the top metal layer 103, and the deposition is physical vapor deposition.
[0051] In step S4, a second interlayer dielectric layer is formed on the first interlayer dielectric layer, and the second interlayer dielectric layer completely covers the top surface and sidewalls of the top metal layer.
[0052] like Figure 5 As shown, a second interlayer dielectric layer 105 is formed on the first interlayer dielectric layer 102, and the second interlayer dielectric layer 105 completely covers the top surface and sidewalls of the top metal layer 103. Exemplarily, another plasma-enhanced tetraethyl orthosilicate layer is formed on the first interlayer dielectric layer 102 as the second interlayer dielectric layer 105 using a deposition process.
[0053] In step S5, a low-temperature alloying process is performed to accelerate the escape of phosphorus from the first interlayer dielectric layer into the external environment.
[0054] like Figure 5 As shown, the lower part of the first interlayer dielectric layer 102 is a boron phosphide orthosilicate layer 102a. The boron / phosphorus introduced by the boron phosphide orthosilicate will affect the doping elements in the gate structure 101. Taking the gate material layer of the gate structure 101 as an example, which is made of low-dose phosphorus implanted polysilicon, the impurity equilibrium concentration of phosphorus in the polysilicon is greater than the equilibrium concentration in the first interlayer dielectric layer 102. The implemented low-temperature alloying process redistributes the impurity concentration, causing the phosphorus in the first interlayer dielectric layer 102 to escape into the external environment more quickly.
[0055] For example, the temperature of the low-temperature alloying process is 200℃~400℃.
[0056] In step S6, a passivation layer is formed on the second interlayer dielectric layer.
[0057] like Figure 6As shown, a passivation layer 106 is formed on the second interlayer dielectric layer 105 to protect the semiconductor device from moisture, scratches, and contamination. Exemplarily, the passivation layer 106 is formed on the second interlayer dielectric layer 105 using a deposition process, and the material of the passivation layer 106 is silicon nitride.
[0058] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this invention and are not drawn according to the actual number, shape and size of the components. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0059] Please see Figure 7 The diagram shows a data analysis of the improved stability of polysilicon gate high resistance provided in this application embodiment compared to the prior art.
[0060] like Figure 7 As shown in the figure, there are three lines: the lines connecting multiple rhombuses represent the differences in high resistance values between different points inside the wafer; the lines connecting multiple squares represent the differences in high resistance values between the same or different points on different wafers from the same batch; and the lines connecting multiple triangles represent the differences in high resistance values between the same or different points on wafers from different batches. Using the method for improving the high resistance stability of polysilicon gates provided in this application embodiment, the high resistance values at all points reach or approach the target value of 3000, and compared with the prior art, the fluctuation range of high resistance values is significantly reduced, and the stability is significantly improved.
[0061] In summary, the method for improving the high resistivity stability of polysilicon gates provided in this application can significantly improve the stability and uniformity of polysilicon high resistivity. Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial applicability.
[0062] Next, the passivation layer 106 and the second interlayer dielectric layer 105 on the top metal layer 103 are etched to form a through opening in the top metal layer 103, thereby connecting the top metal layer 103 to the outside world. Metal is then filled into the opening to complete the fabrication of the bonding joint.
[0063] Because the patterns of the multiple top metal layers 103 are not completely identical, the sum of the thickness of the passivation layer 106 and the thickness of the second interlayer dielectric layer 105 on different patterns of the top metal layers 103 is different. During the etching process to form the opening, when a part of the area forms a through opening to expose the top metal layer 103, the top metal layer 103 in another part of the area is not exposed. Continue etching to form a through opening on the top metal layer 103 in all areas. During this continued etching process, the part of the top metal layer 103 that was exposed earlier will continue to collect free charges on the device surface, forming a potential difference with the other part of the top metal layer 103, resulting in leakage current. This causes plasma damage to the interlayer dielectric layer and the gate oxide layer in the gate structure 101.
[0064] Another low-temperature alloying process is performed on the substrate 100 to improve the electrical performance and reliability of the device. The heating process in this other low-temperature alloying process can repair the aforementioned interlayer dielectric layer and gate oxide layer in the gate structure 101 that have suffered plasma damage.
[0065] After implementing this other cryogenic alloying process, the wafer is tested. The tested wafers are then used for individual chip assembly and packaging. These processes, performed in the final assembly and packaging, are called back-end processes, which also include primary packaging and secondary packaging. Primary packaging includes back-side thinning, wafer slitting, mounting, and wire bonding processes.
[0066] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this invention should still be covered by the claims of this application.
Claims
1. A method for improving polysilicon gate high resistance stability, characterized in that, The method includes: A substrate is provided on which a plurality of gate structures are formed; A first interlayer dielectric layer is formed on the substrate, the first interlayer dielectric layer covering the gate structure and the substrate, and a metal interconnect structure is formed in the first interlayer dielectric layer; Multiple top metal layers are formed on the first interlayer dielectric layer, and the top metal layers are electrically connected to the metal interconnect structure in the first interlayer dielectric layer. A second interlayer dielectric layer is formed on the first interlayer dielectric layer, and the second interlayer dielectric layer completely covers the top surface and sidewalls of the top metal layer; A low-temperature alloying process is implemented to accelerate the escape of phosphorus in the first interlayer dielectric layer into the external environment. The temperature of the low-temperature alloying process is 200℃~400℃. A passivation layer is formed on the second interlayer dielectric layer.
2. The method of claim 1, wherein, The first interlayer dielectric layer is composed of a boron phosphorus tetraethyl orthosilicate layer and a plasma-enhanced tetraethyl orthosilicate layer stacked from bottom to top.
3. The method according to claim 2, characterized in that, The boron phospho orthosilicate layer is formed using a deposition and reflow process.
4. The method according to claim 2, characterized in that, The plasma-enhanced tetraethyl orthosilicate layer was formed using a plasma-enhanced chemical vapor deposition process.
5. The method according to claim 1, characterized in that, The second interlayer dielectric layer is composed of another plasma-enhanced tetraethyl orthosilicate layer.
6. The method according to claim 1, characterized in that, The passivation layer is composed of a silicon nitride layer.
7. The method according to claim 1, characterized in that, After forming the passivation layer, the method further includes etching the passivation layer on the top metal layer and the second interlayer dielectric layer to form a through opening on the top metal layer.
8. The method according to claim 7, characterized in that, After the opening is formed, the process further includes filling the opening with metal to complete the fabrication of the pressure weld joint.
9. The method according to claim 8, characterized in that, After the welding point is fabricated, the process includes another low-temperature alloying process, wherein the temperature of the other low-temperature alloying process is 200℃~400℃.