Chip packaging method and semiconductor packaging structure

Abstract

The application relates to a chip packaging method and a semiconductor packaging structure. The chip packaging method bonds at least one effective chip and at least one deep-groove capacitor chip to one side surface of a first device substrate respectively, wherein the effective chip is electrically connected to electronic components on the first device substrate through the bonding, and the deep-groove capacitor chip makes full use of the surface outside the effective chip bonding area on the first device substrate, helps to increase the integration density of the semiconductor packaging structure, can improve the capacitance density of the semiconductor packaging structure, improves the high-frequency signal stability, and helps to improve the performance of the semiconductor packaging structure. The semiconductor packaging structure can be formed by using the above chip packaging method.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a chip packaging method and a semiconductor packaging structure. BACKGROUND

[0002] Chip to Wafer (C2W) technology is favored by global semiconductor manufacturers because it is not limited by chip size matching, and its Known Good Die (KGD) solution can greatly improve yield.

[0003] In an advanced packaging process, C2W technology is used to bond effective chips to a device substrate, and dummy dies are bonded in the gaps of the device substrate, and another device substrate can also be bonded on the effective chips and the dummy dies, and according to needs, the device substrate is cut vertically, and the unnecessary part is removed, and finally a semiconductor packaging structure is obtained, wherein the setting of the dummy dies can ensure the bonding area and the bonding strength. However, the setting of the dummy dies does not fully utilize the surface area of the substrate, resulting in a low integration density of the finally obtained semiconductor packaging structure, and the performance still needs to be improved. SUMMARY

[0004] In order to fully utilize the surface area of the substrate and improve the performance of the semiconductor packaging structure, the present application provides a chip packaging method, and further provides a semiconductor packaging structure.

[0005] In one aspect, the present application provides a chip packaging method, comprising:

[0006] providing a first device substrate, wherein electronic components are formed on the first device substrate; and

[0007] bonding at least one effective chip and at least one deep trench capacitor chip to one side surface of the first device substrate, wherein through the bonding, the effective chip is electrically connected to the electronic components on the first device substrate.

[0008] Optionally, the chip packaging method further comprises:

[0009] forming a filling material in the gap between the effective chip and the deep trench capacitor chip;

[0010] forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the effective chip and the deep trench capacitor chip; and

[0011] forming a metal interconnection layer on the interlayer dielectric layer, wherein the metal interconnection layer is electrically connected to the effective chip through a contact plug penetrating through the interlayer dielectric layer.

[0012] Optionally, the chip packaging method further comprises:

[0013] forming a bonding layer on the metal interconnection layer; and

[0014] bonding a second device substrate on a side of the bonding layer away from the first device substrate, the second device substrate having electronic components formed thereon, the electronic components on the second device substrate being electrically connected to the active chip through the bonding.

[0015] Optionally, the chip packaging method further comprises: stacking other deep trench capacitor chips above the active chip and / or the deep trench capacitor chip.

[0016] Optionally, micro-bump bonding or hybrid bonding is used when bonding the active chip and / or the deep trench capacitor chip to the first device substrate.

[0017] Optionally, at least one deep trench capacitor is formed on a surface of the first device substrate.

[0018] Optionally, at least part of the deep trench capacitor chips are bonded to the deep trench capacitors and connected in parallel with the corresponding deep trench capacitors.

[0019] Optionally, the area bonded with all the active chips accounts for less than or equal to 50-85% of the surface of the first device substrate.

[0020] In one aspect, the present application provides a semiconductor packaging structure, which comprises:

[0021] a first device substrate having electronic components formed thereon; and

[0022] at least one active chip and at least one deep trench capacitor chip bonded to a side surface of the first device substrate, wherein the active chip is electrically connected to the electronic components on the first device substrate through the bonding.

[0023] Optionally, the semiconductor packaging structure further comprises:

[0024] an interlayer dielectric layer covering the active chip and the deep trench capacitor chip;

[0025] a metal interconnection layer on the interlayer dielectric layer, the metal interconnection layer being electrically connected to the active chip through a contact plug penetrating the interlayer dielectric layer;

[0026] a bonding layer on the metal interconnection layer; and

[0027] a second device substrate bonded with the first device substrate on a side of the bonding layer away from the first device substrate, electronic components formed on the second device substrate, and the electronic components on the second device substrate being electrically connected with the effective chip through the bonding.

[0028] The chip packaging method and the semiconductor packaging structure provided by the application can make the effective chip and the deep trench capacitor chip bonded with one side surface of the first device substrate, and the effective chip is electrically connected with the electronic components on the first device substrate through the bonding, the deep trench capacitor chip makes the surface outside the bonding area of the effective chip on the first device substrate fully utilized, which helps to increase the integration density of the semiconductor packaging structure, improve the capacitance density, improve the stability of high-frequency signals, and improve the performance of the semiconductor packaging structure. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 is a cross-sectional structure schematic diagram of the deep trench capacitor chip and the deep trench capacitor in an embodiment of the application.

[0030] Figure 2 is a flowchart of the chip packaging method in an embodiment of the application.

[0031] Figures 3A to 3F is a cross-sectional structure schematic diagram of the chip packaging method in an embodiment of the application at multiple steps.

[0032] BRIEF DESCRIPTION OF DRAWINGS

[0033] 101-first recess; 102-second recess; 103-first dielectric layer; 104-first conductive layer; 104a-first conductive plug; 105-second dielectric layer; 106-second conductive layer; 106a-second conductive plug; 107-oxide layer; 108-interlayer dielectric layer; 100-first device substrate; 110-deep trench capacitor; 120-effective chip; 130-deep trench capacitor chip; 140-filling material; 150-interlayer dielectric layer; 151-contact plug; 160-metal interconnection layer; 170-bonding layer; 200-second device substrate. DETAILED DESCRIPTION

[0034] The chip packaging method and the semiconductor packaging structure of the application will be further described in detail below in combination with the drawings and specific embodiments. The advantages and features of the application will be more apparent according to the following description. It should be understood that the drawings of the specification are very simplified and use non-precise proportions, which are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the application.

[0035] It should be noted that the terms "first", "second", and the like in the following refer to distinguishing between like elements in a similar manner, and do not necessarily imply a sequence or order of importance, unless specifically so defined by the context of the specification. It is to be understood that the terms so used are interchangeable under appropriate circumstances and embodiments of the application described herein are capable of operating according to other sequences or orders than described or illustrated herein. Similarly, it should be understood that any numerical range recited in this specification is intended to include all sub-ranges of the same numbers except specifically recited, even though these are not expressly stated. Also, it is to be understood that such ranges are not limited to exact values, but rather are intended to encompass a reasonable range or ranges preceding or following the recited ranges. Also, it is to be understood that the use of "or" in the descriptions herein is used to represent that at least one of the items will be employed in the compositions, articles, processes, and methods, for or with which the application is concerned and any and all combinations of two or more of the items can be employed. The text "at least one" and like terms should be interpreted in the same manner.

[0036] The chip packaging method and semiconductor packaging structure of embodiments of the present application relate to deep trench capacitors (DTCs), which are capacitors formed in trenches of a semiconductor substrate, and have a higher power density than some other capacitor types employed in semiconductor integrated circuits. Figure 1 A cross-sectional structure of a deep trench capacitor chip and a deep trench capacitor in an embodiment of the present application is shown. However, it should be understood that the deep trench capacitor chip and deep trench capacitor in embodiments of the present application are not limited to Figure 1 the structure shown, but can employ many different types of structures.

[0037] Referring to Figure 1 , for example, the deep trench capacitor chip and deep trench capacitor in the following embodiments can include:

[0038] a first recess 101 and a second recess 102 formed in a substrate;

[0039] a first dielectric layer 103 covering inner walls of the first recess 101 and the second recess 102 and a surface of the substrate, the first dielectric layer 103 can include at least one of silicon oxide, silicon nitride, and silicon oxynitride;

[0040] a first conductive layer 104 deposited on the first dielectric layer 103, the first conductive layer 104 can include doped polysilicon;

[0041] a second dielectric layer 105 deposited on the first conductive layer 104, the second dielectric layer 105 can include at least one of silicon oxide, silicon nitride, and silicon oxynitride;

[0042] a second conductive layer 106 deposited on the second dielectric layer 105 and filling remaining voids of the first recess 101 and the second recess 102, the second conductive layer 106 can include doped polysilicon, i.e., the second dielectric layer 105 is disposed between and separates the first conductive layer 104 and the second conductive layer 106;

[0043] The oxide layer 107 and the interlayer dielectric layer 108 stacked thereon, in which a first conductive plug 104a connected to the first conductive layer 104 and a second conductive plug 106a connected to the second conductive layer 106 are formed.

[0044] The chip packaging method of an embodiment of the present application includes the following processes.

[0045] Figure 3A is a schematic cross-sectional view of a first device substrate in a chip packaging method of an embodiment of the present application. Referring to Figure 2 and Figure 3A , first, step S1 is performed to provide a first device substrate 100 on which electronic components are formed.

[0046] The first device substrate 100 is, for example, a silicon wafer, and the electronic components formed on the first device substrate 100 can include at least one of MOS components, sensor components, memory components, and passive components. The sensor components can be light-sensing components or the like, the memory components can include non-volatile memories or random memories or the like, the non-volatile memories can include floating gate memories such as NOR-type flash memories or NAND-type flash memories or ferroelectric memories or phase change memories or the like, and the passive components can include resistors or capacitors or the like. The electronic components can be planar components or three-dimensional components such as Fin-FETs (Fin Field Effect Transistors) or three-dimensional memories or the like. The electronic components can be covered by a dielectric material, which can be a laminated structure and can include silicon oxide, silicon nitride, or silicon oxynitride or the like. In this embodiment, at least some of the electronic components are used to connect active chips bonded on the first device substrate.

[0047] In this embodiment, at least one deep trench capacitor 110 is formed on the surface of the first device substrate 100. The deep trench capacitor 110 can play a role in improving the capacitance density in a semiconductor packaging structure containing the deep trench capacitor 110. The deep trench capacitor 110 is isolated from the electronic components on the first device substrate 100 used to connect active chips, for example.

[0048] Figure 3B is a schematic cross-sectional view of a chip packaging method of an embodiment of the present application after active chips and deep trench capacitor chips are bonded on the surface of the first device substrate. Referring to Figure 2 and Figure 3B , then, step S2 is performed to bond at least one active chip 120 (such as DIE1 and DIE2 shown in Figure 3B ) and at least one deep trench capacitor chip 130 (such as DIE3 shown in Figure 3BThe DTC1 and DTC2 are bonded to one side surface of the first device substrate 100 respectively, and the effective chip 120 is electrically connected to the electronic components on the first device substrate 100 through the bonding.

[0049] The deep trench capacitor chip 130 is arranged on the surface of the first device substrate 100 exposed by the effective chip 120, and the electrode end of the deep trench capacitor chip 130 can be directed towards or away from the first device substrate 100 during the bonding. In the embodiment, the electrode end of the deep trench capacitor chip 130 is directed towards the first device substrate 100. The micro bump bonding or hybrid bonding can be used when the effective chip 120 and / or the deep trench capacitor chip 130 are bonded to the first device substrate 100.

[0050] In some embodiments, at least part of the number of the deep trench capacitor chip 130 is bonded to the deep trench capacitor 110 on the surface of the first device substrate 100, and is connected in parallel with the corresponding deep trench capacitor 110 to further increase the capacitance density of the semiconductor packaging structure.

[0051] The number and position of the deep trench capacitor chip 130 bonded to the surface of the first device substrate 100 can be set as needed. In the preferred solution, the surface of the first device substrate 100 other than the bonding area of the effective chip 120 can be fully utilized to bond the deep trench capacitor chip 130 on the surface of the first device substrate 100. For example, the proportion of the area of the surface of the first device substrate 100 bonded with all the effective chips is less than or equal to 50-85%, i.e. 15%-50% of the area of the surface of the first device substrate 100 is not occupied by the effective chip 120. The deep trench capacitor chip 130 can be bonded on the first device substrate 100 corresponding to the gap between adjacent effective chips 120, which does not affect the bonding effect of the effective chip 120, fully utilizes the surface of the first device substrate 100 other than the bonding area of the effective chip 120, increases the integration density of the semiconductor packaging structure relative to the blank chip, improves the capacitance density of the semiconductor packaging structure, improves the stability of high-frequency signals, and improves the uniformity of the coefficient of thermal expansion of the semiconductor packaging structure, thereby improving the performance of the semiconductor packaging structure.

[0052] Figure 3C is a cross-sectional view of a chip packaging method according to an embodiment of the present application after forming a filling material. Figure 3D is a cross-sectional view of a chip packaging method according to an embodiment of the present application after forming an interlayer dielectric layer. Figure 3E is a cross-sectional view of a chip packaging method according to an embodiment of the present application after forming a metal interconnection layer. Figures 3C to 3EFurther, the chip packaging method of the embodiment can further include the following process:

[0053] As shown in Figure 3C , a filling material 140 is formed between the active chip 120 and the deep trench capacitor chip 130, specifically, the filling material 140 can be deposited between and on the active chip 120 and the deep trench capacitor chip 130, and then the excess filling material on the chips is removed by a planarization process (e.g. chemical mechanical polishing, CMP). The deep trench capacitor chip 130 is bonded outside the active chip 120 bonding area of the first device substrate 100, which helps to improve the planarization effect of the planarization process.

[0054] Next, as shown in Figure 3D , an interlayer dielectric layer 150 is formed, which covers the active chip 120 and the deep trench capacitor chip 130.

[0055] Then, as shown in Figure 3E , a metal interconnection layer 160 is formed on the interlayer dielectric layer 150, which is electrically connected to the active chip 120 through a contact plug 151 penetrating the interlayer dielectric layer 150. The interlayer dielectric layer 150 and the metal interconnection layer 160 formed on the active chip 120 and the deep trench capacitor chip 130 can be one or more layers.

[0056] Before or after the formation of the interlayer dielectric layer 150, other deep trench capacitor chips can be selectively stacked on the active chip 120 and / or the deep trench capacitor chip 130, which can be electrically connected or electrically insulated to the underlying active chip 120 or deep trench capacitor chip 130.

[0057] Figure 3F is a cross-sectional structure diagram of the chip packaging method of an embodiment of the present application after bonding a second device substrate on the first device substrate. As shown in Figure 3F , the chip packaging method of the embodiment can further include the steps of forming a bonding layer 170 on the metal interconnection layer 160 and bonding a second device substrate 200 on the side of the bonding layer 170 away from the first device substrate 100.

[0058] The bonding layer 170 formed on the metal interconnection layer 160 can include a dielectric layer and bonding pads embedded in the dielectric layer and electrically connected with the metal interconnection layer 160. Optionally, before bonding with the second device substrate 200, a metal interconnection layer 160 and associated bonding pads can also be provided above the deep trench capacitor chip 130 on the first device substrate 100.

[0059] The second device substrate 200 is, for example, a silicon wafer, and electronic components can be formed on the second device substrate 200. The electronic components formed on the second device substrate 200 can include at least one of MOS devices, sensor devices, memory devices, and passive devices. The second device substrate 200 is formed with bonding pads on a surface facing the first device substrate 100. When bonding the second device substrate 200 on the side of the bonding layer 170 away from the first device substrate 100, a hybrid bonding method can be used to bond the bonding pads in the bonding layer 170 with the bonding pads on the surface of the second device substrate 200. Through this bonding, the electronic components on the second device substrate 200 can be connected (for example, through the bonding pads and the metal interconnection layer 160) with the active chips 120 on the first device substrate 100. During the bonding process, by bonding both the deep trench capacitor chip 130 and the active chip 120 regions with the second device substrate 200, the bonding area of the first device substrate 100 with the second device substrate 200 can be ensured, and sufficient bonding strength between the first device substrate 100 and the second device substrate 200 can be achieved.

[0060] After bonding the second device substrate 200 on the side of the bonding layer 170 away from the first device substrate 100, the chip packaging method can further include a cutting process to form a semiconductor package structure including at least part of the first device substrate 100, part of the active chips 120, part of the deep trench capacitor chips 130, and part of the second device substrate 200.

[0061] Embodiments of the present application also include a semiconductor package structure formed using the chip packaging method described above. Referring to Figure 3F , the semiconductor package structure includes a first device substrate 100 and at least one active chip 120 and at least one deep trench capacitor chip 130 bonded to a surface on one side of the first device substrate 100. The first device substrate 100 is formed with electronic components, and through the bonding, the active chip 120 is electrically connected with the electronic components on the first device substrate 100.

[0062] Optionally, micro-bump bonding or hybrid bonding can be used between the effective chip 120 and the deep-trench capacitor chip 130 and the first device substrate 100. In addition, the area bonded with the effective chip 120 accounts for less than or equal to 50-85% of the surface of the first device substrate 100.

[0063] In some embodiments, the surface of the first device substrate 100 is formed with at least one deep-trench capacitor 110, and at least part of the number of deep-trench capacitor chips 130 are bonded to the deep-trench capacitor 110 and connected in parallel with the deep-trench capacitor 110.

[0064] Further, referring to Figure 3F , the semiconductor packaging structure can further include:

[0065] an interlayer dielectric layer 150 covering the effective chip 120 and the deep-trench capacitor chip 130;

[0066] a metal interconnection layer 160 on the interlayer dielectric layer 150, the metal interconnection layer 160 being electrically connected with the effective chip 120 through a contact plug 151 penetrating the interlayer dielectric layer 160;

[0067] a bonding layer 170 on the metal interconnection layer 160; and

[0068] a second device substrate 200 bonded with the first device substrate 100 on the side of the bonding layer 170 away from the first device substrate 100, the second device substrate 200 being formed with electronic components, and the electronic components on the second device substrate 200 being electrically connected with the effective chip 120 through bonding.

[0069] In the semiconductor packaging structure of the embodiments of the present application, at least one effective chip 120 and at least one deep-trench capacitor chip 130 are bonded with the surface of the first device substrate 100, respectively, wherein the effective chip 120 is electrically connected with the electronic components on the first device substrate 100 through bonding, and the deep-trench capacitor chip 130 can be arranged on the surface of the first device substrate 100 outside the bonding area of the effective chip 120, which helps to increase the integration density of the semiconductor packaging structure, improve the capacitance density, and improve the stability of high-frequency signals, thus improving the performance of the semiconductor packaging structure. In addition, the arrangement of the deep-trench capacitor chip 130 can improve the flatness during chemical mechanical polishing of the filling material, and also improve the uniformity of the thermal expansion coefficient of the semiconductor packaging structure, ensuring sufficient bonding strength between the first device substrate 100 and the second device substrate 200, and improving the performance of the semiconductor packaging structure.

[0070] It should be noted that the various embodiments described in the specification are intended to be exemplary only and that the scope of the application is not in any way limited by the disclosure of these embodiments. Any modification of the embodiments within the spirit and scope of the application will be apparent to those skilled in the art and is intended to be within the scope of the application.

[0071] The above description is only a description of the preferred embodiments of the application and is not any limitation on the scope of the application. Any person skilled in the art can make possible changes and modifications to the technical solutions of the application without departing from the spirit and scope of the application by using the disclosed methods and technical contents. Therefore, any simple modification, equivalent change and modification of the above embodiments according to the technical essence of the application, which does not deviate from the technical solutions of the application, is within the protection scope of the application.

Claims

1. A chip packaging method, characterized by, Comprising: providing a first device substrate having electronic components formed thereon, the first device substrate having at least one deep trench capacitor formed on a surface thereof; bonding at least one active chip and at least one deep trench capacitor chip to a side surface of the first device substrate, wherein the active chip is electrically connected to the electronic components on the first device substrate by the bonding, at least a portion of the deep trench capacitor chips are bonded to the deep trench capacitors and are connected in parallel to the corresponding deep trench capacitors, at least one of the active chip and the deep trench capacitor chip is a different type of chip, and the deep trench capacitor chips are arranged on the surface of the first device substrate exposed by the active chip; and forming a fill material between the active chip and the deep trench capacitor chip, and removing excess fill material above the active chip and the deep trench capacitor chip using a planarization process. Further comprising:

2. The chip packaging method of claim 1, wherein, forming an interlayer dielectric layer covering the active chip and the deep trench capacitor chip; and forming a metal interconnect layer on the interlayer dielectric layer, the metal interconnect layer being electrically connected to the active chip through a contact plug penetrating the interlayer dielectric layer. Further comprising: forming a bonding layer on the metal interconnect layer; and 3. The chip packaging method of claim 2, wherein, bonding a second device substrate having electronic components formed thereon to a side of the bonding layer away from the first device substrate, the electronic components on the second device substrate being electrically connected to the active chip by the bonding. Further comprising: stacking other deep trench capacitor chips above the active chip and / or the deep trench capacitor chip. The active chip and / or the deep trench capacitor chip is bonded to the first device substrate using micro-bump bonding or hybrid bonding.

4. The chip packaging method of claim 1, wherein, The area bonded to the active chip accounts for less than or equal to 50-85% of the surface of the first device substrate. Comprising:

5. The chip packaging method according to any one of claims 1 to 4, wherein, a first device substrate having electronic components formed thereon, the first device substrate having at least one deep trench capacitor formed on a surface thereof; 6. The chip packaging method according to any one of claims 1 to 4, wherein at least one active chip and at least one deep trench capacitor chip bonded to a side surface of the first device substrate, wherein the active chip is electrically connected to the electronic components on the first device substrate by the bonding, at least a portion of the deep trench capacitor chips are bonded to the deep trench capacitors and are connected in parallel to the corresponding deep trench capacitors, at least one of the active chip and the deep trench capacitor chip is a different type of chip, and the deep trench capacitor chips are arranged on the surface of the first device substrate exposed by the active chip; and 7. A semiconductor package structure, comprising: a fill material formed between the active chip and the deep trench capacitor chip, wherein excess fill material above the active chip and the deep trench capacitor chip is removed using a planarization process. Further comprising: an interlayer dielectric layer covering the active chip and the deep trench capacitor chip; and a metal interconnect layer formed on the interlayer dielectric layer, the metal interconnect layer being electrically connected to the active chip through a contact plug penetrating the interlayer dielectric layer.

8. The semiconductor package structure of claim 7, wherein, ​ ​ a metal interconnect layer on the interlayer dielectric layer, the metal interconnect layer being electrically connected to the active chip through a contact plug penetrating the interlayer dielectric layer; a bonding layer on the metal interconnect layer; and a second device substrate bonded to the first device substrate on a side of the bonding layer distal to the first device substrate, the second device substrate having electronic components formed thereon, the electronic components on the second device substrate being electrically connected to the active chip through the bonding. ​

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