Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes a III-V compound semiconductor layer, a III-V compound barrier layer, a gate trench, and a P-type doped III-V compound layer. The III-V compound barrier layer is disposed on the III-V compound semiconductor layer. The gate trench is disposed in the III-V compound barrier layer. The P-type doped III-V compound layer is disposed in the gate trench, and an upper surface of the P-type doped III-V compound layer is substantially coplanar with an upper surface of the III-V compound barrier layer.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device having a III-V compound semiconductor layer and a method of fabricating the same. BACKGROUND

[0002] III-V semiconductor compounds can be applied to form many kinds of integrated circuit devices, such as high power field effect transistors, high frequency transistors or high electron mobility transistors (HEMTs), due to their semiconductor properties. In a high electron mobility transistor, two different band-gap semiconductor materials are combined to form a heterojunction at a junction to provide a channel for carriers. In recent years, gallium nitride (GaN) based materials are suitable for high power and high frequency products due to their wide band-gap and high saturation velocity. The high electron mobility transistors of GaN based materials generate two-dimensional electron gas (2DEG) from the piezoelectric effect of the materials themselves, which has high electron velocity and density, and thus can be used to increase switching speed. Therefore, how to further improve the electrical performance of transistors formed by III-V compound materials through design changes of materials, structures or / and fabrication methods has become the research direction of people in the related field. SUMMARY

[0003] The present application provides a semiconductor device and a method of fabricating the same, which forms a P-type doped III-V compound layer in a trench of a III-V compound barrier layer and makes the upper surface of the P-type doped III-V compound layer substantially coplanar with the upper surface of the III-V compound barrier layer, thereby improving the material quality of the P-type doped III-V compound layer, improving the electrical performance of the semiconductor device or / and simplifying the related fabrication process steps.

[0004] One embodiment of the present application provides a semiconductor device, which includes a III-V compound semiconductor layer, a III-V compound barrier layer, a gate trench and a P-type doped III-V compound layer. The III-V compound barrier layer is disposed on the III-V compound semiconductor layer. The gate trench is disposed in the III-V compound barrier layer. The P-type doped III-V compound layer is disposed in the gate trench, and the upper surface of the P-type doped III-V compound layer is substantially coplanar with the upper surface of the III-V compound barrier layer.

[0005] One embodiment of the present application provides a method for fabricating a semiconductor device. A III-V compound barrier layer is formed on a III-V compound semiconductor layer. A gate trench is formed in the III-V compound barrier layer. A P-type doped III-V compound layer is formed in the gate trench, and an upper surface of the P-type doped III-V compound layer is substantially coplanar with an upper surface of the III-V compound barrier layer. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 A schematic diagram of a semiconductor device according to a first embodiment of the present application;

[0007] Figures 2 to 4 A schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present application, wherein

[0008] Figure 3 A schematic diagram of a semiconductor device according to a first embodiment of the present application; Figure 2 A subsequent schematic diagram;

[0009] Figure 4 A schematic diagram of a semiconductor device according to a first embodiment of the present application; Figure 3 A subsequent schematic diagram;

[0010] Figure 5 A schematic diagram of a semiconductor device according to a second embodiment of the present application;

[0011] Figure 6 A schematic diagram of a method for fabricating a semiconductor device according to a second embodiment of the present application;

[0012] Figure 7 A schematic diagram of a semiconductor device according to a third embodiment of the present application;

[0013] Figure 8 A schematic diagram of a semiconductor device according to a third embodiment of the present application;

[0014] Figure 9 A schematic diagram of a semiconductor device according to a fourth embodiment of the present application;

[0015] Figure 10 A schematic diagram of a semiconductor device according to a fifth embodiment of the present application;

[0016] Figure 11 A schematic diagram of a semiconductor device according to a sixth embodiment of the present application;

[0017] Figure 12 A schematic diagram of a method for fabricating a semiconductor device according to a sixth embodiment of the present application;

[0018] Figure 13 A schematic diagram of a method for fabricating a semiconductor device according to a sixth embodiment of the present application; Figure 14 A schematic diagram of a method for fabricating a semiconductor device according to a sixth embodiment of the present application; Figure 14 A schematic diagram of a method for fabricating a semiconductor device according to a sixth embodiment of the present application; Figure 13Subsequent status schematic diagram

[0019] Figure 15 Schematic diagram of the semiconductor device of the seventh embodiment of the present application;

[0020] Figure 16 Flowchart of the manufacturing method of the semiconductor device of the seventh embodiment of the present application;

[0021] Figure 17 With Figure 18 Schematic diagram of the manufacturing method of the semiconductor device of the seventh embodiment of the present application, wherein Figure 18 Is Figure 17 Subsequent status schematic diagram.

[0022] Explanation of main element symbols

[0023] 10 substrate

[0024] 10B bottom surface

[0025] 10T top surface

[0026] 12 buffer layer

[0027] 20 III-V compound semiconductor layer

[0028] 20B bottom surface

[0029] 20T top surface

[0030] 30 III-V compound barrier layer

[0031] 30B bottom surface

[0032] 30T top surface

[0033] 40 insulating layer

[0034] 40T top surface

[0035] 42 patterned mask layer

[0036] 50 P-type doped III-V compound layer

[0037] 50B bottom surface

[0038] 50T top surface

[0039] 62 dielectric layer

[0040] 64 dielectric layer

[0041] 91 patterned manufacturing process

[0042] 92 epitaxial growth manufacturing process

[0043] 101 Semiconductor Device

[0044] 102 Semiconductor Devices

[0045] 103 Semiconductor Devices

[0046] 104 Semiconductor Device

[0047] 105 Semiconductor Devices

[0048] 201 Semiconductor Devices

[0049] 202 Semiconductor Devices

[0050] 203 Semiconductor Devices

[0051] D1 First Direction

[0052] D2 Second Direction

[0053] DE1 Drain electrode

[0054] DE2 Drain electrode

[0055] DS distance

[0056] GE1 gate electrode

[0057] GE2 gate electrode

[0058] OP1 opening

[0059] OP2 opening

[0060] R1 First District

[0061] R2 Second District

[0062] Steps S10 to S14

[0063] Steps S20 to S25

[0064] SE1 source electrode

[0065] SE2 source electrode

[0066] T1 First Transistor Structure

[0067] T2 Second Transistor Structure

[0068] TK1 Thickness

[0069] TK2 Thickness

[0070] TR gate trench Detailed Implementation

[0071] The following detailed description of the application discloses sufficient information to enable those skilled in the art to practice the application. The embodiments set forth in the following description are illustrative and not restrictive in nature. Various modifications and changes can be made thereto without departing from the spirit and scope of the application, which is set forth in the appended claims.

[0072] Before further description of the embodiments, the following terms are first defined for use throughout the specification.

[0073] The terms "on," "over," and "above" are to be interpreted in the broadest context to mean not only "directly on" something but also to include the meaning of being on something with other intervening features or layers therebetween, and not only "over" or "above" something but also to include the meaning of being "over" or "above" something with no other intervening features or layers therebetween (i.e., directly on something).

[0074] The use of ordinal terms such as "first," "second," etc., in the specification and claims to modify an element of the application does not in itself connote any priority or order of one element to another, or to the process disclosed, but rather the use of such terms is merely intended to identify various elements as they can be received, processed, or executed, etc. in some order or arrangement, unless otherwise indicated by the context.

[0075] The term "etching" is used herein generally to describe a fabrication process to pattern a material such that at least a portion of the material is left after the etching is complete. When a material is "etched," at least a portion of the material can be left after the etching is complete. In contrast, when a material is "removed," substantially all of the material can be removed during the process. However, in some embodiments, "removed" can be considered a broad term that includes etching.

[0076] The terms "forming" or "depositing" are used hereinafter to describe the act of applying a layer of material to a substrate. These terms are intended to describe any workable layer forming technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0077] Reference is made to Figure 1 . Figure 1 A schematic diagram of a semiconductor device 101 is shown as a first embodiment of the present application. As shown in FIG. 1, the semiconductor device 101 includes a substrate 102, a first dielectric layer 104, a first conductive layer 106, a second dielectric layer 108, a second conductive layer 110, a third dielectric layer 112, a third conductive layer 114, a fourth dielectric layer 116, and a fourth conductive layer 118. Figure 1As shown, semiconductor device 101 includes a III-V compound semiconductor layer 20, a III-V compound barrier layer 30, a gate trench TR, and a P-type doped III-V compound layer 50. The III-V compound barrier layer 30 is disposed on the III-V compound semiconductor layer 20. The gate trench TR is disposed within the III-V compound barrier layer 30. The P-type doped III-V compound layer 50 is disposed within the gate trench TR, and the upper surface 50T of the P-type doped III-V compound layer 50 is substantially coplanar with the upper surface 30T of the III-V compound barrier layer 30. By providing the P-type doped III-V compound layer 50 within the gate trench TR, the resistance of semiconductor device 101 can be reduced, allowing semiconductor device 101 to have a positive threshold voltage and thus be considered a normally-off and / or enhancement-mode (E-mode) transistor.

[0078] In some embodiments, the semiconductor device 101 may further include a substrate 10 and a buffer layer 12. A III-V compound semiconductor layer 20 may be disposed on the substrate 10, and the buffer layer 12 may be disposed in a vertical direction (e.g., Figure 1 The first direction D1 shown is disposed between the substrate 10 and the III-V compound semiconductor layer 20 (e.g., between the upper surface 10T of the substrate 10 and the bottom surface 20B of the III-V compound semiconductor layer 20). In some embodiments, the first direction D1 can be considered as the thickness direction of the substrate 10, and the substrate 10 may have an opposing upper surface 10T and a bottom surface 10B in the first direction D1, and the buffer layer 12, the III-V compound semiconductor layer 20, the III-V compound barrier layer 30, and the p-type doped III-V compound layer 50 may be disposed on one side of the upper surface 10T. In addition, a horizontal direction that is substantially orthogonal to the first direction D1 (e.g., between the upper surface 10T of the substrate 10 and the bottom surface 20B of the III-V compound semiconductor layer 20) is disposed on the first direction D1. Figure 1The second direction D2 and other directions orthogonal to the first direction D1 can be substantially parallel to the top surface 10T or / and the bottom surface 10B of the substrate 10, but not limited thereto. In addition, a distance in the first direction D1 between a position or / and a component that is relatively higher in the vertical direction (e.g., the first direction D1) and the bottom surface 10B of the substrate 10 can be greater than a distance in the first direction D1 between a position or / and a component that is relatively lower in the vertical direction (e.g., the first direction D1) and the bottom surface 10B of the substrate 10, a lower portion or a bottom portion of a component can be closer to the bottom surface 10B of the substrate 10 in the first direction D1 than an upper portion or a top portion of the component, another component above a certain component can be considered as relatively further away from the bottom surface 10B of the substrate 10 in the first direction D1, and another component below a certain component can be considered as relatively closer to the bottom surface 10B of the substrate 10 in the first direction D1.

[0079] In some embodiments, the semiconductor device 101 can further include an insulating layer 40, a gate electrode GE1, a source electrode SE1, and a drain electrode DE1. The insulating layer 40 can be disposed on the III-V compound barrier layer 30, and the insulating layer 40 can include an opening OP1 disposed in the first direction D1 corresponding to the gate trench TR. The gate electrode GE1, the source electrode SE1, and the drain electrode DE1 can be disposed on the substrate 10. In some embodiments, the gate electrode GE1 can be disposed on the P-type doped III-V compound layer 50 and the insulating layer 40 in the first direction D1, and the source electrode SE1 and the drain electrode DE1 can be located on opposite sides of the gate electrode GE1 in a horizontal direction (e.g., the second direction D2), and the source electrode SE1 and the drain electrode DE1 can be located on the III-V compound barrier layer 30 in the first direction D1. In some embodiments, the gate electrode GE1, the source electrode SE1, the drain electrode DE1, the P-type doped III-V compound layer 50, the insulating layer 40, the III-V compound barrier layer 30, and the III-V compound semiconductor layer 20 can form a transistor structure, such as a high electron mobility transistor (HEMT), but not limited thereto.

[0080] In semiconductor device 101, the upper surface 50T of P-doped III-V compound layer 50 is substantially coplanar with the upper surface 30T of III-V compound barrier layer 30, that is, the upper surface 50T can be slightly higher or slightly lower than the upper surface 30T in the first direction Dl due to fabrication process variations and fabrication process uniformity. For example, in some embodiments, the distance DS between the upper surface 50T of P-doped III-V compound layer 50 and the bottom surface 30B of III-V compound barrier layer 30 in the first direction Dl can be equal to the thickness TK1 of III-V compound barrier layer 30 in the first direction Dl within a tolerance of ±10%, so the distance DS can be greater than or equal to 0.9 times the thickness TK1 and less than or equal to 1.1 times the thickness TK1.

[0081] Furthermore, the gate trench TR does not extend through III-V compound barrier layer 30 in the first direction Dl, so a portion of III-V compound barrier layer 30 can be located between the gate trench TR and III-V compound semiconductor layer 20 in the first direction Dl, and the thickness TK2 of P-doped III-V compound layer 50 in the first direction Dl can be less than the thickness TK1 of III-V compound barrier layer 30 in the first direction Dl. The thickness TK1 of III-V compound barrier layer 30 can be considered as the distance between the upper surface 30T and the bottom surface 30B of III-V compound barrier layer 30 in the first direction Dl, and the thickness TK2 of P-doped III-V compound layer 50 can be considered as the distance between the upper surface 50T and the bottom surface 50B of P-doped III-V compound layer 50 in the first direction Dl. In some embodiments, the ratio of the thickness TK2 of P-doped III-V compound layer 50 to the thickness TK1 of III-V compound barrier layer 30 (TK2 / TK1) can be less than 1 and greater than or equal to 0.8, so that P-doped III-V compound layer 50 can be as close as possible to the interface between III-V compound barrier layer 30 and III-V compound semiconductor layer 20 (e.g., the portion of the bottom surface 30B of III-V compound barrier layer 30 that is connected to the upper surface 20T of III-V compound semiconductor layer 20) to achieve the desired effects of reducing resistance and reaching positive threshold voltage while avoiding direct contact of P-doped III-V compound layer 50 with III-V compound semiconductor layer 20. For example, in some embodiments, the thickness TK1 of III-V compound barrier layer 30 can be between 50 nm and 100 nm, and the thickness TK2 of P-doped III-V compound layer 50 can be between 40 nm and 90 nm.

[0082] In some embodiments, the openings OP1 and the gate trenches TR can be formed by the same patterning process, and thus the openings OP1 and the gate trenches TR can be arranged in correspondence in the first direction D1, and the projected area of the openings OP1 in the first direction D1 and the projected area of the gate trenches TR in the first direction D1 can be substantially the same and overlap each other. In some embodiments, the P-type doped III-V compound layer 50 can fill the gate trenches TR without being arranged outside the gate trenches TR or only slightly formed outside the gate trenches TR, and thus the upper surface 50T of the P-type doped III-V compound layer 50 can be lower than the upper surface 40T of the insulating layer 40 in the first direction D1, but the present disclosure is not limited thereto. In addition, in some embodiments, the gate electrode GE1 can be arranged on and directly connected to the P-type doped III-V compound layer 50 in the first direction D1, and a portion of the gate electrode GE1 can be arranged on the upper surface 40T of the insulating layer 40 in the first direction D1.

[0083] In some embodiments, the III-V compound semiconductor layer 20 can include gallium nitride (GaN), indium gallium nitride (InGaN), alumium gallium nitride (AlGaN), or other suitable III-V compound semiconductor material, the III-V compound barrier layer 30 can include alumium gallium nitride, alumium indium nitride (AlInN), alumium gallium indium nitride (AlGaInN), alumium nitride (AlN), or other suitable III-V compound barrier material, and the P-type doped III-V compound layer 50 can include P-type doped alumium gallium nitride, P-type doped GaN layer, or other suitable P-type doped III-V compound material. In addition, the P-type dopant in the P-type doped III-V compound layer 50 can include cyclopentadienyl magnesium (Cp2Mg), magnesium, beryllium (Be), zinc (Zn), a combination thereof, or other suitable P-type dopant.

[0084] In some embodiments, the III-V compound semiconductor layer 20 can include a gallium nitride layer, the III-V compound barrier layer 30 can include an aluminum gallium nitride layer, and the P-type doped III-V compound layer 50 can include a P-type doped aluminum gallium nitride layer or / and a P-type doped gallium nitride layer. The P-type doped aluminum gallium nitride layer in the P-type doped III-V compound layer 50 can be formed directly by a suitable fabrication process (e.g., an epitaxial growth fabrication process) or / and by diffusion of aluminum from the III-V compound barrier layer 30 into a gallium nitride layer on the III-V compound barrier layer 30, so that the aluminum atom concentration in the P-type doped III-V compound layer 50 can be lower than the aluminum atom concentration in the III-V compound barrier layer 30. In other words, the P-type doped III-V compound layer 50 can include a P-type doped Al x Ga 1-x N layer, where x is less than 1 and greater than 0. Alternatively, the P-type doped III-V compound layer 50 can include a P-type doped Al x Ga 1-x N layer, and x is less than 1 and greater than or equal to 0, and when x is equal to 0, it is a P-type doped GaN layer.

[0085] In some embodiments, the substrate 10 can include a silicon substrate, a silicon carbide (SiC) substrate, a gallium nitride substrate, a sapphire substrate, or a substrate formed of other suitable materials, and the buffer layer 12 can include, for example, gallium nitride, aluminum gallium nitride, aluminum indium nitride, or other suitable buffer materials. The gate electrode GE1, the source electrode SE1, and the drain electrode DE1 can each include a metal conductive material or other suitable conductive material. The metal conductive material described above can include gold (Au), tungsten (W), cobalt (Co), nickel (Ni), titanium (Ti), molybdenum (Mo), copper (Cu), aluminum (Al), tantalum (Ta), palladium (Pd), platinum (Pt), compounds, composite layers, or alloys of the above materials, but is not limited thereto. The insulating layer 40 can include an oxide insulating material, a nitride insulating material, or other suitable insulating materials.

[0086] Reference is made to Figures 1 to 4 . Figures 2 to 4 a schematic diagram of a method of fabricating a semiconductor device according to an embodiment of the present application, and Figure 1 may be regarded as illustrating Figure 4 subsequent conditions. As Figure 1As shown, the method for fabricating a semiconductor device in this embodiment may include the following steps: A III-V compound barrier layer 30 is formed on a III-V compound semiconductor layer 20; a gate trench TR is formed in the III-V compound barrier layer 30; and a P-type doped III-V compound layer 50 is formed in the gate trench TR, wherein the upper surface 50T of the P-type doped III-V compound layer 50 is substantially coplanar with the upper surface 30T of the III-V compound barrier layer 30.

[0087] Further explanation: The method for fabricating the semiconductor device in this embodiment may include, but is not limited to, the following steps. First, as... Figure 2 As shown, a buffer layer 12, a III-V compound semiconductor layer 20, and a III-V compound barrier layer 30 can be sequentially formed on the substrate 10, and an insulating layer 40 can be formed on the III-V compound barrier layer 30. Then, as... Figure 3 As shown, an opening OP1 and a gate trench TR are formed. The opening OP1 penetrates the insulating layer 40 in the first direction D1 and corresponds to the gate trench TR in the first direction D1. In some embodiments, the opening OP1 and the gate trench TR can be formed by a patterning process 91. For example, in some embodiments, the patterning process 91 may include an etching step, and prior to this etching step, a patterned mask layer 42 may be formed on the insulating layer 40, and the insulating layer 40 and the III-V compound barrier layer 30 may be etched using the patterned mask layer 42 as an etching mask to form the opening OP1 and the gate trench TR. Figures 3 to 4 As shown, after patterning process 91, patterned mask layer 42 can be removed, and an epitaxial growth process 92 can be performed to form a P-type doped III-V compound layer 50 in the gate trench TR. In some embodiments, epitaxial growth process 92 may include a selective epitaxial growth process, wherein the P-type doped III-V compound layer 50 is formed only epitaxially from the surface of the III-V compound barrier layer 30 exposed in the gate trench TR, and not from the insulating layer 40 and the upper surface 30T of the III-V compound barrier layer 30 covered by the insulating layer 40. Furthermore, by selecting the epitaxial growth material and / or controlling the fabrication process conditions, the growth rate of the P-type doped III-V compound layer 50 from the inner sidewall of the gate trench TR can be made greater than the growth rate from the bottom surface of the gate trench TR, thereby controlling the formation of the P-type doped III-V compound layer 50 within the gate trench TR and making it less likely to form outside the gate trench TR.

[0088] Then, as Figure 4 and Figure 1As shown, after the formation of the P-type doped III-V compound layer 50, a gate electrode GE1, a source electrode SE1, and a drain electrode DE1 can be formed to form a semiconductor device 101. In some embodiments, the gate electrode GE1 may be formed on the P-type doped III-V compound layer 50 and the insulating layer 40, while the source electrode SE1 and the drain electrode DE1 may be formed on the insulating layer 40, but are not limited thereto. In some embodiments, the source electrode SE1 and the drain electrode DE1 may each partially extend into the III-V compound barrier layer 30. Through the fabrication method of this embodiment, the P-type doped III-V compound layer 50 can be formed in the gate trench TR in a self-aligned manner. Therefore, it is not necessary to perform an etching process on the P-type doped III-V compound layer 50, thus avoiding etching damage to the P-type doped III-V compound layer 50 and / or the III-V compound barrier layer 30. This can improve the material quality of the P-type doped III-V compound layer 50, improve the electrical performance of the semiconductor device, and / or simplify the related fabrication process steps.

[0089] The following description will focus on different embodiments of the present invention. For the sake of simplicity, the description will mainly focus on the differences between the embodiments, and will not repeat the same points. In addition, the same elements in the various embodiments of the present invention are identified by the same reference numerals to facilitate comparison between the embodiments.

[0090] Please see Figure 5 . Figure 5 The illustration shows a schematic diagram of a semiconductor device 201 according to another embodiment of the present invention. Figure 5 As shown, in some embodiments, the substrate 10 may include a first region R1 and a second region R2. The buffer layer 12, the III-V compound semiconductor layer 20, the III-V compound barrier layer 30, and the insulating layer 40 may be disposed on the first region R1 and the second region R2 of the substrate 10. The gate trench TR, the P-type doped III-V compound layer 50, and the opening OP1 may be disposed on the first region R1 of the substrate 10. The gate electrode GE1 may be regarded as a first gate electrode disposed on the first region R1 of the substrate 10, and the source electrode SE1 and the drain electrode DE1 may be regarded as a first source electrode and a first drain electrode disposed on the first region R1 of the substrate 10, respectively. In addition, the semiconductor device 201 may also include a second gate electrode (e.g., Figure 5 The gate electrode GE2 shown), and a second source electrode (e.g. Figure 5 The source electrode SE2 shown in the figure and a second drain electrode (e.g., Figure 5The drain electrode DE2 shown is disposed on the second region R2 of the substrate 10. The gate electrode GE2 may be disposed on the III-V compound barrier layer 30 and the insulating layer 40 on the second region R2. The gate electrode GE2 may be disposed corresponding to another opening OP2 in the insulating layer 40. The opening OP2 may expose the III-V compound barrier layer 30 on the second region R2, and the gate electrode GE2 may contact the III-V compound barrier layer 30 through the opening OP2. The source electrode SE2 and the drain electrode DE2 may be located on opposite sides of the gate electrode GE2 in a horizontal direction (e.g., the second direction D2), and the source electrode SE2 and the drain electrode DE2 may be located on the III-V compound barrier layer 30 on the second region R2 in the first direction D1.

[0091] In some embodiments, the material composition of the gate electrode GE2 may be similar to that of the gate electrode GE1, and the material compositions of the source electrode SE2 and the drain electrode DE2 may be similar to those of the source electrode SE1 and the drain electrode DE1, but are not limited thereto. In some embodiments, the gate electrode GE1, source electrode SE1, drain electrode DE1, P-type doped III-V compound layer 50, and insulating layer 40, III-V compound barrier layer 30, and III-V compound semiconductor layer 20 located on the first region R1 can form a first transistor structure T1, while the gate electrode GE2, source electrode SE2, drain electrode DE2, and insulating layer 40, III-V compound barrier layer 30, and III-V compound semiconductor layer 20 located on the second region R2 can form a second transistor structure T2. The first transistor structure T1 with P-type doped III-V compound layer 50 can be regarded as an enhancement-mode (E-mode) transistor, while the second transistor structure T2 without gate trench TR and P-type doped III-V compound layer 50 can be regarded as a depletion-mode (D-mode) transistor, but is not limited thereto.

[0092] Please see Figure 5 and Figure 6 . Figure 6 The illustration shows a method for fabricating a semiconductor device according to another embodiment of the present invention. Figure 5 It can be regarded as a drawing Figure 6 A diagram illustrating the subsequent situation. (See example.) Figure 6As shown, the buffer layer 12, the III-V compound semiconductor layer 20, the III-V compound barrier layer 30, and the insulating layer 40 can be simultaneously formed on the substrate 10 in the first region R1 and the second region R2, and the gate trench TR, the P-type doped III-V compound layer 50, and the opening OP1 can be formed on the first region R1 of the substrate 10. When forming the P-type doped III-V compound layer 50, the III-V compound barrier layer 30 on the second region R2 can be completely covered by the insulating layer 40, thus avoiding the formation of the P-type doped III-V compound layer 50 formed by epitaxial growth process on the III-V compound barrier layer 30 on the second region R2. Then, as shown in Figure 6 and Figure 5 As shown, after the formation of the P-type doped III-V compound layer 50, a gate electrode GE1, a source electrode SE1, and a drain electrode DE1 can be formed on the first region R1, and a gate electrode GE2, a source electrode SE2, and a drain electrode DE2 can be formed on the second region R2. The gate electrode GE1 can be formed on the III-V compound barrier layer 30 located on the first region R1 and corresponds to the opening OP1 in the first direction D1, while the gate electrode GE2 can be formed on the III-V compound barrier layer 30 located on the second region R2 and corresponds to the opening OP2 in the first direction D1. In some embodiments, the gate electrode GE1 and the gate electrode GE2 can be formed together by the same fabrication process (e.g., a conductive layer deposition process and a patterning process for patterning this conductive layer) and have the same material composition, while the opening OP2 can be formed in the insulating layer 40 on the second region R2 after the formation of the P-type doped III-V compound layer 50 and before the formation of the gate electrode GE2. Furthermore, the source electrode SE1 and drain electrode DE1 can be the source and drain electrodes of a first transistor structure T1 including a gate electrode GE1, formed on a III-V compound barrier layer 30 located on the first region R1, and the source electrode SE2 and drain electrode DE2 can be the source and drain electrodes of a second transistor structure T2 including a gate electrode GE2, formed on a III-V compound barrier layer 30 located on the second region R2. In some embodiments, the source electrode SE1, drain electrode DE1, source electrode SE2, and drain electrode DE2 can be formed together by the same fabrication process (e.g., a film deposition process for a conductive layer and a patterning process for patterning this conductive layer) and have the same material composition, but this is not a limitation. In other words, at least a portion of the first transistor structure T1 and the second transistor structure T2 of different types can be formed together by the same fabrication process, thereby achieving the effect of simplified fabrication process.

[0093] Please see Figure 7 . Figure 7 The illustration shows a schematic diagram of a semiconductor device 102 according to a second embodiment of the present invention.Figure 7 As shown, in some embodiments, a portion of the P-type doped III-V compound layer 50 may be disposed on the insulating layer 40 in the first direction D1, and the P-type doped III-V compound layer 50 on the insulating layer 40 may be located between the insulating layer 40 and the gate electrode GE1 in the first direction D1. For example, the P-type doped III-V compound layer 50 formed by epitaxial growth may be partially formed outside the gate trench TR, resulting in a portion of the P-type doped III-V compound layer 50 being formed on the insulating layer 40 in the first direction D1, but this is not a limitation. Furthermore, the arrangement of the P-type doped III-V compound layer 50 in this embodiment can also be applied to other embodiments of the present invention as needed (e.g., in the above-described embodiments). Figure 5 (and in the first transistor structure T1 in subsequent embodiments).

[0094] Please see Figure 8 . Figure 8 The illustration shows a schematic diagram of a semiconductor device 103 according to a third embodiment of the present invention. Figure 8 As shown, in some embodiments, the upper surface 50T of the p-type doped III-V compound layer 50 may include a recessed surface, a portion of the upper surface 50T (e.g., the lowest portion) may be slightly lower than the upper surface of the III-V compound barrier layer 30 in the first direction D1, and the distance DS between the upper surface 50T and the bottom surface 30B of the III-V compound barrier layer 30 in the first direction D1 may be slightly smaller than the thickness TK1 of the III-V compound barrier layer 30 in the first direction D1. In some embodiments, before the formation of the gate electrode GE1, the p-type doped III-V compound layer 50 may be subjected to a planarization process (e.g., chemical mechanical polishing or other suitable planarization method) to remove the p-type doped III-V compound layer 50 outside the gate trench TR (e.g., as described above). Figure 7 The state of the P-type doped III-V compound layer 50 shown in the diagram), and the upper surface 50T of the P-type doped III-V compound layer 50 may have a slightly concave surface due to this planarization fabrication process. Furthermore, the state of the upper surface 50T of the P-type doped III-V compound layer 50 in this embodiment, including a concave surface, can also be applied in other embodiments of the present invention as needed (e.g., in the above-described...). Figure 5 (and in the first transistor structure T1 in subsequent embodiments).

[0095] Please see Figure 9 . Figure 9 The illustration shows a schematic diagram of a semiconductor device 104 according to a fourth embodiment of the present invention. Figure 9In some embodiments, as shown, a portion of the P-type doped III-V compound layer 50 can be disposed on the side of the insulating layer 40 in the horizontal direction (e.g., the second direction D2), and the upper surface 50T of the P-type doped III-V compound layer 50 can be considered as a recessed surface, but the application is not limited thereto. Moreover, the disposition of the P-type doped III-V compound layer 50 in the present embodiment can also be applied in other embodiments of the application as needed (e.g., in the first transistor structure T1 in the above Figure 5 and other subsequent embodiments).

[0096] Referring to Figure 10 . Figure 10 A schematic view of a semiconductor device 105 according to a fifth embodiment of the application is shown. As shown, Figure 10 in some embodiments, the source electrode SE1 and the drain electrode DE1 can be partially disposed in the III-V compound barrier layer 30 by penetrating the insulating layer 40 in the first direction D1, respectively. Moreover, the disposition of the source electrode SE1 and the drain electrode DE1 in the present embodiment can also be applied in other embodiments of the application as needed (e.g., in the first transistor structure T1 in the above Figure 5 and other subsequent embodiments).

[0097] Referring to Figure 11 . Figure 11 A schematic view of a semiconductor device 202 according to a sixth embodiment of the application is shown. As shown, Figure 11 different from the semiconductor device 201 in the above Figure 5 embodiment, the semiconductor device 202 can further include a dielectric layer 62 covering the insulating layer 40, the gate electrode GE1 and the gate electrode GE2, and the source electrode SE1, the drain electrode DE1, the source electrode SE2 and the drain electrode DE2 can be partially disposed in the III-V compound barrier layer 30 by penetrating the dielectric layer 62 and the insulating layer 40, respectively. The dielectric layer 62 can include a single layer or multiple layers of dielectric materials such as oxide dielectric materials or other suitable dielectric materials. In some embodiments, a portion of the source electrode SE1 can be disposed on the dielectric layer 62 between the gate electrode GE1 and the drain electrode DE1 for adjusting the electric field distribution between the gate electrode GE1 and the drain electrode DE1, but the application is not limited thereto.

[0098] Referring to Figures 11 to 14 . Figure 12 A flowchart of a method for fabricating the semiconductor device 202 according to the sixth embodiment of the application is shown, Figure 13 and Figure 14 a schematic view of a method for fabricating the semiconductor device according to the present embodiment is shown, and Figure 11 can be considered to showFigure 14 A diagram illustrating the subsequent situation. (See example.) Figure 12 and Figure 13 As shown, in some embodiments, step S10 can be performed first, where a buffer layer 12, a III-V compound semiconductor layer 20, a III-V compound barrier layer 30, and an insulating layer 40 are simultaneously and sequentially formed on a first region R1 and a second region R2 of the substrate. An opening OP1 is formed in the insulating layer 40 on the first region R1, and a gate trench TR is formed in the III-V compound barrier layer 30 on the first region R1. Then, step S11 can be performed, where a P-type doped III-V compound layer 50 is formed in the gate trench TR. When the P-type doped III-V compound layer 50 is formed, the III-V compound barrier layer 30 on the second region R2 can be completely covered by the insulating layer 40, thus avoiding the formation of the P-type doped III-V compound layer 50 formed by epitaxial growth process on the III-V compound barrier layer 30 on the second region R2. Then, as... Figure 12 and Figure 14 As shown, step S12 can be performed to form gate electrode GE1 and gate electrode GE2. In some embodiments, opening OP2 can be formed after the formation of the p-type doped III-V compound layer 50 and before the formation of gate electrode GE2, but is not limited thereto. Figure 12 and Figure 11 As shown, after the gate electrode GE1 and gate electrode GE2 are formed, step S13 can be performed to form a dielectric layer 62 covering the gate electrode GE1, gate electrode GE2, and insulating layer 40. After the dielectric layer 62 is formed, step S14 can be performed to form the source electrode SE1, drain electrode DE1, source electrode SE2, and drain electrode DE2. In other words, the gate electrode and the source / drain electrode can be formed separately using different fabrication processes. The gate electrode GE1 and gate electrode GE2 can be formed before the source electrode SE1, drain electrode DE1, source electrode SE2, and drain electrode DE2. Different types of first transistor structures T1 and second transistor structures T2 can be formed together on the substrate 10, and at least a portion of the first transistor structure T1 and the second transistor structure T2 (e.g., the gate electrode or the source / drain electrode) can be formed together using the same fabrication process, thereby achieving the effect of simplified fabrication process. Furthermore, since the enhancement mode of the first transistor structure T1 can be achieved by forming a gate trench TR in the III-V compound barrier layer 30 and forming a P-type doped III-V compound layer 50 in the gate trench TR, different types of first transistor structures T1 and second transistor structures T2 can be fabricated on the same substrate 10, and the corresponding material layers (e.g., buffer layer 12, III-V compound semiconductor layer 20, III-V compound barrier layer 30) of the first transistor structure T1 and the second transistor structure T2 can be formed simultaneously on the same substrate 10.

[0099] Please see Figure 15 . Figure 15 The illustration shows a schematic diagram of a semiconductor device 203 according to a seventh embodiment of the present invention. (As described above) Figure 5 The semiconductor device 203 differs from semiconductor device 201 in that it may further include a dielectric layer 62 and a dielectric layer 64. Dielectric layer 62 may be disposed on insulating layer 40, and dielectric layer 64 may be disposed on dielectric layer 62. Source electrode SE1, drain electrode DE1, source electrode SE2, and drain electrode DE2 may penetrate dielectric layer 62 and insulating layer 40 respectively in a first direction D1, thereby contacting III-V compound barrier layer 30. Gate electrode GE1 may penetrate dielectric layer 64 and dielectric layer 62 in the first direction to connect to P-type doped III-V compound layer 50, while gate electrode GE2 may penetrate dielectric layer 64, dielectric layer 62, and insulating layer 40 in the first direction to contact III-V compound barrier layer 30. Dielectric layer 64 may comprise a single or multiple layers of dielectric material, such as oxide dielectric material or other suitable dielectric material.

[0100] Please see Figures 15 to 18 . Figure 16 The illustration is a schematic diagram of the fabrication method of the semiconductor device 203 according to the seventh embodiment of the present invention. Figure 17 and Figure 18 The illustration is a schematic diagram of a method for manufacturing a semiconductor device according to this embodiment, and Figure 15 It can be regarded as a drawing Figure 18 A diagram illustrating the subsequent situation. (See example.) Figure 16 and Figure 17 As shown, in some embodiments, step S20 can be performed first, where a buffer layer 12, a III-V compound semiconductor layer 20, a III-V compound barrier layer 30, and an insulating layer 40 are simultaneously and sequentially formed on a first region R1 and a second region R2 of the substrate. An opening OP1 is formed in the insulating layer 40 on the first region R1, and a gate trench TR is formed in the III-V compound barrier layer 30 on the first region R1. Then, step S21 can be performed, where a P-type doped III-V compound layer 50 is formed in the gate trench TR. When the P-type doped III-V compound layer 50 is formed, the III-V compound barrier layer 30 on the second region R2 can be completely covered by the insulating layer 40, thus avoiding the formation of the P-type doped III-V compound layer 50 formed by epitaxial growth process on the III-V compound barrier layer 30 on the second region R2. Then, as... Figure 16 and Figure 18As shown, step S22 can be performed to form a dielectric layer 62 covering the insulating layer 40 and the p-type doped III-V compound layer 50. After the dielectric layer 62 is formed, step S23 can be performed to form the source electrode SE1, drain electrode DE1, source electrode SE2, and drain electrode DE2. Then, as... Figure 16 and Figure 15 As shown, step S24 can be performed to form a dielectric layer 64 covering the dielectric layer 62, source electrode SE1, drain electrode DE1, source electrode SE2, and drain electrode DE2. Then, step S25 can be performed to form the gate electrode GE1 and gate electrode GE2. In other words, the gate electrode and the source / drain electrode can be formed separately using different fabrication processes. The gate electrode GE1 and gate electrode GE2 can be formed after the source electrode SE1, drain electrode DE1, source electrode SE2, and drain electrode DE2. Different types of first transistor structures T1 and second transistor structures T2 can be formed together on the substrate 10, and at least a portion of the first transistor structure T1 and the second transistor structure T2 (e.g., the gate electrode or the source / drain electrode) can be formed together using the same fabrication process, thereby achieving a simplified fabrication process. Furthermore, since the enhancement mode of the first transistor structure T1 can be achieved by forming a gate trench TR in the III-V compound barrier layer 30 and forming a P-type doped III-V compound layer 50 in the gate trench TR, different types of first transistor structures T1 and second transistor structures T2 can be fabricated on the same substrate 10, and the corresponding material layers (e.g., buffer layer 12, III-V compound semiconductor layer 20, III-V compound barrier layer 30) of the first transistor structure T1 and the second transistor structure T2 can be formed simultaneously on the same substrate 10.

[0101] In summary, in the semiconductor device and its fabrication method of the present invention, a P-type doped III-V compound layer can be formed in the gate trench located in the III-V compound barrier layer, and the upper surface of the P-type doped III-V compound layer is substantially coplanar with the upper surface of the III-V compound barrier layer. The P-type doped III-V compound layer disposed in the gate trench can be used to reduce the resistance of the semiconductor device and enable the semiconductor device to have a positive critical voltage. Furthermore, the P-type doped III-V compound layer can be epitaxially grown in the gate trench, thus eliminating the need for an etching process on the P-type doped III-V compound layer and avoiding the negative impacts of the etching process. This, in turn, improves the material quality of the P-type doped III-V compound layer, improves the electrical performance of the semiconductor device, and / or simplifies related fabrication steps.

[0102] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor device comprising: a III-V compound semiconductor layer; a III-V compound barrier layer disposed on the III-V compound semiconductor layer; a gate trench disposed in the III-V compound barrier layer; and a P-type doped III-V compound layer disposed in the gate trench, wherein an upper surface of the P-type doped III-V compound layer is substantially coplanar with an upper surface of the III-V compound barrier layer, wherein the upper surface of the P-type doped III-V compound layer comprises a recessed surface, wherein a distance between the upper surface of the P-type doped III-V compound layer and a bottom surface of the III-V compound barrier layer in a vertical direction is equal to a thickness of the III-V compound barrier layer in the vertical direction within a tolerance of ±10%, wherein the semiconductor device is an off-state transistor.

2. The semiconductor device of claim 1, wherein a ratio of a thickness of the P-type doped III-V compound layer in a vertical direction to a thickness of the III-V compound barrier layer in the vertical direction is less than 1 and greater than or equal to 0.

8.

3. The semiconductor device of claim 1, wherein the P-type doped III-V compound layer comprises a P-type doped aluminum gallium nitride layer, the III-V compound barrier layer comprises an aluminum gallium nitride layer, and an aluminum atom concentration in the P-type doped III-V compound layer is lower than an aluminum atom concentration in the III-V compound barrier layer.

5. The semiconductor device of claim 1, wherein the P-type doped III-V compound layer comprises a P-type doped gallium nitride layer.

4. The semiconductor device of Claim 1, wherein the P-type doped III-V compound layer comprises a P-type doped Al x Ga 1-x N layer, and x is less than 1 and greater than 0.

6. The semiconductor device of claim 1, further comprising: an insulating layer disposed on the III-V compound barrier layer, wherein the insulating layer comprises an opening corresponding to the gate trench in a vertical direction; and a gate electrode disposed on the P-type doped III-V compound layer.

7. The semiconductor device of claim 6, wherein a portion of the gate electrode is disposed on the insulating layer in the vertical direction.

8. The semiconductor device of claim 6, wherein a portion of the P-type doped III-V compound layer is disposed on the insulating layer in the vertical direction.

9. The semiconductor device of claim 6, wherein the upper surface of the P-type doped III-V compound layer is lower than an upper surface of the insulating layer in the vertical direction.

10. A method of manufacturing a semiconductor device, comprising: forming a III-V compound barrier layer on a III-V compound semiconductor layer; forming a gate trench in the III-V compound barrier layer; and forming a P-type doped III-V compound layer in the gate trench, wherein an upper surface of the P-type doped III-V compound layer is substantially coplanar with an upper surface of the III-V compound barrier layer, wherein the upper surface of the P-type doped III-V compound layer comprises a recessed surface, wherein a distance between the upper surface of the P-type doped III-V compound layer and a bottom surface of the III-V compound barrier layer in a vertical direction is equal to a thickness of the III-V compound barrier layer in the vertical direction within a tolerance of ±10%, wherein the semiconductor device is an off-state transistor. ​ ​ forming a P-type doped III-V compound layer in the gate trench, wherein an upper surface of the P-type doped III-V compound layer is substantially coplanar with an upper surface of the III-V compound barrier layer, wherein the upper surface of the P-type doped III-V compound layer comprises a recessed surface, wherein a distance between the upper surface of the P-type doped III-V compound layer and a bottom surface of the III-V compound barrier layer in a vertical direction is equal to a thickness of the III-V compound barrier layer in the vertical direction within a tolerance of ±10%, wherein the semiconductor device is an off-state transistor.

11. The method of claim 10, further comprising: forming an insulating layer on the III-V compound barrier layer before forming the gate trench; and forming an opening in a vertical direction, the opening penetrating the insulating layer, wherein the opening corresponds to the gate trench to be formed in the vertical direction.

12. The method of claim 11, wherein the opening and the gate trench are formed by a patterning fabrication process.

13. The method of claim 11, further comprising: forming a first gate electrode on the P-type doped III-V compound layer and the insulating layer.

14. The method of claim 13, wherein the III-V compound semiconductor layer, the III-V compound barrier layer, and the insulating layer are formed on a first region and a second region of a substrate, the opening, the gate trench, the P-type doped III-V compound layer, and the first gate electrode are formed on the first region of the substrate, and the method further comprises: forming a second gate electrode on the III-V compound barrier layer on the second region, wherein the first gate electrode and the second gate electrode are formed by a same fabrication process.

15. The method of claim 14, further comprising: forming a first source electrode and a first drain electrode on the III-V compound barrier layer on the first region, wherein the first source electrode and the first drain electrode are source and drain electrodes of a first transistor structure comprising the first gate electrode; and forming a second source electrode and a second drain electrode on the III-V compound barrier layer on the second region, wherein the second source electrode and the second drain electrode are source and drain electrodes of a second transistor structure comprising the second gate electrode, and the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are formed by a same fabrication process.

16. The method of claim 15, wherein the first transistor structure is an enhancement mode (E-mode) transistor, and the second transistor structure is a depletion mode (D-mode) transistor.

17. The method of claim 10, wherein the P-type doped III-V compound layer is formed by a selective epitaxial growth fabrication process.

18. The method of claim 10, wherein a ratio of a thickness of the P-type doped III-V compound layer in a vertical direction to a thickness of the III-V compound barrier layer in the vertical direction is less than 1 and greater than or equal to 0.

8.

19. The method of claim 10, wherein the P-type doped III-V compound layer comprises a P-type doped aluminum gallium nitride layer, the III-V compound barrier layer comprises an aluminum gallium nitride layer, and an aluminum atom concentration in the P-type doped III-V compound layer is lower than an aluminum atom concentration in the III-V compound barrier layer.

20. The method of making a semiconductor device of claim 10, wherein the P-type doped III-V compound layer comprises a P-type doped Al x Ga 1-x N layer, and x is less than 1 and greater than or equal to 0.

21. The method of claim 10, wherein a portion of the III-V compound barrier layer is located between the gate trench and the III-V compound semiconductor layer in a vertical direction.

Images