A semiconductor device and a manufacturing method thereof

Abstract

The application discloses a semiconductor device and a manufacturing method thereof, and relates to the technical field of semiconductors, and is used for improving the driving capability of a lower nanowire / sheet in a channel region when a ring gate transistor comprises a multi-layer nanowire / sheet. The semiconductor device comprises a semiconductor substrate, an active structure, and a gate stack structure. The channel region of the active structure comprises a first channel part and a second channel part located above the first channel part and spaced from the first channel region. The first channel part comprises at least one layer of first nanowire / sheet and a semiconductor connector between each layer of first nanowire / sheet and an adjacent first structure. The width of the semiconductor connector is smaller than that of the first nanowire / sheet, and the material of the semiconductor connector is different from that of the first nanowire / sheet. The first structure is the semiconductor substrate and / or the adjacent layer of first nanowire / sheet. The second channel part comprises at least one layer of second nanowire / sheet. The gate stack structure is formed at the outer periphery of the channel region.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] Gate-around transistors (GMT-A) have advantages over planar transistors and fin field-effect transistors, such as higher gate control capability, which can improve the operating performance of semiconductor devices including GMT-A.A. transistors.

[0003] However, in the case of existing gate-around transistors where the channel region has multiple nanowires / sheets, the driving capability of the nanowires / sheets located in the lower part of the channel region is poor, which in turn leads to poor electrical performance of the gate-around transistor. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and a method for manufacturing the same, which improves the driving capability of the lower nanowires / sheets in the channel region of a gate-around transistor when the channel region includes multiple nanowires / sheets, thereby enhancing the electrical performance of the gate-around transistor.

[0005] To achieve the above objectives, the present invention provides a semiconductor device comprising: a semiconductor substrate, an active structure, and a gate stack structure.

[0006] The aforementioned active structure is formed on a semiconductor substrate. The active structure includes a source region, a drain region, and a channel region located between the source and drain regions, the channel region contacting both the source and drain regions. The channel region includes a first channel portion and a second channel portion located above and spaced apart from the first channel portion. The first channel portion includes at least one layer of first nanowires / sheets and semiconductor interconnects located between each layer of first nanowires / sheets and adjacent first structures. The width of the semiconductor interconnects is smaller than the width of the first nanowires / sheets, and the material of the semiconductor interconnects is different from the material of the first nanowires / sheets. The first structure is a semiconductor substrate and / or adjacent layers of first nanowires / sheets. The second channel portion includes at least one layer of second nanowires / sheets. A gate stack structure is formed on the outer periphery of the channel region.

[0007] Compared with the prior art, the semiconductor device provided by the present invention includes an active structure comprising a channel region comprising a first channel portion and a second channel portion located above and spaced apart from the first channel portion. The first channel portion includes at least one layer of first nanowires / sheets and semiconductor interconnects located between each layer of first nanowires / sheets and adjacent first structures. In this case, although the distance between the first nanowires / sheets and the source and drain electrodes of the first channel portion located below the second channel portion is still relatively large, resulting in a voltage between the two ends of the first nanowires / sheets along the length direction being less than the voltage between the two ends of the second nanowires / sheets along the length direction, each layer of first nanowires / sheets is connected to a corresponding semiconductor interconnect. At this time, when the gate-ring transistor is in the on state, the presence of the semiconductor interconnect can increase the conductive area of ​​the structure formed by the semiconductor interconnect and the corresponding layer of first nanowires / sheets. Based on this, given a constant voltage across both ends of the first nanowire / sheet along its length, increasing the conductive area of ​​the aforementioned structure can reduce its conductive resistance, thereby increasing the current in each first nanowire / sheet, improving the driving capability of each first nanowire / sheet, and ultimately enhancing the electrical performance of the semiconductor device.

[0008] In addition, the width of the semiconductor interconnect is smaller than the width of the first nanowire / sheet. At this time, the bottom surface of the first nanowire / sheet located at the top layer, as well as the bottom and top surfaces of the remaining first nanowires / sheets located below the top layer, still have some surfaces that are not blocked by the corresponding semiconductor interconnect. This can improve the control capability of the gate stack structure over each layer of first nanowires / sheets, which is beneficial to further improve the electrical performance of the semiconductor device.

[0009] The present invention also provides a method for manufacturing a semiconductor device, the method comprising:

[0010] Provide a semiconductor substrate.

[0011] An active structure is formed on a semiconductor substrate. The active structure includes a source region, a drain region, and a channel region located between the source and drain regions, the channel region being in contact with the source and drain regions respectively. The channel region includes a first channel portion and a second channel portion located above and spaced apart from the first channel portion. The first channel portion includes at least one layer of first nanowires / wafers and semiconductor interconnects located between each layer of first nanowires / wafers and an adjacent first structure, the width of the semiconductor interconnects being smaller than the width of the first nanowires / wafers, and the material of the semiconductor interconnects being different from the material of the first nanowires / wafers. The first structure is a semiconductor substrate and / or an adjacent layer of first nanowires / wafers. The second channel portion includes at least one layer of second nanowires / wafers.

[0012] A grid stacking structure is formed on the outer periphery of the trench area.

[0013] Compared with the prior art, the beneficial effects of the semiconductor device manufacturing method provided by the present invention can be found in the analysis of the beneficial effects of the semiconductor device provided by the present invention, and will not be repeated here. Attached Figure Description

[0014] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0015] Figure 1 This is a cross-sectional view of an existing gate-around transistor along the length of the channel region.

[0016] Figures 2 to 45 This is a schematic diagram of a semiconductor device manufacturing process provided in an embodiment of the present invention.

[0017] Reference numerals: 11 is semiconductor substrate, 12 is sacrificial material layer, 13 is channel material layer, 14 is shallow trench isolation structure, 15 is fin, 151 is source formation region, 152 is drain formation region, 153 is channel formation region, 16 is sacrificial gate, 17 is gate sidewall, 18 is source region, 19 is drain region, 20 is fin structure, 201 is first stack, 202 is second stack, 203 is sacrificial layer, 204 is channel layer, 21 is dielectric layer, 22 is second protective layer, 23 is third protective layer, 24 is fourth protective layer, 25 is channel region, 251 is first channel portion, 2511 is first nanowire / wafer, 2512 is semiconductor interconnect, 252 is second channel portion, 2521 is second nanowire / wafer, 26 is gate stack structure, 261 is first gate stack portion, 262 is second gate stack portion. Detailed Implementation

[0018] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0019] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0020] In the context of this disclosure, when a layer / element is referred to as being "on top of" another layer / element, the layer / element may be directly on top of the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0021] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0022] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0023] like Figure 1 As shown, the channel region of the gate-around transistor includes at least one layer of nanowires / sheets. Each nanowire / sheet layer has a gap with the semiconductor substrate 11. Furthermore, when the channel region includes at least two nanowires / sheets, there are also gaps between adjacent nanowires / sheets. Based on this, the gate stack structure 26 of the gate-around transistor can surround the outer periphery of each nanowire / sheet layer through the aforementioned gaps. In other words, the gate stack structure 26 of the gate-around transistor can be formed not only on the top of each nanowire / sheet layer and on the sidewalls along the width direction, but also on the bottom of each nanowire / sheet layer. Therefore, the gate-around transistor has advantages such as higher gate control capability compared to planar transistors and fin field-effect transistors, which can improve the operating performance of semiconductor devices including this gate-around transistor.

[0024] However, as Figure 1As shown, in the case where the channel region of the gate-around transistor includes multiple nanowires / sheets, since the source (not shown) is formed on top of the source region 18 and the drain (not shown) is formed on top of the drain region 19, the distance between the lower nanowires / sheets and the source and drain, respectively, is larger along the direction close to the semiconductor substrate 11. Correspondingly, when the gate-around transistor is in the on state, the transmission path between the source and drain through the lower nanowires / sheets is longer. Furthermore, the transmission path is proportional to the on-resistance; therefore, the on-resistance of the lower nanowires / sheets is greater than that of the upper nanowires / sheets, resulting in a smaller current at the lower nanowires / sheets. This leads to poor driving capability of the lower nanowires / sheets, and consequently, poor electrical performance of the gate-around transistor.

[0025] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same. In the semiconductor device provided by these embodiments, the channel region includes a lower first channel portion comprising at least one layer of first nanowires / sheets and semiconductor interconnects located between each layer of first nanowires / sheets and adjacent first structures. This increases the conductive area of ​​the structure formed by the semiconductor interconnects and the corresponding layers of first nanowires / sheets, thereby increasing the current in each layer of first nanowires / sheets, improving the driving capability of each layer of nanowires / sheets, and ultimately enhancing the electrical performance of the semiconductor device.

[0026] like Figure 45 As shown, an embodiment of the present invention provides a semiconductor device, which includes a semiconductor substrate 11, an active structure, and a gate stack structure 26.

[0027] like Figure 7 and Figure 45 As shown, the active structure is formed on a semiconductor substrate 11. The active structure includes a source region 18, a drain region 19, and a channel region 25 located between the source region 18 and the drain region 19, with the channel region 25 contacting both the source region 18 and the drain region 19. The channel region 25 includes a first channel portion 251 and a second channel portion 252 located above and spaced apart from the first channel portion 251. The first channel portion 251 includes at least one layer of first nanowires / sheets 2511 and semiconductor interconnects 2512 located between each layer of first nanowires / sheets 2511 and an adjacent first structure. The width of the semiconductor interconnect 2512 is smaller than the width of the first nanowires / sheets 2511, and the material of the semiconductor interconnect 2512 is different from the material of the first nanowires / sheets 2511. The first structure is the semiconductor substrate 11 and / or an adjacent layer of first nanowires / sheets 2511. The second channel portion 252 includes at least one layer of second nanowires / sheets 2521. A gate stack structure 26 is formed on the outer periphery of the channel region 25.

[0028] Specifically, the specific structure of the aforementioned semiconductor substrate can be set according to the actual application scenario. For example, the semiconductor substrate can be a silicon substrate, a germanium-silicon substrate, a germanium substrate, a silicon-on-insulator substrate, or other semiconductor substrates on which no other structures are formed. As another example, if the semiconductor device provided in this embodiment is applied to a second or higher layer of a gate-around transistor in an integrated circuit, the semiconductor substrate can at least include a semiconductor substrate, a first device structure formed on the semiconductor substrate, and a dielectric layer covering the first device structure. In this case, the materials of each part of the semiconductor substrate can be set according to actual needs, as long as they can be applied to the semiconductor device provided in this embodiment.

[0029] Regarding the aforementioned active structure, from a material perspective, the source region, drain region, and channel region of the active structure can be made of semiconductor materials such as silicon, germanium-silicon, germanium, or group III-V compound semiconductors. Specifically, the materials of the source region and drain region can be the same or different. When the materials of the source region and drain region are the same, the source region and drain region can be formed simultaneously in a unified operation step, simplifying the semiconductor device manufacturing process. Furthermore, the material of the first nanowire / wafer included in the first channel portion of the channel region can be the same as the material of the second nanowire / wafer included in the second channel portion. For example, the materials of the first nanowire / wafer and the second nanowire / wafer can both be silicon or germanium-silicon. Alternatively, the materials of the first nanowire / wafer and the second nanowire / wafer can also be different. For example, the material of the first nanowire / wafer can be germanium-silicon, and the material of the second nanowire / wafer can be silicon. When the materials of the first nanowire / wafer and the second nanowire / wafer are the same, the difficulty of selectively etching the sacrificial layer can be reduced, which is beneficial for improving the compatibility between the semiconductor device provided in this embodiment of the invention and the conventional gate-around transistor manufacturing process.

[0030] Furthermore, the material of the semiconductor interconnect in the first channel can be any semiconductor material different from the material of the first nanowire / wafer. For example, one of the semiconductor interconnect and the first nanowire / wafer can be made of silicon, and the other can be made of a III-V compound material. Another example is that the material of the first nanowire / wafer can be Si. x Ge 1-x The material of the semiconductor interconnect can be Si y Ge 1-y Where 0≤x≤1, 0≤y≤1, |xy|≥0.2. In this case, the difference in germanium content between the first nanowire / sheet and the semiconductor interconnect can be determined based on the conductivity type of the semiconductor device and actual requirements, and is not specifically limited here. For example, when the conductivity type of the semiconductor device is N-type, the material of the first nanowire / sheet can be Si, and the material of the semiconductor interconnect can be a material with a relatively low germanium content in germanium-silicon materials (such as Si). 0.7 Ge0.3 For example, when the conductivity type of the semiconductor device is P-type, the material of the second nanowire / sheet can be germanium, or a germanium-silicon material with a relatively high germanium content (such as Si). 0.1 Ge 0.9 The semiconductor interconnect material can be a germanium-silicon material with a germanium content at least 20% lower than that of the second nanowire / wafer (e.g., Si). 0.4 Ge 0.6 This is to improve carrier mobility in the channel region.

[0031] It is worth noting that, such as Figures 4 to 44 As shown, when the material of the semiconductor interconnect 2512 included in the first channel portion 251 is different from the material of the first nanowire / wafer 2511, in the actual manufacturing process of the semiconductor device provided in this embodiment of the invention, the channel layer 204 can be used as the film layer for manufacturing the first nanowire / wafer 2511, and the sacrificial layer 203 can be used as the film layer for manufacturing the semiconductor interconnect 2512. Based on this, when the semiconductor interconnect 2512 is obtained by laterally thinning the sacrificial layer 203 along its width direction, when the material of the semiconductor interconnect 2512 in the first channel portion 251 is different from the material of the first nanowire / wafer 2511, the etchant used for laterally thinning the sacrificial layer 203 can be prevented from affecting the channel layer 204, improving the formation quality of the first nanowire / wafer 2511, further improving the compatibility of the semiconductor device provided in this embodiment of the invention with the conventional gate-around transistor manufacturing method, and reducing the manufacturing difficulty of the semiconductor device.

[0032] Structurally, the number of layers of the first nanowire / wafer included in the first channel portion is equal to the number of semiconductor interconnects included in the first channel portion. Specifically, the first channel portion may include only one layer of the first nanowire / wafer and one semiconductor interconnect located between the first nanowire / wafer layer and the adjacent first structure. In this case, the first structure adjacent to the first nanowire / wafer is a semiconductor substrate.

[0033] Alternatively, the first channel portion may further include at least two layers of first nanowires / sheets and at least two semiconductor interconnects. In this case, the first structure adjacent to each layer of first nanowires / sheets can be determined based on the number of layers of first nanowires / sheets. For example: Figure 45As shown, the first channel portion 251 includes three layers of first nanowires / sheets 2511 and three semiconductor interconnects 2512. The three layers of first nanowires / sheets 2511 are arranged in ascending order of number from bottom to top. Based on this, the first structure adjacent to the top third layer of first nanowires / sheets 2511 is the second layer of first nanowires / sheets 2511. The first structure adjacent to the middle second layer of first nanowires / sheets 2511 includes both the third layer of first nanowires / sheets 2511 and the first layer of first nanowires / sheets 2511. The first structure adjacent to the bottom first layer of first nanowires / sheets 2511 is the semiconductor substrate 11 and the second layer of first nanowires / sheets 2511.

[0034] Furthermore, when the first channel portion includes at least two layers of first nanowires / sheets and at least two semiconductor interconnects, the distribution relationship between the at least two semiconductor interconnects and the distribution relationship between each semiconductor interconnect and the adjacent first nanowire / sheet can be set according to actual needs, and is not specifically limited here. Specifically, when the first channel portion includes at least two layers of first nanowires / sheets, the line connecting the geometric centers of at least one pair of semiconductor interconnects has an angle greater than 0 and less than 90° with the height direction of the active structure. Or, as... Figure 45 As shown, when the first channel portion 251 includes at least two layers of first nanowires / sheets 2511, the line connecting the geometric centers of the semiconductor interconnects 2512 included in the first channel portion 251 is parallel to the height direction of the active structure. In this case, the geometric centers of the at least two layers of semiconductor interconnects 2512 included in the first channel portion 251 can be spaced apart along the height direction of the active structure and aligned along the width direction of the active structure, making the distribution of the at least two layers of semiconductor interconnects 2512 included in the first channel portion 251 more regular.

[0035] Regarding the distribution relationship between each semiconductor interconnect and the adjacent first nanowire / sheet, the line connecting at least one semiconductor interconnect and the geometric center of the adjacent first nanowire / sheet may have an angle greater than 0 and less than 90° with the height direction of the active structure. Alternatively, as... Figure 45 As shown, the line connecting each semiconductor connector 2512 to the geometric center of the adjacent first nanowire / sheet 2511 is parallel to the height direction of the active structure. In this case, each semiconductor connector 2512 and the adjacent first nanowire / sheet 2511 can form a regular "T" or "H" shaped structure, which is beneficial for improving the compatibility of the semiconductor device provided in this embodiment with the manufacturing process of conventional gate-around transistors and reducing the manufacturing difficulty of the semiconductor device.

[0036] In terms of specifications, the width of the first nanowire / wafer in the first channel portion and the width of the semiconductor interconnect can be set according to actual needs, as long as the width of the semiconductor interconnect is smaller than the width of the first nanowire / wafer. For example, the width of the semiconductor interconnect can be 3nm to 15nm. Of course, the width of the semiconductor interconnect can also be set to other suitable values ​​according to the specifications of the semiconductor device in the actual application scenario.

[0037] Regarding the second nanowire / wafer included in the second channel portion, the second channel portion may include only one layer of second nanowire / wafer, or it may include at least two layers of second nanowire / wafer. The number of layers of second nanowire / wafer included in the second channel portion can be determined based on the driving capability requirements of each layer of second nanowire / wafer and each layer of first nanowire / wafer in the actual application scenario, and no specific limitation is made here. It is understood that the greater the distance from the semiconductor substrate, the stronger the driving capability of the second nanowire / wafer. Correspondingly, the greater the distance from the semiconductor substrate, the stronger the driving capability of the first nanowire / wafer. Based on this, under the same conditions, when the driving capability requirements of each layer of second nanowire / wafer and each layer of first nanowire / wafer in the actual application scenario are higher, the number of layers of second nanowire / wafer included in the second channel portion is smaller.

[0038] For the above-mentioned gate stack structure, such as Figure 45 As shown, the gate stack structure 26 includes a first gate stack portion 261 and a second gate stack portion 262. The first gate stack portion 261 is formed on the outer periphery of the first channel portion 251, and the second gate stack portion 262 is formed on the outer periphery of the second channel portion 252. The first gate stack portion 261 includes a gate dielectric layer and a gate electrode formed sequentially on the outer periphery of the first channel portion 251. The second gate stack portion 262 includes a gate dielectric layer and a gate electrode formed sequentially around the outer periphery of the second channel portion 252. The material of the gate dielectric layer can be an insulating material with a low dielectric constant, such as silicon oxide or silicon nitride, or an insulating material with a high dielectric constant, such as HfO2, ZrO2, TiO2, or Al2O3. The material of the gate electrode can be a conductive material, such as polysilicon, TiN, TaN, or TiSiN. Specifically, the material of the gate dielectric layer included in the first gate stack portion 261 can be the same as the material of the gate dielectric layer included in the second gate stack portion 262. Meanwhile, the material of the gate included in the first gate stack 261 can also be the same as the material of the gate included in the second gate stack 262. For example, the material of the gate dielectric layer included in the first gate stack 261 and the second gate stack 262 can both be HfO2, and the material of the gate included in the first gate stack 261 and the second gate stack 262 can both be TiN.

[0039] Alternatively, the material of the first gate stack may be different from the material of the second gate stack.

[0040] Specifically, the difference between the material of the first gate stack and the material of the second gate stack can mean that only the material of the gate dielectric layer included in the first gate stack is different from the material of the gate dielectric layer included in the second gate stack. For example, the material of the gate dielectric layer included in the first gate stack can be HfO2, the material of the gate dielectric layer included in the second gate stack can be ZrO2, and the material of the gate in both the first and second gate stacks can be TiN.

[0041] It can also refer to a situation where only the material of the gate in the first gate stack is different from the material of the gate in the second gate stack. For example, the material of the gate dielectric layer in both the first and second gate stacks can be TiO2, the material of the gate in the first gate stack can be TaN, and the material of the gate in the second gate stack can be TiN.

[0042] It can also refer to: such as Figure 45 As shown, the material of the gate dielectric layer included in the first gate stack 261 is different from the material of the gate dielectric layer included in the second gate stack 262, and the material of the gate included in the first gate stack 261 is also different from the material of the gate included in the second gate stack 262. For example, the material of the gate dielectric layer included in the first gate stack 261 can be HfO2, and the material of the gate dielectric layer included in the second gate stack 262 can be ZrO2. Furthermore, the material of the gate included in the first gate stack 261 can be TaN, and the material of the gate included in the second gate stack 262 can be TiN.

[0043] It is worth noting that the portion of the active structure corresponding to the first gate stack, and the first gate stack, can constitute the lower device. The portion of the active structure corresponding to the second gate stack, and the second gate stack, can constitute the upper device. Wherein, when the materials of the first gate stack and the second gate stack are different, the threshold voltages of the upper and lower devices can be adjusted separately, improving the applicability of the semiconductor device provided in this embodiment of the invention in different application scenarios.

[0044] As can be seen from the above, such as Figure 7 and Figure 45As shown, in the semiconductor device provided in this embodiment of the invention, the active structure includes a channel region 25 comprising a first channel portion 251 and a second channel portion 252 disposed above and spaced apart from the first channel portion 251. The first channel portion 251 includes at least one layer of first nanowires / sheets 2511 and semiconductor connectors 2512 located between each layer of first nanowires / sheets 2511 and adjacent first structures. In this case, although the distance between the first nanowires / sheets 2511 and the source (not shown) and drain (not shown) of the first channel portion 251 located below the second channel portion 252 is still relatively large, the voltage between the two ends of the first nanowire / sheet 2511 along the length direction is less than the voltage between the two ends of the second nanowire / sheet 2521 along the length direction. However, each layer of first nanowires / sheets 2511 is connected to a corresponding semiconductor connector 2512. At this time, when the gate-ring transistor is in the on state, the presence of the semiconductor connector 2512 can increase the conductive area of ​​the structure formed by the semiconductor connector 2512 and the corresponding first nanowire / sheet 2511. Based on this, with a constant voltage across each first nanowire / sheet 2511 along its length, increasing the conductive area of ​​the structure can reduce the conductive resistance of the structure, thereby increasing the current through each first nanowire / sheet 2511, improving the driving capability of each first nanowire / sheet 2511, and ultimately enhancing the electrical performance of the semiconductor device. Furthermore, the width of the semiconductor connector 2512 is smaller than the width of the first nanowire / sheet. At this time, the bottom surface of the first nanowire / sheet 2511 located at the top layer, as well as the bottom and top surfaces of the remaining first nanowires / sheets 2511 located below the top layer, still have some surfaces that are not blocked by the corresponding semiconductor connectors 2512. This can improve the control capability of the gate stack structure 26 over each layer of first nanowires / sheets 2511, which is beneficial to further improve the electrical performance of the semiconductor device.

[0045] In practical applications, such as Figure 13 , Figure 27 , Figure 36 and Figure 45 As shown, when the first channel portion 251 includes at least two layers of first nanowires / sheets 2511, the widths of the different semiconductor interconnects 2512 included in the first channel portion 251 can be the same. Based on this, in the actual manufacturing process, the sacrificial layer included in the first stack is a film layer used to manufacture the semiconductor interconnects 2512. In this case, when the widths of the different semiconductor interconnects 2512 included in the first channel portion 251 are the same, the sacrificial layers included in the multiple first stacks can be simultaneously subjected to lateral thinning processing, thereby simplifying the manufacturing process of the first channel portion 251 and reducing the manufacturing difficulty of the first channel portion 251.

[0046] like Figure 13 , Figure 27 , Figure 36 and Figure 45 As shown, when the first channel portion 251 includes at least two layers of first nanowires / wafers 2511, the heights of the different semiconductor interconnects 2512 included in the first channel portion 251 can be the same. Based on this, as mentioned above, in the actual manufacturing process, the sacrificial layer included in the first stack is a film layer used to manufacture the semiconductor interconnects 2512. In this case, when the heights of the different semiconductor interconnects 2512 included in the first channel portion 251 are the same, the thickness of the sacrificial layer included in the multiple first stacks is also the same. At this time, when the sacrificial layers included in the multiple first stacks are simultaneously subjected to lateral thinning, it is possible to prevent the lateral length of the etchant etching different sacrificial layers from being different due to the different heights of the different sacrificial layers, which would increase the difficulty of controlling the lateral thinning process and make it easier to obtain semiconductor devices.

[0047] Of course, when the first channel portion includes at least two layers of first nanowires / sheets, the width and / or height of the semiconductor interconnect can gradually increase along the direction close to the semiconductor substrate. In this case, along the direction close to the semiconductor substrate, the conductive area of ​​the structure formed by each layer of first nanowires / sheets and the adjacent, lower semiconductor interconnect gradually increases. In this case, as mentioned above, the on-resistance corresponding to each layer of first nanowires / sheets gradually increases along the direction close to the semiconductor substrate. Correspondingly, along the direction close to the semiconductor substrate, the voltage across each end of the first nanowire / sheet along its length gradually decreases. Therefore, when the conductive area of ​​each layer gradually increases along the direction close to the semiconductor substrate, it is advantageous to make the current magnitude of the first nanowires / sheets in different layers equal when the semiconductor device is in the working state, thereby making the driving capability of the first nanowires / sheets in different layers approximately the same, further improving the electrical performance of the semiconductor device.

[0048] Among them, such as Figure 23 , Figure 33 and Figure 42 As shown, when the first channel portion 251 includes at least two layers of first nanowires / sheets 2511, the width of the semiconductor interconnect 2512 may gradually increase along the direction close to the semiconductor substrate 11. Alternatively, as Figure 43 As shown, when the first channel portion 251 includes at least two layers of first nanowires / sheets 2511, the height of the semiconductor interconnect 2512 may gradually increase along the direction close to the semiconductor substrate 11. Alternatively, as... Figure 44 As shown, when the first channel portion 251 includes at least two layers of first nanowires / sheets 2511, the width and height of the semiconductor connector 2512 may gradually increase along the direction close to the semiconductor substrate 11.

[0049] Specifically, the relationship between the height and width of each semiconductor connector can be set according to actual needs, and is not specifically limited here. For example, the aspect ratio of the semiconductor connector can be from 1:5 to 5:1. In this case, while ensuring that the gate stack structure has a high degree of control over the first channel, the driving capability of each layer of the first nanowire / wafer can also be improved.

[0050] In one example, such as Figure 45 As shown, at least one first nanowire / sheet 2511 and at least one second nanowire / sheet 2521 can be self-aligned. In this case, the structure of the channel region 25 is relatively regular, which is beneficial to simultaneously forming the channel layer for manufacturing the first nanowire / sheet 2511 and the channel layer for manufacturing the second nanowire / sheet 2521 under the masking effect of the same mask layer, thereby reducing the difficulty of forming the channel region 25.

[0051] Of course, along a direction parallel to the surface of the semiconductor substrate, the first nanowire / sheet included in the first channel portion may also be staggered from the second nanowire / sheet included in the second channel portion.

[0052] In one example, such as Figure 8 and Figure 45 As shown, the semiconductor device further includes a shallow trench isolation structure 14, a gate sidewall 17, and a dielectric layer 21. The shallow trench isolation structure 14 is formed on the semiconductor substrate 11 to isolate different active regions of the semiconductor substrate 11, preventing leakage. The thickness of the shallow trench isolation structure 14 can be set according to actual conditions. The material of the shallow trench isolation structure 14 can be an insulating material such as SiN, Si3N4, SiO2, or SiCO. The gate sidewall 17 is formed at least on both sides of the gate stack structure 26 along its length direction (parallel to the length direction of the channel region 25) to isolate the gate included in the gate stack structure 26 from other subsequently formed conductive structures, improving the electrical stability of the semiconductor device. The material of the gate sidewall 17 can be an insulating material such as silicon oxide or silicon nitride. The dielectric layer 21 covers the semiconductor substrate 11, and its top is flush with the top of the gate stack structure 26. In actual manufacturing, the presence of the dielectric layer 21 can protect the source region 18 and the drain region 19 from subsequent operations such as removing the sacrificial layer included in the second stack and manufacturing the semiconductor interconnect 2512, thereby improving the yield of the semiconductor device. The material of the dielectric layer 21 can be an insulating material such as silicon oxide or silicon nitride.

[0053] In some cases, the aforementioned semiconductor device may also include an inner sidewall (not shown in the figure). This inner sidewall is formed between the gate stack structure and the source region, and between the gate stack structure and the drain region, to define the length of the gate stack structure. The material of the inner sidewall may be an insulating material such as silicon oxide or silicon nitride.

[0054] This invention provides a method for manufacturing a semiconductor device. The following will describe a method based on... Figures 2 to 45 The illustrated cross-sectional or perspective view describes the manufacturing process. Specifically, the method for manufacturing this semiconductor device includes:

[0055] First, a semiconductor substrate is provided. The structure and materials of this semiconductor substrate can be referred to in the previous text, and will not be repeated here.

[0056] like Figure 7 , Figure 36 ,as well as Figures 42 to 44 As shown, an active structure is formed on a semiconductor substrate 11. The active structure includes a source region 18, a drain region 19, and a channel region 25 located between the source region 18 and the drain region 19, with the channel region 25 contacting both the source region 18 and the drain region 19. The channel region 25 includes a first channel portion 251 and a second channel portion 252 located above and spaced apart from the first channel portion 251. The first channel portion 251 includes at least one layer of first nanowires / sheets 2511 and semiconductor interconnects 2512 located between each layer of first nanowires / sheets 2511 and an adjacent first structure. The width of the semiconductor interconnect 2512 is smaller than the width of the first nanowires / sheets 2511, and the material of the semiconductor interconnect 2512 is different from the material of the first nanowires / sheets 2511. The first structure is the semiconductor substrate 11 and / or an adjacent layer of first nanowires / sheets 2511. The second channel portion 252 includes at least one layer of second nanowires / sheets 2521.

[0057] Specifically, information regarding the structure and materials of the source region, drain region, and channel region included in this active structure can be found in the previous text and will not be repeated here.

[0058] In practical applications, forming an active structure on a semiconductor substrate may include the following steps:

[0059] like Figure 9 As shown, a fin structure 20 is formed on a semiconductor substrate 11. Along the thickness direction of the semiconductor substrate 11, the fin structure 20 includes at least one first stack 201 and at least one second stack 202 located on the at least one first stack 201. Each first stack 201 and each second stack 202 includes a sacrificial layer 203 and a channel layer 204 located on the sacrificial layer 203.

[0060] Specifically, the channel layer in the first stack of the fin structure is used to fabricate the first nanowire / wafer included in the first channel portion. The sacrificial layer in the first stack is used to fabricate the aforementioned semiconductor interconnect. Therefore, the number of layers in the first stack of the fin structure is equal to the number of layers in the first nanowire / wafer included in the first channel portion. The material and thickness of the channel layer in each first stack are the same as the material and thickness of the corresponding first nanowire / wafer layer. The material and thickness of the sacrificial layer in each first stack are the same as the material and thickness of the corresponding semiconductor interconnect layer.

[0061] For example, as mentioned above, when the first channel portion includes at least two layers of first nanowires / sheets, the thickness of the different semiconductor interconnects is the same along the direction close to the semiconductor substrate. In this case, as... Figure 9 As shown, the sacrificial layers 203 included in different first stacks 201 have the same thickness.

[0062] For example, as mentioned above, when the first channel portion includes at least two layers of first nanowires / sheets, the thickness of the semiconductor interconnects included in the first channel portion gradually increases along the direction close to the semiconductor substrate. In this case, the fin structure includes at least two first stacked layers, and the thickness of the sacrificial layer included in the at least two first stacked layers gradually increases along the direction close to the semiconductor substrate.

[0063] Regarding the second stack included in the fin structure, the channel layer in the second stack is used to fabricate the second nanowire / sheet included in the second channel portion. The sacrificial layer in the second stack is used to form voids between adjacent second nanowires / sheets, or voids between the bottom second nanowire / sheet and the first channel portion. Based on this, the number of layers in the second stack included in the fin structure is equal to the number of layers in the second nanowire / sheet included in the second channel portion. The material and thickness of the channel layer included in each second stack are the same as the material and thickness of the corresponding second nanowire / sheet. The material of the sacrificial layer included in each second stack can be any semiconductor material different from the material of the channel layer included in the first and second stacks. The thickness of the sacrificial layer included in each second stack can be determined according to the specifications of the second gate stack, and is not specifically limited here.

[0064] Furthermore, when the first nanowire / sheet and the second nanowire / sheet are made of the same material, the channel layers included in the first and second stacks are made of the same material. Alternatively, when the first nanowire / sheet and the second nanowire / sheet are made of different materials, the channel layers included in the first and second stacks are made of different materials. Moreover, the sacrificial layers included in the first and second stacks can be made of the same or different materials.

[0065] In actual manufacturing processes, back-gate technology is mostly used to form the gate stack structure of semiconductor devices to prevent doped conductive particles from affecting the gate stack structure during the formation of the source and drain regions, thereby improving the formation quality of the gate stack structure. Based on this, the following describes the manufacturing steps for forming a fin structure on a semiconductor substrate using a back-gate process as an example:

[0066] like Figure 4 As shown, a fin 15 is formed on a semiconductor substrate 11. Along the length direction of the fin 15, the fin 15 includes a source formation region 151, a drain formation region 152, and a channel formation region 153 located between the source formation region 151 and the drain formation region 152.

[0067] For example, such as Figure 2 As shown, alternating sacrificial material layers 12 and channel material layers 13 can be sequentially formed on a semiconductor substrate 11 using processes such as epitaxial growth. Of all the sacrificial material layers 12, the lower sacrificial material layer 12 is a film layer used to manufacture the sacrificial layer included in the first stack, and the upper sacrificial material layer 12 is a film layer used to manufacture the sacrificial layer included in the second stack. Of all the channel material layers 13, the lower channel material layer 13 is a film layer used to manufacture the channel layer included in the second stack, and the upper channel material layer 13 is a film layer used to manufacture the channel layer included in the second stack. Next, as... Figure 3 As shown, photolithography and etching processes can be used to etch downwards from the top trench material layer to a portion of the semiconductor substrate 11 to form a fin-like structure on the semiconductor substrate 11. The depth of etching on the semiconductor substrate 11 is greater than or equal to the height of the subsequently formed shallow trench isolation structure. Then, as... Figure 4 As shown, shallow trench isolation structures 14 can be formed on the portion of the semiconductor substrate 11 exposed outside the fin-like structure using processes such as chemical vapor deposition and etching. The portion of the fin-like structure exposed outside the shallow trench isolation structure 14 is the fin portion 15.

[0068] like Figure 5 As shown, a sacrificial gate 16 is formed across the channel forming area included in the fin 15.

[0069] For example, processes such as chemical vapor deposition can be used to form a sacrificial gate material covering the shallow trench isolation structure and fins. This sacrificial gate material can be an easily removable material such as polycrystalline silicon. Figure 5 As shown, then, under the masking effect of the corresponding mask layer, wet or dry etching processes can be used to selectively etch the sacrificial gate material, so that the remaining part of the sacrificial gate material forms the sacrificial gate 16. For example, Figure 6As shown above, when the semiconductor device also includes gate sidewalls 17, processes such as chemical vapor deposition and dry etching can be used to form gate sidewalls 17 located on both sides of the sacrificial gate 16 along the length direction.

[0070] like Figure 7 As shown, the portions of the fin located in the source formation region and the drain formation region are processed respectively to form the source region 18 and the drain region 19. The portion of the fin located in the channel formation region forms a fin-like structure 20.

[0071] For example, processes such as plasma implantation can be used to directly process the portions of the fin located in the source and drain formation regions, at least under the masking effect of the sacrificial gate, so that the portion of the fin located in the source formation region forms the source region, and the portion of the fin located in the drain formation region forms the drain region. Alternatively, processes such as dry etching can be used to remove the portions of the fin located in the source and drain formation regions, at least under the masking effect of the sacrificial gate. Figure 7 As shown, a source region 18 can then be formed at least within the source formation region and a drain region 19 can be formed at least within the drain formation region using processes such as epitaxial growth. The portion of the fin located within the channel formation region forms the aforementioned fin structure 20.

[0072] like Figure 8 As shown above, when the semiconductor device also includes a dielectric layer 21, after forming the source region 18 and the drain region, a dielectric material covering the formed structure can be formed using processes such as chemical vapor deposition. The dielectric material can then be planarized using processes such as chemical mechanical polishing until the top of the sacrificial gate 16 is exposed, with the remaining dielectric material forming the dielectric layer 21.

[0073] like Figure 9 As shown, after the fin structure 20 is formed on the semiconductor substrate 11, before performing subsequent operations, the above-mentioned semiconductor device manufacturing method further includes the step of removing the sacrificial gate to expose the fin structure 20 for subsequent operations.

[0074] like Figure 7 , Figure 36 ,as well as Figures 42 to 44 As shown, the sacrificial layer 203 included in each second stack 202 is then removed, so that the channel layer 204 included in each second stack 202 forms a corresponding second nanowire / sheet 2521; and along the width direction of the fin structure 20, the sacrificial layer 203 included in each first stack 201 is subjected to a first lateral thinning process, so that the remaining portion of the sacrificial layer 203 included in each first stack 201 forms a corresponding semiconductor interconnect 2512, and the channel layer 204 included in each first stack 201 forms a first nanowire / sheet 2511.

[0075] In the actual manufacturing process, depending on whether the sacrificial layers included in the first and second stacks are made of the same material, the above-mentioned situations of forming the first nanowire / sheet and the second nanowire / sheet can be divided into the following two types:

[0076] The first scenario involves a sacrificial layer in the first stack being made of a material different from that in the second stack. In this case, there is a specific etching selectivity between the sacrificial layers in the first and second stacks. Furthermore, since both the sacrificial layers in the first and second stacks have specific etching selectivity ratios with their respective channel layers, the formation order of the first nanowire / wafer and the second nanowire / wafer can be determined based on the number of semiconductor interconnects included in the first channel portion and the size of the semiconductor interconnects.

[0077] Specifically, when the first channel portion includes one semiconductor interconnect, or when the first channel portion includes multiple semiconductor interconnects with the same width, after removing the sacrificial gate, an etchant that only etches the sacrificial layer included in the second stack can be directly used to remove all the sacrificial layers included in the second stack, so that the channel layer included in the second stack forms the second nanowire / wafer. Then, an etchant that only etches the sacrificial layer included in the first stack is used to laterally thin each sacrificial layer included in the first stack along the width direction of the active structure until the remaining portion of the sacrificial layer included in the first stack forms a semiconductor interconnect.

[0078] Alternatively, after removing the sacrificial gate, an etchant effective only against the sacrificial layer of the first stack can be used to laterally thin each sacrificial layer of the first stack along the width of the active structure until the remaining portion of the sacrificial layer of the first stack forms a semiconductor interconnect. Then, an etchant effective only against the sacrificial layer of the second stack is used to remove all the sacrificial layers of the second stack, so that the channel layer of the second stack forms a second nanowire / wafer.

[0079] When the first channel portion includes multiple semiconductor interconnects, and the width of the semiconductor interconnects included in the first channel portion gradually increases along the direction close to the semiconductor substrate, the fin structure includes at least two first stacked layers. Furthermore, after removing the sacrificial gate and before performing a first lateral thinning process on the sacrificial layer included in each of the first stacked layers, a first protective layer covering the sidewalls of the at least two first stacked layers along the width direction can be formed on the semiconductor substrate using processes such as chemical vapor deposition and etching. This first protective layer can be a protective film layer that is easy to remove, such as a spin-coated carbon layer, a bottom anti-reflective layer, or an advanced patterning layer. The top height of the first protective layer is less than the bottom height of the top sacrificial layer in the at least two first stacked layers, and greater than the top height of the second-to-top sacrificial layer in the at least two first stacked layers. For example, in a fin structure comprising three first layers, with the number of layers in each first layer ordered from smallest to largest from bottom to top, the top height of the first protective layer needs to be less than the bottom height of the sacrificial layer included in the third first layer, and greater than the top height of the sacrificial layer included in the second first layer. Next, dry etching or wet etching processes can be used to sequentially perform a first lateral thinning process on at least two of the sacrificial layers included in the first layer, along the direction close to the semiconductor substrate and under the protection of the first protective layer, until the sacrificial layers included in at least two of the first layers form the corresponding semiconductor interconnect. The number of times the first lateral thinning process is performed is equal to the number of first layers in the fin structure. For example, taking a fin structure comprising three first layers as an example: as mentioned above, when the top height of the first protective layer is less than the bottom height of the sacrificial layer included in the third first layer, and greater than the top height of the sacrificial layer included in the second first layer, the sacrificial layer included in the third first layer is exposed. Based on this, in the first execution process: under the protection of the first protective layer, a wet etching process or a dry etching process can be used to perform the first lateral thinning treatment only on the sacrificial layer included in the third layer of the first stack. Then, in the second execution process: the first protective layer is etched back, so that the top height of the first protective layer is less than the bottom height of the sacrificial layer included in the second layer of the first stack, but greater than the top height of the sacrificial layer included in the first layer of the first stack, so that the sacrificial layer included in the second layer of the first stack is also exposed. Under the protection of the first protective layer, a wet etching process or a dry etching process can be used to simultaneously perform the first lateral thinning treatment on the sacrificial layers included in the third and second layers of the first stack. Finally, in the third execution process: the first protective layer is removed, so that the sacrificial layer included in the first layer of the first stack is also exposed. A wet etching process or a dry etching process is then used to simultaneously perform the first lateral thinning treatment on the sacrificial layers included in the first to third layers of the first stack.

[0080] It is understandable that the sacrificial layer included in the third layer of the first stack underwent three first lateral thinning processes, the sacrificial layer included in the second layer of the first stack underwent two first lateral thinning processes, and the sacrificial layer included in the first layer of the first stack underwent only one first lateral thinning process. In other words, as the number of sacrificial layers included in the first stack increases, the more layers in the first stack, the more times the sacrificial layer undergoes first lateral thinning processes. Therefore, under the same processing conditions, the width of the semiconductor interconnect included in the obtained first channel portion can gradually increase along the direction close to the semiconductor substrate.

[0081] Specifically, regardless of which method is used to form the first nanowire / wafer and the second nanowire / wafer, the process and etchant used for lateral thinning of the sacrificial layer in each first stack along the width direction of the active structure can be determined based on the materials of the channel layer and the sacrificial layer in the first stack, and are not specifically limited here. For example, if the material of the channel layer in the first stack is silicon and the material of the sacrificial layer is germanium-silicon, an oxidizing solution such as nitric acid can be used to first oxidize the sacrificial layer in the first stack to reduce the size of the sacrificial layer along the width direction and form a sacrificial oxide layer on the sidewalls of the sacrificial layer along the width direction. Then, hydrofluoric acid can be used to remove the sacrificial oxide layer. The above operation is repeated until the width of the remaining portion of the sacrificial layer is equal to the width of the corresponding semiconductor interconnect.

[0082] The second scenario involves the sacrificial layer in the first stack being made of the same material as the sacrificial layer in the second stack. In this case, the etchant that etches the sacrificial layer in the first stack will also etch the sacrificial layer in the second stack. Therefore, a protective layer needs to be formed to prevent over-etching of the sacrificial layer in the first stack during the etching process of the sacrificial layer in the second stack, which could prevent the formation of semiconductor interconnects and improve the yield of semiconductor devices. Depending on the formation order of the protective layer, the formation of the first nanowire / wafer and the second nanowire / wafer can be further subdivided into the following scenarios:

[0083] The first method: In the second case described above, removing the sacrificial layer included in each second stack and performing a first lateral thinning process on the sacrificial layer included in each first stack along the width direction of the fin structure may include the following steps: Figure 10 As shown, the sacrificial layer 203 included in each first stack 201 and each second stack 202 can be simultaneously subjected to a first lateral thinning process along the width direction of the fin structure, using the method described above. Figure 11As shown, a second protective layer 22 is then formed on the semiconductor substrate 11, covering the sidewalls of at least one first stack 201 along its width direction. The top height of this second protective layer 22 is greater than the top height of the sacrificial layer 203 located at the top layer of the at least one first stack 201, and less than the bottom height of the sacrificial layer 203 located at the bottom layer of the at least one second stack 202. For example, in the case where the fin structure 20 includes three first stacks 201, the top height of the second protective layer 22 is greater than the top height of the sacrificial layer 203 included in the third first stack 201, and less than the bottom height of the sacrificial layer 203 included in the first second stack 202. The material of the second protective layer 22 can be referenced to the material of the first protective layer described above, and will not be repeated here. Figure 12 As shown, then, under the protection of the second protective layer 22, the remaining portion of the sacrificial layer 203 included in each second stack 202 can be selectively removed using processes such as dry etching or wet etching. At this time, although the materials of the sacrificial layer 203 included in the first stack 201 and the second stack 202 are the same, under the protection of the second protective layer 22, the remaining portion of the sacrificial layer 203 included in the first stack 201 (i.e., the semiconductor interconnect 2512) is not affected by the aforementioned selective etching. Figure 13 As shown, the second protective layer can finally be removed by dry or wet etching processes to expose the first channel portion 251, which facilitates the subsequent formation of the gate stack structure.

[0084] In the first scenario described above, as mentioned earlier, the first channel portion includes a plurality of semiconductor interconnects. Furthermore, the width of these plurality of semiconductor interconnects can gradually increase along the direction close to the semiconductor substrate. In this case, the fin structure includes at least two first stacked layers. And, after removing the sacrificial gate, and before simultaneously performing a first lateral thinning process on the sacrificial layer included in each first stacked layer and the sacrificial layer included in each second stacked layer along the width direction of the fin structure, the semiconductor device manufacturing method further includes the step of: Figure 14 As shown, a third protective layer 23 is formed on the semiconductor substrate 11, covering the sidewalls of at least two first stacked layers 201 along the width direction. The top height of the third protective layer 23 is less than the bottom height of the sacrificial layer 203 located at the top layer of the at least two first stacked layers 201, and greater than the top height of the sacrificial layer 203 located at the second-to-top layer of the at least two first stacked layers 201. For example, in the case where the fin structure 20 includes three first stacked layers 201, the top height of the third protective layer 23 is less than the bottom height of the sacrificial layer 203 included in the third first stacked layer 201, and greater than the top height of the sacrificial layer 203 included in the second first stacked layer 201. The material and formation method of the third protective layer 23 can be referred to the material and formation method of the first protective layer described above, and will not be repeated here. Figures 15 to 19As shown, then along the direction close to the semiconductor substrate 11 and under the protection of the third protective layer 23, the sacrificial layer 203 included in at least one second stack 202 is subjected to a second lateral thinning process, while the sacrificial layer 203 included in at least two first stacks 201 is subjected to a third lateral thinning process layer by layer until the width of the sacrificial layer 203 included in at least two first stacks 201 is thinned to the target width.

[0085] Specifically, the process of sequentially performing a third lateral thinning treatment on at least two sacrificial layers of the first stack under the protection of the third protective layer can be referenced to the process of sequentially performing a first lateral thinning treatment on at least two sacrificial layers of the first stack under the protection of the first protective layer, as described above, and will not be repeated here. The difference is that, since the sacrificial layers of the first and second stacks are made of the same material, a second lateral thinning treatment will also be performed on the sacrificial layers of the second stack exposed outside the third protective layer during the aforementioned third lateral thinning treatment. Additionally, as... Figures 20 to 23 As shown, since the third lateral thinning process described above is performed, the first lateral thinning process is also required for the sacrificial layer 203 included in at least two first stacked layers 201. Therefore, the target width value of the sacrificial layer 203 included in each first stacked layer 201 after the third lateral thinning process can be determined based on the semiconductor connector 2512 and the width of the first lateral thinning process. No specific limitation is made here.

[0086] The second method: In the second case described above, after removing the sacrificial gate and before performing a first lateral thinning process on the sacrificial layer included in each first stack along the width direction of the fin structure, the manufacturing method of the semiconductor device further includes: Figure 24 As shown, a fourth protective layer 24 is formed on a semiconductor substrate 11, covering the sidewalls of at least one first stack 201 along its width direction. The top height of the fourth protective layer 24 is greater than the top height of the sacrificial layer 203 located at the top layer of the at least one first stack 201, and less than the bottom height of the sacrificial layer 203 located at the bottom layer of the at least one second stack 202. For example, in the case where the fin structure 20 includes three first stacks 201, the top height of the fourth protective layer 24 is greater than the top height of the sacrificial layer 203 included in the third first stack 201, and less than the bottom height of the sacrificial layer 203 included in the first second stack 202. The material of the fourth protective layer 24 can refer to the material of the first protective layer described above, and will not be repeated here. In this case, after the above-mentioned fourth protective layer 24 is formed on the semiconductor substrate 11, and before performing a first lateral thinning process on the sacrificial layer 203 included in each first stack 201 along the width direction of the fin structure 20, the method for manufacturing the semiconductor device includes the steps as follows: Figure 25As shown, dry or wet etching processes can be used to completely remove the sacrificial layer 203 included in each second stack 202. Then, the removal method of the fourth protective layer 24 can be determined according to the number and size of the semiconductor interconnects 2512 included in the first channel portion 251.

[0087] For example, when the first channel portion includes one semiconductor connector, or when the first channel portion includes multiple semiconductor connectors and the multiple semiconductor connectors have the same width, such as Figure 26 As shown, the fourth protective layer can be removed after all the sacrificial layers included in each second stack have been removed. At this point, at least two first stacks 201 of the fin structure are fully exposed. Figure 27 As shown, the first lateral thinning process can be performed simultaneously on the sacrificial layers of at least two first stacks in the manner described above to obtain the first nanowire / sheet 2511.

[0088] For example, when the first channel portion includes multiple semiconductor connectors, and the width of the semiconductor connectors included in the first channel portion gradually increases along the direction close to the semiconductor substrate, such as... Figures 28 to 33 As shown, along the direction close to the semiconductor substrate 11 and under the protection of the fourth protective layer 24, the sacrificial layers 203 included in at least two first stacked layers 201 are sequentially subjected to a first lateral thinning process until the sacrificial layers 203 included in at least two first stacked layers 201 form the corresponding semiconductor interconnect 2512. The specific execution process can refer to the execution process of performing the first lateral thinning process on the sacrificial layers 203 included in at least two first stacked layers 201 sequentially under the protection of the first protective layer, as described above, and will not be repeated here.

[0089] The third method: In the second case described above, after removing the sacrificial gate and before performing a first lateral thinning process on the sacrificial layer included in each first stack along the width direction of the fin structure, the manufacturing method of the semiconductor device further includes: Figure 24 As shown, a fourth protective layer 24 is formed on a semiconductor substrate 11, covering the sidewalls of at least one first stack 201 along its width direction. The top height of the fourth protective layer 24 is greater than the top height of the sacrificial layer 203 located at the top layer of the at least one first stack 201, and less than the bottom height of the sacrificial layer 203 located at the bottom layer of the at least one second stack 202. Specifically, the top height, formation method, and material of the fourth protective layer 24 can be referred to the foregoing. In the above case, after forming the fourth protective layer 24 on the semiconductor substrate 11 and before forming the gate stack structure on the outer periphery of the channel region 25, the manufacturing method of the above semiconductor device includes: Figure 34As shown, under the protection of the fourth protective layer 24, the sacrificial layer 203 included in each second stack 202 undergoes a fourth lateral thinning process along the width direction of the fin structure 20. For example... Figures 35 to 42 As shown, the fourth protective layer is then removed, and the remaining portion of the sacrificial layer 203 included in each first stack 201 is removed while the first lateral thinning process is performed on the sacrificial layer 203 included in each second stack 202.

[0090] It is understandable that after the fourth lateral thinning process and the first lateral thinning process described above, the sacrificial layer included in the second stack can be completely removed. Therefore, after the fourth lateral thinning process, the width of the remaining part of the sacrificial layer included in each second stack is less than or equal to the width that can be etched by the subsequent first lateral thinning process.

[0091] In addition, after the fourth lateral thinning process, the method of removing the fourth protective layer can be determined based on the number and size of the semiconductor connectors included in the first channel portion.

[0092] For example, when the first channel portion includes one semiconductor connector, or when the first channel portion includes multiple semiconductor connectors and the multiple semiconductor connectors have the same width, such as Figure 35 As shown, the fourth protective layer can be removed using either dry or wet etching methods to expose at least one first stack 201 of the fin structure. Figure 36 As shown, the first lateral thinning process can be performed simultaneously on all exposed first stacks, including the sacrificial layer, in the manner described above to obtain the first nanowire / sheet 2511.

[0093] For example, when the first channel portion includes multiple semiconductor connectors, and the width of the semiconductor connectors included in the first channel portion gradually increases along the direction close to the semiconductor substrate, such as... Figures 37 to 42 As shown, along the direction close to the semiconductor substrate 11 and under the protection of the fourth protective layer 24, at least two layers of the first stack 201, including the sacrificial layer 203, are sequentially subjected to a first lateral thinning process until the sacrificial layer 203 of the at least two layers of the first stack 201 forms the corresponding semiconductor interconnect 2512. The specific execution process can be referred to the previously described process of sequentially performing the first lateral thinning process on the sacrificial layer 203 of the at least two layers of the first stack 201 under the protection of the first protective layer, and will not be repeated here.

[0094] like Figure 45 As shown, a gate stack structure 26 is finally formed on the outer periphery of the channel region 25.

[0095] For example, the above-described gate stack structure can be formed using processes such as atomic layer deposition. The components of the gate stack structure and the materials of each component can be referred to the preceding text.

[0096] Where, as mentioned above, when the materials of the first gate stack and the second gate stack included in the gate stack structure are different, the above-mentioned formation of the gate stack structure on the outer periphery of the channel region may include the following steps:

[0097] First, a first gate stack can be formed on the outer periphery of both the first and second channel portions using processes such as atomic layer deposition. Next, the first gate stack formed on the outer periphery of the second channel portion is removed. Specifically, the gate dielectric layer and gate electrode included in the first gate stack formed on the outer periphery of the second channel portion can be completely removed. Alternatively, if the gate dielectric layers of the first and second gate stack portions are made of the same material, only the gate electrode included in the first gate stack formed on the outer periphery of the second channel portion can be removed. Finally, as... Figure 45 As shown, a second gate stack 262 is formed on the outer periphery of the second channel portion 252 to obtain a gate stack structure 26.

[0098] Compared with the prior art, the beneficial effects of the semiconductor device manufacturing method provided in the embodiments of the present invention can be referred to the beneficial effects analysis of the semiconductor device provided in the above embodiments, and will not be repeated here.

[0099] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0100] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: Semiconductor substrate; An active structure is formed on the semiconductor substrate; The active structure includes a source region, a drain region, and a channel region located between the source region and the drain region, the channel region being in contact with the source region and the drain region respectively; the channel region includes a first channel portion and a second channel portion located above and spaced apart from the first channel portion; the first channel portion includes at least one layer of first nanowire / wafer and a semiconductor interconnect located between each layer of first nanowire / wafer and an adjacent first structure, the width of the semiconductor interconnect being smaller than the width of the first nanowire / wafer, and the material of the semiconductor interconnect being different from the material of the first nanowire / wafer; The first structure is the semiconductor substrate and / or the adjacent layer of the first nanowire / sheet; the second channel portion includes at least one layer of second nanowire / sheet; And a gate stack structure is formed on the outer periphery of the channel region; In the case where the first channel portion includes at least two layers of the first nanowire / sheet, the height of the semiconductor connector gradually increases along the direction close to the semiconductor substrate.

2. The semiconductor device according to claim 1, characterized in that, When the first channel portion includes at least two layers of the first nanowire / sheet, the line connecting the geometric centers of the semiconductor interconnects included in the first channel portion is parallel to the height direction of the active structure; and / or, The line connecting each of the semiconductor interconnects to the geometric center of the adjacent first nanowire / sheet is parallel to the height direction of the active structure.

3. The semiconductor device according to claim 1 or 2, characterized in that, The aspect ratio of the semiconductor connector is 1:5 to 5:1; and / or, The width of the semiconductor connector is 3nm to 15nm.

4. The semiconductor device according to claim 1 or 2, characterized in that, The material of the first nanowire / sheet is Si x Ge 1-x The semiconductor connector is made of Si. y Ge 1-y ; Where, 0≤x≤1, 0≤y≤1, |xy|≥0.2; and / or, The material of the first nanowire / sheet is the same as that of the second nanowire / sheet.

5. The semiconductor device according to claim 1 or 2, characterized in that, The at least one first nanowire / sheet and the at least one second nanowire / sheet are self-aligned.

6. The semiconductor device according to claim 1 or 2, characterized in that, The gate stack structure includes a first gate stack portion and a second gate stack portion; the first gate stack portion is formed on the outer periphery of the first channel portion, and the second gate stack portion is formed on the outer periphery of the second channel portion; the material of the first gate stack portion is different from the material of the second gate stack portion.

7. A method for manufacturing a semiconductor device, characterized in that, include: Provide a semiconductor substrate; An active structure is formed on the semiconductor substrate; the active structure includes a source region, a drain region, and a channel region located between the source region and the drain region, the channel region being in contact with the source region and the drain region respectively; the channel region includes a first channel portion and a second channel portion located above and spaced apart from the first channel portion; the first channel portion includes at least one layer of first nanowires / sheets and a semiconductor connector located between each layer of first nanowires / sheets and an adjacent first structure, the width of the semiconductor connector being smaller than the width of the first nanowires / sheets, and the material of the semiconductor connector being different from the material of the first nanowires / sheets; the first structure is the semiconductor substrate and / or an adjacent layer of first nanowires / sheets; the second channel portion includes at least one layer of second nanowires / sheets; when the first channel portion includes at least two layers of first nanowires / sheets, the height of the semiconductor connector gradually increases along the direction close to the semiconductor substrate; A grid stack structure is formed on the outer periphery of the channel region.

8. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The formation of the active structure on the semiconductor substrate includes: A fin-like structure is formed on the semiconductor substrate; along the thickness direction of the semiconductor substrate, the fin-like structure includes at least one first stack and at least one second stack located on the at least one first stack; each of the first stack and each of the second stack includes a sacrificial layer and a channel layer located on the sacrificial layer; The sacrificial layer included in each second stack is removed, so that the channel layer included in each second stack forms the corresponding second nanowire / sheet; and along the width direction of the fin structure, the sacrificial layer included in each first stack is subjected to a first lateral thinning process, so that the remaining portion of the sacrificial layer included in each first stack forms the corresponding semiconductor interconnect, and the channel layer included in each first stack forms the first nanowire / sheet.

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that, The formation of the fin-like structure on the semiconductor substrate includes: A fin is formed on the semiconductor substrate; along the length direction of the fin, the fin includes a source formation region, a drain formation region, and a channel formation region located between the source formation region and the drain formation region; A sacrificial gate is formed across the channel formation area included in the fin; The portions of the fin located within the source formation region and the drain formation region are processed respectively to form the source region and the drain region; the portion of the fin located within the channel formation region forms the fin-like structure; The method for manufacturing a semiconductor device further includes removing the sacrificial gate before removing the sacrificial layer included in each second stack after forming the fin structure on the semiconductor substrate and before performing a first lateral thinning process on the sacrificial layer included in each first stack along the width direction of the fin structure.

10. The method for manufacturing a semiconductor device according to claim 9, characterized in that, The material of the sacrificial layer included in the first stack is different from the material of the sacrificial layer included in the second stack.

11. The method for manufacturing a semiconductor device according to claim 10, characterized in that, In the case where the fin structure comprises at least two layers of the first stack, After removing the sacrificial gate, and before performing a first lateral thinning process on the sacrificial layer included in each of the first stacked layers, the method for manufacturing the semiconductor device further includes: forming a first protective layer on the semiconductor substrate, covering the sidewalls of the at least two first stacked layers along the width direction; the top height of the first protective layer is less than the bottom height of the top sacrificial layer in the at least two first stacked layers, and greater than the top height of the second-to-top sacrificial layer in the at least two first stacked layers; The first lateral thinning process for each of the first stacked layers includes: performing the first lateral thinning process on the sacrificial layers of the at least two first stacked layers sequentially along the direction close to the semiconductor substrate and under the protection of the first protective layer, until the sacrificial layers of the at least two first stacked layers form the corresponding semiconductor interconnect.

12. The method for manufacturing a semiconductor device according to claim 9, characterized in that, The material of the sacrificial layer included in the first stack is the same as the material of the sacrificial layer included in the second stack; Remove the sacrificial layer included in each layer of the second stack; and perform a first lateral thinning process on the sacrificial layer included in each layer of the first stack along the width direction of the fin structure, including: Along the width direction of the fin structure, the sacrificial layer included in each first stack and the sacrificial layer included in each second stack are simultaneously subjected to the first lateral thinning process; On the semiconductor substrate, a second protective layer is formed covering the sidewalls of the at least one first stack along the width direction; the top height of the second protective layer is greater than the top height of the sacrificial layer located at the top layer in the at least one first stack, and less than the bottom height of the sacrificial layer located at the bottom layer in the at least one second stack. Under the protection of the second protective layer, the remaining portion of the sacrificial layer included in each second stack is selectively removed; Remove the second protective layer.

13. The method for manufacturing a semiconductor device according to claim 12, characterized in that, In the case where the fin structure comprises at least two first stacked layers, before the first lateral thinning process is simultaneously performed on the sacrificial layer comprising each first stacked layer and the sacrificial layer comprising each second stacked layer along the width direction of the fin structure after removing the sacrificial gate, the method for manufacturing the semiconductor device further includes: On the semiconductor substrate, a third protective layer is formed covering the sidewalls of the at least two first stacked layers along the width direction; the top height of the third protective layer is less than the bottom height of the top sacrificial layer in the at least two first stacked layers, and greater than the top height of the second-to-top sacrificial layer in the at least two first stacked layers. Along the direction close to the semiconductor substrate and under the protection of the third protective layer, while performing a second lateral thinning process on the sacrificial layer included in the at least one second stack, a third lateral thinning process is performed layer by layer on the sacrificial layer included in the at least two first stacks until the width of the sacrificial layer included in the at least two first stacks is reduced to the target width.

14. The method for manufacturing a semiconductor device according to claim 9, characterized in that, The material of the sacrificial layer included in the first stack is the same as the material of the sacrificial layer included in the second stack; After removing the sacrificial gate, before performing a first lateral thinning process on the sacrificial layer included in each of the first stacks along the width direction of the fin structure, the method for manufacturing the semiconductor device further includes: forming a fourth protective layer on the semiconductor substrate covering the sidewalls of the at least one first stack along the width direction; the top height of the fourth protective layer is greater than the top height of the sacrificial layer located at the top layer in the at least one first stack, and less than the bottom height of the sacrificial layer located at the bottom layer in the at least one second stack; After forming the fourth protective layer on the semiconductor substrate, before performing a first lateral thinning process on the sacrificial layer included in each of the first stacked layers along the width direction of the fin structure, the method of manufacturing the semiconductor device includes: completely removing the sacrificial layer included in each of the second stacked layers; or, after forming the fourth protective layer on the semiconductor substrate, before forming a gate stack structure on the outer periphery of the channel region, the method of manufacturing the semiconductor device includes: under the protection of the fourth protective layer, performing a fourth lateral thinning process on the sacrificial layer included in each of the second stacked layers along the width direction of the fin structure; then removing the fourth protective layer, and simultaneously removing the remaining portion of the sacrificial layer included in each of the second stacked layers while performing the first lateral thinning process on the sacrificial layer included in each of the first stacked layers.

15. The method for manufacturing a semiconductor device according to claim 14, characterized in that, In the case where the fin structure comprises at least two layers of the first stack, the first lateral thinning process performed on the sacrificial layer comprising each layer of the first stack along the width direction of the fin structure includes: Along the direction close to the semiconductor substrate and under the protection of the fourth protective layer, the first lateral thinning process is performed on at least two of the first stacked layers, including the sacrificial layers, layer by layer, until the at least two of the first stacked layers, including the sacrificial layers, form the corresponding semiconductor interconnect.

16. A method for manufacturing a semiconductor device according to any one of claims 8 to 15, characterized in that, In the case where the fin structure includes at least two of the first stacked layers, the thickness of the sacrificial layer included in the at least two first stacked layers gradually increases along the direction close to the semiconductor substrate.

17. A method for manufacturing a semiconductor device according to any one of claims 7 to 15, characterized in that, The formation of the gate stack structure on the outer periphery of the channel region includes: A first gate stack portion is formed on the outer periphery of both the first channel portion and the second channel portion; Remove the first gate stack portion formed on the outer periphery of the second channel portion; A second gate stack is formed on the outer periphery of the second channel portion; the material of the second gate stack is different from that of the first gate stack; the gate stack structure includes the first gate stack and the second gate stack.

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