Charge pump circuit and memory

Abstract

The disclosure provides a charge pump circuit and a memory, and relates to the technical field of memory. The charge pump circuit comprises: a plurality of charge pumps connected in series, each charge pump comprising a voltage input end, a voltage output end, and a first signal input end and a second signal input end; and a clock driving circuit comprising a plurality of clock modules connected one by one with the plurality of charge pumps connected in series, wherein each clock module comprises a first signal output end and a second signal output end, the first signal output end is connected with the first signal input end, the second signal output end is connected with the second signal input end, the clock module outputs a clock driving signal to the corresponding charge pump, and is configured to output the clock driving signal with a delay relative to an adjacent previous clock module, and the phase difference of the delay is within a specified delay range. Through the technical scheme of the disclosure, clock delay is generated between the clock driving signals of the charge pumps in front and back stages, so that additional power consumption can be avoided when the output voltage of the charge pump is improved.

Description

Technical Field

[0001] This disclosure relates to the field of memory technology, and more particularly to a charge pump circuit and a memory. Background Technology

[0002] Various operations of flash memory (e.g., programming and erasing operations) require operating voltages higher than the power supply voltage, so charge pump circuits are typically used to boost the voltage.

[0003] In related technologies, such as Figure 1 The multi-stage charge pump circuit shown has a clock signal Clock processed by clock module 102, which outputs two inverted signals Clk and Clkb, which are then input into each stage of the charge pump (including the first stage charge pump 104, the second stage charge pump 106, and the third stage charge pump 108). The input voltage Vin is input into the first stage charge pump 104. The two inverted signals Clk and Clkb control the charge pump to charge and discharge the boosting capacitor, thereby boosting the output voltage Vout.

[0004] exist Figure 1 In the charge pump circuit shown, each stage of the multi-stage charge pump circuit uses the same pair of clock signals Clk and Clkb. The first signal input terminal of the odd-numbered stage charge pump receives the clock signal Clk, and the second signal input terminal of the even-numbered stage charge pump receives the clock signal Clkb. Without changing the device parameters, if it is necessary to further increase the output voltage of the charge pump, the only way is to increase the frequency of the clock signal, which will incur additional power consumption.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this disclosure is to provide a charge pump circuit and a memory that overcomes, at least to some extent, the problem of additional power consumption caused by increasing the output voltage of the charge pump in the related art.

[0007] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0008] According to one aspect of this disclosure, a charge pump circuit is provided, comprising: a multi-stage series-connected charge pump, each stage of the charge pump including a voltage input terminal, a voltage output terminal, a first signal input terminal, and a second signal input terminal; a clock driving circuit including a plurality of clock modules connected in series with each of the multi-stage series-connected charge pumps, each clock module including a first signal output terminal and a second signal output terminal, the first signal output terminal being connected to the first signal input terminal, and the second signal output terminal being connected to the second signal input terminal, the clock module being used to output a clock driving signal to the corresponding charge pump; wherein the clock module is configured to output the clock driving signal with a delay relative to the adjacent preceding clock module, the phase difference of the delay being greater than or equal to 1 / 5 of a clock cycle and less than or equal to 1 / 4 of a clock cycle.

[0009] In one embodiment of this disclosure, the plurality of clock modules include a first clock module and at least one second clock module connected together. The first clock module is connected to a first-stage charge pump in the multi-stage series charge pump. The second clock module includes a delay unit for delaying the output of the clock drive signal input from the front end to configure the phase difference.

[0010] In one embodiment of this disclosure, the at least one second clock module is connected in series with the first clock module, and when there are multiple second clock modules, the multiple second clock modules are connected in series, wherein each second clock module has the delay unit with the same structure to sequentially configure the delay phase difference.

[0011] In one embodiment of this disclosure, the at least one second clock module is connected in parallel with the first clock module, and when there are multiple second clock modules, multiple second clocks are connected in parallel, wherein each second clock module has a delay unit with a different structure, such that the output phase of the delay unit sequentially increases the phase difference of the delay.

[0012] In one embodiment of this disclosure, the delay unit includes: an inverter chain, the input of which is connected to the adjacent preceding clock module, and the output of which is used to delay the output of the clock drive signal; and a configuration module connected to the inverter chain for configuring the phase difference of the delay.

[0013] In one embodiment of this disclosure, the configuration module includes: a plurality of MOS transistors, which are connected one-to-one with each inverter in the inverter chain; the gate of each MOS transistor is connected to the output terminal of the inverter; the source, drain, and substrate of each MOS transistor are all connected to the source power supply voltage; wherein the phase difference of the delay is configured by adjusting the source power supply voltage.

[0014] In one embodiment of this disclosure, the inverter chain includes a first inverter, a second inverter, a third inverter, and a fourth inverter connected in series. The configuration module includes a resistor and a first capacitor. The resistor is connected in series between the second inverter and the third inverter. One end of the first capacitor is connected between the first inverter and the second inverter, and the other end of the first capacitor is connected between the resistor and the third inverter. The phase difference of the delay is configured based on the resistor and the first capacitor.

[0015] In one embodiment of this disclosure, the first clock module includes a fifth inverter, a first NAND gate, and a second NAND gate. The delay unit includes a first delay unit and a second delay unit in parallel. The input terminal of the fifth inverter and the first input terminal of the first NAND gate receive the original clock signal. The second input terminal of the first NAND gate is connected to the output terminal of the second NAND gate, and the output terminal of the first NAND gate is used to output a positive clock drive signal and is connected to the first delay unit of the connected second clock module. The first input terminal of the second NAND gate is connected to the output terminal of the fifth inverter, and the second input terminal of the second NAND gate is connected to the output terminal of the first NAND gate. The output terminal of the second NAND gate is used to output an inverted clock drive signal and is connected to the second delay unit of the connected second clock module.

[0016] In one embodiment of this disclosure, the clock module further includes a first buffer and a second buffer in parallel. In the first clock module, the input terminal of the first buffer is connected to the output terminal of the first NAND gate, and the output terminal of the first buffer is connected to the first signal terminal of the first-stage charge pump. The input terminal of the second buffer is connected to the output terminal of the second NAND gate, and the output terminal of the second buffer is connected to the second signal terminal of the first-stage charge pump. In the second clock module, the input terminal of the first buffer is connected to the output terminal of the first delay unit, and the output terminal of the first buffer outputs the positive clock drive signal. The input terminal of the second buffer is connected to the output terminal of the second delay unit, and the output terminal of the second buffer outputs the inverted clock drive signal.

[0017] In one embodiment of this disclosure, the charge pump includes a first N-type MOSFET, a second N-type MOSFET, a first P-type MOSFET, a second P-type MOSFET, a second capacitor, and a third capacitor. The sources of the first N-type MOSFET and the second N-type MOSFET are connected to the voltage input terminal, as are the sources of the first P-type MOSFET and the second P-type MOSFET. The drains of the first N-type MOSFET, the first P-type MOSFET, the gates of the second N-type MOSFET, and the second P-type MOSFET are connected to the first terminal of the second capacitor. The drains of the second N-type MOSFET, the second P-type MOSFET, the gates of the first N-type MOSFET, and the first P-type MOSFET are connected to the first terminal of the third capacitor. The second terminal of the second capacitor is the first signal input terminal, and the second terminal of the third capacitor is the second signal input terminal.

[0018] According to another aspect of this disclosure, a memory is provided, including the charge pump circuit described in any of the foregoing technical solutions.

[0019] The charge pump circuit scheme provided by the embodiments of this disclosure includes multiple charge pumps connected in series. Each charge pump is connected to a clock module that provides a clock drive signal. Along the charge transfer direction, the clock drive signal output by each clock module is configured to generate a clock delay relative to the clock drive signal output by the previous clock module. This clock delay extends the charging time of the capacitor in each charge pump, thereby improving the efficiency of charge transfer between charge pumps. Furthermore, by limiting the clock delay to a specified delay range, the charge transfer performance between each stage of charge pump can be guaranteed. This allows for increasing the output voltage and output current of the charge pump circuit without increasing the clock frequency of the clock drive signal or increasing the charge pump capacitance. In other words, by configuring a clock delay between the clock drive signals of the preceding and following charge pumps, the output voltage of the charge pump can be increased without generating additional power consumption.

[0020] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0022] Figure 1This diagram illustrates the structure of a charge pump circuit in the relevant technology.

[0023] Figure 2 This diagram illustrates the structure of a multi-stage series charge pump in a charge pump circuit according to an embodiment of the present disclosure.

[0024] Figure 3 A schematic diagram of a clock drive circuit in a charge pump circuit according to an embodiment of the present disclosure is shown;

[0025] Figure 4 This diagram shows a schematic of the clock drive circuit in a charge pump circuit according to an embodiment of the present disclosure.

[0026] Figure 5 A schematic diagram of a delay unit in a clock drive circuit of a charge pump circuit according to an embodiment of the present disclosure is shown.

[0027] Figure 6 A schematic diagram of a delay unit in a clock drive circuit of another charge pump circuit in an embodiment of this disclosure is shown;

[0028] Figure 7 A schematic diagram of a multi-stage series charge pump in another charge pump circuit according to an embodiment of this disclosure is shown.

[0029] Figure 8 A schematic diagram comparing the transmission signal curves of a charge pump circuit in the related art with those in the present disclosure is shown.

[0030] Figure 9 The graph showing the relationship between the output voltage and output current of the charge pump in an embodiment of this disclosure is illustrated.

[0031] Figure 10 A schematic diagram comparing the output current of a charge pump circuit in the related art with that in the charge pump circuit of this disclosure is shown.

[0032] in, Figures 1 to 6 The annotations in the accompanying drawings are explained as follows:

[0033] 102 Clock module, 104 First-stage charge pump, 106 Second-stage charge pump, 108 Third-stage charge pump, 20 Multi-stage cascaded charge pumps, 30 Clock drive circuit, clk first signal output terminal, clkb second signal output terminal, 302 First clock module, 304 Second clock module, U1 First NAND gate, U2 First NAND gate, 3042 First delay unit, 3044 Second delay unit, X1 First inverter, X2 Second inverter, X3 Third inverter, X4 Fourth inverter, X5 Fifth inverter. Detailed Implementation

[0034] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0035] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0036] To facilitate understanding, the following is an explanation of several terms used in this application.

[0037] A charge pump is a type of DC-DC converter that uses a capacitor as its energy storage element. The solutions provided in this application relate to charge pump circuits and clock signal processing technologies, which are specifically illustrated in the following embodiments.

[0038] A charge pump circuit according to an embodiment of the present disclosure includes a multi-stage series charge pump 20 and a clock drive circuit 30.

[0039] In the multi-stage series charge pump 20, each stage of the charge pump includes a voltage input terminal, a voltage output terminal, a first signal input terminal, and a second signal input terminal.

[0040] Specifically, the multi-stage charge pump has two or more stages, and the multi-stage charge pump connected in series includes at least a first-stage charge pump and a final-stage charge pump. The voltage input terminal of the first-stage charge pump is used to receive the initial voltage, and the voltage output terminal of the final-stage charge pump is used to output the target voltage.

[0041] Specifically, such as Figure 2As shown, the multi-stage series charge pump includes a first-stage charge pump, a second-stage charge pump, and a final-stage charge pump. The first-stage charge pump includes a first N-type MOSFET MN1, a second N-type MOSFET MN2, a first P-type MOSFET MP1, a second P-type MOSFET MP2, a second capacitor Cb1, and a third capacitor Cb2. The sources of the first N-type MOSFET MN1 and the second N-type MOSFET MN2 are connected to the voltage input terminal, and the sources of the first P-type MOSFET MP1 and the second P-type MOSFET MP2 are also connected to the voltage input terminal. The drain of an N-type MOSFET MN1, the drain of a first P-type MOSFET MP1, the gate of a second N-type MOSFET MN2, and the gate of a second P-type MOSFET MP2 are connected to the first terminal of a second capacitor Cb1. The drain of the second N-type MOSFET MN2, the drain of the second P-type MOSFET MP2, the gate of the first N-type MOSFET MN1, and the gate of the first P-type MOSFET MP1 are connected to the first terminal of a third capacitor Cb2. The second terminal of the second capacitor Cb1 is the first signal input terminal, and the second terminal of the third capacitor Cb2 is the second signal input terminal.

[0042] The second-stage charge pump includes a first N-type MOSFET MN3, a second N-type MOSFET MN4, a first P-type MOSFET MP3 and a second P-type MOSFET MP4, a second capacitor Cb1, and a third capacitor Cb2. The sources of the first N-type MOSFET MN3 and the second N-type MOSFET MN4 are connected to the voltage input terminal. The sources of the first P-type MOSFET MP3 and the second P-type MOSFET MP4 are also connected to the voltage input terminal. The drains of the first N-type MOSFET MN3, the first P-type MOSFET MP3, the gates of the second N-type MOSFET MN4 and the second P-type MOSFET MP4 are connected to the first terminal of the second capacitor Cb1. The drains of the second N-type MOSFET MN4, the second P-type MOSFET MP4, the gates of the first N-type MOSFET MN3 and the first P-type MOSFET MP3 are connected to the first terminal of the third capacitor Cb2. The second terminal of the second capacitor Cb1 is the first signal input terminal, and the second terminal of the third capacitor Cb2 is the second signal input terminal.

[0043] The final-stage charge pump includes a first N-type MOSFET MN5, a second N-type MOSFET MN6, a first P-type MOSFET MP5, a second P-type MOSFET MP6, a second capacitor Cb1, and a third capacitor Cb2. The sources of the first N-type MOSFET MN5 and the second N-type MOSFET MN6 are connected to the voltage input terminal. The sources of the first P-type MOSFET MP5 and the second P-type MOSFET MP6 are also connected to the voltage input terminal. The drains of the first N-type MOSFET MN5, the first P-type MOSFET MP5, the gates of the second N-type MOSFET MN6 and the second P-type MOSFET MP6 are connected to the first terminal of the second capacitor Cb1. The drains of the second N-type MOSFET MN6, the second P-type MOSFET MP6, the gates of the first N-type MOSFET MN5 and the first P-type MOSFET MP5 are connected to the first terminal of the third capacitor Cb2. The second terminal of the second capacitor Cb1 is the first signal input terminal, and the second terminal of the third capacitor Cb2 is the second signal input terminal.

[0044] The clock drive circuit 30 includes multiple clock modules connected one-to-one with a series-connected charge pump. Each clock module includes a first signal output terminal clk and a second signal output terminal clkb. The first signal output terminal is connected to the first signal input terminal of the corresponding charge pump, and the second signal output terminal is connected to the second signal input terminal of the corresponding charge pump. The clock module is used to output a clock drive signal to the corresponding charge pump. The pair of clock signals provided by each clock module are inverted clock signals, that is, the phase difference between the pair of clock signals provided by each clock module is half a cycle, or 180 degrees. The clock signals of multiple clock modules have the same period and duty cycle, for example, a 50% duty cycle. The corresponding clock signals of two adjacent clock modules have a delay, and the phase difference is greater than or equal to 1 / 5 of a clock cycle and less than or equal to 1 / 4 of a clock cycle.

[0045] Those skilled in the art will understand that the multiple clock modules in the clock drive circuit can be a circuit with a single integrated structure having a pairwise connection, or a circuit with multiple independent separate structures for the clock modules.

[0046] In some embodiments, multiple clock modules of the clock driving circuit are cascaded, with each clock module corresponding to a multi-stage charge pump. The clock signal output by the previous stage clock module serves as the input signal for the next stage clock module. For example, the first stage clock module receives the original clock signal Clock generated by the oscillator and generates clock driving signals Clk0 and Clk0b, while the second stage clock module receives the clock driving signals Clk0 and Clk0b and generates clock driving signals Clk1 and Clk1b.

[0047] Specifically, such as Figure 3As shown, the multi-stage cascaded charge pump includes a first-stage charge pump, a second-stage charge pump, and a third-stage charge pump (final-stage charge pump). The corresponding clock drive circuit 30 includes a first clock module 302, a second clock module 304a, and a second clock module 304b. The clock modules are configured to output clock drive signals with a delay relative to the preceding clock module, wherein the phase difference of the delay is greater than or equal to 1 / 5 of a clock cycle and less than or equal to 1 / 4 of a clock cycle.

[0048] For example, the drive signal Clk1 of the second clock module 304a is delayed by a predetermined phase difference compared to the clock drive signal Clk0 of the first clock module 302, and the drive signal Clkb1 of the second clock module 304a is delayed by a predetermined phase difference compared to the clock drive signal Clkb0 of the first clock module 302. The predetermined phase difference is greater than or equal to 1 / 5 of a clock cycle and less than or equal to 1 / 4 of a clock cycle. By limiting the delay range to greater than or equal to 1 / 5 of a clock cycle and less than or equal to 1 / 4 of a clock cycle, the limitation of this delay range can ensure that the charge pump circuit has better transfer performance.

[0049] Furthermore, those skilled in the art will understand that when there are two or more clock modules in a clock circuit, the clock drive signal is delayed relative to the adjacent preceding clock module. This can be achieved by only one set of adjacent clock modules having a clock delay, or by generating a clock delay once between adjacent clock modules along the charge transfer direction. The second method is preferred.

[0050] In this embodiment, in the multi-stage series charge pump circuit, each charge pump is connected to a clock module that provides a clock drive signal. Along the charge transfer direction, the clock drive signal output by each clock module is configured to generate a clock delay relative to the clock drive signal output by the previous clock module. This clock delay extends the charging time of the capacitor in each charge pump, thereby improving the efficiency of charge transfer between charge pumps. Furthermore, by limiting the clock delay to a specified delay range, the charge transfer performance between each stage of charge pump can be guaranteed. This allows for an increase in the output voltage and output current of the charge pump circuit without increasing the clock frequency of the clock drive signal or increasing the charge pump capacitance. In other words, by configuring a clock delay between the clock drive signals of the preceding and following stages of charge pumps, the output voltage of the charge pump can be increased without generating additional power consumption.

[0051] In one embodiment of this disclosure, the plurality of clock modules include a first clock module 302 connected to each other and at least one second clock module. The first clock module 302 is connected to a first-stage charge pump in a multi-stage series charge pump. The second clock module includes a delay unit for delaying the output of an input clock drive signal to configure a phase difference.

[0052] In this embodiment, by setting a delay unit in the second clock module other than the first clock module connected to the first-stage charge pump, the timing of the output clock drive signal is adjusted by the delay unit, thereby realizing a clock drive module with a delay relative to the output of the previous clock module. In this way, by setting the delay unit to output a clock drive signal with a relative delay, the charging and discharging of the capacitors in the charge pump, namely the second capacitor and the third capacitor, is controlled based on the clock drive signal with a relative delay, thereby obtaining a larger output voltage without increasing the power consumption of the circuit.

[0053] In one embodiment of this disclosure, as a configuration method for the clock circuit, such as Figure 3 As shown, in the clock circuit, at least one second clock module is connected in series with the first clock module 302, and when there are multiple second clock modules, multiple second clock modules 304 are connected in series, wherein each second clock module has a delay unit with the same structure to sequentially configure the delay phase difference.

[0054] In this embodiment, multiple clock modules in the clock circuit are connected in series. By setting the same delay unit in the second clock module connected to the non-first stage charge pump, the next clock module can generate the same delay phase difference relative to the previous clock module. On the one hand, the configuration of this clock circuit is simple and reliable with low setup cost. On the other hand, it is also beneficial to ensure the charge transfer performance between two adjacent charge pumps.

[0055] Specifically, the clock module outputs a first signal and a second signal, which are inverted clock signals. The first signal output terminal of the preceding clock module is connected to the first signal input terminal of the following clock module, and the second signal output terminal of the preceding clock module is connected to the second signal input terminal of the following clock module.

[0056] like Figure 4 As shown, the first clock module 302 and a plurality of subsequent second clock modules 304 are connected in series.

[0057] In some embodiments, the clock circuit includes a first clock module and a plurality of second clock modules connected in parallel, with the inputs of the second clock modules all connected to the output of the first clock module. Each second clock module has a delay unit with a different delay, so that the outputs of the multiple second clock modules have clock drive signals with different delays. For example, the clock circuit includes two second clock modules connected in parallel, one of which outputs a clock drive signal with a predetermined delay, and the other outputs a clock drive signal with a delay of twice the predetermined delay. The predetermined delay is greater than or equal to 1 / 5 of a clock cycle and less than or equal to 1 / 4 of a clock cycle.

[0058] In this embodiment, multiple clock modules in the clock circuit can also be connected in parallel. By setting delay units with different delays in the second clock module connected to the non-first stage charge pump, it is also possible to ensure that the next clock module can generate the same delay phase difference relative to the previous clock module. This makes the configuration of the clock circuit more flexible.

[0059] In one embodiment of this disclosure, the delay unit includes multiple inverters and a configuration module, with the multiple inverters forming an inverter chain. The configuration module includes, for example, multiple capacitors. The configuration module can also be an RC delay circuit composed of resistors and capacitors.

[0060] Specifically, the input of the inverter chain is connected to the adjacent preceding clock module, the output of the inverter chain is used to delay the output of the clock drive signal, and the configuration module is connected to the inverter chain to configure the phase difference of the delay.

[0061] In some embodiments, the capacitor is implemented using a MOSFET, whose source, drain, and substrate are all connected to a low-level voltage Vss, such as ground. Figure 5 As shown, the second clock module 304a includes a first delay unit 3042 and a second delay unit 3044. Taking the first delay unit 3042 as an example, the first delay unit 3042 includes n inverters, namely inverter X1 to inverter Xn. Correspondingly, n MOS transistors, namely MOS1 to MOSn, are also provided. Specifically, the gate of the MOS transistor is connected to the output terminal of the inverter, and the source, drain and substrate of the MOS transistor are all connected to a low-level voltage Vss.

[0062] Specifically, among the multiple MOSFETs, P-type MOSFETs and N-type MOSFETs are alternately arranged. On the one hand, this delay unit helps to ensure the reliability of the phase difference configured for the delay. On the other hand, the phase difference of the delay of the clock drive signal is adjustable, so the specific phase difference of the delay can be flexibly configured within the delay range.

[0063] In another possible implementation of the delay unit, such as Figure 6 As shown, the inverter chain is configured to include a first inverter X1, a second inverter X2, a third inverter X3, and a fourth inverter X4 connected in series. Correspondingly, the configuration module adapted to it includes a resistor R and a first capacitor C. The resistor R is connected in series between the second inverter X2 and the third inverter X3. One end of the first capacitor C is connected between the first inverter X1 and the second inverter X2, and the other end of the first capacitor C is connected between the resistor R and the third inverter X3. The phase difference of the delay is configured based on the resistor R and the first capacitor C.

[0064] In this embodiment, an inverter chain configuration module is constructed by using a resistor and a first capacitor. The phase difference of the delay is determined by the time constant T generated by the resistor and the first capacitor, where T = RC. Therefore, the larger the values ​​of the resistor and the first capacitor, the longer the delay time of the clock drive signal. The setting method of this delay module has a relatively simple structure and low manufacturing cost. Moreover, once the resistor and the first capacitor are determined, the phase difference of the delay is also determined.

[0065] In one embodiment of this disclosure, such as Figure 4 As shown, the first clock module 302 receives the original clock signal Clock and generates two non-overlapping inverted signals clk0 and clk0b. The first clock module may not include the aforementioned delay unit. Specifically, the first clock module 302 includes a fifth inverter X5, a first NAND gate U1, and a second NAND gate U2. The input terminals of the fifth inverter X5 and the first input terminal of the first NAND gate U1 receive the original clock signal Clock; the second input terminal of the first NAND gate U1 is connected to the output terminal of the second NAND gate U2; the first input terminal of the second NAND gate U2 is connected to the output terminal of the fifth inverter X5, and the second input terminal of the second NAND gate U2 is connected to the output terminal of the first NAND gate U1. The output terminal of the first NAND gate U1 is connected to a buffer, and the buffer outputs a clock drive signal clk0. The output terminal of the second NAND gate U2 is connected to a buffer, and the buffer outputs a clock drive signal clk0b. Alternatively, the output terminal of the first NAND gate U1 is connected to an inverter, and the inverter outputs a clock drive signal clk0b. The output of the second NAND gate U2 is connected to an inverter, which outputs a clock drive signal clk0. The clock drive signals clk0 and clk0b are provided to the first-stage charge pump. The second clock module 302a includes a first delay unit 3042 and a second delay unit 3044. The input of the first delay unit 3042 is connected to the output of the first NAND gate U1, and the input of the second delay unit 3044 is connected to the output of the second NAND gate U2. The output of the first delay unit 3042 of the second clock module 302a is connected to the input of the first delay unit 3042 of the second clock module 304b, and the output of the second delay unit 3044 of the second clock module 302a is connected to the input of the second delay unit 3044 of the second clock module 304b.

[0066] In this embodiment, a first clock module 302 is set up. The input terminal of the first clock module 302 receives the original clock signal. The original clock signal is divided into two paths. One path is input to the first NAND gate U1, and the other path is input to the second NAND gate U2 after phase flipping through the fifth inverter X5. Then, two inverted clock drive signals are output respectively.

[0067] like Figure 4As shown, clock drive signals clk0 and clk0b are input to the second clock module 304a, so that phase delay output is achieved through the corresponding first delay unit 3042 and second delay unit 3044 respectively.

[0068] The following is combined with Figures 7 to 10 The improved effects of the charge pump circuit in the embodiments of this disclosure are further described.

[0069] like Figure 7 As shown, the charge pump circuit includes a two-stage charge pump. The first-stage charge pump includes a first N-type MOSFET MN1, a second N-type MOSFET MN2, a first P-type MOSFET MP1, a second P-type MOSFET MP2, a second capacitor Cb1, and a third capacitor Cb2. The sources of the first N-type MOSFET MN1 and the second N-type MOSFET MN2 are connected to the voltage input terminal, as are the sources of the first P-type MOSFET MP1 and the second P-type MOSFET MP2. The drains of the first N-type MOSFET MN1 and the first P-type MOSFET MP1, the gate of the second N-type MOSFET MN2, and the gate of the second P-type MOSFET MP2 are also connected to the voltage input terminal. The gate of the OS transistor MP2 is connected to the first terminal of the second capacitor Cb1, and the connection point is marked as point A. The drain of the second N-type MOS transistor MN2, the drain of the second P-type MOS transistor MP2, the gate of the first N-type MOS transistor MN1, and the gate of the first P-type MOS transistor MP1 are connected to the first terminal of the third capacitor Cb2, and the connection point is marked as point B. The second terminal of the second capacitor Cb1 is the first signal input terminal, receiving the Clk0b signal. The second terminal of the third capacitor Cb2 receives the Clk0 signal. The second capacitor Cb1 and the third capacitor Cb2 realize the charging and discharging of the first-stage charge pump by receiving the inverted clock drive signals Clk0 and Clk0b.

[0070] The connection point between the first-stage charge pump and the second-stage charge pump is denoted as point C. The second-stage charge pump includes a first N-type MOSFET MN3, a second N-type MOSFET MN4, a first P-type MOSFET MP3 and a second P-type MOSFET MP4, a second capacitor Cb3, and a third capacitor Cb4. The sources of the first N-type MOSFET MN3 and the second N-type MOSFET MN4 are connected to the voltage input terminal. The sources of the first P-type MOSFET MP3 and the second P-type MOSFET MP4 are also connected to the voltage input terminal. The drain of the first N-type MOSFET MN3 and the drain of the first P-type MOSFET MP3 are also connected to the voltage input terminal. The drain of the first N-type MOSFET MN4, the gate of the second N-type MOSFET MP4, and the gate of the second P-type MOSFET MP4 are connected to the first terminal of the second capacitor Cb1, and the connection point is marked as point D. The drain of the second N-type MOSFET MN4, the drain of the second P-type MOSFET MP4, the gate of the first N-type MOSFET MN3, and the gate of the first P-type MOSFET MP3 are connected to the first terminal of the third capacitor Cb2, and the connection point is marked as point E. The second terminal of the second capacitor Cb3 is the first signal input terminal, receiving the Clk1 signal, and the second terminal of the third capacitor Cb4 is the second signal input terminal, receiving the Clk1b signal.

[0071] like Figure 7 As shown, when Clk0b is low, MN2 and MP1 are turned on, and charge is transferred from Vin to the second capacitor Cb1. However, due to the phase delay between the Clk1 and Clk1b signals of the second-stage charge pump and the Clk0 and Clk0b signals, there is a large voltage fluctuation at point C, the connection point of the two charge pumps, resulting in charge accumulation at point C. Figure 8 As shown, waveform group 1 illustrates the voltage diagrams at each marked point in the clock drive signal and charge pump circuit of the related art, and waveform group 2 illustrates the voltage diagrams at each marked point in the clock drive signal and charge pump circuit of this disclosure. As shown in waveform group 1, the Clk0' signal and the Clk1' signal are in phase, and the Clk0b' signal and the Clk1b' signal are in phase. As shown in waveform group 2, the Clk1 signal has a phase delay relative to the Clk0 signal. Due to charge accumulation at point C, points D and E in waveform group 2 have larger voltage values ​​than points D and E in waveform group 1. Correspondingly, at point F of the voltage output, the output voltage in waveform group 2 is increased by ΔV compared to waveform group 1, thereby achieving a higher voltage output without adjusting the capacitor parameters or increasing the clock frequency.

[0072] Depend on Figure 9 It is known that the output voltage and output current of a charge pump have an inverse linear relationship. Therefore, with the output current value remaining constant, the charge pump circuit used in this disclosure can increase the output voltage; or, with the output voltage value remaining constant, the charge pump circuit used in this disclosure can increase the output current.

[0073] like Figure 10 As shown, the current curve is the output current curve of the charge pump circuit in the related art, and the target curve is the output current curve of the charge pump circuit used in this disclosure. Under the condition that the output current I remains unchanged, the charge pump circuit used in this disclosure can reduce the clock frequency of the clock drive signal.

[0074] The memory according to embodiments of this disclosure includes the charge pump circuit described in any of the foregoing embodiments. The memory is, for example, a non-volatile memory, such as flash memory. Flash memory includes NAND flash memory and NOR flash memory. The charge pump circuit is used to provide the memory with voltages used in various operations, such as programming voltages applied to word lines during programming operations and erase voltages applied to the substrate during erase operations.

[0075] The charge pump circuit and memory disclosed herein include a charge pump circuit comprising multiple charge pumps connected in series. Each charge pump is connected to a clock module that provides a clock drive signal. Along the charge transfer direction, the clock drive signal output by each clock module is configured to generate a clock delay relative to the clock drive signal output by the previous clock module. This clock delay extends the charging time of the capacitor in each charge pump, thereby improving the efficiency of charge transfer between charge pumps. Furthermore, by limiting the clock delay to a specified delay range, the charge transfer performance between each stage of the charge pump can be guaranteed. This allows for an increase in the output voltage and output current of the charge pump circuit without increasing the clock frequency of the clock drive signal or increasing the charge pump capacitance. In other words, by configuring a clock delay between the clock drive signals of the preceding and following charge pumps, the driving capability of the charge pump circuit is improved, thereby enhancing the performance of the memory using the charge pump circuit.

[0076] In this application, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance; the term "multiple" refers to two or more unless otherwise expressly defined. The terms "install," "connect," "link," and "fix" should be interpreted broadly. For example, "connect" can mean a fixed connection, a detachable connection, or an integral connection; "link" can mean a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0077] In the description of this application, it should be understood that the terms "upper", "lower", "left", "right", "front", "rear", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or unit referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0078] In the description of this specification, the terms "one embodiment," "some embodiments," "specific embodiment," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0079] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0080] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A charge pump circuit, characterized in that, include: A multi-stage charge pump connected in series, each stage of the charge pump including a voltage input terminal, a voltage output terminal, a first signal input terminal, and a second signal input terminal; A clock driving circuit includes multiple clock modules that are connected one-to-one with the multi-stage series charge pumps. Each clock module includes a first signal output terminal and a second signal output terminal. The first signal output terminal is connected to the first signal input terminal, and the second signal output terminal is connected to the second signal input terminal. The clock module is used to output a clock driving signal to the corresponding charge pump. The clock module is configured to output the clock drive signal with a delay relative to the preceding adjacent clock module. The phase difference of the delay is greater than or equal to 1 / 5 of a clock cycle and less than or equal to 1 / 4 of a clock cycle. The plurality of clock modules include a first clock module connected to each other and at least one second clock module. The second clock module includes a delay unit, which includes: an inverter chain, the input of which is connected to the preceding adjacent clock module, and the output of which is used to output the clock drive signal with a delay; and a configuration module connected to the inverter chain for configuring the phase difference of the delay.

2. The charge pump circuit according to claim 1, characterized in that, The first clock module is connected to the first stage charge pump in the multi-stage series charge pump; The delay unit is used to delay the output of the clock drive signal input from the front end in order to configure the phase difference.

3. The charge pump circuit according to claim 2, characterized in that, The at least one second clock module is connected in series with the first clock module, and when there are multiple second clock modules, the multiple second clock modules are connected in series. Each of the second clock modules has the same delay unit structure to sequentially configure the phase difference of the delay.

4. The charge pump circuit according to claim 2, characterized in that, The at least one second clock module is connected in parallel with the first clock module, and when there are multiple second clock modules, the multiple second clocks are connected in parallel. Each of the second clock modules has a delay unit with a different structure, such that the output phase of the delay unit sequentially increases the phase difference of the delay.

5. The charge pump circuit according to claim 1, characterized in that, The configuration module includes: Multiple MOSFETs are connected one-to-one with each inverter in the inverter chain. The gate of each MOSFET is connected to the output terminal of the inverter. The source, drain, and substrate of each MOSFET are all connected to the source power supply voltage. The delay phase difference is configured by adjusting the source power supply voltage.

6. The charge pump circuit according to claim 1, characterized in that, The inverter chain includes a first inverter, a second inverter, a third inverter, and a fourth inverter connected in series. The configuration module includes a resistor and a first capacitor. The resistor is connected in series between the second inverter and the third inverter; One end of the first capacitor is connected between the first inverter and the second inverter, and the other end of the first capacitor is connected between the resistor and the third inverter. The phase difference of the delay is configured based on the resistor and the first capacitor.

7. The charge pump circuit according to any one of claims 2 to 4, characterized in that, The first clock module includes a fifth inverter, a first NAND gate, and a second NAND gate. The delay unit includes a first delay unit and a second delay unit in parallel. The input terminal of the fifth inverter and the first input terminal of the first NAND gate receive the original clock signal; The second input terminal of the first NAND gate is connected to the output terminal of the second NAND gate. The output terminal of the first NAND gate is used to output a positive clock drive signal and is connected to the first delay unit of the connected second clock module. The first input terminal of the second NAND gate is connected to the output terminal of the fifth inverter, the second input terminal of the second NAND gate is connected to the output terminal of the first NAND gate, and the output terminal of the second NAND gate is used to output an inverted clock drive signal and is connected to the second delay unit of the connected second clock module.

8. The charge pump circuit according to claim 7, characterized in that, The clock module also includes a first buffer and a second buffer in parallel. In the first clock module, the input terminal of the first buffer is connected to the output terminal of the first NAND gate, the output terminal of the first buffer is connected to the first signal terminal of the first stage charge pump, the input terminal of the second buffer is connected to the output terminal of the second NAND gate, and the output terminal of the second buffer is connected to the second signal terminal of the first stage charge pump. In the second clock module, the input terminal of the first buffer is connected to the output terminal of the first delay unit, and the output terminal of the first buffer outputs the positive clock drive signal. The input terminal of the second buffer is connected to the output terminal of the second delay unit, and the output terminal of the second buffer outputs the inverted clock drive signal.

9. The charge pump circuit according to any one of claims 1 to 4, characterized in that, The charge pump includes a first N-type MOSFET, a second N-type MOSFET, a first P-type MOSFET, a second P-type MOSFET, a second capacitor, and a third capacitor, wherein... The source of the first N-type MOSFET and the source of the second N-type MOSFET are connected to the voltage input terminal, and the source of the first P-type MOSFET and the source of the second P-type MOSFET are connected to the voltage input terminal. The drain of the first N-type MOS transistor, the drain of the first P-type MOS transistor, the gate of the second N-type MOS transistor, and the gate of the second P-type MOS transistor are connected to the first terminal of the second capacitor, and the drain of the second N-type MOS transistor, the drain of the second P-type MOS transistor, the gate of the first N-type MOS transistor, and the gate of the first P-type MOS transistor are connected to the first terminal of the third capacitor. The second terminal of the second capacitor is the first signal input terminal, and the second terminal of the third capacitor is the second signal input terminal.

10. A memory, characterized in that, include: The charge pump circuit as described in any one of claims 1 to 9.

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