Two-stage three-level ac / dc converter dc bus secondary ripple voltage suppression method

Abstract

This invention discloses a method for suppressing secondary ripple voltage on the DC bus of a two-stage three-level AC / DC converter. The converter includes a grid-side inductor, a front-stage three-level AC-DC converter, a split capacitor unit, and a rear-stage three-level DC-DC converter. The input of the front-stage three-level AC-DC converter is connected to the grid side via the grid-side inductor, and its output is connected to the input of the rear-stage three-level DC-DC converter via the split capacitor unit. The output of the rear-stage three-level DC-DC converter is connected to the load via a filter capacitor. During the voltage and current dual closed-loop control process of the front-stage three-level AC-DC converter, a small amount of third harmonic is added to the grid current, causing fourth-order ripple power to be generated at the system input. This fourth-order ripple power is then used to offset the fourth-order ripple power on the DC bus, completely eliminating low-frequency fluctuations in the DC bus voltage. The rear-stage three-level DC-DC converter, through duty cycle control and phase-shift modulation, enables the split capacitor unit to absorb secondary ripple power to eliminate the secondary ripple voltage on the DC bus while simultaneously adjusting the inter-bridge phase shift angle of the primary and secondary sides of the high-frequency transformer to achieve constant system power output.

Description

Technical Field

[0001] This invention belongs to the field of power electronics technology, specifically a method for suppressing secondary ripple voltage on the DC bus of a two-stage three-level AC / DC converter. Background Technology

[0002] Single-phase AC-DC converters serve as interface devices between AC loads or single-phase AC power grids and DC loads or DC power sources, undertaking the responsibility of converting single-phase AC and DC power between each other, and are widely used in the field of power electronics. However, single-phase DC-AC energy conversion systems have an inherent problem: power mismatch between the DC and AC sides, that is, second-harmonic power fluctuations on the AC side will cause second-harmonic components to appear in the DC side voltage.

[0003] To address power fluctuation issues, a traditional solution is to employ a passive power decoupling strategy, which involves increasing the capacitance and inductance values ​​within the converter to suppress secondary ripple within a reasonable range, ensuring it does not affect system operation. While this method has proven effective, it introduces problems such as excessive system size, high cost, and poor reliability.

[0004] To overcome the shortcomings of passive power decoupling schemes, active power decoupling schemes have received widespread attention. The implementation method is to add a power decoupling circuit to the original converter. The energy storage device inside the power decoupling circuit absorbs power fluctuations and eliminates the adverse effects of the secondary frequency ripple inside the converter. Although the use of electrolytic capacitors and large inductors is avoided, most of these methods require the addition of additional power decoupling circuits, which is costly and does not reduce power density. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the technical problem this invention aims to solve is to provide a method for suppressing secondary ripple voltage on the DC bus of a two-stage three-level AC / DC converter.

[0006] The technical solution adopted by the present invention to solve the aforementioned technical problem is as follows:

[0007] A method for suppressing secondary ripple voltage on the DC bus of a two-stage three-level AC / DC converter is disclosed. The converter includes a grid-side inductor, a front-stage three-level AC-DC converter, a split capacitor unit, and a rear-stage three-level DC-DC converter. The input of the front-stage three-level AC-DC converter is connected to the grid side via the grid-side inductor, and its output is connected to the input of the rear-stage three-level DC-DC converter via the split capacitor unit. The output of the rear-stage three-level DC-DC converter is connected to the load via a filter capacitor. The front-stage three-level AC-DC converter includes switching devices Q1 to Q8, with switching devices Q1 to Q4 forming one bridge arm and switching devices Q5 to Q8 forming the other bridge arm. The split capacitor unit includes capacitors C1 to C4 and a filter inductor L.f1 L f2 The subsequent three-level DC-DC converter includes switching devices Q9 to Q16 and DC blocking capacitor C. b1 ~C b2 The system consists of a high-frequency inductor Lt and a high-frequency transformer T1; the positive terminal of capacitor C1 is connected to one end of the preceding three-level AC-DC converter, the negative terminal of capacitor C1 is connected to the positive terminal of capacitor C2, the negative terminal of capacitor C2 is connected to the positive terminal of capacitor C3, the negative terminal of capacitor C3 is connected to the positive terminal of capacitor C4, and the negative terminal of capacitor C4 is connected to the other end of the preceding three-level AC-DC converter; the filter inductor L... f1 One end of the filter inductor is connected to the connection point of capacitors C1 and C2, and the other end is connected to the connection point of switching devices Q9 and Q10 in the subsequent three-level DC-DC converter. f2 One end is connected to the connection point of capacitors C3 and C4, and the other end is connected to the connection point of switching devices Q11 and Q12 in the subsequent three-level DC-DC converter; the switching devices Q9 to Q12 in the subsequent three-level DC-DC converter are connected in series, the drain of switch Q9 is connected to the positive terminal of capacitor C1, and the source of switching device Q12 is connected to the negative terminal of capacitor C4. The DC blocking capacitor C... b1 One end is connected to the connection point of switching devices Q9 and Q10, and the other end is connected to the high-frequency inductor L. t One end is connected to the high-frequency inductor L t The other end is connected to one end of the primary winding of high-frequency transformer T1. The other end of the primary winding of high-frequency transformer T1 is connected to the connection point of switching devices Q11 and Q12. Switching devices Q13 and Q14 are connected in series to form one bridge arm, and switching devices Q15 and Q16 are connected in series to form another bridge arm. The filter capacitor is connected in parallel with the two bridge arms; DC blocking capacitor C b2 One end of the high-frequency transformer T1 is connected to one end of the secondary side, and the other end is connected to the connection point of switching devices Q13 and Q14. The other end of the secondary side of the high-frequency transformer T1 is connected to the connection point of switching devices Q15 and Q16. This method includes voltage and current dual closed-loop control of the front-stage three-level AC-DC converter and duty cycle and phase shift angle control of the rear-stage three-level DC-DC converter. The modulation voltage is obtained through the voltage and current dual closed-loop control of the front-stage three-level AC-DC converter. That is, the reference voltage on the AC side of the preceding three-level AC-DC converter, expressed as:

[0008]

[0009] In the formula, v g (t) represents the grid voltage, i g (t) represents the grid current, ω represents the power frequency angular frequency, and L g For grid-side inductance, K is the reference value for the fundamental amplitude of the power grid current, K3 is the ratio of the amplitude of the third harmonic to the amplitude of the fundamental frequency, and K i t is the proportionality coefficient of the inner current loop, and t is the time variable;

[0010] modulating voltage The duty cycle signals of switching devices Q1 to Q8 are generated by SPWM modulation, and the switching devices Q1 to Q8 are controlled according to the duty cycle signals to adjust the DC component of the DC bus voltage.

[0011] The duty cycle and phase shift angle control process of the subsequent three-level DC-DC converter is as follows: First, the duty cycle of the switching device Q9 is obtained through voltage and current dual closed-loop control; then, based on the complementary duty cycles of the switching devices Q10 and Q9, the same duty cycles of the switching devices Q11 and Q9 except that the phase difference is 180° within the switching cycle, and the complementary duty cycles of Q12 and Q11, the switching signals of the switching devices Q10 to Q12 are obtained; then, the inter-bridge phase shift ratio D is calculated according to equations (2) and (3).

[0012]

[0013]

[0014] Among them, P o The system output power is given by α1, where α1 is the duty cycle of switching device Q9, and V is the voltage. dc_link Here, n is the sampled value of the DC bus voltage, n is the turns ratio of the primary to secondary side of the high-frequency transformer, and T is the input voltage. s For the switching cycle, U out L is the load voltage. t This refers to the inductance value of a high-frequency inductor.

[0015] Finally, based on the fact that the duty cycle of switching device Q13 is the same as that of Q9, but there is a phase shift angle within the switching cycle, the phase shift angle between switching devices Q13 and Q9 is adjusted to 360°·D; switching devices Q14 and Q13 are complementary, switching devices Q15 and Q14 have the same duty cycle but are 180° out of phase within the switching cycle, and Q16 and Q15 are complementary, thus obtaining the switching signals of switching devices Q13 to Q16.

[0016] Furthermore, the voltage of each capacitor in the split capacitor unit is:

[0017]

[0018] Where ω is the power frequency angular frequency, θ is the phase difference between the capacitor voltage and the grid voltage, and V c U is the amplitude of the capacitor voltage. c1 (t), u c2 (t), u c3 (t), uc4 (t) represent the voltages across capacitors C1, C2, C3, and C4, respectively;

[0019] The phase difference θ between the capacitor voltage and the mains voltage and the amplitude V of the capacitor voltage. c They are respectively:

[0020]

[0021]

[0022] The capacitance values ​​of the four capacitors in the split capacitor unit must meet the following requirements:

[0023]

[0024] Among them, C f V is the total capacitance of capacitors C1 and C2. g L represents the grid voltage amplitude. f1 Filter inductor L f1 The value of .

[0025] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0026] 1. This invention designs a split capacitor unit, which connects the front-end diode-clamped three-level AC-DC converter to the rear-end three-level DC-DC converter. The split capacitor unit includes two filter inductors and four capacitors. While supporting the DC bus voltage, the split capacitor unit absorbs the system's second-order ripple power. The front-end circuit achieves DC bus voltage control through dual closed-loop control of the DC bus voltage and grid current. Because the four capacitors in the split capacitor unit are of unequal size, a small amount of fourth-order ripple power will remain on the DC bus. Therefore, a small amount of third harmonic is added to the grid current to generate fourth-order ripple power at the system input, thus offsetting the fourth-order ripple power on the DC bus and completely eliminating low-frequency fluctuations in the DC bus voltage, making the DC bus voltage more stable.

[0027] 2. The subsequent three-level DC-DC converter, through duty cycle control and phase-shift modulation, enables the split capacitor unit to absorb secondary ripple power while adjusting the inter-bridge phase shift angle of the primary and secondary sides of the high-frequency transformer, thereby achieving constant system power output. This eliminates the secondary ripple voltage of the DC bus voltage, reduces the capacitance value on the DC bus side, reduces the voltage stress on the power transistor, and increases the power density. It solves the problems of poor economy and low power density in traditional methods of eliminating secondary ripple voltage.

[0028] 3. Traditional two-stage converters add a power decoupling circuit between the front-end and rear-end converters (see...). Figure 6) By controlling the duty cycles of the two power switching tubes in the power decoupling circuit, the secondary ripple power retained on the DC bus is transferred to the decoupling capacitor C f so that no secondary ripple voltage will be generated on the DC bus voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is the topological structure diagram of the two-stage three-level AC / DC converter of the present invention;

[0030] Figure 2 is the control flow chart of the front-stage three-level AC-DC converter of the present invention;

[0031] Figure 3 is the control flow chart of the rear-stage three-level DC-DC converter of the present invention;

[0032] Figs. 4(a), (b), and (c) are the drive signal waveforms and working waveforms of each MOSFET power tube in a switching cycle during the phase-shift modulation of the three-level DC-DC converter when the duty cycle α1 of the MOSFET power tube Q9 is less than 0.5 and the phase-shift ratio between bridges is respectively 0 < D < 0.5 - α1, 0.5 - α1 < D < α1, and α1 < D < 0.5;

[0033] Figs. 4(d), (e), and (f) are the drive signal waveforms and working waveforms of each MOSFET power tube in a cycle during the phase-shift modulation of the three-level DC-DC converter when the duty cycle α1 of the MOSFET power tube Q9 is greater than 0.5 and the phase-shift ratio is respectively 0 < D < α1 - 0.5, α1 - 0.5 < D < 1 - α1, and 1 - α1 < D < 0.5;

[0034] Figure 5 is the waveform diagram of the grid voltage, grid current, system input power and output power, absorbed power of the split capacitor unit, voltages of each capacitor in the split capacitor unit, and DC bus voltage when the control method of the present invention is adopted;

[0035] Figure 6 is the control schematic diagram of the traditional two-stage converter. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0036] The technical solution of the present invention will be described in detail below in conjunction with the drawings and specific embodiments, but the protection scope of this application is not limited thereby.

[0037] Figure 1 is the topological structure of the two-stage three-level AC / DC converter of the present invention, including the grid-side inductor L g , a diode-clamped three-level AC-DC converter, a split capacitor unit, a three-level DC-DC converter, and a DC output-side filter capacitor C OThe input of the diode-clamped three-level AC-DC converter is connected to the grid-side inductor L. g Connected to the mains, the output of the diode-clamped three-level AC-DC converter is connected to a split capacitor unit, which is also connected to the input of the three-level DC-DC converter. The output of the three-level DC-DC converter is connected to a DC output side filter capacitor C. O Connect to the load;

[0038] The grid-side inductor is used to filter out harmonics of the grid current. The diode-clamped three-level AC-DC converter is used to convert AC power from the grid side to DC power or, when connected to the grid, to convert DC power from the DC bus side to AC power and maintain the DC bus voltage. The split capacitor unit is used to eliminate the secondary ripple voltage of the DC bus voltage and support the DC bus voltage. The three-level DC-DC converter modulates the voltage waveform of each capacitor on the split capacitor unit while transmitting power. The DC output side filter capacitor suppresses harmonics of the DC output side voltage and supports the DC side voltage.

[0039] The diode-clamped three-level AC-DC converter includes eight MOSFET power transistors Q1-Q8 and four clamping diodes D1-D4. The split capacitor unit includes four capacitors C1-C4 and a filter inductor L. f1 ~L f2 The three-level DC-DC converter includes eight MOSFET power transistors Q9 to Q16 and a DC blocking capacitor C. b1 ~C b2 , high-frequency inductor Lt and high-frequency transformer T1;

[0040] In a diode-clamped three-level AC-DC converter, MOSFET power transistors Q1, Q2, Q3, and Q4 are connected in series to form one bridge arm, with two clamping diodes D1 and D2 connected in series on this arm. MOSFET power transistors Q5, Q6, Q7, and Q8 are connected in series to form another bridge arm, with two clamping diodes D3 and D4 connected in series on this arm. The midpoint of the two clamping diodes in each bridge arm is connected to the neutral point O. The midpoint 'a' of one bridge arm of the diode-clamped three-level AC-DC converter is connected to the grid-side inductor L. g It is connected to the positive terminal of the grid side, and the negative terminal of the grid side is connected to the midpoint b of the other bridge arm of the diode clamped three-level AC-DC converter.

[0041] In the split capacitor unit, the positive terminal of capacitor C1 is connected to one end of the diode-clamped three-level AC-DC converter, the negative terminal of capacitor C1 is connected to the positive terminal of capacitor C2, the negative terminal of capacitor C2 is connected to the positive terminal of capacitor C3, the negative terminal of capacitor C3 is connected to the positive terminal of capacitor C4, and the negative terminal of capacitor C4 is connected to the other end of the diode-clamped three-level AC-DC converter. The filter inductor L... f1One end of the filter inductor is connected to the connection point of capacitors C1 and C2, and the other end is connected to the connection point of MOSFET power transistors Q9 and Q10 in the three-level DC-DC converter. f2 One end of the capacitor is connected to the junction of capacitors C3 and C4, and the other end is connected to the junction of MOSFET power transistors Q11 and Q12 in the three-level DC-DC converter. The junction of capacitors C2 and C3 is designated as neutral point O. MOSFET power transistors Q9, Q10, Q11, and Q12 in the three-level DC-DC converter are connected in series. The drain of MOSFET power transistor Q9 is connected to the positive terminal of capacitor C1, and the source of MOSFET power transistor Q12 is connected to the negative terminal of capacitor C4. The junction of MOSFET power transistors Q10 and Q11 is connected to neutral point O. The DC blocking capacitor C... b1 One end is connected to the junction of MOSFET power transistors Q9 and Q10, and the other end is connected to the high-frequency inductor L. t One end is connected to the high-frequency inductor L t The other end is connected to one end of the primary winding of high-frequency transformer T1. The other end of the primary winding of high-frequency transformer T1 is connected to the connection point of MOSFET power transistors Q11 and Q12. MOSFET power transistors Q13 and Q14 are connected in series to form one bridge arm, and MOSFET power transistors Q15 and Q16 are connected in series to form another bridge arm. The DC output side filter capacitor C... O The DC blocking capacitor C is connected in parallel with the two bridge arms. b2 One end of the high-frequency transformer T1 is connected to one end of the secondary side of the high-frequency transformer T1, and the other end is connected to the connection point of MOSFET power transistors Q13 and Q14. The other end of the high-frequency transformer T1 is connected to the connection point of MOSFET power transistors Q15 and Q16.

[0042] The key to this invention lies in allowing the split capacitor unit to completely absorb the secondary ripple power based on the instantaneous power balance of the system, so that the three-level DC-DC converter only transmits DC power, thereby preventing the secondary ripple power from lingering on the DC bus and achieving no second harmonic oscillation of the DC bus voltage. The method for suppressing the secondary ripple voltage of the DC bus in a two-stage three-level AC / DC converter includes two aspects. One aspect is the voltage and current dual closed-loop control of the front-stage three-level AC-DC converter, that is, based on the diode-clamped three-level AC-DC converter, the voltage and current dual closed-loop control is adopted and a small amount of third harmonic is added to the grid current. The main purpose is to achieve system power balance, that is, P c +P o =P in P c P represents the power absorbed by the split capacitor unit. o P represents the system output power. inThis indicates the system input power; it also avoids the influence of the small amount of fourth-order ripple voltage generated when the duty cycle and phase shift angle control of the subsequent three-level DC-DC converter eliminates the secondary ripple voltage, making the DC bus voltage more stable; on the other hand, it is the duty cycle and phase shift angle control of the subsequent three-level DC-DC converter, that is, according to the three-level DC-DC converter, the duty cycle and phase shift angle control is used to control the voltage ripple of the upper and lower sets of capacitors in the split capacitor unit to a complementary state, so as to eliminate the secondary ripple voltage of the DC bus voltage while performing constant power output.

[0043] like Figure 2 As shown, the voltage and current dual closed-loop control process of the front-end three-level AC-DC converter is as follows: the DC bus voltage, grid voltage, and grid current are sampled in real time, and the given steady-state average value of the DC bus voltage is... DC bus voltage sampling value V dc_link By subtracting the values, we obtain the DC bus voltage difference ΔV. dc_link DC bus voltage difference ΔV dc_link After passing through the voltage loop PI regulator, a reference value for the fundamental amplitude of the grid current is obtained. Grid voltage v g (t) The grid voltage phase ωt is obtained through a phase-locked loop (PLL). On the one hand, the grid voltage phase is sinusoidally calculated and then compared with the reference value of the grid current fundamental amplitude. Multiplying them together yields a reference value for the instantaneous fundamental value of the grid current. Reference value of the fundamental amplitude of the power grid current Multiply by K3 to obtain a reference value for the amplitude of the third harmonic of the grid current. On the other hand, the grid voltage phase is multiplied by 3 and added Obtain the phase of the third harmonic of the grid current. The phase of the third harmonic of the grid current is calculated using a sine wave, and then compared with the reference value of the amplitude of the third harmonic of the grid current. Multiplying them together yields a reference value for the instantaneous third harmonic of the grid current. Reference value of the instantaneous value of the third harmonic of the grid current Reference value of the fundamental instantaneous value of the grid current Add them together, and then add them to the actual sampled grid current i. g Subtracting (t) yields the current error; after proportional adjustment via the inner current loop, the current error is used to obtain the error adjustment term. The formula for calculating the grid-side inductor voltage is as follows: The current i flowing through the grid-side inductor L This refers to the grid current, therefore the reference value of the grid current is... Substituting into the formula for calculating the grid-side inductor voltage, we obtain the grid-side inductor voltage. Based on the steady-state relationship of the AC side of the rectifier, the modulation voltage is obtained. The reference voltage on the AC side of a diode-clamped three-level AC-DC converter is expressed as:

[0044]

[0045] In the formula, v g (t) represents the grid voltage, i g (t) represents the grid current, K3 is the ratio of the third harmonic amplitude to the fundamental amplitude, ω is the power frequency angular frequency, and L g For the grid-side inductor, K i t is the proportionality coefficient of the inner current loop, and t is the time variable;

[0046] modulating voltage The duty cycle signals of MOSFET power transistors Q1 to Q8 are generated by SPWM modulation, and the eight MOSFET power transistors Q1 to Q8 of the diode clamped three-level AC-DC converter are controlled to adjust the DC component of the DC bus voltage.

[0047] like Figure 3 As shown, the duty cycle and phase shift angle control of the subsequent three-level DC-DC converter have an outer loop that is a ripple voltage loop. Only the secondary ripple component in the DC bus voltage needs to be controlled; therefore, a PR controller (proportional resonant controller) is selected to track the secondary ripple voltage in the DC bus voltage. The specific implementation process is as follows: The DC bus voltage and the filter inductor L... f1 The current is sampled in real time, and the DC bus voltage sample value V is obtained. dc_link With a given steady-state average value of DC bus voltage By subtracting the values, we obtain the DC bus voltage difference ΔV. dc_link This refers to the secondary ripple voltage in the straight bus voltage; the secondary ripple voltage ΔV dc_link With secondary ripple voltage reference value The difference is used to obtain the second-order ripple voltage error V. rip_error Since the purpose of this invention is to eliminate secondary ripple voltage, the secondary ripple voltage reference value is... Set it to 0, then set the secondary ripple voltage error V rip_error The input to the PR controller generates a decoupling current, which is then transferred to the filter inductor L. f1 Current reference value The filter inductor L f1 Current reference value With the sampling filter inductor L f1 Current value i Lf By subtracting the values, we obtain the filter inductance L. f1 Current error i Lf_error Due to the filter inductor L f1The current does not need to be strictly sinusoidal, so a proportional controller is sufficient to achieve a fast response. Therefore, the filter inductor L... f1 Current error i Lf_error The input is fed into the proportional controller, which outputs the AC component of the duty cycle α1 of the MOSFET power transistor Q9. Since the DC component of the voltage on each capacitor in the split capacitor unit must be equal, the DC component of the duty cycle α1 is set to 0.5. The AC component and the DC component of the duty cycle α1 are added together to obtain the complete switching signal, that is, the duty cycle α1 of the MOSFET power transistor Q9.

[0048] Based on the complementary duty cycles of MOSFET power transistors Q10 and Q9, the identical duty cycles of MOSFET power transistors Q11 and Q9 with a 180° phase difference during the switching cycle, and the complementary duty cycles of Q12 and Q11, the switching signals of MOSFET power transistors Q10, Q11, and Q12 can be obtained. Then, based on the bridge phase shift ratio D (the ratio of the phase shift angle between MOSFET power transistors Q9 and Q13 to 360°), the duty cycle α1 of MOSFET power transistor Q9, and the system output power P... o The relationship between the bridge phase shift angles is used to calculate the inter-bridge phase shift angle. Figures 4(a) to (f) show the drive signal waveforms and operating waveforms of each MOSFET power transistor in a three-level DC-DC converter during one switching cycle when the duty cycle of MOSFET power transistor Q9 is less than 0.5 and greater than 0.5, respectively. Based on the operating waveforms, the relationship between the inter-bridge phase shift angle, the duty cycle of MOSFET power transistor Q9, and the system output power can be obtained as follows:

[0049]

[0050]

[0051] Where n is the turns ratio of the primary to the secondary side of the high-frequency transformer, and T s For the switching cycle, U out L is the load voltage. t It is a high-frequency inductor;

[0052] The phase-shifting module generates switching signals for MOSFETs Q13, Q14, Q15, and Q16 located on the secondary side of the high-frequency transformer based on the switching patterns of each MOSFET power transistor in the three-level DC-DC converter. The duty cycle of MOSFET Q13 is the same as that of MOSFET Q9, but there is a phase shift angle within the switching cycle. The phase-shifting module adjusts the phase shift angle between MOSFETs Q13 and Q9 to 360°·D. MOSFETs Q14 and Q13 are complementary, and MOSFETs Q15 and Q14 have the same duty cycle but are 180° out of phase within the switching cycle. Q16 and Q15 are complementary. This is how the switching signals for MOSFETs Q13, Q14, Q15, and Q16 located on the secondary side of the high-frequency transformer are obtained.

[0053] Figure 5 The grid voltage v obtained using the method of this invention g (t), grid current i g (t), System input power P in System output power P o Power absorbed by the split capacitor unit P c The waveforms of the DC bus voltage and the four capacitor voltages of the split capacitor unit are shown; the voltage modulation of each capacitor in the split capacitor unit is as follows:

[0054]

[0055] Where θ is the phase difference between the capacitor voltage and the grid voltage, V c U is the amplitude of the capacitor voltage. c1 (t), u c2 (t), u c3 (t), u c4 (t) represent the voltages across capacitors C1, C2, C3, and C4, respectively;

[0056] Based on the system power balance, the phase difference θ between the capacitor voltage and the grid voltage and the amplitude V of the capacitor voltage can be obtained in equation (4). c They are respectively:

[0057]

[0058]

[0059] The capacitance values ​​of the four capacitors in the split capacitor unit must meet the following requirements:

[0060]

[0061] Among them, C f V is the total capacitance of capacitors C1 and C2.g L represents the grid voltage amplitude. g It is the grid-side inductor.

[0062] Any aspects not covered in this invention are applicable to existing technologies.

Claims

1. A method for suppressing secondary ripple voltage on the DC bus of a two-stage three-level AC / DC converter, wherein the converter includes a grid-side inductor, a front-stage three-level AC-DC converter, a split capacitor unit, and a rear-stage three-level DC-DC converter; the input terminal of the front-stage three-level AC-DC converter is connected to the grid side through the grid-side inductor, and the output terminal is connected to the input terminal of the rear-stage three-level DC-DC converter through the split capacitor unit; the output terminal of the rear-stage three-level DC-DC converter is connected to the load through a filter capacitor; the front-stage three-level AC-DC converter includes switching devices Q1 to Q8, with switching devices Q1 to Q4 forming one bridge arm and switching devices Q5 to Q8 forming another bridge arm; the split capacitor unit includes capacitors C1 to C4 and a filter inductor L. f1 L f2 The subsequent three-level DC-DC converter includes switching devices Q9 to Q16 and DC blocking capacitor C. b1 ~C b2 The system consists of a high-frequency inductor Lt and a high-frequency transformer T1; the positive terminal of capacitor C1 is connected to one output of the preceding three-level AC-DC converter, the negative terminal of capacitor C1 is connected to the positive terminal of capacitor C2, the negative terminal of capacitor C2 is connected to the positive terminal of capacitor C3, the negative terminal of capacitor C3 is connected to the positive terminal of capacitor C4, and the negative terminal of capacitor C4 is connected to the other output of the preceding three-level AC-DC converter; the filter inductor L... f1 One end of the filter inductor is connected to the connection point of capacitors C1 and C2, and the other end is connected to the connection point of switching devices Q9 and Q10 in the subsequent three-level DC-DC converter. f2 One end is connected to the connection point of capacitors C3 and C4, and the other end is connected to the connection point of switching devices Q11 and Q12 in the subsequent three-level DC-DC converter; the switching devices Q9 to Q12 in the subsequent three-level DC-DC converter are connected in series, the drain of switch Q9 is connected to the positive terminal of capacitor C1, and the source of switching device Q12 is connected to the negative terminal of capacitor C4. The DC blocking capacitor C... b1 One end is connected to the connection point of switching devices Q9 and Q10, and the other end is connected to the high-frequency inductor L. t One end is connected to the high-frequency inductor L t The other end is connected to one end of the primary winding of high-frequency transformer T1. The other end of the primary winding of high-frequency transformer T1 is connected to the connection point of switching devices Q11 and Q12. Switching devices Q13 and Q14 are connected in series to form one bridge arm, and switching devices Q15 and Q16 are connected in series to form another bridge arm. The filter capacitor is connected in parallel with the two bridge arms; DC blocking capacitor C b2 One end of the circuit is connected to one end of the secondary side of the high-frequency transformer T1, and the other end is connected to the connection point of switching devices Q13 and Q14; the other end of the secondary side of the high-frequency transformer T1 is connected to the connection point of switching devices Q15 and Q16; characterized in that... This method includes voltage and current dual closed-loop control of the front-end three-level AC-DC converter and duty cycle and phase shift angle control of the rear-end three-level DC-DC converter; the modulation voltage is obtained through the voltage and current dual closed-loop control of the front-end three-level AC-DC converter. That is, the reference voltage on the AC side of the preceding three-level AC-DC converter, expressed as: In the formula, v g (t) represents the grid voltage, i g (t) represents the grid current, ω represents the power frequency angular frequency, and L g For grid-side inductance, K is the reference value for the fundamental amplitude of the power grid current, K3 is the ratio of the amplitude of the third harmonic to the amplitude of the fundamental frequency, and K i t is the proportionality coefficient of the inner current loop, and t is the time variable; modulating voltage The duty cycle signals of switching devices Q1 to Q8 are generated by SPWM modulation, and the switching devices Q1 to Q8 are controlled according to the duty cycle signals to adjust the DC component of the DC bus voltage. The duty cycle and phase shift angle control process of the subsequent three-level DC-DC converter is as follows: First, the duty cycle of the switching device Q9 is obtained through voltage and current dual closed-loop control; then, based on the complementary duty cycles of the switching devices Q10 and Q9, the same duty cycles of the switching devices Q11 and Q9 except that the phase difference is 180° within the switching cycle, and the complementary duty cycles of Q12 and Q11, the switching signals of the switching devices Q10 to Q12 are obtained; then, the inter-bridge phase shift ratio D is calculated according to equations (2) and (3). Among them, P o The system output power is given by α1, where α1 is the duty cycle of switching device Q9, and V is the voltage. dc_link Here, n is the sampled value of the DC bus voltage, n is the turns ratio of the primary to secondary side of the high-frequency transformer, and T is the input voltage. s For the switching cycle, U out L is the load voltage. t It is a high-frequency inductor; Finally, based on the fact that the duty cycle of switching device Q13 is the same as that of Q9, but there is a phase shift angle within the switching cycle, the phase shift angle between switching devices Q13 and Q9 is adjusted to 360°·D; switching devices Q14 and Q13 are complementary, switching devices Q15 and Q14 have the same duty cycle but are 180° out of phase within the switching cycle, and Q16 and Q15 are complementary, thus obtaining the switching signals of switching devices Q13 to Q16.

2. The method for suppressing secondary ripple voltage on the DC bus of a two-stage three-level AC / DC converter according to claim 1, characterized in that, The voltages of each capacitor in the split capacitor unit are: Where ω is the power frequency angular frequency, θ is the phase difference between the capacitor voltage and the grid voltage, and V c U is the amplitude of the capacitor voltage. c1 (t), u c2 (t), u c3 (t), u c4 (t) represent the voltages across capacitors C1, C2, C3, and C4, respectively; The phase difference θ between the capacitor voltage and the mains voltage and the amplitude V of the capacitor voltage. c They are respectively: The capacitance values ​​of the four capacitors in the split capacitor unit must meet the following requirements: Among them, C f V is the total capacitance of capacitors C1 and C2. g L represents the grid voltage amplitude. f1 Filter inductor L f1 The value of .

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