Relaxation Oscillator

Abstract

The relaxation oscillator disclosed by the present invention includes: a voltage source VDD, a current source I1, transistors M0, M1, M2, M3, M4, M5, M6, a resistor R1, four switches SW1, SW2, SW3, SW4, a capacitor C1, a comparator, a Schmitt trigger, and inverters INV1, INV2, INV3. Based on the prior art, the present invention adds transistors M5 and M6, and transistors M5 and M6 are PMOS transistors or PNP bipolar transistors with the same parameters. The circuit design of the present invention enables the output high-threshold comparison voltage to be V H +V GS5 or V H +V GS6 , realizing a source follower similar to one with a pull-down ability but without a pull-up ability. Therefore, during the charging process of capacitor C1, the source follower does not work. When capacitor C1 is charged to V H +V GS5 or V H +V GS6 , the voltage will be clamped by the source follower formed by M5 and M3 and will not increase further, thereby improving the accuracy of the relaxation oscillator.

Description

Technical Field

[0001] The invention belongs to the technical field of electronic circuits, and in particular relates to a relaxation oscillator. Background Art

[0002] Oscillators are indispensable for smart chips. Currently, chips have high demands for high-performance oscillators. However, it is not easy to improve performance parameters such as oscillator accuracy. Although there are various adjustment and temperature compensation solutions, there is no good solution to the overshoot problem during the charging process of the relaxation oscillator, making it the biggest obstacle to improving the accuracy of the relaxation oscillator.

[0003] Figure 1 The figure shows the schematic diagram of a traditional relaxation oscillator, which mainly includes: a current source I1, MOS tubes M1, M2, M3, a transistor M0, a resistor R1, four switches SW1, SW2, SW3, SW4, a capacitor C1, a comparator, a Schmitt trigger, and three inverters INV1, INV2, INV3 connected in series. Figure 1 The working principle of the oscillator shown is: If the voltage V on capacitor C1 CIN Lower than the E terminal voltage V of transistor M0 L , then V CIN Through the comparator and V L By comparison, the switches SW1 and SW3 controlled by the signal S1 are closed, and the switches SW2 and SW4 controlled by the signal S2 are opened; at this time, V CIN The voltage V at the high voltage end of resistor R1 H Compare, at this time V CIN Less than V H , the logic remains unchanged (switches SW1 and SW3 controlled by signal S1 are closed, switches SW2 and SW4 controlled by signal S2 are open), and the oscillator outputs a high level; at the same time, the current I1 provided by the current source charges the capacitor C1 through the MOS tube M3, and the voltage V on the capacitor C1 is CIN Continuously increasing, when V CIN Greater than V H When the comparator output changes, the logic changes (the switches SW1 and SW3 controlled by signal S1 are disconnected, and the switches SW2 and SW4 controlled by signal S2 are closed), and the oscillator outputs high and low levels; the charging time of capacitor C1 is recorded as T1. After the logic changes, V CIN With V L In comparison, V CIN Greater than V L , the output logic remains unchanged (switches SW1 and SW3 controlled by signal S1 are disconnected, switches SW2 and SW4 controlled by signal S2 are closed), the oscillator output is high and low, at this time capacitor C1 starts to discharge to ground, V CIN Continuously decreases, when V CINWhen it is lower than VL, the logic changes again (switches SW1 and SW3 controlled by signal S1 are closed, and switches SW2 and SW4 controlled by signal S2 are opened), and the oscillator outputs a high level, and the cycle repeats.

[0004] In the above working process, assuming that the capacitance of capacitor C1 is C, the charging current is I3, the discharging current is I4, and the current of MOS tube M2 is I2, then we can get the expression (1) of charging time T1, the expression (2) of discharging time T2, and the expression (3) of voltage VR on resistor R1:

[0005]

[0006]

[0007] VR=V H -V L =I2*R1 (3).

[0008] Substituting expression (3) into expressions (1) and (2), we can further obtain expressions (4) and (5) for charging time and discharging time:

[0009]

[0010]

[0011] Figure 2 for Figure 1 The waveform diagram of the relaxation oscillator node signal shown in FIG. 1 shows that the conventional relaxation oscillator has overshoot during the charging process. Figure 2 The phenomenon is shown in the dashed line interval. Figure 2 As shown, under normal circumstances, the voltage on capacitor C1 reaches V H However, due to the influence of factors such as delay, overshoot will occur, and the final frequency is 1 / 2 the inverse of the rise time, which in turn affects the accuracy of the oscillator. Summary of the invention

[0012] The present invention provides a relaxation oscillator, aiming to improve the accuracy of the relaxation oscillator; the present invention is achieved through the following technical solution.

[0013] A relaxation oscillator, characterized in that it includes: a voltage source VDD, a current source I1, transistors M0, M1, M2, M3, M4, M5, M6, a resistor R1, four switches SW1, SW2, SW3, SW4, a capacitor C1, a comparator, a Schmitt trigger, and inverters INV1, INV2, and INV3; the input electrodes of the transistors M0, M1, M2, M3, and M4 are respectively connected to the voltage source VDD, and the control electrodes of the transistors M0, M1, M2, M3, and M4 are respectively connected to the input end of the current source I1, the output electrode of the transistor M1 is connected to the input end of the current source I1, and the output end of the current source I1 is grounded; the output electrode of the transistor M2 is connected to the input electrode of the transistor M0 via the resistor R1, and the control electrode and the output electrode of the transistor M0 are both grounded; the transistors M5 and M6 are PMOS tubes or PNP triodes with consistent parameters; the high voltage end of the resistor R1 is connected to the control electrode of the transistor M6 and the control electrode of the transistor M5, and the low voltage end is connected to the switch S One end of W2, the output electrode of transistor M6 and the output electrode of transistor M5 are grounded; the output electrode of transistor M4 is connected to the input electrode of transistor M6 and one end of switch SW1, and the other end of switch SW1 and the other end of switch SW2 are both connected to the first input end of the comparator; the output electrode of transistor M3 is connected to one end of switch SW3 and the input electrode of transistor M5, the other end of switch SW3 is connected to the positive electrode of capacitor C1 and the second input end of the comparator, and the negative electrode of capacitor C1 is grounded; one end of switch SW4 is connected to the second input end of the comparator, and the other end is grounded; the input end of the Schmitt trigger is connected to the output end of the comparator, and the output end is sequentially connected in series with three inverters INV1, INV2, and INV3, the first inverter INV1 outputs a signal S1 that controls switches SW1 and SW3, the second inverter INV2 outputs a signal S2 that controls switches SW2 and SW4, and the third inverter INV3 outputs a clock signal CLK.

[0014] Preferably, the transistor M0 is a PNP transistor.

[0015] Preferably, the transistors M1, M2, M3, M4, M5 and M6 are PMOS transistors.

[0016] Preferably, the transistors M1, M2, M3, M4, M5 and M6 are PNP transistors.

[0017] Preferably, a current source I2 is further included, and the other end of the switch SW4 is grounded via the current source I2.

[0018] Preferably, it further includes NMOS tubes M7 and M8, the low voltage end of the resistor R1 is connected to the control electrodes of the NMOS tubes M7 and M8 respectively, and the input electrodes of the NMOS tubes M7 and M8 are respectively connected to the voltage source VDD; one end of the switch SW2 is connected to the low voltage end of the resistor R1 via the output electrode and the control electrode of the NMOS tube M7; the other end of the switch SW4 is connected to the output electrode of the NMOS tube M8.

[0019] Preferably, a current source I3 is further included, and the output electrode of the NMOS tube M7 is grounded via the current source I3.

[0020] Preferably, the NMOS transistors M7 and M8 are replaced by NPN transistors respectively.

[0021] The beneficial effects of the present invention include: based on the prior art, transistors M5 and M6 are added, and the transistors M5 and M6 are PMOS tubes or PNP triodes with the same parameters. The circuit design of the present invention makes the output high threshold comparison voltage V H +V GS5 or V H +V GS6 , a source follower with pull-down capability but no pull-up capability is realized. Therefore, when the capacitor C1 is charged, the source follower does not work. When the capacitor C1 is charged to V H +V GS5 or V H +V GS6 When , the voltage will be clamped by the source follower composed of M5 and M3 and will no longer increase, thereby improving the accuracy of the relaxation oscillator. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Schematic diagram of a traditional relaxation oscillator.

[0023] Figure 2 for Figure 1 The waveform diagram of the signals at each node of the relaxation oscillator is shown.

[0024] Figure 3 This is a schematic diagram of a relaxation oscillator provided in Embodiment 1 of the present invention.

[0025] Figure 4 This is a principle waveform diagram of the relaxation oscillator for eliminating overshoot provided in the first embodiment of the present invention.

[0026] Figure 5 This is a schematic diagram of a relaxation oscillator provided in Embodiment 2 of the present invention.

[0027] Figure 6 This is a schematic diagram of a relaxation oscillator provided in Embodiment 3 of the present invention.

[0028] Figure 7 This is a principle waveform diagram of the relaxation oscillator for eliminating overshoot provided in the third embodiment of the present invention.

[0029] Figure 8 This is a schematic diagram of a relaxation oscillator provided in Embodiment 4 of the present invention. DETAILED DESCRIPTION

[0030] Embodiment 1

[0031] like Figure 3 As shown, this embodiment provides a relaxation oscillator, including: a voltage source VDD, a current source I1, a current source I2, PMOS tubes M1, M2, M3, M4, M5, M6, a PNP transistor M0, a resistor R1, four switches SW1, SW2, SW3, SW4, a capacitor C1, a comparator, a Schmitt trigger, and inverters INV1, INV2, INV3.

[0032] Among them, the S poles of the PMOS tubes M1, M2, M3, and M4 are connected to the voltage source VDD, and the G poles of the PMOS tubes M1, M2, M3, and M4 are connected to the input end of the current source I1, the D pole of the PMOS tube M1 is connected to the input end of the current source I1, and the output end of the current source I1 is grounded; the D pole of the PMOS tube M2 is connected to the E pole of the PNP transistor M0 through the resistor R1, and the B pole and the C pole of the PNP transistor M0 are both grounded; the high voltage end of the resistor R1 is connected to the G pole of the PMOS tube M6 and the G pole of the PMOS tube M5, and the low voltage end is connected to one end of the switch SW2, and the D pole of the PMOS tube M6 and the D pole of the PMOS tube M5 are grounded; the D pole of the PMOS tube M4 is connected to the S pole of the PMOS tube M6 and one end of the switch SW1, and the other end of the switch SW1 and the other end of the switch SW2 are both connected to the comparator The first input terminal (negative input terminal) of the comparator is connected to the D pole of the PMOS tube M3 and the S pole of the PMOS tube M5. The other end of the switch SW3 is connected to the positive electrode of the capacitor C1 and the second input terminal (positive input terminal) of the comparator, and the negative electrode of the capacitor C1 is grounded. One end of the switch SW4 is connected to the second input terminal of the comparator, and the other end is connected to the input terminal of the current source I2. The output terminal of the current source I2 is grounded. The input terminal of the Schmitt trigger is connected to the output terminal of the comparator, and the output terminal is sequentially connected in series with three inverters INV1, INV2, and INV3. The first inverter INV1 outputs a signal S1 for controlling the switches SW1 and SW3, the second inverter INV2 outputs a signal S2 for controlling the switches SW2 and SW4, and the third inverter INV3 outputs a clock signal CLK.

[0033] The working principle and process of the relaxation oscillator are as follows:

[0034] PMOS tubes M4 and M6 form a source follower, and PMOS tubes M5 and M3 form a source follower, so that the output high threshold comparison voltage is V H +V GS5 or V H +V GS6 , where V GS5 and V GS6are the VGS voltages of M5 and M6 (the driving voltage of the MOS tubes); in this embodiment, the PMOS tubes M5 and M6 are of the same model, so their VGS are equal. Since the PMOS source follower has the pull-down capability but not the pull-up capability, the source follower does not work when the capacitor C1 is charged. H +V GS5 or V H +V GS6 When , the voltage will be clamped by the source follower composed of M5 and M3 and will no longer increase, thereby improving the accuracy of the relaxation oscillator.

[0035] Combination Figure 3 and Figure 4 As shown in the figure: when the switches SW1 and SW3 controlled by the signal S1 are closed and the switches SW2 and SW4 controlled by the signal S2 are opened, the PMOS tubes M1 and M3 form a current mirror, M3 mirrors the current of M1, and M3 generates a current I3. Since the capacitor C1 is in the previous state (the switches SW1 and SW3 controlled by the signal S1 are opened, and the switches SW2 and SW4 controlled by the signal S2 are closed), the voltage on the capacitor C1 is V L , V L Less than V H -V th5 (V th5 is the threshold voltage of M5), M5 works in the deep linear region, the current is very small and can be ignored. It can be considered that the current is all used to charge the capacitor C1. As time goes by, the voltage on the capacitor C1 gradually increases. When the voltage value reaches V H +V GS5 When the current that charges capacitor C1 will all flow through M5, capacitor C1 will not be charged by current, so the voltage will remain at V H +V gs5 , thereby reducing overshoot, and V GS5 It is calculated by setting the width-to-length ratio of M5, and the expression is as follows:

[0036]

[0037] Where I3 is the current of M3, u p is the hole mobility, c ox is the gate oxide capacitance, (w / l)5 is the width-to-length ratio of M5, V th5 is the threshold voltage of M5. When a certain width-to-length ratio is given, it can be determined that the voltage of capacitor C1 is clamped to V H +V gs5 , at this time the comparator's flip ratio comparison threshold is V H +V gs6 , through appropriate settings (the current flowing through M4 is equal to M3, and the width-to-length ratio of M5 is equal to the width-to-length ratio of M6), Vgs5 Equal to V gs6 , then the voltage on capacitor C1 will reach V H +V gs5 The comparator flips.

[0038] Figure 4 In the figure, t1 is the theoretical flipping point, but because the comparator needs to reflect time, it will only flip at t2. The t2 time can be reduced by increasing the comparator speed. Figure 4 The dotted slash line in the figure is a waveform diagram without using the above technology of the present invention, and the solid slash line is a waveform diagram using the above technology of the present invention. By comparison, it can be found that the present invention can effectively avoid overshoot and improve the accuracy of the oscillator.

[0039] Embodiment 2

[0040] like Figure 5 As shown, the relaxation oscillator provided in the second embodiment is different from that in the first embodiment in that the PMOS tubes M5 and M6 are replaced by PNP transistors.

[0041] Embodiment 3

[0042] The previous embodiment mentioned that the capacitor C1 will have overshoot during charging, so adding M6 and M5 can solve the overshoot problem. In fact, there will also be overshoot during the discharge of the capacitor C1, so this embodiment adds NMOS tubes M7, M8 and current source I3 to solve this problem. Figure 6 As shown, the connection mode of this embodiment is different from that of the first embodiment in that: the low voltage end of the resistor R1 is connected to the control electrodes of the NMOS transistors M7 and M8 respectively, and the input electrodes of the NMOS transistors M7 and M8 are connected to the voltage source VDD; one end of the switch SW2 is connected to the low voltage end of the resistor R1 via the output electrode and the control electrode of the NMOS transistor M7; the other end of the switch SW4 is connected to the output electrode of the NMOS transistor M8; the current source I3, the output electrode of the NMOS transistor M7 is grounded via the current source I3.

[0043] Here, M7 and M8 can only be NMOS transistors, not PMOS transistors, but NPN transistors can be used instead. In this embodiment, the overshoot of the discharge process is as follows: Figure 7 Ideally, the voltage on capacitor C1 drops to V L When the voltage drops to V, it should stop decreasing and start charging. However, due to delays and other reasons, the voltage may drop to V L By using the solution of this embodiment, the voltage of capacitor C1 can be clamped at a set voltage and no longer decrease, thereby achieving the purpose of improving accuracy.

[0044] Embodiment 4

[0045] like Figure 8 As shown, the relaxation oscillator provided in the fourth embodiment is different from that in the third embodiment in that the PMOS tubes M1, M2, M3, and M4 are replaced by PNP transistors.

[0046] It is specially noted here that in all embodiments of the present invention, M5 and M6 can only be P-type devices (PMOS tube or PNP transistor), not NMOS tube or NPN transistor; and M7 and M8 can only be N-type devices (NMOS tube or NPN transistor), not PMOS tube or PNP transistor, otherwise they will not work. PMOS tubes M1, M2, M3, M4 and PNP transistor M0 can be appropriately and flexibly replaced by other transistors with input pole, output pole and control pole.

[0047] The above embodiments are intended to fully disclose rather than limit the present invention. Any replacement of equivalent technical features that can be obtained based on the creative purpose of the present invention without creative work should be regarded as within the scope of the present invention.

Claims

1. A relaxation oscillator, characterized in that: include: Voltage source VDD, current source I1, transistors M0, M1, M2, M3, M4, M5, M6, resistor R1, four switches SW1, SW2, SW3, SW4, capacitor C1, comparator, Schmitt trigger, inverters INV1, INV2, INV3; The input electrodes of transistors M0, M1, M2, M3, and M4 are connected to the voltage source VDD, and the control electrodes of the transistors M0, M1, M2, M3, and M4 are connected to the input end of the current source I1. The output electrode of transistor M1 is connected to the input end of the current source I1, and the output end of the current source I1 is grounded. The output electrode of transistor M2 is connected to the input electrode of transistor M0 via resistor R1, and the control electrode and output electrode of transistor M0 are both grounded. The transistors M5 and M6 are PMOS transistors or PNP transistors with consistent parameters. The high-voltage end of resistor R1 is connected to the control electrode of transistor M6 and the control electrode of transistor M5, and the low-voltage end is connected to one end of switch SW2, and the output electrode of transistor M6 and the output electrode of transistor M5 are grounded. The output electrode of transistor M4 is connected to the input electrode of transistor M6 and one end of switch SW1. , the other end of the switch SW1 and the other end of the switch SW2 are both connected to the first input end of the comparator; the output electrode of the transistor M3 is connected to one end of the switch SW3 and the input electrode of the transistor M5, the other end of the switch SW3 is connected to the positive electrode of the capacitor C1 and the second input end of the comparator, and the negative electrode of the capacitor C1 is grounded; one end of the switch SW4 is connected to the second input end of the comparator, and the other end is grounded; the input end of the Schmitt trigger is connected to the output end of the comparator, and the output end is sequentially connected in series with three inverters INV1, INV2, and INV3, the first inverter INV1 outputs a signal S1 that controls the switches SW1 and SW3, the second inverter INV2 outputs a signal S2 that controls the switches SW2 and SW4, and the third inverter INV3 outputs a clock signal CLK.

2. The relaxation oscillator according to claim 1, characterized in that The transistor M0 is a PNP transistor.

3. The relaxation oscillator according to claim 1, characterized in that The transistors M1, M2, M3, M4, M5 and M6 are PMOS transistors.

4. The relaxation oscillator according to claim 1, characterized in that: The transistors M1, M2, M3, M4, M5 and M6 are PNP transistors.

5. The relaxation oscillator according to claim 1, characterized in that: A current source I2 is further included, and the other end of the switch SW4 is grounded via the current source I2.

6. The relaxation oscillator according to any one of claims 1 to 5, characterized in that: It also includes NMOS tubes M7 and M8, the low voltage end of the resistor R1 is connected to the control electrodes of the NMOS tubes M7 and M8 respectively, and the input electrodes of the NMOS tubes M7 and M8 are connected to the voltage source VDD; one end of the switch SW2 is connected to the low voltage end of the resistor R1 via the output electrode and the control electrode of the NMOS tube M7; the other end of the switch SW4 is connected to the output electrode of the NMOS tube M8.

7. The relaxation oscillator according to claim 6, characterized in that: A current source I3 is also included, and the output terminal of the NMOS tube M7 is grounded via the current source I3.

8. The relaxation oscillator according to claim 6, characterized in that: The NMOS transistors M7 and M8 are replaced by NPN transistors respectively.

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