Flip-flop circuit, decision feedback equalizer, chip and electronic equipment

Abstract

The invention discloses a flip-flop circuit, a decision feedback equalizer, a chip and electronic equipment, and belongs to the technical field of integrated circuits. The flip-flop circuit comprises a first latch sub-circuit and a second latch sub-circuit; the first latch sub-circuit comprises a first input pair transistor, a first switch pair transistor and a switch unit; the first end of the first input geminate transistor is electrically connected with the first power supply end, the second end is electrically connected with the first end of the first switch geminate transistor, and the control end conducts the first power supply end and the first switch geminate transistor under the control of a differential analog signal; the first end of the first input pair transistor is a differential output end; the second end of the first switch geminate transistor is electrically connected with the second power supply end, and the control end conducts the first input geminate transistor and the second power supply end under the control of a first clock signal; the switch unit is used for conducting the differential output end under the control of a second clock signal; and the second latch sub-circuit is used for processing the output signal of the first latch sub-circuit and outputting a differential digital signal. Circuit speed can be improved, and power consumption is prevented from being increased.

Description

Technical Field

[0001] The present application belongs to the technical field of integrated circuits, and specifically relates to a trigger circuit, a decision feedback equalizer, a chip and an electronic device. Background Art

[0002] D-type flip-flops are widely used in signal transmission of high-speed links. For example, the decision maker in a decision feedback equalizer (DFE) is generally implemented by a D-type flip-flop. A D-type flip-flop can be composed of two-stage latches, such as latches based on current mode logic (CML).

[0003] In the related art, when the switch pair of the latch in the D-type flip-flop is turned on, the branch where the input pair is located is turned on. If one input signal in the differential signal received by the input pair is greater than the other input signal, the current in one branch is greater than the current in the other branch, thereby pulling up the voltage of one output terminal in the differential output terminal and pulling down the voltage of the other output terminal.

[0004] In order to increase the working speed, the current D-type flip-flop adds transistors in the latch current branch, which is equivalent to adding a pseudo current source. The newly added transistors can be used to increase the bias current of the current branch, so that the current branch can achieve a higher amplification gain, which plays a role in increasing the circuit speed. However, adding transistors in the current branch will increase power consumption. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide a trigger circuit, a decision feedback equalizer, a chip and an electronic device, which can solve the problem that adding transistors in the latch current branch will increase power consumption in order to increase the operating speed of the trigger.

[0006] In a first aspect, an embodiment of the present application provides a trigger circuit, the trigger circuit comprising: a first latch subcircuit and a second latch subcircuit; the first latch subcircuit at least comprises a first input pair of transistors, a first switch pair of transistors and a switch unit;

[0007] The first end of the first input pair of transistors is electrically connected to the first power supply end, and the second end is electrically connected to the first end of the first switch pair of transistors. The control end is used to receive a differential analog signal. The first input pair of transistors is used to conduct the first power supply end and the first switch pair of transistors under the control of the differential analog signal. The first end of the first input pair of transistors also serves as a differential output end of the first latch subcircuit.

[0008] The second end of the first switch pair is electrically connected to the second power supply end, and the control end is used to receive a first clock signal; the first switch pair is used to conduct the first input pair and the second power supply end under the control of the first clock signal;

[0009] The switch unit is connected between the differential output terminals, and is used to turn on the differential output terminals under the control of a second clock signal;

[0010] The second latch sub-circuit is electrically connected to the differential output terminal of the first latch sub-circuit, and is used to process the output signal of the first latch sub-circuit and output a differential digital signal.

[0011] Optionally, the first switch pair includes a first transistor and a second transistor; the first transistor is of opposite type to the second transistor;

[0012] The first electrode of the first transistor is electrically connected to the second end of the first input pair tube, the second electrode is electrically connected to the second power supply end, and the control electrode is used to receive the first sub-signal; under the triggering of the first signal edge of the first sub-signal, the first transistor turns on the first input pair tube and the second power supply end;

[0013] The first electrode of the second transistor is electrically connected to the second end of the first input pair transistor, the second electrode is electrically connected to the second power supply end, and the control electrode is used to receive the second sub-signal;

[0014] The switch unit comprises a switch transistor, the switch transistor is of the same type as the first transistor; the switch transistor is connected between the differential output terminals of the first latch sub-circuit; the control electrode of the switch transistor is used to receive the second clock signal;

[0015] The first clock signal includes the first sub-signal and the second sub-signal, the first sub-signal and the second sub-signal are inverted signals; and the first signal edge of the second clock signal is advanced by a preset time length relative to the first signal edge of the first sub-signal.

[0016] Optionally, the first input transistor pair includes a third transistor and a fourth transistor;

[0017] The first electrode of the third transistor is electrically connected to the first power supply terminal, the second electrode is electrically connected to the first end of the first switch pair, and the control electrode is used to receive a first input signal;

[0018] The first electrode of the fourth transistor is electrically connected to the first power supply terminal, the second electrode is electrically connected to the first end of the first switch pair, and the control electrode is used to receive a second input signal; wherein the differential analog signal includes the first input signal and the second input signal;

[0019] The first electrode of the third transistor and the first electrode of the fourth transistor serve as differential output terminals of the first latch subcircuit; the first electrode of the switching transistor in the switching unit is electrically connected to the first electrode of the third transistor, and the second electrode is electrically connected to the first electrode of the fourth transistor.

[0020] Optionally, the second latch subcircuit at least includes: a second input pair of transistors, a second switch pair of transistors, a first positive feedback pair of transistors, an output pair of transistors, and a second positive feedback pair of transistors;

[0021] The first end of the second input pair is electrically connected to the ground end, the second end is electrically connected to the first end of the second switch pair, and the control end is electrically connected to the differential output end of the first latch sub-circuit;

[0022] The second end of the second switch pair is electrically connected to the first end of the first positive feedback pair, and the control end is used to receive a third clock signal; the second switch pair is used to conduct the second input pair and the first positive feedback pair under the control of the third clock signal;

[0023] The first end of the first positive feedback pair of transistors is also electrically connected to the control end of the output pair of transistors, and the second end is electrically connected to the first power supply end; the first positive feedback pair of transistors is a cross-coupling structure, which is used to amplify the voltage difference of the control end of the output pair of transistors to a target voltage difference; wherein the target voltage difference is the voltage difference between the first power supply end and the ground end;

[0024] The first end of the output pair of transistors is electrically connected to the second end of the second positive feedback pair of transistors, and the second end is electrically connected to the first power supply end. The first end of the output pair of transistors serves as the differential output end of the second latch subcircuit.

[0025] The first end of the second positive feedback transistor pair is electrically connected to the ground end; the second positive feedback transistor pair is a cross-coupling structure, which is used to amplify the voltage difference of the differential output end to the target voltage difference.

[0026] Optionally, the first positive feedback transistor pair includes a fifth transistor and a sixth transistor; the output transistor pair includes a seventh transistor and an eighth transistor;

[0027] The first electrode of the fifth transistor is electrically connected to the control electrode of the sixth transistor, the control electrode of the eighth transistor, and the second end of the second switch pair respectively; the second electrode of the fifth transistor is electrically connected to the first power supply end, and the control electrode is electrically connected to the first electrode of the sixth transistor;

[0028] The first electrode of the sixth transistor is also electrically connected to the control electrode of the seventh transistor and the second end of the second switch pair, and the second electrode is electrically connected to the first power supply end.

[0029] Optionally, the second positive feedback transistor pair includes a ninth transistor and a tenth transistor;

[0030] The first electrode of the ninth transistor is electrically connected to the ground terminal, and the second electrode is electrically connected to the control electrode of the tenth transistor and the first electrode of the seventh transistor in the output pair of transistors respectively;

[0031] The first electrode of the tenth transistor is electrically connected to the ground terminal, and the second electrode is electrically connected to the control electrode of the ninth transistor and the first electrode of the eighth transistor in the output pair of transistors.

[0032] Optionally, the second latch subcircuit further includes a third switch pair; the transistor type of the third switch pair is opposite to the transistor type of the second switch pair;

[0033] The first end of the third switch pair is electrically connected to the first end of the first positive feedback pair, and the second end is electrically connected to the second end of the first positive feedback pair, and is used to conduct the first power supply end and the first end of the first positive feedback pair under the control of the third clock signal in the first level state;

[0034] The second switch pair is used to turn on the first end of the second input pair and the first positive feedback pair under the control of the third clock signal in the second level state.

[0035] In a second aspect, an embodiment of the present application provides a decision feedback equalizer, wherein the decision feedback equalizer includes a trigger circuit as described in the first aspect.

[0036] In a third aspect, an embodiment of the present application provides a chip, wherein the chip includes the trigger circuit as described in the first aspect.

[0037] In a fourth aspect, an embodiment of the present application provides an electronic device, wherein the electronic device comprises the chip as described in the third aspect.

[0038] A trigger circuit, a decision feedback equalizer, a chip, and an electronic device provided in the embodiments of the present application have at least the following advantages:

[0039] The first latch subcircuit receives the first clock signal through the first switch pair. When the first clock signal controls the first input pair to be turned on with the second power supply terminal, the first latch subcircuit can sample the differential analog signal through the first input pair, so that the output signal of the differential output terminal changes with the input differential analog signal. The second latch subcircuit processes the output signal of the first latch subcircuit, and then outputs the differential digital signal to the subsequent digital circuit. A switch unit is connected between the differential output terminals of the first latch subcircuit. The second clock signal can control the switch unit to turn on the differential output terminal, which is equivalent to connecting a resistor between the differential output terminals. At this time, the voltage of the differential output terminal will be pulled to a close level value, which can reduce the change time of the voltage of the differential output terminal, thereby improving the circuit speed. Compared with the method of increasing the circuit speed by adding transistors in the current branch in the related art, the switch unit in the embodiment of the present application only plays a switch role without providing current, so it will not increase the power consumption of the trigger circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a structural schematic diagram of a trigger circuit provided in an embodiment of the present application;

[0041] Figure 2 It is a structural schematic diagram of a current mode logic latch in the related art;

[0042] Figure 3 is a structural schematic diagram of a first latch sub-circuit provided in an embodiment of the present application;

[0043] Figure 4 is a structural schematic diagram of a second latch sub-circuit provided in an embodiment of the present application;

[0044] Figure 5 It is a structural diagram of a D-type flip-flop provided in an embodiment of the present application;

[0045] Figure 6 This is a simulation schematic diagram of a D-type trigger provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0047] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or at least two. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0048] In the related technology, the D-type flip-flop (D Flip Flop, DFF) is a commonly used unit in the circuit, which is controlled by the clock signal and triggered by the edge. When the rising edge (or falling edge) of the clock signal arrives, the output state changes according to the input signal. At other times, the output state will maintain the previously written value.

[0049] The transistor may be a metal oxide semiconductor (MOS) field effect transistor, and may be an N-type MOS transistor, namely an NMOS transistor, or a P-type MOS transistor, namely a PMOS transistor. The control electrode of the transistor may be the gate of the MOS transistor, the first electrode of the transistor may be the source or drain of the MOS transistor, and the second electrode may be the drain or the source.

[0050] Figure 1 is a schematic diagram of the structure of a trigger circuit 10 provided in an embodiment of the present application, such as Figure 1 As shown, the trigger circuit 10 includes: a first latch subcircuit 101 and a second latch subcircuit 102; the first latch subcircuit 101 at least includes a first input pair of transistors 1011, a first switch pair of transistors 1012 and a switch unit 1013;

[0051] The first end of the first input pair transistor 1011 is electrically connected to the first power supply end, and the second end is electrically connected to the first end of the first switch pair transistor 1012. The control end is used to receive a differential analog signal. The first input pair transistor 1011 is used to conduct the first power supply end and the first switch pair transistor 1012 under the control of the differential analog signal. The first end of the first input pair transistor 1011 also serves as the differential output end of the first latch sub-circuit 101.

[0052] The second end of the first switch pair 1012 is electrically connected to the second power supply end, and the control end is used to receive the first clock signal; the first switch pair 1012 is used to conduct the first input pair 1011 and the second power supply end under the control of the first clock signal;

[0053] The switch unit 1013 is connected between the differential output terminals, and is used to turn on the differential output terminals under the control of the second clock signal;

[0054] The second latch sub-circuit 102 is electrically connected to the differential output terminal of the first latch sub-circuit 101 , and is used to process the output signal of the first latch sub-circuit 101 and output a differential digital signal.

[0055] In some embodiments, the trigger circuit 10 can be applied to a D-type trigger, the first latch subcircuit 101 can be used as a first-stage latch, and the second latch subcircuit 102 can be used as a second-stage latch, thereby forming a two-stage latch of a D-type trigger.

[0056] At present, when signals are transmitted in high-speed links, due to the influence of the channel and the transmission rate, problems such as inter-symbol interference, reflection, and crosstalk will occur. In order to eliminate these problems and meet the system bit error rate requirements, equalization technology is usually required. For example, the decision feedback equalizer (DFE) in the nonlinear equalizer is often used at the signal receiving end. The DFE consists of a feedback device and a decision device, and the decision device is generally implemented by a D-type flip-flop. The decision device needs to receive a differential analog signal and make a decision to form a digital signal output.

[0057] In some embodiments, the trigger circuit 10 can receive a differential analog signal input at a high speed, output a differential digital signal after signal processing, and provide it to a subsequent digital circuit, so it can be applied to a D-type trigger in a DFE.

[0058] In some embodiments, the first input pair of transistors 1011 may include two transistors of the same type, for example, the first input pair of transistors 1011 may be a pair of NMOS transistors or a pair of PMOS transistors. The control end of the first input pair of transistors 1011 may be the control electrodes of the two transistors, for receiving differential analog signals. The first end of the first input pair of transistors 1011 may be the first electrodes of the two transistors, electrically connected to the first power supply end, and the first electrodes of the two transistors also serve as the differential output end of the first latch subcircuit 101. The second end of the first input pair of transistors 1011 may be the second electrodes of the two transistors, electrically connected to the first end of the first switch pair of transistors 1012. The two transistors may be located in two branches of the first latch subcircuit 101, respectively.

[0059] In some embodiments, the first switch pair 1012 may include two transistors of opposite types, for example, the first switch pair 1012 may include an NMOS transistor and a PMOS transistor. The control end of the first switch pair 1012 may be the control electrodes of the two transistors, for receiving the first clock signal. The first end of the first switch pair 1012 may be the first electrodes of the two transistors, electrically connected to the first input pair 1011. The second end of the first switch pair 1012 may be the second electrodes of the two transistors, electrically connected to the second power supply end.

[0060] In some embodiments, the first power supply terminal can be connected to a working power supply to receive a working voltage VDD, and the two transistors in the first input pair 1011 can be electrically connected to the first power supply terminal through resistors. The second power supply terminal can be connected to a current source, such as a current source including a transistor, and the control electrode of the transistor can receive a bias voltage VBIAS. The ground terminal can be a common ground terminal such as a digital ground VSS.

[0061] In some embodiments, the second latch subcircuit 102 is electrically connected to the differential output terminal of the first latch subcircuit 101, and can receive the output signal of the first latch subcircuit 101, and then process the output signal of the first latch subcircuit 101. The output signal of the first latch subcircuit 101 is an analog signal, and the second latch subcircuit 102 can convert the output signal of the first latch subcircuit 101 into a digital signal, and output the differential digital signal to the subsequent digital circuit.

[0062] In some embodiments, the first clock signal and the second clock signal may be periodic square wave signals provided by an external clock circuit, and the first clock signal and the second clock signal play a control role in the trigger circuit 10. For example, they may be periodic square wave signals provided by a phase locked loop (PLL) circuit.

[0063] In some embodiments, the switch unit 1013 is connected between the differential output terminals of the first latch sub-circuit 101. Specifically, the switch unit 1013 is connected between the first electrodes of the two transistors in the first input pair 1011. The control terminal of the switch unit 1013 is used to receive the second clock signal. Under the control of the second clock signal, the switch unit 1013 turns on the differential output terminals of the first latch sub-circuit 101. In this way, the differential output terminals of the first latch sub-circuit 101 are equivalent to being connected with a resistor.

[0064] If one input signal of the differential analog signal received by the first input pair tube 1011 is greater than the other input signal, then one branch current is greater than the other branch current, thereby pulling up the voltage of one output terminal of the differential output terminal and pulling down the voltage of the other output terminal. By connecting the resistors between the differential output terminals, the voltages of the differential output terminals can be pulled to a close level value, which can reduce the change time of the differential output terminal voltage, thereby improving the circuit speed.

[0065] In the embodiment of the present application, the first latch subcircuit 101 receives the first clock signal through the first switch pair 1012. When the first clock signal controls the first input pair 1011 to be turned on with the second power supply terminal, the first latch subcircuit 101 can receive the differential analog signal through the first input pair 1011, so that the output signal of the differential output terminal changes with the input differential analog signal. The second latch subcircuit 102 processes the output signal of the first latch subcircuit 101, and then outputs the differential digital signal to the subsequent digital circuit. A switch unit 1013 is connected between the differential output terminals of the first latch subcircuit 101. The second clock signal can control the switch unit 1013 to turn on the differential output terminal, which is equivalent to connecting a resistor between the differential output terminals. At this time, the voltage of the differential output terminal will be pulled to a close level value, which can reduce the change time of the voltage of the differential output terminal, thereby improving the circuit speed. Compared with the method of increasing the circuit speed by adding a current branch in the related art, the switch unit 1013 in the embodiment of the present application only plays a switch role without providing current, so it will not increase the power consumption of the trigger circuit 10.

[0066] Optionally, the first switch pair 1012 includes a first transistor and a second transistor; the first transistor is of opposite type to the second transistor;

[0067] The first electrode of the first transistor is electrically connected to the second end of the first input pair tube 1011, the second electrode is electrically connected to the second power supply end, and the control electrode is used to receive the first sub-signal; when triggered by the first signal edge of the first sub-signal, the first transistor conducts the first input pair tube 1011 and the second power supply end;

[0068] The first electrode of the second transistor is electrically connected to the second end of the first input pair transistor 1011, the second electrode is electrically connected to the second power supply end, and the control electrode is used to receive the second sub-signal;

[0069] The switch unit 1013 includes a switch transistor, which is of the same type as the first transistor; the switch transistor is connected between the differential output terminals of the first latch sub-circuit 101; and the control electrode of the switch transistor is used to receive the second clock signal;

[0070] The first clock signal includes a first sub-signal and a second sub-signal, the first sub-signal and the second sub-signal are anti-phase signals; and a first signal edge of the second clock signal is advanced by a preset time length relative to a first signal edge of the first sub-signal.

[0071] In some embodiments, the first switch pair 1012 includes a first transistor and a second transistor of opposite types. For example, one of the first transistor and the second transistor may be an NMOS transistor and the other may be a PMOS transistor.

[0072] In some embodiments, the first electrode of the first transistor may be electrically connected to the second electrode of the third transistor in the first input pair 1011, the second electrode of the first transistor may be electrically connected to the second power supply terminal, and further connected to the current source. The first electrode of the second transistor may be electrically connected to the second electrode of the fourth transistor in the first input pair 1011, the second electrode of the second transistor may be electrically connected to the second power supply terminal, and further connected to the current source.

[0073] In some embodiments, the control electrode of the first transistor is used to receive the first sub-signal, and the control electrode of the second transistor is used to receive the second sub-signal. The first clock signal includes a first sub-signal and a second sub-signal, the first sub-signal and the second sub-signal are inverted signals, and the first sub-signal and the second sub-signal are used to control the first transistor and the second transistor, which are two opposite types of transistors. Under the triggering of the first signal edge of the first sub-signal, the first transistor turns on the first input pair 1011 and the second power supply terminal. The first signal edge can be a rising edge or a falling edge, and the first signal edge is related to the type of the first transistor.

[0074] For example, the first transistor is an NMOS tube, and the second transistor is a PMOS tube. When the first sub-signal is a high-level signal, the first transistor is controlled to be turned on, and when the second sub-signal is a low-level signal, the second transistor is controlled to be turned on. The first transistor is an NMOS tube, and the first signal edge of the first sub-signal is a rising edge. When the rising edge of the first sub-signal is triggered, the first transistor turns on the first input pair tube 1011 and the second power supply terminal. This is only an example, and the embodiment of the present application does not limit this.

[0075] In some embodiments, the switch unit 1013 includes a switch transistor, which may be an NMOS transistor or a PMOS transistor, and the switch transistor is of the same type as the first transistor. The switch transistor is connected between the differential output terminals of the first latch subcircuit 101. Specifically, the first electrode of the third transistor and the first electrode of the fourth transistor in the first input pair 1011 serve as the differential output terminals of the first latch subcircuit 101, and the switch transistor is connected between the first electrode of the third transistor and the first electrode of the fourth transistor.

[0076] In some embodiments, the control electrode of the switching transistor is configured to receive a second clock signal. The second clock signal and the first sub-signal corresponding to the first transistor are associated clock signals, and the first signal edge of the second clock signal is advanced by a preset duration relative to the first signal edge of the first sub-signal. Since the switching transistor and the first transistor are of the same type, the switching transistor conducts the differential output terminals of the first latch sub-circuit 101 under the trigger of the first signal edge of the second clock signal. For example, the switching transistor conducts the first pole of the third transistor and the first pole of the fourth transistor.

[0077] In some embodiments, the signal waveforms of the second clock signal and the first sub-signal may be the same, and the only difference is that the first signal edge of the second clock signal is advanced by a preset duration relative to the first signal edge of the first sub-signal. The preset duration may be several picoseconds (ps). In this way, the switching transistor is turned on earlier than the first transistor by the preset duration, conducts the differential output terminals of the first latch sub-circuit 101, and enables the first transistor to be turned on under the control of the first sub-signal. After the first transistor is turned on, the first latch sub-circuit 101 samples the differential analog signal. Since the differential output terminals of the first latch sub-circuit 101 are equivalent to resistors after the switching transistor is turned on, they can be quickly pulled close to the approximate level value, which can improve the circuit speed and reduce the probability of sampling errors.

[0078] Optionally, the first input pair of transistors 1011 includes a third transistor and a fourth transistor;

[0079] The first pole of the third transistor is electrically connected to the first power supply terminal, the second pole is electrically connected to the first end of the first switching pair of transistors 1012, and the control electrode is configured to receive the first input signal;

[0080] The first pole of the fourth transistor is electrically connected to the first power supply terminal, the second pole is electrically connected to the first end of the first switching pair of transistors 1012, and the control electrode is configured to receive the second input signal; wherein, the differential analog signal includes the first input signal and the second input signal;

[0081] The first poles of the third transistor and the fourth transistor serve as the differential output terminals of the first latch sub-circuit 101; the first pole of the switching transistor in the switching unit 1013 is electrically connected to the first pole of the third transistor, and the second pole is electrically connected to the first pole of the fourth transistor.

[0082] In some embodiments, the first input pair 1011 includes a third transistor and a fourth transistor, two transistors of the same type, and the third transistor and the fourth transistor may be a pair of NMOS transistors or a pair of PMOS transistors. The first electrode of the third transistor is electrically connected to the first power supply terminal through the first resistor R1, and then connected to the working power supply to receive the working voltage VDD. The second electrode of the third transistor is electrically connected to the first electrode of the first transistor in the first switch pair 1012, and the third transistor of the first input pair 1011 and the first transistor of the first switch pair 1012 may belong to a branch of the first latch subcircuit 101.

[0083] In some embodiments, the first electrode of the fourth transistor is electrically connected to the first power supply terminal through the second resistor, and further connected to the working power supply to receive the working voltage VDD. The second electrode of the fourth transistor is electrically connected to the first electrode of the second transistor in the first switch pair 1012, and the fourth transistor of the first input pair 1011 and the second transistor of the first switch pair 1012 may belong to another branch of the first latch sub-circuit 101.

[0084] In some embodiments, the differential analog signal includes a first input signal and a second input signal, the control electrode of the third transistor is used to receive the first input signal, and the control electrode of the fourth transistor is used to receive the second input signal. The first electrode of the third transistor and the first electrode of the fourth transistor serve as the differential output end of the first latch subcircuit 101, the first electrode of the switch transistor is electrically connected to the first electrode of the third transistor, and the second electrode is electrically connected to the first electrode of the fourth transistor.

[0085] In some embodiments, when the switch transistor is turned on under the control of the second clock signal, the first electrode of the third transistor and the first electrode of the fourth transistor are turned on, so that the first electrode of the third transistor and the first electrode of the fourth transistor are equivalent to connecting a resistor. The voltage of the differential output terminal can be pulled to a close level value through the resistor connected between the differential output terminals, which can reduce the change time of the differential output terminal voltage, thereby improving the circuit speed.

[0086] Figure 2 is a schematic diagram of a current mode logic latch in the related art, such as Figure 2 As shown, the CML latch adds an NMOS tube 222 on the basis of the traditional CML latch, and uses the transistor to increase the bias current of the latch branch 202, so that the latch branch 202 can achieve a higher amplification gain, which plays a role in improving the circuit speed. However, this will increase the power consumption of the circuit, and because the circuit branch current becomes larger, the line width required by the layout is also larger, which will increase the layout area.

[0087] Figure 31 is a schematic diagram of the structure of a first latch subcircuit 101 provided in an embodiment of the present application. The first latch subcircuit 101 adopts current mode logic (CML) and can be used as a first-level latch of a D-type flip-flop. Figure 3 As shown, the first switch pair 1012 includes a first transistor, namely an NMOS tube M5, and a second transistor, namely a PMOS tube M6. The gate of the NMOS tube M5 receives the first sub-signal, namely the clock signal CLKP, and the gate of the PMOS tube M6 receives the second sub-signal, namely the clock signal CLKN. The clock signals CLKP and CLKN are a pair of inverted signals. The switch transistor is an NMOS tube M0, which is an NMOS tube like the first transistor. The gate of the NMOS tube M0 receives the second clock signal, namely the clock signal CLKC. Among them, the clock signal CLKC leads the clock signal CLKP by a buffer time. For example, the waveform of the clock signal CLKC is the same as that of the clock signal CLKP. The waveform of the clock signal CLKC is obtained by shifting the waveform of the clock signal CLKP forward by several ps.

[0088] like Figure 3 As shown, the first input pair 1011 includes a third transistor, namely, an NMOS transistor M1, and a fourth transistor, namely, an NMOS transistor M2. The gate of the NMOS transistor M1 receives a first input signal, namely, an input signal D, and the gate of the NMOS transistor M2 receives a second input signal, namely, an input signal DX, and the differential analog signal includes the input signal D and the input signal DX. The drains of the NMOS transistors M1 and M2 serve as differential output terminals QX and Q of the first latch subcircuit 101. The switch transistor, namely, the NMOS transistor M0, is connected between the differential output terminals QX and Q. The NMOS transistor M5 and the PMOS transistor M6 are also connected to the sources of the NMOS transistors M1 and M2. The NMOS transistor M1 is connected to the working power supply VDD through the first resistor R1, and the NMOS transistor M2 is connected to the working power supply VDD through the second resistor R2. The gate of the NMOS transistor M9 receives a bias voltage VBIAS as a current source. The source of the NMOS transistor M5 is connected to the drain of the NMOS transistor M9, and the drain of the PMOS transistor M6 is connected to the drain of the NMOS transistor M9.

[0089] like Figure 3As shown, the first latch subcircuit 101 also includes a positive feedback structure formed by cross-coupling of NMOS tube M3 and NMOS tube M4, and a fourth switch pair. Among them, the gate of NMOS tube M3 is connected to the drain of NMOS tube M4, and the gate of NMOS tube M4 is connected to the drain of M3. The fourth switch pair includes PMOS tube M7 controlled by clock signal CLKP, and NMOS tube M8 controlled by clock signal CLKN. The drains of NMOS tube M1 and NMOS tube M2 are connected to the drains of NMOS tube M4 and NMOS tube M3. The source of PMOS tube M7 and the drain of NMOS tube M8 are also connected to the source of NMOS tube M3 and NMOS tube M4. The gate of NMOS tube M10 receives bias voltage VBIAS as a current source. The drain of PMOS tube M7 is connected to the drain of NMOS tube M10, and the source of NMOS tube M8 is connected to the drain of NMOS tube M10.

[0090] like Figure 3 As shown, when the first sub-signal is at a high level, that is, the clock signal CLKP=1, and the second sub-signal is at a low level, that is, the clock signal CLKN=0, the first switch pair 1012M5, M6 is turned on, and the branch where the first input pair 1011M1, M2 is located is turned on. At this time, the fourth switch pair M7, M8 is turned off, and the branch where the NMOS tube M3 and the NMOS tube M4 are located is turned off. If the first input signal D is greater than the second input signal DX, the current on the NMOS tube M1 is greater than the current flowing through the NMOS tube M2, so that the voltage drop on the first resistor R1 is greater than the voltage drop on the second resistor R2, thereby pulling the output terminal QX down and pulling the output terminal Q up.

[0091] like Figure 3 As shown, when the first sub-signal is at a low level, that is, the clock signal CLKP=0, and the second sub-signal is at a high level, that is, the clock signal CLKN=1, the first switch pair 1012M5, M6 is turned off, the branch where the first input pair 1011M1, M2 is located is turned off, the fourth switch pair M7, M8 is turned on, and the branch where the NMOS tubes M3 and M4 are located is turned on. Since the gate and drain of the NMOS tubes M3 and M4 are connected to form a positive feedback structure, the output signals of the differential output terminals QX and Q are latched.

[0092] like Figure 3As shown, at the rising edge of the clock signal CLKP jumping from 0 to 1, that is, the rising edge of the clock signal CLKN jumping from 1 to 0, the first latch sub-circuit 101 samples the input differential analog signal. During the period when the clock signal CLKP=1, that is, the clock signal CLKN=0, the output signals of the differential output terminals Q and QX will change due to the NMOS tube M1 and NMOS tube M2 controlled by the input signals D and DX, and the change time is related to the capacitance values ​​of the first resistor R1, the second resistor R2 and the differential output terminals Q and QX. For example, in a high-speed link, the frequency of the clock signal is 8GHz, then each cycle is only 125ps, and each half cycle is 62.5ps. The differential output terminals Q and QX need to change to the correct value within 62.5ps, otherwise the sampling error will occur. This affects the size of the first input pair tubes 1011M1 and M2 and the selection of the resistors R1 and R2, making the size that meets the timing requirements strict.

[0093] The trigger circuit 10 provided in the embodiment of the present application has a switch transistor M0 controlled by a clock signal CLKC connected between the differential output terminals Q and QX. The clock signal CLKC is offset from the clock signal CLKP by a buffer of time, and the clock signal CLKC leads the clock signal CLKP by a buffer of time. When the clock signal CLKC=1, the switch transistor M0 is turned on, which is equivalent to connecting a resistor between the differential output terminals Q and QX. At this time, the differential output terminals Q and QX will be pulled close to a similar level value, which saves the time that originally needs to change and reduces the probability of sampling errors.

[0094] Optionally, the second latch subcircuit 102 at least includes: a second input pair of transistors 1021, a second switch pair of transistors 1022, a first positive feedback pair of transistors 1023, an output pair of transistors 1024 and a second positive feedback pair of transistors 1025;

[0095] The first end of the second input pair transistor 1021 is electrically connected to the ground end, the second end is electrically connected to the first end of the second switch pair transistor 1022, and the control end is electrically connected to the differential output end of the first latch sub-circuit 101;

[0096] The second end of the second switch pair 1022 is electrically connected to the first end of the first positive feedback pair 1023, and the control end is used to receive the third clock signal; the second switch pair 1022 is used to conduct the second input pair 1021 and the first positive feedback pair 1023 under the control of the third clock signal;

[0097] The first end of the first positive feedback pair of transistors 1023 is also electrically connected to the control end of the output pair of transistors 1024, and the second end is electrically connected to the first power supply end; the first positive feedback pair of transistors 1023 is a cross-coupling structure, which is used to amplify the voltage difference of the control end of the output pair of transistors 1024 to a target voltage difference; wherein the target voltage difference is the voltage difference between the first power supply end and the ground end;

[0098] The first end of the output pair transistor 1024 is electrically connected to the second end of the second positive feedback pair transistor 1025, and the second end is electrically connected to the first power supply end. The first end of the output pair transistor 1024 serves as the differential output end of the second latch sub-circuit 102;

[0099] The first end of the second positive feedback transistor pair 1025 is electrically connected to the ground end. The second positive feedback transistor pair 1025 is a cross-coupling structure, which is used to amplify the voltage difference of the differential output end to the target voltage difference.

[0100] In some embodiments, the second latch subcircuit 102 can provide a full-swing output. The output signal of the first latch subcircuit 101 can be processed into 0 and 1 by using the full-swing characteristic of the second latch subcircuit 102, so that the differential digital signal can be directly output to the subsequent digital circuit. The second latch subcircuit 102 can be used as a secondary latch of a D-type flip-flop and applied to the decision device in the DFE.

[0101] In some embodiments, the second input pair of transistors 1021 may include two transistors of the same type, for example, the second input pair of transistors 1021 may be a pair of NMOS transistors or a pair of PMOS transistors. The control end of the second input pair of transistors 1021 may be the control electrodes of the two transistors, electrically connected to the differential output end of the first latch subcircuit 101. The first end of the second input pair of transistors 1021 may be the first electrodes of the two transistors, electrically connected to the ground end. The second end of the second input pair of transistors 1021 may be the second electrodes of the two transistors, electrically connected to the first end of the second switch pair of transistors 1022. The two transistors may be located in two branches of the second latch subcircuit 102, respectively.

[0102] In some embodiments, the second switch pair 1022 may include two transistors of the same type. For example, the second input pair 1021 may be a pair of NMOS transistors or a pair of PMOS transistors. The control end of the second switch pair 1022 may be the control electrodes of the two transistors, for receiving the third clock signal. The first end of the second switch pair 1022 may be the first electrodes of the two transistors, and may be electrically connected to the second end of the second input pair 1021. The second end of the second switch pair 1022 may be the second electrodes of the two transistors, and may be electrically connected to the first end of the first positive feedback pair 1023.

[0103] In some embodiments, the first positive feedback pair of transistors 1023 may include two transistors of the same type, for example, the first positive feedback pair of transistors 1023 may be a pair of NMOS transistors or a pair of PMOS transistors. The two transistors of the first positive feedback pair of transistors 1023 are cross-coupled structures, for example, the control electrodes of the two transistors are electrically connected to the first electrodes of each other, so that the two transistors form a positive feedback structure through cross-coupling. The first end of the first positive feedback pair of transistors 1023 may be the first electrodes of the two transistors, electrically connected to the control end of the output pair of transistors 1024. The second end of the first positive feedback pair of transistors 1023 may be the second electrodes of the two transistors, electrically connected to the first power supply end.

[0104] In some embodiments, the output pair of transistors 1024 may include two transistors of the same type, for example, the output pair of transistors 1024 may be a pair of NMOS transistors or a pair of PMOS transistors. The control end of the output pair of transistors 1024 may be the control electrodes of the two transistors, and the control electrodes of the two transistors are respectively electrically connected to the first electrode of a transistor in the first positive feedback pair of transistors 1023. The first end of the output pair of transistors 1024 may be the first electrodes of the two transistors, which are electrically connected to the second end of the second positive feedback pair of transistors 1025, and the first electrodes of the two transistors also serve as the differential output end of the second latch subcircuit 102. The second end of the output pair of transistors 1024 may be the second electrodes of the two transistors, which are electrically connected to the first power supply end.

[0105] In some embodiments, the second positive feedback pair of transistors 1025 may include two transistors of the same type, for example, the second positive feedback pair of transistors 1025 may be a pair of NMOS transistors or a pair of PMOS transistors. The two transistors of the second positive feedback pair of transistors 1025 are cross-coupled structures, for example, the control electrodes of the two transistors are electrically connected to the first electrodes of the other party respectively, so that the two transistors form a positive feedback structure through cross-coupling. The first end of the second positive feedback pair of transistors 1025 may be the first electrodes of the two transistors, electrically connected to the ground end. The second end of the second positive feedback pair of transistors 1025 may be the second electrodes of the two transistors, electrically connected to the first end of the output pair of transistors 1024.

[0106] In some embodiments, the second switch pair 1022 turns on the first end of the second input pair 1021 and the first positive feedback pair 1023 under the control of the third clock signal, so that the second input pair 1021 receives the output signal of the first latch subcircuit 101, that is, the second latch subcircuit 102 samples the output signal of the first latch subcircuit 101. Since the signals received by the two transistors in the second input pair 1021 are different, a voltage difference is generated between the first electrodes of the two transistors in the first positive feedback pair 1023, and a voltage difference is also generated between the control electrodes of the two transistors in the output pair 1024.

[0107] When the second switch pair 1022 is turned on, the first power supply terminal is connected to the ground terminal, and the two transistors in the first positive feedback pair 1023 form a positive feedback structure by cross coupling, so that the voltage difference between the control electrodes of the two transistors in the output pair 1024 can be amplified to the voltage difference between the first power supply terminal and the ground terminal, that is, the target voltage difference. For example, the target voltage difference can be the voltage difference between VDD and VSS.

[0108] Among them, since the two transistors in the second positive feedback pair 1025 adopt cross-coupling to form a positive feedback structure, the voltage difference between the first electrodes of the two transistors in the output pair 1024, that is, the voltage difference between the differential output ends of the second latch sub-circuit 102, can be amplified to the target voltage difference, thereby ensuring that the swing amplitude of the differential digital signal output by the second latch sub-circuit 102 is high.

[0109] Optionally, the first positive feedback transistor pair 1023 includes a fifth transistor and a sixth transistor; the output transistor pair 1024 includes a seventh transistor and an eighth transistor;

[0110] The first electrode of the fifth transistor is electrically connected to the control electrode of the sixth transistor, the control electrode of the eighth transistor, and the second end of the second switch pair 1022; the second electrode of the fifth transistor is electrically connected to the first power supply terminal, and the control electrode is electrically connected to the first electrode of the sixth transistor;

[0111] The first electrode of the sixth transistor is also electrically connected to the control electrode of the seventh transistor and the second end of the second switch pair 1022, and the second electrode is electrically connected to the first power supply end.

[0112] In some embodiments, the first positive feedback transistor pair 1023 includes a fifth transistor and a sixth transistor, two transistors of the same type. For example, the first positive feedback transistor pair 1023 may be a pair of NMOS transistors or a pair of PMOS transistors. The fifth transistor and the sixth transistor form a positive feedback structure through cross coupling, the control electrode of the fifth transistor is electrically connected to the first electrode of the sixth transistor, and the first electrode of the fifth transistor is electrically connected to the control electrode of the sixth transistor.

[0113] In some embodiments, the output pair 1024 may include a seventh transistor and an eighth transistor, two transistors of the same type, and the seventh transistor and the eighth transistor may be a pair of NMOS transistors or a pair of PMOS transistors. The control end of the output pair 1024 includes the control electrodes of the seventh transistor and the eighth transistor in the output pair 1024. The first electrode of the fifth transistor is also electrically connected to the control electrode of the eighth transistor and the second electrode of one transistor in the second switch pair 1022. The first electrode of the sixth transistor is also electrically connected to the control electrode of the seventh transistor and the second electrode of another transistor in the second switch pair 1022. The second electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the sixth transistor is also electrically connected to the first power supply terminal.

[0114] Optionally, the second positive feedback transistor pair 1025 includes a ninth transistor and a tenth transistor;

[0115] The first electrode of the ninth transistor is electrically connected to the ground terminal, and the second electrode is electrically connected to the control electrode of the tenth transistor and the first electrode of the seventh transistor in the output pair 1024;

[0116] The first electrode of the tenth transistor is electrically connected to the ground terminal, and the second electrode is electrically connected to the control electrode of the ninth transistor and the first electrode of the eighth transistor in the output pair 1024 respectively.

[0117] In some embodiments, the second positive feedback transistor pair 1025 includes a ninth transistor and a tenth transistor, two transistors of the same type. For example, the second positive feedback transistor pair 1025 may be a pair of NMOS transistors or a pair of PMOS transistors. The ninth transistor and the tenth transistor form a positive feedback structure through cross coupling, the control electrode of the ninth transistor is electrically connected to the second electrode of the tenth transistor, and the second electrode of the ninth transistor is electrically connected to the control electrode of the tenth transistor.

[0118] In some embodiments, the first electrode of the ninth transistor is electrically connected to the ground terminal, the second electrode is electrically connected to the first electrode of the seventh transistor in the input pair, and the seventh transistor and the ninth transistor belong to the same branch. The first electrode of the tenth transistor is electrically connected to the ground terminal, the second electrode is electrically connected to the first electrode of the eighth transistor in the input pair, and the eighth transistor and the tenth transistor belong to the same branch.

[0119] In the second latch subcircuit 102 provided in the embodiment of the present application, the first electrode of the seventh transistor and the first electrode of the eighth transistor in the output pair 1024 serve as the differential output terminal of the second latch subcircuit 102. The signal output from the differential output terminal of the second latch subcircuit 102 can be amplified to the target voltage difference, that is, the voltage difference between the first power supply terminal and the ground terminal, for example, to VDD and VSS, under the effect of the positive feedback structure formed by the cross-coupling of the ninth transistor and the tenth transistor, so as to process the output signal of the first latch subcircuit 101 into 1 and 0, so that the second latch subcircuit 102 can achieve full swing output and provide differential digital signals to the subsequent digital circuit.

[0120] Optionally, the second latch subcircuit 102 further includes a third switch pair 1026; the transistor type of the third switch pair 1026 is opposite to the transistor type of the second switch pair 1022;

[0121] The first end of the third switch pair 1026 is electrically connected to the first end of the first positive feedback pair 1023, and the second end is electrically connected to the second end of the first positive feedback pair 1023, and is used to conduct the first power supply end and the first end of the first positive feedback pair 1023 under the control of the third clock signal in the first level state;

[0122] The second switch pair 1022 is used to turn on the first end of the second input pair 1021 and the first positive feedback pair 1023 under the control of the third clock signal in the second level state.

[0123] In some embodiments, the first end of the third switch pair 1026 is electrically connected to the first end of the first positive feedback pair 1023, and the second end is electrically connected to the second end of the first positive feedback pair 1023, that is, the third switch pair 1026 is connected in parallel next to the first positive feedback pair 1023. The control end of the third switch pair 1026 is used to receive the third clock signal. Since the transistor type of the third switch pair 1026 is opposite to the transistor type of the second switch pair 1022, the second end of the first positive feedback pair 1023 is also electrically connected to the first current source. Therefore, when the third clock signal is in the first level state, the third switch pair 1026 is turned on, so that the first power supply end is connected to the first end of the first positive feedback pair 1023. When the third clock signal is in the second level state, the second switch pair 1022 is turned on, so that the second input pair 1021 and the first end of the first positive feedback pair 1023 are connected.

[0124] In some embodiments, when the third switch pair 1026 is turned on, the third switch pair 1026 is turned off, and the second latch subcircuit 102 is in a sampling state, and the output signal of the first latch subcircuit 101 can be sampled through the second input pair 1021. Conversely, when the third switch pair 1026 is turned on, the third switch pair 1026 is turned off, and the second latch subcircuit 102 is in a holding state. Since the second switch pair 1022 is turned off, the output signal of the first latch subcircuit 101 cannot affect the output state of the output pair 1024. The third switch pair 1026 can set the first end of the first positive feedback pair 1023 to a level state corresponding to the first power supply end, for example, to a high level state, to facilitate the change of the next sampling state.

[0125] Figure 4 1 is a schematic diagram of the structure of a second latch subcircuit 102 provided in an embodiment of the present application. The second latch subcircuit 102 can be used as a secondary latch of a D-type flip-flop and has the characteristic of full swing output. Figure 4 As shown, the second input pair 1021 includes an NMOS tube M17 and an NMOS tube M18, the output signal of the first latch sub-circuit 101 is used as the input signal INP, INN of the second input pair 1021, the gate of the NMOS tube M17 receives the input signal INP, and the gate of the NMOS tube M18 receives the input signal INN. The second switch pair 1022 includes an NMOS tube M15 and an NMOS tube M16, the third clock signal is the clock signal CLK, the gate of the NMOS tube M15 and the gate of the NMOS tube M16 receive the clock signal CLK respectively, and the clock signal CLK plays a control role. The drain of the NMOS tube M17 is connected to the source of the NMOS tube M15, and the drain of the NMOS tube M18 is connected to the source of the NMOS tube M16. The sources of the NMOS tube M17 and the NMOS tube M18 are electrically connected to the ground terminal respectively.

[0126] like Figure 4 As shown, the first positive feedback transistor 1023 includes a fifth transistor, namely a PMOS transistor M12, and a sixth transistor, namely a PMOS transistor M13, and the gates and drains of the PMOS transistors M12 and M13 are cross-coupled to form a positive feedback structure. The sources of the PMOS transistors M12 and M13 are connected to the working power supply VDD, and the drains of the PMOS transistors M12 and M13 are connected to the drains of M15 and M16, respectively.

[0127] like Figure 4As shown, the output transistor pair 1024 includes a seventh transistor, namely a PMOS transistor M19, and an eighth transistor, a PMOS transistor M20. The drain of the PMOS transistor M12 in the first positive feedback transistor pair 1023 is connected to the gate of the PMOS transistor M20, and the drain of the PMOS transistor M13 is connected to the gate of the PMOS transistor M19. The sources of the PMOS transistors M19 and M20 are connected to the working power supply VDD, and the drains of the PMOS transistors M19 and M20 serve as the differential output terminals OUTN and OUTP of the second latch sub-circuit 102.

[0128] like Figure 4 As shown, the second positive feedback pair 1025 includes a ninth transistor, namely an NMOS tube M21, and a tenth transistor, namely an NMOS tube M22, and the gates and drains of the NMOS tubes M21 and M22 are cross-coupled to form a positive feedback structure. The sources of the NMOS tubes M21 and M22 are respectively connected to the ground terminal, and the drains of the NMOS tubes M21 and M22 are electrically connected to the drains of the PMOS tubes M19 and M20.

[0129] like Figure 4 As shown, the third switch pair 1026 includes a PMOS tube M11 and a PMOS tube M14, that is, the type of the third switch pair 1026 is opposite to that of the second switch pair 1022. The gates of the PMOS tubes M11 and M14 are used to receive the clock signal CLK, the sources of the PMOS tubes M11 and M14 are connected to the working power supply VDD, the drain of the PMOS tube M11 is connected to the drain of the PMOS tube M12, and the drain of the PMOS tube M12 is connected to the drain of the PMOS tube M14. That is, the PMOS tubes M11 and M14 are connected in parallel with the PMOS tubes M12 and M13 respectively.

[0130] like Figure 4 As shown, when the third clock signal is at a high level, that is, the clock signal CLK=1, the second switch pair 1022M15, M16 is turned on, and the third switch pair 1026M11, M14 is turned off, and the second latch subcircuit 102 is in a sampling state. Due to the difference between the input signals INP and INN, the gate voltages of the output pair 1024M19, M20 produce a voltage difference, and the gate voltage is further amplified to close to VDD and VSS by the cross-coupled positive feedback structure formed by the first positive feedback pair 1023M12, M13. The signals output by the differential output terminals OUTN and OUTP are amplified to VDD and VSS under the cross-coupled positive feedback structure formed by the second positive feedback pair 1025M21, M22, thereby ensuring a high output swing.

[0131] like Figure 4As shown, when the clock CLK=0, the second switch pair 1022M15, M16 is turned off, and the third switch pair 1026M11, M14 is turned on, and the second latch sub-circuit 102 is in a holding state. The input signals INN and INP cannot affect the output state due to the turn-off of the second switch pair 1022M15 and M16. The third switch pair 1026M11, M14 is turned on to set the drain of the first positive feedback pair 1023M12, M13 to a high level, which is convenient for the change of the next sampling state. The first positive feedback affects the output of OUTN and OUTP by the off state of the tubes 1023M12 and M13. If the PMOS tube M12 is off, the positive feedback will turn on the PMOS tube M13, the PMOS tube M20 controlled by the drain of the PMOS tube M12 is turned on, and the PMOS tube M19 controlled by the drain of the PMOS tube M13 is turned off, thereby affecting the differential output terminals OUTN and OUTP. Conversely, if the PMOS tube M12 is turned on, the PMOS tube M13 is turned off.

[0132] Figure 5 is a structural diagram of a D-type trigger provided in an embodiment of the present application, such as Figure 5 As shown, the D-type flip-flop includes two stages of latches, the first latch subcircuit 101 is used as the first stage latch, and the second latch subcircuit 102 is used as the second stage latch. The clock signal CLKN of the first stage latch is used as the clock signal CLK to the second stage latch.

[0133] like Figure 5 As shown, the output terminal Q of the first latch subcircuit 101 is connected to the input terminal INP of the second latch subcircuit 102, and the output terminal QX is connected to the input terminal INN. The D-type flip-flop will sample at each rising edge of the clock signal CLKN. If the input signal D is greater than the input signal DX, the output terminal OUTP outputs 1, and the output terminal OUTN outputs 0. If the input signal DX is greater than the input signal D, the output terminal OUTP outputs 0, and the output terminal OUTN outputs 1.

[0134] Figure 6 is a simulation schematic diagram of a D-type flip-flop provided in an embodiment of the present application. Figure 5 The D-type flip-flop shown in the figure is simulated, and the simulation results are shown in Figure 6 The first column of signal waveforms is the clock signal CLKP, the second column of signal waveforms is the clock signal CLKN, the third column of signal waveforms is the output signals OUTP and OUTN, and the fourth column of signal waveforms is the input signals D and DX.

[0135] In some embodiments, the first latch subcircuit 101 is used as a CML latch, and the second latch subcircuit 102 is used as a latch with full swing output. The CML latch and the latch with full swing output can be combined to form a high-speed D-type flip-flop. The D-type flip-flop can receive analog signals with differential inputs and can be applied to higher-speed circuits. The first-stage latch can respond to changes in input signals more quickly, and the second-stage latch can form the output signal into a full swing, which can be applied to digital circuits. In the first-stage latch, Figure 3 For example, the NMOS tube M0 controlled by the clock signal CLKC can help the circuit change the level state of the output terminals Q and QX more quickly, so as to respond to the input signal more quickly.

[0136] An embodiment of the present application provides a decision feedback equalizer, which includes a trigger circuit 10 as described in the above embodiment.

[0137] In some embodiments, the decision device in the decision feedback equalizer can be implemented by a D-type flip-flop. The D-type flip-flop can adopt the flip-flop circuit 10 structure in this embodiment. For example, the D-type flip-flop can be Figure 5 The circuit structure shown.

[0138] The decision feedback equalizer has the same advantages as those of the related art and the trigger circuit 10 of the aforementioned embodiment, which will not be described in detail here.

[0139] An embodiment of the present application provides a chip, which includes a trigger circuit 10 as described in the above embodiment.

[0140] The advantages of this chip compared to the related art and the trigger circuit 10 of the aforementioned embodiment are the same, which will not be described in detail here.

[0141] An embodiment of the present application provides an electronic device, and the electronic device includes a chip as described in the above embodiment.

[0142] The advantages of the electronic device compared to the related art and the trigger circuit 10 of the aforementioned embodiment are the same, which will not be described in detail here.

[0143] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0144] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A trigger circuit, characterized in that: The trigger circuit comprises: a first latch subcircuit and a second latch subcircuit; the first latch subcircuit at least comprises a first input pair of transistors, a first switch pair of transistors and a switch unit; The first end of the first input pair of transistors is electrically connected to the first power supply end, and the second end is electrically connected to the first end of the first switch pair of transistors. The control end is used to receive a differential analog signal. The first input pair of transistors is used to conduct the first power supply end and the first switch pair of transistors under the control of the differential analog signal. The first end of the first input pair of transistors also serves as a differential output end of the first latch subcircuit. The second end of the first switch pair is electrically connected to the second power supply end, and the control end is used to receive a first clock signal; the first switch pair is used to conduct the first input pair and the second power supply end under the control of the first clock signal; The switch unit is connected between the differential output terminals, and is used to turn on the differential output terminals under the control of a second clock signal; The second latch sub-circuit is electrically connected to the differential output terminal of the first latch sub-circuit, and is used to process the output signal of the first latch sub-circuit and output a differential digital signal.

2. The trigger circuit according to claim 1, characterized in that: The first switch pair comprises a first transistor and a second transistor; the first transistor is of opposite type to the second transistor; The first electrode of the first transistor is electrically connected to the second end of the first input pair, the second electrode is electrically connected to the second power supply end, and the control electrode is used to receive the first sub-signal; When triggered by the first signal edge of the first sub-signal, the first transistor conducts the first input pair of transistors and the second power supply terminal; The first electrode of the second transistor is electrically connected to the second end of the first input pair transistor, the second electrode is electrically connected to the second power supply end, and the control electrode is used to receive the second sub-signal; The switch unit comprises a switch transistor, the switch transistor is of the same type as the first transistor; the switch transistor is connected between the differential output terminals of the first latch sub-circuit; the control electrode of the switch transistor is used to receive the second clock signal; The first clock signal includes the first sub-signal and the second sub-signal, the first sub-signal and the second sub-signal are inverted signals; and the first signal edge of the second clock signal is advanced by a preset time length relative to the first signal edge of the first sub-signal.

3. The trigger circuit according to claim 1, characterized in that: The first input pair includes a third transistor and a fourth transistor; The first electrode of the third transistor is electrically connected to the first power supply terminal, the second electrode is electrically connected to the first end of the first switch pair, and the control electrode is used to receive a first input signal; The first electrode of the fourth transistor is electrically connected to the first power supply terminal, the second electrode is electrically connected to the first end of the first switch pair, and the control electrode is used to receive a second input signal; wherein the differential analog signal includes the first input signal and the second input signal; The first electrode of the third transistor and the first electrode of the fourth transistor serve as differential output terminals of the first latch subcircuit; the first electrode of the switching transistor in the switching unit is electrically connected to the first electrode of the third transistor, and the second electrode is electrically connected to the first electrode of the fourth transistor.

4. The trigger circuit according to any one of claims 1 to 3, characterized in that: The second latch subcircuit at least includes: a second input pair of transistors, a second switch pair of transistors, a first positive feedback pair of transistors, an output pair of transistors, and a second positive feedback pair of transistors; The first end of the second input pair is electrically connected to the ground end, the second end is electrically connected to the first end of the second switch pair, and the control end is electrically connected to the differential output end of the first latch sub-circuit; The second end of the second switch pair is electrically connected to the first end of the first positive feedback pair, and the control end is used to receive a third clock signal; the second switch pair is used to conduct the second input pair and the first positive feedback pair under the control of the third clock signal; The first end of the first positive feedback pair of transistors is also electrically connected to the control end of the output pair of transistors, and the second end is electrically connected to the first power supply end; the first positive feedback pair of transistors is a cross-coupling structure, which is used to amplify the voltage difference of the control end of the output pair of transistors to a target voltage difference; wherein the target voltage difference is the voltage difference between the first power supply end and the ground end; The first end of the output pair of transistors is electrically connected to the second end of the second positive feedback pair of transistors, and the second end is electrically connected to the first power supply end. The first end of the output pair of transistors serves as the differential output end of the second latch subcircuit. The first end of the second positive feedback transistor pair is electrically connected to the ground end; the second positive feedback transistor pair is a cross-coupling structure, which is used to amplify the voltage difference of the differential output end to the target voltage difference.

5. The trigger circuit according to claim 4, characterized in that: The first positive feedback transistor pair includes a fifth transistor and a sixth transistor; the output transistor pair includes a seventh transistor and an eighth transistor; The first electrode of the fifth transistor is electrically connected to the control electrode of the sixth transistor, the control electrode of the eighth transistor, and the second end of the second switch pair respectively; the second electrode of the fifth transistor is electrically connected to the first power supply end, and the control electrode is electrically connected to the first electrode of the sixth transistor; The first electrode of the sixth transistor is also electrically connected to the control electrode of the seventh transistor and the second end of the second switch pair, and the second electrode is electrically connected to the first power supply end.

6. The trigger circuit according to claim 4, characterized in that: The second positive feedback transistor pair includes a ninth transistor and a tenth transistor; The first electrode of the ninth transistor is electrically connected to the ground terminal, and the second electrode is electrically connected to the control electrode of the tenth transistor and the first electrode of the seventh transistor in the output pair of transistors respectively; The first electrode of the tenth transistor is electrically connected to the ground terminal, and the second electrode is electrically connected to the control electrode of the ninth transistor and the first electrode of the eighth transistor in the output pair of transistors.

7. The trigger circuit according to claim 4, characterized in that: The second latch subcircuit further includes a third switch pair; the transistor type of the third switch pair is opposite to the transistor type of the second switch pair; The first end of the third switch pair is electrically connected to the first end of the first positive feedback pair, and the second end is electrically connected to the second end of the first positive feedback pair, and is used to conduct the first power supply end and the first end of the first positive feedback pair under the control of the third clock signal in the first level state; The second switch pair is used to turn on the first end of the second input pair and the first positive feedback pair under the control of the third clock signal in the second level state.

8. A decision feedback equalizer, characterized in that: The decision feedback equalizer comprises a trigger circuit as described in any one of claims 1-7.

9. A chip, characterized in that: The chip comprises a trigger circuit as described in any one of claims 1-7.

10. An electronic device, characterized in that: The electronic device comprises the chip according to claim 9.

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