Clock signal generation circuit and clock signal generation method thereof

Abstract

A clock signal generation device and a clock signal generation method thereof are provided. 【Solution means】When the analog clock signal generator circuit does not provide the output clock signal CLK3, the control circuit controls the multiplexer circuit 108 to selectively output the oscillator signal CLK2 to the analog clock signal generator circuit, and controls the clock path circuit to stop the transmission of the input clock signal CLK1.

Description

Technical Field

[0001] The present invention relates to a clock signal generation device, and more particularly, to a multi-phase clock signal generation circuit and a clock signal generation method thereof.

Background Art

[0002] Generally speaking, in order to achieve high-speed read / write operations, a memory device often uses a multi-phase clock signal provided by a multi-phase clock circuit to serialize or deserialize data signals. The multi-phase clock circuit may be, for example, a four-phase analog clock generator circuit used to generate a four-phase clock signal. Even when the four-phase analog clock generator circuit does not need to output a clock signal and is in a power-off mode, it is necessary to continuously provide the clock signal to the four-phase clock generator circuit via a clock path circuit, so that the four-phase clock generator circuit can return to the normal mode and operate normally. However, the clock path circuit usually includes relatively power-consuming circuit components such as buffers, and configuring the clock path circuit to provide a clock signal to the four-phase clock generator in this way will consume a significant amount of power.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The present invention provides a clock signal generation circuit and a clock signal generation method thereof that can effectively and significantly reduce the power consumption of the clock signal generation circuit.

Means for Solving the Problems

[0004] The clock signal generation circuit of the present invention includes a receiver circuit, a clock path circuit, an oscillator circuit, a multiplexer circuit, an analog clock signal generator circuit, and a control circuit. The receiver circuit receives an input clock signal. The clock path circuit is coupled to the receiver circuit and transmits the input clock signal. The oscillator circuit provides an oscillator signal having the same frequency as the input clock signal. The input end of the multiplexer circuit is coupled to the clock path circuit and the oscillator circuit. The analog clock signal generator circuit is Output terminal of the multiplexer circuit coupled thereto and provides an output clock signal. The control circuit is coupled to the clock path circuit and the multiplexer circuit. When the analog clock signal generator circuit is not providing the output clock signal, the multiplexer circuit is controlled to selectively output the oscillator signal to the analog clock signal generator circuit, and the clock path circuit is controlled to stop the transmission of the input clock signal.

[0005] In one embodiment of the present invention, in order to generate the oscillator signal based on the input clock signal or the output clock signal, the input end of the oscillator circuit is to coupled to the input end of the clock path circuit.

[0006] In one embodiment of the present invention, the oscillator circuit includes a ring oscillator circuit or an injection-locked oscillator circuit.

[0007] In one embodiment of the present invention, the analog clock signal generator circuit includes a four-phase analog clock signal generator circuit.

[0008] In one embodiment of the present invention, when the analog clock signal generator circuit enters the idle mode or the power-off mode, the control circuit determines that the analog clock signal generator circuit is not providing the output clock signal.

[0009] The present invention also provides a method for generating a clock signal in a clock signal generation circuit. The clock signal generation circuit includes a clock path circuit, an oscillator circuit, a multiplexer circuit, and an analog clock signal generator circuit. The clock path circuit and the oscillator circuit are coupled to an input terminal of the multiplexer circuit. An output terminal of the oscillator circuit is coupled to the analog clock signal generator circuit. The clock path circuit is configured to transmit an input clock signal. The method for generating a clock signal in the clock signal generation circuit includes the following steps. Determine whether the analog clock signal generator circuit is providing an output clock signal. In response to the analog clock signal generator circuit providing an output clock signal, control the multiplexer circuit to selectively output the input clock signal to the analog clock signal generator circuit. In response to the analog clock signal generator circuit not providing an output clock signal, control the multiplexer circuit to selectively output the oscillator signal to the analog clock signal generator circuit, and control the clock path circuit to stop transmitting the input clock signal.

[0010] In one embodiment of the present invention, in order to generate an oscillator signal based on the input clock signal, the input terminal of the oscillator circuit receives the input clock signal. to with

[0011] In one embodiment of the present invention, the oscillator circuit includes a ring oscillator circuit or an injection-locked oscillator circuit.

[0012] In one embodiment of the present invention, the analog clock signal generator circuit includes a four-phase analog clock signal generator circuit.

[0013] In one embodiment of the present invention, when the analog clock signal generator circuit enters the idle mode or the power-off mode, it is determined that the analog clock signal generator circuit is not providing an output clock signal.

Advantages of the Invention

[0014] ​​Based on the above, when the analog clock signal generator circuit does not provide an output clock signal, the control circuit of the embodiment of the present invention controls the multiplexer circuit to selectively output the oscillator signal provided by the oscillator circuit to the analog clock signal generator circuit, and can control the clock path circuit to stop the transmission of the input clock signal. In this way, when the analog clock signal generator circuit does not provide an output clock signal, the oscillator circuit is used instead of the clock path circuit to provide an oscillator signal with the same frequency as the input clock signal to the analog clock signal generator circuit, thereby effectively reducing the power consumption of the clock signal generation circuit.

[0015] To make the above-described features and advantages of the present invention clearer and easier to understand, embodiments will be given below and described in detail with reference to the following accompanying drawings.

Brief Description of the Drawings

[0016]

Figure 1

Figure 2

Figure 3

Modes for Carrying Out the Invention

[0017] FIG. 1 is a schematic diagram of a clock signal generation circuit according to one embodiment of the present invention. Referring to FIG. 1, the clock signal generation circuit may include a receiver circuit 102, a clock path circuit 104, a control circuit 106, a multiplexer circuit 108, an oscillator circuit 110, and an analog clock signal generator circuit 112. The clock path circuit 104 is coupled to the input terminals of the receiver circuit 102, the control circuit 106, and the multiplexer circuit 108. The oscillator circuit 110 is coupled to another input terminal of the multiplexer circuit 108. The control terminal of the oscillator circuit 110 is coupled to the control circuit 106. The output terminal of the multiplexer circuit 108 is coupled to the analog clock signal generator circuit 112. The analog clock signal generator circuit 112 may be, for example, a 4-phase analog clock signal generator circuit, but the present invention is not limited thereto. In other embodiments, the analog clock signal generator circuit 112 may be an analog clock signal generator with a different number of phases. The receiver circuit 102, the clock path circuit 104, the control circuit 106, the multiplexer circuit 108, the oscillator circuit 110, and the analog clock signal generator circuit 112 may be applied to, for example, a memory device and may be implemented as an integrated circuit, a system-on-chip (SoC), a chipset, or a chip assembly.

[0018] The receiver circuit 102 can receive an input clock signal CLK1 that is transmitted to the input terminal of the multiplexer circuit 108 via the clock path circuit 104. The oscillator circuit 110 is configured to receive an input clock signal CLK0 and provide an oscillator signal CLK2 having the same frequency as the input clock signal CLK1. The oscillator circuit 110 may be, for example, an injection locked oscillator (ILO) circuit or a ring oscillator circuit, but the present invention is not limited thereto. For example, emit the oscillator circuit 110 may be coupled to the input terminal of the clock path circuit 104 to provide the oscillator signal CLK2 based on the input clock signal CLK1, as shown in FIG. 2 In other embodiments, the input clock signal CLK0 received by the oscillator circuit 110 is Figure 2Without being limited to the embodiments, it may be from other circuits.

[0019] The control circuit 106 may determine whether the analog clock signal generator circuit 112 is providing the output clock signal CLK3, for example, by determining whether the analog clock signal generator circuit 112 has entered the idle mode or the power-off mode. When the analog clock signal generator circuit 112 enters the idle mode or the power-off mode, it is determined that the analog clock signal generator circuit 112 is not providing the output clock signal. Otherwise, it is determined that the analog clock signal generator circuit 112 is providing the output clock signal. When the control circuit 106 determines that the analog clock signal generator circuit 112 is not providing the output clock signal, the control circuit 106 can control the multiplexer circuit 108 to selectively output the oscillator signal CLK2 to the analog clock signal generator circuit 112 and control the clock path circuit 104 to stop the transmission of the input clock signal CLK1. In this way, when the analog clock signal generator circuit 112 does not need to provide the output clock signal, the oscillator circuit 110 is used instead of the clock path circuit 104 to provide the oscillator signal CLK2 having the same frequency as the input clock signal CLK1 to the analog clock signal generator circuit 112, and the clock path circuit 104 is configured to stop the transmission of the input clock signal CLK1, thereby effectively reducing the power consumption of the clock signal generation circuit without affecting the normal operation of the clock signal generation circuit.

[0020] Figure 3is a flowchart of a clock signal generation method of a clock signal generation circuit according to an embodiment of the present invention. The clock signal generation circuit includes a clock path circuit, an oscillator circuit, a multiplexer circuit, and an analog clock signal generator circuit. The clock path circuit and the oscillator circuit are coupled to an input terminal of the multiplexer circuit. An output terminal of the multiplexer circuit is coupled to the analog clock signal generator circuit. The oscillator circuit may be implemented as a ring oscillator circuit or an injection-locked oscillator circuit, but the present invention is not limited thereto. The clock path circuit is configured to transmit an input clock signal. From the above embodiment, it can be seen that the clock signal generation method of the clock signal generation circuit may include at least the following steps. First, it is determined whether the analog clock signal generator circuit is providing an output clock signal (step S402). For example, it can be determined whether the analog clock signal generator circuit has entered an idle mode or a power-off mode. When the analog clock signal generator circuit enters the idle mode or the power-off mode, it is determined that the analog clock signal generator circuit is not providing an output clock signal. The analog clock signal generator circuit may be, for example, a four-phase analog clock signal generator circuit, but the present invention is not limited thereto. When the analog clock signal generator circuit is providing an output clock signal, the multiplexer circuit is controlled to selectively output the input clock signal to the analog clock signal generator circuit. When it is determined that the analog clock signal generator circuit is providing an output clock signal, the multiplexer circuit is controlled to selectively output the input clock signal provided by the clock path circuit to the analog clock signal generator circuit (step S404). When it is determined that the analog clock signal generator circuit is not providing an output clock signal, the multiplexer circuit is controlled to selectively output the oscillator signal to the analog clock signal generator circuit (step S406), and the clock path circuit is controlled to stop transmitting the input clock signal (step S408). The oscillator circuit generates an oscillator signal based on the input clock signal to and can receive the input clock signal input to generate the oscillator signal. with The input clock signal can be received.

[0021] In summary, when the analog clock signal generator circuit does not provide an output clock signal, the control circuit of the embodiment of the present invention controls the multiplexer circuit to selectively output the oscillator signal provided by the oscillator circuit to the analog clock signal generator circuit, and can control the clock path circuit to stop the transmission of the input clock signal. In this way, when the analog clock signal generator circuit does not provide an output clock signal, the oscillator circuit is used instead of the clock path circuit to provide the analog clock signal generator circuit with an oscillator signal having the same frequency as the input clock signal, thereby effectively reducing the power consumption of the clock signal generation circuit.

Industrial Applicability

[0022] The clock signal generation circuit and its clock signal generation method can be applied to the field of memory devices.

Explanation of Reference Numerals

[0023] 102: Receiver circuit 104: Clock path circuit 106: Control circuit 108: Multiplexer circuit 110: Oscillator circuit 112: Analog clock signal generator circuit CLK1~CLK3: Clock signals S402~S408: Steps of the clock signal generation method of the clock signal generation circuit

Claims

1. a receiver circuit configured to receive an input clock signal; a clock path circuit coupled to the receiver circuit for transmitting the input clock signal; an oscillator circuit configured to provide an oscillator signal at the same frequency as the input clock signal; a multiplexer circuit having inputs coupled to the clock path circuit and the oscillator circuit; an analog clock signal generator circuit coupled to an output of the multiplexer circuit for providing an output clock signal; a control circuit coupled to the clock path circuitry and the multiplexer circuitry and configured to control the multiplexer circuitry to selectively output the oscillator signal to the analog clock signal generator circuitry and to control the clock path circuitry to cease transmitting the input clock signal when the analog clock signal generator circuitry is not providing the output clock signal; Including, Clock signal generation circuit.

2. an input of the oscillator circuit coupled to an input of the clock path circuit for generating the oscillator signal based on the input clock signal; 2. The clock signal generating circuit according to claim 1.

3. The oscillator circuit comprises a ring oscillator circuit or an injection-locked oscillator circuit.

2. The clock signal generating circuit according to claim 1.

4. the analog clock signal generator circuit includes a four-phase analog clock signal generator circuit; 2. The clock signal generating circuit according to claim 1.

5. when the analog clock signal generator circuit enters an idle mode or a power off mode, the control circuit determines that the analog clock signal generator circuit is not providing the output clock signal; 2. The clock signal generating circuit according to claim 1.

6. A clock signal generating method for a clock signal generating circuit, comprising the steps of: the clock signal generation circuit includes a clock path circuit, an oscillator circuit, a multiplexer circuit, and an analog clock signal generator circuit, the clock path circuit and the oscillator circuit being coupled to an input of the multiplexer circuit, an output of the multiplexer circuit being coupled to the analog clock signal generator circuit, the clock path circuit being configured to transmit an input clock signal; The clock signal generating method of the clock signal generating circuit includes: determining whether the analog clock signal generator circuit is providing an output clock signal; controlling the multiplexer circuit to selectively output the input clock signal to the analog clock signal generator circuit in response to the analog clock signal generator circuit providing the output clock signal; controlling the multiplexer circuit to selectively output an oscillator signal to the analog clock signal generator circuit and controlling the clock path circuit to cease transmitting the input clock signal in response to the analog clock signal generator circuit not providing the output clock signal. Including, A clock signal generating method for a clock signal generating circuit.

7. an input of the oscillator circuit receiving an input clock signal for generating the oscillator signal based on the input clock signal; 7. A clock signal generating method for the clock signal generating circuit according to claim 6.

8. The oscillator circuit comprises a ring oscillator circuit or an injection-locked oscillator circuit.

7. A clock signal generating method for the clock signal generating circuit according to claim 6.

9. the analog clock signal generator circuit includes a four-phase analog clock signal generator circuit; 7. A clock signal generating method for the clock signal generating circuit according to claim 6.

10. determining that the analog clock signal generator circuit is not providing an output clock signal when the analog clock signal generator circuit enters an idle mode or a power off mode; 7. A clock signal generating method for the clock signal generating circuit according to claim 6.

Images