Counter, phase-locked loop, automatic frequency control system and control method

Abstract

The invention provides a counter, a phase-locked loop, an automatic frequency control system and a control method, and the counter comprises a sampling window generation module which generates a sampling window signal according to a reference clock signal; the counting module is used for counting the number of cycles of the local oscillator clock signal according to the sampling window signal to obtain an initial count value; the edge detector is used for detecting clock edges of the reference clock signal and the local oscillator clock signal and obtaining an addition and subtraction indication signal according to detected edge information; and the counter calibrates the initial count value according to the addition and subtraction indication signal to obtain a counting result. According to the scheme of the invention, an additional edge detection mechanism is added in the counter, and the counting result of the counting module is calibrated, so that the counting precision of the counter is improved, and the accuracy of a frequency control result can be ensured.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and particularly to a counter, a phase-locked loop, an automatic frequency control system and a control method. Background Art

[0002] A phase-locked loop (PLL) is a feedback control circuit system, which is widely used in fields such as wireless communication, navigation, control, instrumentation, digital signal processing, clock synchronization, frequency synthesis, etc. A typical PLL circuit consists of a phase frequency detector (PFD), a charge pump, a loop filter, a voltage-controlled oscillator VCO and a frequency divider. The characteristic of the PLL is to use the input reference clock provided by an external crystal oscillator to control the local oscillator frequency and phase of the oscillation signal inside the loop, so that its output signal (referred to as the local oscillator clock in this article) maintains a stable phase relationship with the input reference clock, thereby obtaining the required frequency signal.

[0003] Existing PLL circuits often use a counter to obtain the frequency information of the local oscillator clock, so as to obtain the phase difference between the local oscillator clock and the input reference clock, guide the frequency adjustment of the local oscillator clock, and achieve the automatic frequency control (AFC) of the PLL, that is, automatically adjust the clock frequency of the local oscillator clock to track the frequency change of the input reference clock.

[0004] During the process of automatic frequency control, the counting accuracy of the counter is particularly important. For example, when there is a counting deviation in the counter, this counting deviation will cause the locking time of the PLL to become longer after the automatic frequency calibration is completed. Even if the PLL loop has insufficient frequency tracking ability, it will cause the PLL to lose lock. Summary of the Invention

[0005] In order to solve the above technical problems, this application provides a counter, a phase-locked loop, an automatic frequency control system and a control method, aiming to improve the counting accuracy of the counter in the automatic frequency control system and ensure the accuracy of the frequency control result.

[0006] According to the first aspect of this application, a counter is provided, including:

[0007] A sampling window generation module that generates a sampling window signal according to a reference clock signal, and the period of the sampling window signal is an integer multiple of the period of the reference clock signal;

[0008] A counting module that counts the number of periods of the local oscillator clock signal according to the sampling window signal to obtain an initial count value;

[0009] An edge detector that detects the clock edges of the reference clock signal and the local oscillator clock signal, and obtains an addition / subtraction indication signal according to the detected edge information;

[0010] The counter calibrates the initial count value according to the addition / subtraction indication signal to obtain a count result.

[0011] Optionally, when the addition / subtraction indication signal is in the first logic state, the counter adds 1 to the initial count value to obtain the count result;

[0012] When the addition / subtraction indication signal is in the second logic state, the counter subtracts 1 from the initial count value to obtain the count result;

[0013] When the addition / subtraction indication signal is in the third logic state, the counter uses the initial count value as the count result.

[0014] Optionally, within the valid period of the sampling window signal, the edge detector detects the number of rising edges and falling edges of the local oscillator clock signal, and generates the addition / subtraction indication signal according to the number of rising edges and the number of falling edges.

[0015] Optionally, within the valid period of the sampling window signal, the counting module counts the number of cycles of the local oscillator clock signal by detecting the rising edges of the local oscillator clock signal;

[0016] When it is detected that the number of rising edges is less than the number of falling edges, the edge detector outputs the addition / subtraction indication signal having the first logic state;

[0017] When it is detected that the number of rising edges is greater than the number of falling edges, the edge detector outputs the addition / subtraction indication signal having the second logic state;

[0018] When it is detected that the number of rising edges is equal to the number of falling edges, the edge detector outputs the addition / subtraction indication signal having the third logic state.

[0019] Optionally, within the valid period of the sampling window signal, the counting module counts the number of cycles of the local oscillator clock signal by detecting the falling edges of the local oscillator clock signal;

[0020] When it is detected that the number of rising edges is greater than the number of falling edges, the edge detector outputs the addition / subtraction indication signal having the first logic state;

[0021] When it is detected that the number of rising edges is less than the number of falling edges, the edge detector outputs the addition / subtraction indication signal having the second logic state;

[0022] When it is detected that the number of rising edges is equal to the number of falling edges, the edge detector outputs the addition / subtraction indication signal having a third logic state.

[0023] Optionally, the edge detector detects the positional relationship of the transition edges of the sampling window signal with respect to the high and low levels of the local oscillator clock signal, and generates the addition / subtraction indication signal according to the positional relationship.

[0024] Optionally, within the valid period of the sampling window signal, the counting module counts the number of cycles of the local oscillator clock signal by detecting the rising edges of the local oscillator clock signal;

[0025] When it is detected that the first transition edge where the sampling window signal switches from the invalid state to the valid state is during the high level of the local oscillator clock signal, and the second transition edge where the sampling window signal switches from the valid state to the invalid state is during the low level of the local oscillator clock signal, the edge detector outputs the addition / subtraction indication signal having a first logic state;

[0026] When it is detected that the first transition edge where the sampling window signal switches from the invalid state to the valid state is during the low level of the local oscillator clock signal, and the second transition edge where the sampling window signal switches from the valid state to the invalid state is during the high level of the local oscillator clock signal, the edge detector outputs the addition / subtraction indication signal having a second logic state;

[0027] When it is detected that both the first transition edge where the sampling window signal switches from the invalid state to the valid state and the second transition edge where the sampling window signal switches from the valid state to the invalid state are during the high level or the low level of the local oscillator clock signal, the edge detector outputs the addition / subtraction indication signal having a third logic state.

[0028] Optionally, within the valid period of the sampling window signal, the counting module counts the number of cycles of the local oscillator clock signal by detecting the falling edges of the local oscillator clock signal;

[0029] When it is detected that the first transition edge where the sampling window signal switches from the invalid state to the valid state is during the low level of the local oscillator clock signal, and the second transition edge where the sampling window signal switches from the valid state to the invalid state is during the high level of the local oscillator clock signal, the edge detector outputs the addition / subtraction indication signal having a first logic state;

[0030] When the first edge transition of the sampling window signal from the invalid state to the valid state is during the high level of the local oscillator clock signal, and the second edge transition of the sampling window signal from the valid state to the invalid state is during the low level of the local oscillator clock signal, the edge detector outputs the addition / subtraction indication signal having a second logic state;

[0031] When both the first edge transition of the sampling window signal from the invalid state to the valid state and the second edge transition of the sampling window signal from the valid state to the invalid state are during the high level or the low level of the local oscillator clock signal, the edge detector outputs the addition / subtraction indication signal having a third logic state.

[0032] Optionally, the addition / subtraction indication signal includes a first indication signal and a second indication signal;

[0033] When the first indication signal is logic 1 and the second indication signal is logic 0, the addition / subtraction indication signal is in a first logic state;

[0034] When the first indication signal is logic 0 and the second indication signal is logic 1, the addition / subtraction indication signal is in a second logic state;

[0035] When both the first indication signal and the second indication signal are logic 0 or both are logic 1, the addition / subtraction indication signal is in a third logic state.

[0036] Optionally, the edge detector includes:

[0037] A first D flip-flop, having its data terminal receiving the sampling window signal, its clock terminal receiving the local oscillator clock signal, and its in-phase output terminal outputting a first detection signal;

[0038] A second D flip-flop, having its data terminal receiving the sampling window signal, its clock terminal receiving the inverted signal of the local oscillator clock signal, and its in-phase output terminal outputting a second detection signal;

[0039] A third D flip-flop, having its data terminal receiving the second detection signal, its clock terminal receiving the first detection signal, and its in-phase output terminal outputting a first indication signal;

[0040] A fourth D flip-flop, having its data terminal receiving the inverted signal of the second detection signal, its clock terminal receiving the inverted signal of the first detection signal, and its in-phase output terminal outputting a second indication signal.

[0041] According to a second aspect of the present application, an automatic frequency control system is provided, including: a counter as described in any embodiment of the present application.

[0042] According to the third aspect of the present application, a phase-locked loop is provided, including: an automatic frequency control system as described in any embodiment of the present application.

[0043] According to the fourth aspect of the present application, an automatic frequency control method for a phase-locked loop is provided, including:

[0044] Generating a sampling window signal according to a reference clock signal, wherein the period of the sampling window signal is an integer multiple of the period of the reference clock signal;

[0045] Counting the number of periods of a local oscillator clock signal according to the sampling window signal to obtain an initial count value;

[0046] Detecting clock edges of the reference clock signal and the local oscillator clock signal, and obtaining an addition and subtraction indication signal according to the detected edge information;

[0047] Calibrating the initial count value according to the addition and subtraction indication signal to obtain a count result;

[0048] Comparing the count result with an expected count value, and generating a frequency adjustment signal according to the comparison result, wherein the frequency adjustment signal is used to adjust the frequency of the local oscillator clock signal.

[0049] Optionally, calibrating the initial count value according to the addition and subtraction indication signal includes:

[0050] When the addition and subtraction indication signal is in a first logic state, adding 1 to the initial count value to obtain the count result;

[0051] When the addition and subtraction indication signal is in a second logic state, subtracting 1 from the initial count value to obtain the count result;

[0052] When the addition and subtraction indication signal is in a third logic state, using the initial count value as the count result.

[0053] Optionally, detecting clock edges of the reference clock signal and the local oscillator clock signal, and obtaining an addition and subtraction indication signal according to the detected edge information includes:

[0054] Detecting the number of rising edges and the number of falling edges of the local oscillator clock signal within the valid period of the sampling window signal;

[0055] Obtaining the addition and subtraction indication signal according to the number of rising edges and the number of falling edges.

[0056] Optionally, detecting clock edges of the reference clock signal and the local oscillator clock signal, and obtaining an addition and subtraction indication signal according to the detected edge information includes:

[0057] Detect the position relationship between the jump edge of the sampling window signal and the high and low levels of the local oscillator clock signal;

[0058] Obtain the addition and subtraction indication signal according to the position relationship.

[0059] The beneficial effects of this application at least include:

[0060] The embodiment of this application provides a counter. On the basis of the existing counter scheme, an edge detector is added to detect the edge information of the sampling window signal and the high-speed clock to be counted (such as the local oscillator clock). According to the detected edge information, it can be determined whether there are overcounting or undercounting situations in the counting of the cycle number of the high-speed clock by the counting module. Furthermore, after calibrating the initial count value by generating the corresponding addition and subtraction indication signals, the counting accuracy of the counter can be improved, so as to obtain an accurate counting result, and then reduce the PLL locking time and improve the stability of the PLL loop.

[0061] It should be noted that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit this application. Brief Description of the Drawings

[0062] Figure 1 Show a structural block diagram of a phase-locked loop provided according to an embodiment of this application;

[0063] Figure 2 Show a structural block diagram of an automatic frequency control system in the related art;

[0064] Figure 3 Show Figure 2 The timing schematic diagram of the automatic frequency control system during normal counting in;

[0065] Figure 4 Show Figure 2 The timing schematic diagram of the automatic frequency control system during abnormal counting in;

[0066] Figure 5 Show a structural block diagram of an automatic frequency control system provided according to an embodiment of this application;

[0067] Figure 6 Show a schematic diagram of an embodiment of an edge detector provided according to an embodiment of this application;

[0068] Figure 7 Show Figure 5 The timing schematic diagram of an automatic frequency control system in;

[0069] Figure 8 Show Figure 5 Another timing schematic diagram of the automatic frequency control system in;

[0070] Figure 9 Shows Figure 5 Another timing schematic diagram of the automatic frequency control system;

[0071] Figure 10 Shows the implementation process schematic diagram of the automatic frequency control method of the phase-locked loop provided according to the embodiments of the present application. Specific implementation manners

[0072] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure content of the present application more thorough and comprehensive.

[0073] In the description of the present application, references to "one embodiment" or "some embodiments" etc. mean that specific features, structures, or characteristics described in conjunction with the embodiment are included in one or more embodiments of the present application. Thus, the statements "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments" etc. that appear in different places in this specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "comprising", "including", "having" and their variants all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0074] In the description of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment described as "exemplary" or "for example" in the present application should not be construed as being more preferred or more advantageous than other embodiments. The "and / or" herein is a description of the association relationship of the associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in order to facilitate the clear description of the technical solutions of the embodiments of the present application, words such as "first" and "second" are used to distinguish the same items or similar items with basically the same functions and effects. Those skilled in the art can understand that the words such as "first" and "second" do not limit the quantity and execution order, and the words such as "first" and "second" do not necessarily limit to be different.

[0075] In addition, the same reference numerals in the drawings represent the same or similar structures, so the repeated description thereof will be omitted. That is, each part in this specification is described in a combined manner of parallelism and progression. The key point of each part is to illustrate the differences from other parts. For the same or similar parts between each part, reference can be made to each other.

[0076] In some application scenarios, in order to adjust the frequency of the local clock signal during system operation, it is first necessary to lock the frequency of the local clock signal during system operation. Existing phase locked loops (PLLs) or frequency locked loops (FLLs) can both achieve the purpose of locking the frequency of the local clock signal during system operation.

[0077] Taking a digital architecture phase locked loop as an example, referring to Figure 1 As shown, an embodiment of the present application provides a schematic structural diagram of a phase locked loop. The phase locked loop includes a frequency discriminator and phase detector 110, a loop filter (LF) 120, a voltage controlled oscillator (VCO) 130, a frequency divider 140, and an automatic frequency control system 150. The first input terminal of the frequency discriminator and phase detector 110 receives a reference clock signal F_ref. The output terminal of the frequency discriminator and phase detector 110 is connected to the voltage controlled oscillator 130 through the loop filter 120. The output terminal of the voltage controlled oscillator 130 is connected to the second input terminal of the frequency discriminator and phase detector 110 through the frequency divider 140. Among them, the voltage controlled oscillator 130 is used to generate a local clock signal (also referred to as a local oscillator clock signal in this article) F_target, and after dividing the local oscillator clock signal F_target by N (N>0), it is transmitted to the second input terminal of the frequency discriminator and phase detector 110. The frequency discriminator and phase detector 110 compares the phase difference between the N-divided signal F_target / N of the local oscillator clock signal and the reference clock signal F_ref, generates a voltage control signal Vd according to the phase difference, and transmits the voltage control signal Vd to the loop filter 120 through the output terminal of the frequency discriminator and phase detector 110. The loop filter 120 receives the voltage control signal Vd, filters the voltage control signal Vd to generate a first control voltage Vc1 for the voltage controlled oscillator 130, and transmits the first control voltage Vc1 to the voltage controlled oscillator 130, so that the voltage controlled oscillator 130 adjusts the frequency and phase of the local oscillator clock signal F_target, and realizes the locking of the frequency and phase of the local oscillator clock signal F_target to the frequency and phase of the reference clock signal F_ref. In some other embodiments, the frequency divider 140 in the phase locked loop can be omitted. At this time, the second input terminal of the frequency discriminator and phase detector 110 directly receives the local oscillator clock signal F_target output by the voltage controlled oscillator 130. Based on this, Figure 1 the frequency divider 140 in

[0078] It should be noted that when the frequency discriminator and phase detector 110 is used to compare the frequency of the N-divided signal F_target / N of the local oscillator clock signal and the reference clock signal F_ref, this digital architecture phase locked loop can also be referred to as a digital architecture frequency locked loop.

[0079] Exemplarily, in a phase-locked loop of a digital architecture, there is usually also a target clock signal. Among them, both the target clock signal and the reference clock signal are determined, and there is a fixed ratio relationship between the target clock signal and the reference clock signal. To achieve the purpose of fast phase locking, the phase-locked loop usually locks the frequency first and then locks the phase, that is, first aligns the frequency of the local clock signal with the target clock signal, and then aligns the phase of the local clock signal with the target clock signal. Among them, in order to achieve the frequency locking of the phase-locked loop of the digital structure, an automatic frequency control (AFC) system 150 is added to the phase-locked loop. Among them, the automatic frequency control system 150 needs to perform frequency discrimination, that is, determine the frequency difference between the target clock signal and the local oscillator clock signal F_target. The automatic frequency control system 150 often constructs a counting time window (also called a sampling time window in this article) using the reference clock signal F_ref, and counts the target clock signal within this counting time window to generate a target quantity (that is, an expected target count value), and also counts the local oscillator clock signal F_target within this counting time window to generate a local oscillator quantity, and then calculates the difference between the target quantity and the local oscillator quantity. This difference is the equivalent frequency difference between the target clock signal and the local oscillator clock signal F_target. Further, the automatic frequency control system 150 generates a second control signal Vc2 according to this difference and transmits it to the voltage-controlled oscillator 130. The voltage-controlled oscillator 130 adjusts the frequency of the local oscillator clock signal F_target according to the second control signal Vc2 to make the frequency of the output local oscillator clock signal F_target match the frequency of the target clock signal (that is, the target frequency).

[0080] In some embodiments, in order to increase the counting time, the automatic frequency control system 150 also divides the reference clock signal F_ref by N; and, since the frequency of the local oscillator clock signal F_target is usually in the GHz range, but it is often difficult to achieve the GHz range in the digital architecture, the local oscillator clock signal F_target also needs to be divided by a frequency to meet the current frequency requirements in the digital structure.

[0081] The structure and working process of the automatic frequency control system will be described below in conjunction with some specific embodiments.

[0082] Figure 2 The block diagram of a structure of an automatic frequency control system in the related art is shown, as Figure 2As shown in the figure, the automatic frequency control system 200 includes: a sampling window generation module 210, a counting module 220, a comparator 230, and a frequency control module 240. Among them, the input end of the sampling window generation module 210 receives the reference clock signal F_ref, and the output end outputs the sampling window signal window to the first input end of the counting module 220. At the same time, the second input end of the counting module 220 receives the local oscillator clock signal F_target. The output end of the counting module 220 outputs the count value counter to the input end of the comparator 230. The output end of the comparator 230 outputs the difference between the count value counter and the target count value and outputs it to the input end of the frequency control module 240. The frequency control module 240 outputs the second control signal Vc2 according to this difference.

[0083] Reference Figure 3 , Figure 2 The working process of the automatic frequency control system 200 shown in [reference] is as follows:

[0084] First, the sampling window generation module 210 generates a sampling window signal window with a period that is an integer multiple of the period of the reference clock signal F_ref using the reference clock signal F_ref. Then, the counting module 220 counts the number of periods of the local oscillator clock signal F_target during the valid period of the sampling window signal window (such as during the high-level period), equivalently obtaining the frequency information of the local oscillator clock signal F_target. Then, the comparator 230 compares the count value counter of the counting module 220 with the target count value to obtain the difference (this difference is the equivalent frequency difference between the target clock signal and the local oscillator clock signal F_target) or the magnitude relationship between the count value counter and the target count value. Furthermore, the frequency control module 240 generates the second control signal Vc2 according to the difference or magnitude relationship indication signal output by the comparator 230 to adjust the local oscillator frequency of the local oscillator clock signal F_target.

[0085] However, when the local oscillator clock signal F_target and the reference clock signal F_ref are two completely asynchronous clocks, reference Figure 4 , the local oscillator clock signal F_target and the sampling window signal window are also completely asynchronous. At this time, the counting result of the counting module 220 may deviate from the actual counting result, that is, there is a counting deviation. For example, the expected count value is 10, and the actual count value is 9, resulting in a 10% counting deviation. This counting deviation will cause the locking time of the phase-locked loop to become longer after the automatic frequency calibration is completed. Even if the phase-locked loop has insufficient frequency tracking ability, it will cause the phase-locked loop to lose lock.

[0086] Based on this, the present application provides a new automatic frequency control system. On the basis of the existing solution, the counting part in the automatic frequency control system is optimized. Specifically, an edge detection mechanism is added to the counter part in the automatic control system. By detecting, detailed information about the edges of the sampling window signal window and the high-speed clock signal is obtained. Thus, according to the edge positions, it is determined whether the count value of the counting module is overcounted or undercounted, and corresponding addition and subtraction indication signals are generated according to the detection results to calibrate the initial count value of the counter. In this way, the counting deviation of the counter can be reduced or even eliminated, the counting accuracy of the counter can be improved, and the accuracy of the frequency control result of the automatic control system can be ensured.

[0087] Reference Figure 5 , Figure 5 FIG. shows a structural block diagram of an automatic frequency control system provided by an embodiment of the present application. This automatic frequency control system can be applied in Figure 1 the phase-locked loop shown. Specifically, as Figure 5 shown, in this embodiment, the automatic frequency control system 150 includes: a counter 510, a comparator 520, and a frequency control module 530. Among them, the counter 510 receives a reference clock signal F_ref and a local oscillator clock signal F_target respectively. The output end of the counter 510 is connected to the input end of the comparator 520. The output end of the comparator 520 is connected to the input end of the frequency control module 530. The output end of the frequency control module 530 outputs a second control signal Vc2.

[0088] The counter 510 is used to count and calibrate the number of cycles of the local oscillator clock signal F_target within a certain time according to the reference clock signal F_ref and the local oscillator clock signal F_target, and obtain a calibrated count result counter, so as to equivalently obtain the frequency information of the current local oscillator clock signal F_target. The counter 510 outputs the count result counter to the comparator 520. The comparator 520 compares the count result counter with an expected target count value to obtain information about whether the frequency of the current local oscillator clock signal F_target is fast or slow. The comparator 520 outputs the comparison result to the frequency control module 530. The frequency control module 530 generates a second control signal Vc2 according to the comparison result of the comparator 520 to control the frequency of the local oscillator clock signal F_target to increase or decrease correspondingly, so as to realize the frequency adjustment of the local oscillator clock signal F_target, so that the frequency of the local oscillator clock signal F_target can match the target frequency, including being equal to the target frequency or reaching near the target frequency.

[0089] In some other embodiments, a processing module may also be added to the automatic frequency control system 150, or the comparator 520 in the automatic frequency control system 150 may be replaced with a processing module. This processing module (not shown) is used to calculate the difference between the count result counter of the counter 510 and the expected target count value according to the count result counter and the expected target count value (this difference is the equivalent frequency difference between the local oscillator clock signal F_target and the target clock signal), and the frequency control module 530 further generates a second control signal Vc2 according to this difference to adjust the local oscillator frequency of the local oscillator clock signal F_target.

[0090] Optionally, in some embodiments, the information output by the counter 510 to the comparator 520 and / or the processing module includes an initial count value counter_pre and an addition / subtraction indication signal. The comparator 520 and / or the processing module further obtains an accurate count result counter according to the initial count value counter_pre and the addition / subtraction indication signal. That is to say, in these embodiments, the process of obtaining the accurate count result counter according to the initial count value counter_pre and the addition / subtraction indication signal occurs outside the counter 510, such as inside the comparator 520 and / or the processing module.

[0091] In some other embodiments, the information output by the counter 510 to the comparator 520 and / or the processing module is directly the count result counter. That is to say, in these embodiments, the process of obtaining the accurate count result counter according to the initial count value counter_pre and the addition / subtraction indication signal occurs inside the counter 510.

[0092] It should be noted that the process of obtaining the accurate count result counter according to the initial count value counter_pre and the addition / subtraction indication signal can be implemented by setting up devices / units such as addition / subtraction counters that can perform addition and subtraction on count values, or by selecting counters with the function of processing addition and subtraction of count values, or the comparator 520 and / or the processing module. This application does not make strict restrictions on this.

[0093] Further, continue to refer to Figure 5, in the embodiments of the present application, the counter 510 specifically includes: a sampling window generation module 511, a counting module 512, and an edge detector 513. Among them, the input end of the sampling window generation module 511 receives the reference clock signal F_ref, the output end of the sampling window generation module 511 is connected to the first input end of the counting module 512, the second input end of the sampling window generation module 511 receives the local oscillator clock signal F_target, the output end of the sampling window generation module 511 outputs an initial count value counter_pre, and the input ends of the edge detector 513 respectively receive the reference clock signal F_ref and the local oscillator clock signal F_target, and the output end of the edge detector 513 outputs an addition and subtraction indication signal.

[0094] The sampling window generation module 511 is used to generate a sampling window signal window according to the reference clock signal F_ref and output the sampling window signal window to the counting module 512. The counting module 512 is used to count the number of cycles of the local oscillator clock signal F_target within the valid period of the sampling window signal window (such as during the high level period) to obtain an initial count value counter_pre. The edge detector 513 is used to detect the clock edges of the reference clock signal F_ref and the local oscillator clock signal F_target and obtain an addition and subtraction indication signal according to the detected edge information. In this embodiment, the counter 510 calibrates the initial count value counter_pre according to the addition and subtraction indication signal to obtain an accurate counting result counter.

[0095] The period of the sampling window signal window is an integer multiple of the period of the reference clock signal F_ref. In other words, the sampling window signal window is a frequency division signal of the reference clock signal F_ref, and the frequency division ratio is an integer greater than 1.

[0096] The counting module 512 mainly counts the number of cycles of the local oscillator clock signal F_target within the valid period (such as during the high level period) of the sampling window signal window. It should be noted that the statement that the valid period is the high level period in this article is only an exemplary expression. In practical applications, the valid period or valid state of each signal may refer to the high level state of the signal, or it may refer to the low level state of the signal. Correspondingly, the invalid period or invalid state of each signal is the opposite state, and the valid period or valid state of different signals may be the same or different, and can be specifically selected according to the actual situation.

[0097] In this embodiment, when the addition / subtraction indication signal is in the first logic state, the counter 510 adds x to the initial count value counter_pre to obtain the count result counter; when the addition / subtraction indication signal is in the second logic state, the counter 510 subtracts x from the initial count value counter_pre to obtain the count result counter; when the addition / subtraction indication signal is in the third logic state, the counter 510 uses the initial count value counter_pre as the count result counter. In some preferred embodiments, x is 1. Of course, in some other embodiments, x can also be other values.

[0098] In some embodiments, the edge detector 513 detects the number of rising edges and falling edges of the local oscillator clock signal F_target within the valid period of the sampling window signal window, and generates an addition / subtraction indication signal according to the detected number of rising edges and falling edges.

[0099] In these embodiments, the edge detector 513 includes, for example, a first counting unit (not shown), a second counting unit (not shown), and a comparison unit (not shown). Among them, the first counting unit increments the count value by 1 each time it detects a rising edge of the local oscillator clock signal F_target within the valid period of the sampling window signal window to sample the number of rising edges of the local oscillator clock signal F_target; the second counting unit increments the count value by 1 each time it detects a falling edge of the local oscillator clock signal F_target within the valid period of the sampling window signal window to sample the number of falling edges of the local oscillator clock signal F_target; the comparison unit is used to compare the counted number of rising edges and the number of falling edges detected, and generate an addition / subtraction indication signal according to the comparison result. Optionally, in some embodiments, one of the first counting unit and the second counting unit can be served by the counting module 512, or rather, the edge detector 513 can obtain the number of rising edges or falling edges of the local oscillator clock signal F_target by receiving the initial count value counter_pre of the counting module 512.

[0100] Specifically, when the counting module 512 is configured to count the number of cycles of the local oscillator clock signal F_target by detecting the rising edges of the local oscillator clock signal F_target within the valid period of the sampling window signal window:

[0101] When the edge detector 513 detects that the number of rising edges of the local oscillator clock signal F_target is less than the number of falling edges, such as Figure 7As shown, an addition / subtraction indication signal with a first logic state is output to indicate that 1 needs to be added to the initial count value counter_pre output by the counting module 512 as the final count result counter; when the edge detector 513 detects that the number of rising edges of the local oscillator clock signal F_target is greater than the number of falling edges, as Figure 8 shown, an addition / subtraction indication signal with a second logic state is output to indicate that 1 needs to be subtracted from the initial count value counter_pre output by the counting module 512 as the final count result counter; when the edge detector 513 detects that the number of rising edges of the local oscillator clock signal F_target is equal to the number of falling edges, as Figure 9 shown, an addition / subtraction indication signal with a third logic state is output to indicate that the initial count value counter_pre output by the counting module 512 can be directly used as the final count result counter.

[0102] During the valid period of the sampling window signal window, when the counting module 512 is configured to count the number of cycles of the local oscillator clock signal F_target by detecting the falling edges of the local oscillator clock signal F_target:

[0103] When the edge detector 513 detects that the number of rising edges of the local oscillator clock signal F_target is greater than the number of falling edges, as Figure 7 shown, an addition / subtraction indication signal with a first logic state is output to indicate that 1 needs to be added to the initial count value counter_pre output by the counting module 512 as the final count result counter; when the edge detector 513 detects that the number of rising edges of the local oscillator clock signal F_target is less than the number of falling edges, as Figure 8 shown, an addition / subtraction indication signal with a second logic state is output to indicate that 1 needs to be subtracted from the initial count value counter_pre output by the counting module 512 as the final count result counter; when the edge detector 513 detects that the number of rising edges of the local oscillator clock signal F_target is equal to the number of falling edges, as Figure 9 shown, an addition / subtraction indication signal with a third logic state is output to indicate that the initial count value counter_pre output by the counting module 512 can be directly used as the final count result counter.

[0104] In some other embodiments, the edge detector 513 is used to detect the positional relationship between the transition edge of the sampling window signal window and the high and low levels of the local oscillator clock signal F_target, and generate an addition / subtraction indication signal according to the detected positional relationship.

[0105] In these embodiments, the addition and subtraction indication signals output by the edge detector 513 include, for example, a first indication signal plus and a second indication signal minus. Among them, when the first indication signal plus is logic 1 and the second indication signal minus is logic 0, the addition and subtraction indication signal exhibits a first logic state; when the first indication signal plus is logic 0 and the second indication signal minus is logic 1, the addition and subtraction indication signal minus exhibits a second logic state; when both the first indication signal plus and the second indication signal minus are logic 0 or both are logic 1, the addition and subtraction indication signal exhibits a third logic state.

[0106] Further, referring to Figure 6 , Figure 6 FIG. shows a schematic diagram of an embodiment of an edge detector provided by an embodiment of the present application. As Figure 6 shown, the edge detector 513 includes, for example, a D flip-flop 610, a D flip-flop 620, a D flip-flop 630, and a D flip-flop 640. It can be understood that a D flip-flop is an information storage device with a memory function and two stable states. The D flip-flop includes at least a data input terminal D, a clock input terminal clk, a positive-phase output terminal Q, and an inverted output terminal , and the level output by the positive-phase output terminal Q is always opposite to the level output by the inverted output terminal.

[0107] The data terminal D of the D flip-flop 610 receives the sampling window signal window, the clock terminal clk of the D flip-flop 610 receives the local oscillator clock signal F_target, and the in-phase output terminal Q of the D flip-flop 610 outputs a first detection signal window_sample0; the data terminal D of the D flip-flop 620 receives the sampling window signal window, the clock terminal clk of the D flip-flop 620 receives the inverted signal of the local oscillator clock signal F_target, and the in-phase output terminal Q of the D flip-flop 620 outputs a second detection signal window_sample1; the data terminal D of the D flip-flop 630 receives the second detection signal window_sample1, the clock terminal clk of the D flip-flop 630 receives the first detection signal window_sample0, and the in-phase output terminal Q of the D flip-flop 630 outputs a first indication signal plus; the data terminal D of the D flip-flop 640 receives the inverted signal of the second detection signal , for example, the data terminal D of the D flip-flop 640 is connected to the inverted output terminal of the D flip-flop 620 , and the clock terminal clk of the D flip-flop 640 receives the inverted signal of the first detection signal , for example, the clock terminal clk of the D flip-flop 640 is connected to the inverted output terminal of the D flip-flop 610 Connected, the in-phase output terminal Q of the D flip-flop 640 outputs the second indication signal minus.

[0108] In specific implementation, within the valid period of the sampling window signal window, when the counting module 512 is configured to count the number of cycles of the local oscillator clock signal F_target by detecting the rising edge of the local oscillator clock signal F_target:

[0109] When the edge detector 513 detects that the first transition edge (such as the rising edge) of the sampling window signal window switching from the invalid state to the valid state is during the high level of the local oscillator clock signal F_target, and the second transition edge (such as the falling edge) of the sampling window signal window switching from the valid state to the invalid state is during the low level of the local oscillator clock signal F_target, as Figure 7 shown, outputs an addition and subtraction indication signal with a first logic state to indicate that it is necessary to add 1 to the initial count value counter_pre output by the counting module 512 as the final count result counter;

[0110] When the edge detector 513 detects that the first transition edge (such as the rising edge) of the sampling window signal window switching from the invalid state to the valid state is during the low level of the local oscillator clock signal F_target, and the second transition edge (such as the falling edge) of the sampling window signal window switching from the valid state to the invalid state is during the high level of the local oscillator clock signal F_target, as Figure 8 shown, outputs an addition and subtraction indication signal with a second logic state to indicate that it is necessary to subtract 1 from the initial count value counter_pre output by the counting module 512 as the final count result counter;

[0111] When the edge detector 513 detects that both the first transition edge (such as the rising edge) of the sampling window signal window switching from the invalid state to the valid state and the second transition edge (such as the falling edge) of the sampling window signal window switching from the valid state to the invalid state are during the high level or the low level of the local oscillator clock signal F_target, as Figure 9 shown, outputs an addition and subtraction indication signal with a third logic state to indicate that the initial count value counter_pre output by the counting module 512 can be directly used as the final count result counter.

[0112] In the valid period of the sampling window signal window, when the counting module 512 is configured to count the number of cycles of the local oscillator clock signal F_target by detecting the falling edge of the local oscillator clock signal F_target:

[0113] When the first edge transition (such as a rising edge) of the sampling window signal window from an invalid state to a valid state detected by the edge detector 513 is during the low level of the local oscillator clock signal F_target, and the second edge transition (such as a falling edge) of the sampling window signal window from a valid state to an invalid state is during the high level of the local oscillator clock signal F_target, as Figure 7 shown, an addition / subtraction indication signal with a first logic state is output to indicate that 1 needs to be added to the initial count value counter_pre output by the counting module 512 as the final count result counter;

[0114] When the first edge transition (such as a rising edge) of the sampling window signal window from an invalid state to a valid state detected by the edge detector 513 is during the high level of the local oscillator clock signal F_target, and the second edge transition (such as a falling edge) of the sampling window signal window from a valid state to an invalid state is during the low level of the local oscillator clock signal F_target, as Figure 8 shown, an addition / subtraction indication signal with a second logic state is output to indicate that 1 needs to be subtracted from the initial count value counter_pre output by the counting module 512 as the final count result counter;

[0115] When both the first edge transition (such as a rising edge) of the sampling window signal window from an invalid state to a valid state and the second edge transition (such as a falling edge) of the sampling window signal window from a valid state to an invalid state detected by the edge detector 513 are during the high level or the low level of the local oscillator clock signal F_target, as Figure 9 shown, an addition / subtraction indication signal with a third logic state is output to indicate that the initial count value counter_pre output by the counting module 512 can be directly used as the final count result counter.

[0116] In summary, in the embodiment of the present application, by adding an edge detector 513 in the counter 510 to detect the edge information of the sampling window signal window and the local oscillator clock signal F_target to be counted, it is possible to determine whether there is overcounting or undercounting in the counting of the number of cycles of the local oscillator clock signal F_target by the counting module 512 during the valid period of the sampling window signal window according to the detected edge information, and further generate a corresponding addition / subtraction indication signal to calibrate the initial count value counter_pre of the counting module 512, so as to obtain a higher-precision count result, effectively improving the counting accuracy of the counter 510 and having a small hardware overhead.

[0117] Furthermore, through the high-precision counting of the counter, the accuracy of frequency control can be guaranteed, thereby reducing the locking time of the phase-locked loop and improving the stability of the phase-locked loop circuit.

[0118] Furthermore, an embodiment of the present application also provides an automatic frequency control method for a phase-locked loop. This method can be used in the automatic frequency control system or phase-locked loop disclosed in any embodiment of the present application. Specifically, as Figure 10 shown, the automatic frequency control method includes the following steps:

[0119] In step 101, a sampling window signal is generated according to a reference clock signal, and the period of the sampling window signal is an integer multiple of the period of the reference clock signal.

[0120] In step 102, the number of periods of the local oscillator clock signal is counted according to the sampling window signal to obtain an initial count value.

[0121] In step 103, the clock edges of the reference clock signal and the local oscillator clock signal are detected, and an addition and subtraction indication signal is obtained according to the detected edge information.

[0122] Optionally, in some embodiments, this step specifically includes: detecting the number of rising edges and falling edges of the local oscillator clock signal within the valid period of the sampling window signal; obtaining the addition and subtraction indication signal according to the detected number of rising edges and falling edges.

[0123] In some other embodiments, this step specifically includes: detecting the positional relationship between the transition edge of the sampling window signal and the high and low levels of the local oscillator clock signal; obtaining the addition and subtraction indication signal according to the detected positional relationship.

[0124] In step 104, the initial count value is calibrated according to the addition and subtraction indication signal to obtain a count result.

[0125] This step specifically includes: when the addition and subtraction indication signal is in the first logic state, adding 1 to the initial count value to obtain the count result; when the addition and subtraction indication signal is in the second logic state, subtracting 1 from the initial count value to obtain the count result; when the addition and subtraction indication signal is in the third logic state, using the initial count value as the count result.

[0126] In step 105, the count result is compared with the expected count value, and a frequency adjustment signal is generated according to the comparison result. The frequency adjustment signal is used to adjust the frequency of the local oscillator clock signal.

[0127] Specifically in implementation, for the specific implementation and the beneficial effects that can be obtained for each step in the above-described automatic frequency control method of the phase-locked loop, reference can be made to the various embodiments of the automatic frequency control system or phase-locked loop disclosed above, which will not be elaborated here.

[0128] Finally, it should be noted that: Obviously, the above embodiments are merely examples given for clearly explaining the present application, rather than limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation manners here. And the obvious changes or modifications derived therefrom still fall within the protection scope of the present application.

Claims

1. A counter, comprising: A sampling window generation module that generates a sampling window signal according to a reference clock signal, and a period of the sampling window signal is an integer multiple of a period of the reference clock signal; A counting module that counts the number of periods of a local oscillator clock signal according to the sampling window signal to obtain an initial count value; An edge detector that detects clock edges of the reference clock signal and the local oscillator clock signal, and obtains an addition / subtraction indication signal according to detected edge information; The counter calibrates the initial count value according to the addition / subtraction indication signal to obtain a counting result.

2. The counter according to claim 1, wherein, When the addition / subtraction indication signal is in a first logic state, the counter adds 1 to the initial count value to obtain the counting result; When the addition / subtraction indication signal is in a second logic state, the counter subtracts 1 from the initial count value to obtain the counting result; When the addition / subtraction indication signal is in a third logic state, the counter uses the initial count value as the counting result.

3. The counter according to claim 2, wherein, The edge detector detects the number of rising edges and the number of falling edges of the local oscillator clock signal within a valid period of the sampling window signal, and generates the addition / subtraction indication signal according to the number of rising edges and the number of falling edges.

4. The counter according to claim 3, wherein, Within the valid period of the sampling window signal, the counting module counts the number of periods of the local oscillator clock signal by detecting rising edges of the local oscillator clock signal; When it is detected that the number of rising edges is less than the number of falling edges, the edge detector outputs the addition / subtraction indication signal having the first logic state; When it is detected that the number of rising edges is greater than the number of falling edges, the edge detector outputs the addition / subtraction indication signal having the second logic state; When it is detected that the number of rising edges is equal to the number of falling edges, the edge detector outputs the addition / subtraction indication signal having the third logic state.

5. The counter according to claim 3, wherein, Within the valid period of the sampling window signal, the counting module counts the number of periods of the local oscillator clock signal by detecting falling edges of the local oscillator clock signal; When it is detected that the number of rising edges is greater than the number of falling edges, the edge detector outputs the addition / subtraction indication signal having the first logic state; When it is detected that the number of rising edges is less than the number of falling edges, the edge detector outputs the addition / subtraction indication signal having the second logic state; When it is detected that the number of rising edges is equal to the number of falling edges, the edge detector outputs the addition / subtraction indication signal having the third logic state.

6. The counter according to claim 2, wherein, The edge detector detects a position relationship between a transition edge of the sampling window signal and high / low levels of the local oscillator clock signal, and generates the addition / subtraction indication signal according to the position relationship.

7. The counter according to claim 6, wherein, Within the valid period of the sampling window signal, the counting module counts the number of periods of the local oscillator clock signal by detecting rising edges of the local oscillator clock signal; When the first transition edge where the sampled window signal switches from the invalid state to the valid state is during the high level of the local oscillator clock signal, and the second transition edge where the sampled window signal switches from the valid state to the invalid state is during the low level of the local oscillator clock signal, the edge detector outputs the addition / subtraction indication signal having a first logic state; When the first transition edge where the sampled window signal switches from the invalid state to the valid state is during the low level of the local oscillator clock signal, and the second transition edge where the sampled window signal switches from the valid state to the invalid state is during the high level of the local oscillator clock signal, the edge detector outputs the addition / subtraction indication signal having a second logic state; When both the first transition edge where the sampled window signal switches from the invalid state to the valid state and the second transition edge where the sampled window signal switches from the valid state to the invalid state are during the high level or the low level of the local oscillator clock signal, the edge detector outputs the addition / subtraction indication signal having a third logic state.

8. The counter according to claim 6, wherein, Within the valid period of the sampled window signal, the counting module counts the number of cycles of the local oscillator clock signal by detecting the falling edges of the local oscillator clock signal; When the first transition edge where the sampled window signal switches from the invalid state to the valid state is during the low level of the local oscillator clock signal, and the second transition edge where the sampled window signal switches from the valid state to the invalid state is during the high level of the local oscillator clock signal, the edge detector outputs the addition / subtraction indication signal having a first logic state; When the first transition edge where the sampled window signal switches from the invalid state to the valid state is during the high level of the local oscillator clock signal, and the second transition edge where the sampled window signal switches from the valid state to the invalid state is during the low level of the local oscillator clock signal, the edge detector outputs the addition / subtraction indication signal having a second logic state; When both the first transition edge where the sampled window signal switches from the invalid state to the valid state and the second transition edge where the sampled window signal switches from the valid state to the invalid state are during the high level or the low level of the local oscillator clock signal, the edge detector outputs the addition / subtraction indication signal having a third logic state.

9. The counter according to any one of claims 6-8, wherein, The addition / subtraction indication signal includes a first indication signal and a second indication signal; When the first indication signal is logic 1 and the second indication signal is logic 0, the addition / subtraction indication signal is in the first logic state; When the first indication signal is logic 0 and the second indication signal is logic 1, the addition / subtraction indication signal is in the second logic state; When both the first indication signal and the second indication signal are logic 0 or both are logic 1, the addition / subtraction indication signal is in the third logic state.

10. The counter according to claim 9, wherein, The edge detector includes: A first D flip-flop, with the data terminal receiving the sampled window signal, the clock terminal receiving the local oscillator clock signal, and the in-phase output terminal outputting a first detection signal; A second D flip-flop, with its data terminal receiving the sampling window signal, its clock terminal receiving the inverted signal of the local oscillator clock signal, and its in-phase output terminal outputting a second detection signal; A third D flip-flop, with its data terminal receiving the second detection signal, its clock terminal receiving the first detection signal, and its in-phase output terminal outputting a first indication signal; A fourth D flip-flop, with its data terminal receiving the inverted signal of the second detection signal, its clock terminal receiving the inverted signal of the first detection signal, and its in-phase output terminal outputting a second indication signal.

11. An automatic frequency control system, comprising: The counter according to any one of claims 1-10.

12. A phase-locked loop, comprising: The automatic frequency control system according to claim 11.

13. An automatic frequency control method for a phase-locked loop, comprising: Generating a sampling window signal according to a reference clock signal, wherein the period of the sampling window signal is an integer multiple of the period of the reference clock signal; Counting the number of periods of the local oscillator clock signal according to the sampling window signal to obtain an initial count value; Detecting the clock edges of the reference clock signal and the local oscillator clock signal, and obtaining an addition and subtraction indication signal according to the detected edge information; Calibrating the initial count value according to the addition and subtraction indication signal to obtain a count result; Comparing the count result with an expected count value, and generating a frequency adjustment signal according to the comparison result, wherein the frequency adjustment signal is used to adjust the frequency of the local oscillator clock signal.

14. The automatic frequency control method of the phase-locked loop according to claim 13, wherein, Calibrating the initial count value according to the addition and subtraction indication signal includes: When the addition and subtraction indication signal is in a first logic state, adding 1 to the initial count value to obtain the count result; When the addition and subtraction indication signal is in a second logic state, subtracting 1 from the initial count value to obtain the count result; When the addition and subtraction indication signal is in a third logic state, using the initial count value as the count result.

15. The automatic frequency control method of the phase-locked loop according to claim 14, wherein, Detecting the clock edges of the reference clock signal and the local oscillator clock signal, and obtaining an addition and subtraction indication signal according to the detected edge information, includes: Detecting the number of rising edges and the number of falling edges of the local oscillator clock signal within the valid period of the sampling window signal; Obtaining the addition and subtraction indication signal according to the number of rising edges and the number of falling edges.

16. The automatic frequency control method of the phase-locked loop according to claim 14, wherein, Detecting the clock edges of the reference clock signal and the local oscillator clock signal, and obtaining an addition and subtraction indication signal according to the detected edge information, includes: Detecting the position relationship between the transition edge of the sampling window signal and the high and low levels of the local oscillator clock signal; Obtaining the addition and subtraction indication signal according to the position relationship.

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