A calibration circuit and calibration method for a bridging capacitor array

Abstract

This invention relates to a calibration circuit and method for a bridging capacitor array, comprising a comparator, a P-terminal capacitor array, and an N-terminal capacitor array. The P-terminal capacitor array includes a high-segment capacitor array, a low-segment capacitor array, a bridging capacitor, and a calibration capacitor array. The high-segment capacitor array includes a capacitor to be calibrated. The first terminal of the bridging capacitor is connected to the first terminal of the capacitor to be calibrated, and the second terminal of the bridging capacitor is connected to the first terminal of a capacitor in the low-segment capacitor array. The second terminal of the capacitor to be calibrated is connected to a reference voltage, and the second terminal of the capacitor in the low-segment capacitor array is also connected to a reference voltage. The first terminal of the capacitor in the calibration capacitor array is connected to the first terminal of a capacitor in the low-segment capacitor array, and the second terminal of the capacitor in the calibration capacitor array is connected to a reference voltage or is in a high-impedance state. This invention improves the weighting error during capacitor potential transition caused by parasitic capacitance and process deviations in the bridging capacitor array.

Description

Technical Field

[0001] This invention relates to the field of successive approximation analog-to-digital converter technology, and particularly to a calibration circuit and calibration method for a bridge capacitor array. Background Technology

[0002] Analog-to-digital converters (ADCs) convert analog electrical signals into digital signals for easier processing and computation. Compared to other ADC structures, successive approximation analog-to-digital converters (SAR ADCs) offer superior speed and accuracy, making them increasingly popular among designers.

[0003] Bridged capacitor arrays are widely used in successive approximation analog-to-digital converters (ADCs). During the ADC conversion process, charge redistribution is achieved by switching the potentials of the capacitor plates, thereby changing the potential at the comparator input. The voltage change at the comparator input caused by the potential switching of adjacent bit capacitors needs to have a precise two-fold relationship. The linearity of this two-fold relationship determines the performance of the ADC. Due to parasitic capacitance and process variations, bridged capacitor arrays often require capacitor calibration to achieve a two-fold linearity during potential switching.

[0004] Typically, calibration involves reversing the weights of high-order capacitors and all low-order capacitors (those with fewer digits below them) to obtain their weight differences. These differences are then quantified and compensated for by a calibration circuit. However, the calibration range required for high-order capacitors increases due to errors in the bridging capacitors. For example, the lowest-order capacitor in a high-order capacitor array needs its weight calibrated to match the weights of the low-order capacitor array. Considering the weight deviation dw = dw1 + dw2, where dw1 represents the weight change caused by the mismatch of the lowest-order capacitor itself, and dw2 represents the deviation caused by non-ideal factors in the bridging capacitors and the low-order capacitor array, when calibrating the second-lowest-order capacitor in the high-order array, since its weight needs to be adjusted to twice that of the lowest-order capacitor, its dw, in addition to its own mismatch effect, also needs to be increased by 2*dw2. This increases the calibration range for subsequent high-order capacitors, and so on, with subsequent high-order capacitors requiring additional calibration weights of 4*dw2, 8*dw2, etc. Summary of the Invention

[0005] The purpose of this invention is to improve the weighting error during capacitor potential transition in a bridging capacitor array caused by parasitic capacitance and process variations, so that the weights of adjacent capacitors exhibit a precise two-fold linear relationship during potential transition. A calibration circuit and calibration method for a bridging capacitor array are provided.

[0006] To achieve the above-mentioned objectives, the embodiments of the present invention provide the following technical solutions:

[0007] A calibration circuit with a bridged capacitor array includes a comparator, a P-terminal capacitor array, and an N-terminal capacitor array. The P-terminal capacitor array and the N-terminal capacitor array are respectively connected to the first input terminal and the second input terminal of the comparator.

[0008] The P-end capacitor array includes a high-segment capacitor array, a low-segment capacitor array, a bridging capacitor, and a calibration capacitor array. The structure of the N-end capacitor array is the same as that of the P-end capacitor array.

[0009] The capacitors in the high-segment capacitor array include the capacitor to be calibrated, wherein the first end of the bridging capacitor is connected to the first end of the capacitor to be calibrated, and the second end of the bridging capacitor is connected to the first end of the capacitor in the low-segment capacitor array.

[0010] The second end of the capacitor to be calibrated is connected to the first reference voltage potential or the second reference voltage potential, and the second end of the capacitor in the low-segment capacitor array is connected to the first reference voltage potential or the second reference voltage potential;

[0011] The first terminal of the capacitor in the calibration capacitor array is connected to the first terminal of the capacitor in the low-segment capacitor array, and the second terminal of the capacitor in the calibration capacitor array is connected to the first reference voltage potential or the second reference voltage potential, or is in a high-resistance state.

[0012] Furthermore, the capacitor to be calibrated is the capacitor adjacent to the bridging capacitor in the high-segment capacitor array.

[0013] Furthermore, the P-terminal capacitor array also includes a fixed capacitor CT, the first end of which is connected to the first end of the capacitor in the low-segment capacitor array, and the second end of which is connected to ground potential.

[0014] Furthermore, the first terminal of the capacitor in the high-segment capacitor array is connected to the common-mode voltage VCM via a switch.

[0015] Furthermore, the first terminal of the capacitor in the calibration capacitor array is also connected to a first reference voltage potential or a second reference voltage potential, or is in a high-resistivity state.

[0016] A calibration method for a bridging capacitor array, wherein the calibration circuit using the method includes a comparator, a P-terminal capacitor array, and an N-terminal capacitor array, wherein the P-terminal capacitor array and the N-terminal capacitor array are respectively connected to the first input terminal and the second input terminal of the comparator, and includes the following steps:

[0017] Step 1: Convert the capacitor to be calibrated in the high-segment capacitor array of the P-end capacitor array from the first reference voltage potential to the second reference voltage potential, and convert the capacitor in the low-segment capacitor array of the P-end capacitor array from the second reference voltage potential to the first reference voltage potential. At this time, the capacitor to be calibrated in the P-end capacitor array generates a first voltage difference, and the capacitor in the low-segment capacitor array of the P-end capacitor array generates a second voltage difference.

[0018] Simultaneously, the capacitor to be calibrated in the high-segment capacitor array of the N-terminal capacitor array is converted from the second reference voltage potential to the first reference voltage potential, and the capacitor in the low-segment capacitor array of the N-terminal capacitor array is converted from the first reference voltage potential to the second reference voltage potential. At this time, the capacitor to be calibrated in the N-terminal capacitor array generates a third voltage difference, and the capacitor in the low-segment capacitor array of the N-terminal capacitor array generates a fourth voltage difference.

[0019] Step 2: Determine whether the sum of the absolute values ​​of the first voltage difference and the third voltage difference is equal to the sum of the absolute values ​​of the second voltage difference and the fourth voltage difference. If they are not equal, proceed to step 3.

[0020] Step 3: Adjust the charge provided by the calibration capacitor array at the low-segment capacitor array in the P-terminal capacitor array and N-terminal capacitor array, and repeat steps 1 and 2 to change the second voltage difference and the fourth voltage difference until the sum of the absolute values ​​of the first voltage difference and the third voltage difference is equal to the sum of the absolute values ​​of the second voltage difference and the fourth voltage difference.

[0021] Furthermore, a sampling step is included before performing step 1:

[0022] Connect the first terminal of the P-terminal capacitor array and the first terminal of the N-terminal capacitor array to the common-mode voltage VCM, so that the voltage V_P1 of the first terminal of the P-terminal capacitor array is VCM, and the voltage V_N1 of the first terminal of the N-terminal capacitor array is VCM.

[0023] Furthermore, step 2 specifically includes the following steps:

[0024] If the first reference voltage potential is less than the second reference voltage potential, then:

[0025] The first voltage difference |dv1| and the second voltage difference |dv2| generated in the P-terminal capacitor array cause the voltage change at the first terminal of the P-terminal capacitor array to be V_P1`=VCM+|dv1|-|dv2|.

[0026] The third voltage difference |dv3| and the fourth voltage difference |dv4| generated in the N-terminal capacitor array cause the voltage change at the first terminal of the N-terminal capacitor array to be V_N1`=VCM-|dv3|+|dv4|.

[0027] If the first reference voltage potential is greater than the second reference voltage potential, then:

[0028] The first voltage difference |dv1| and the second voltage difference |dv2| generated in the P-terminal capacitor array cause the voltage change at the first terminal of the P-terminal capacitor array to be V_P1`=VCM-|dv1|+|dv2|.

[0029] The third voltage difference |dv3| and the fourth voltage difference |dv4| generated in the N-terminal capacitor array cause the voltage change at the first terminal of the N-terminal capacitor array to be V_N1`=VCM+|dv3|-|dv4|.

[0030] The comparator is connected to the first terminal of the P-terminal capacitor array and the first terminal of the N-terminal capacitor array to calculate the magnitudes of V_P1` and V_N1`, thereby determining whether the sum of the absolute values ​​of the first voltage difference and the third voltage difference is equal to the sum of the absolute values ​​of the second voltage difference and the fourth voltage difference.

[0031] Furthermore, a pre-charging step is included before performing step 1:

[0032] The first terminal of the capacitor to be calibrated in the high-segment capacitor array, the first terminal of the capacitor in the low-segment capacitor array, and the first terminal of the capacitor in the calibration capacitor array are all connected to the second reference voltage potential. The second terminal of the capacitor to be calibrated in the high-segment capacitor array is connected to the first reference voltage potential. The second terminal of the capacitor in the low-segment capacitor array and the second terminal of the capacitor in the calibration capacitor array are connected to the second reference voltage potential.

[0033] The first terminal of the capacitor to be calibrated in the high-segment capacitor array of the N-terminal capacitor array, the first terminal of the capacitor in the low-segment capacitor array, and the first terminal of the capacitor in the calibration capacitor array are all connected to the first reference voltage potential. The second terminal of the capacitor to be calibrated in the high-segment capacitor array of the N-terminal capacitor array is connected to the second reference voltage potential. The second terminal of the capacitor in the low-segment capacitor array of the P-terminal capacitor array and the second terminal of the capacitor in the calibration capacitor array are connected to the first reference voltage potential.

[0034] Furthermore, before repeating step 1 in step 3, a pre-charging step is also included:

[0035] The first terminal of the capacitor to be calibrated in the high-segment capacitor array, the first terminal of the capacitor in the low-segment capacitor array, and the first terminal of the capacitor in the calibration capacitor array in the P-terminal capacitor array are all connected to the second reference voltage potential. The second terminal of the capacitor to be calibrated in the high-segment capacitor array in the P-terminal capacitor array is connected to the first reference voltage potential. The second terminal of the capacitor in the low-segment capacitor array in the P-terminal capacitor array is connected to the second reference voltage potential.

[0036] Control the second terminal of the capacitor in the calibration capacitor array of the P-terminal capacitor array that provides charge to the lower segment capacitor array, and connect it to the lower reference voltage potential of the first reference voltage potential and the second reference voltage potential; control the second terminal of the capacitor in the calibration capacitor array of the P-terminal capacitor array that does not provide charge to the lower segment capacitor array, and connect it to the second reference voltage potential.

[0037] The first terminal of the capacitor to be calibrated in the high-segment capacitor array, the first terminal of the capacitor in the low-segment capacitor array, and the first terminal of the capacitor in the calibration capacitor array in the N-terminal capacitor array are all connected to the first reference voltage potential. The second terminal of the capacitor to be calibrated in the high-segment capacitor array in the N-terminal capacitor array is connected to the second reference voltage potential. The second terminal of the capacitor in the low-segment capacitor array in the N-terminal capacitor array is connected to the first reference voltage potential.

[0038] Control the second terminal of the capacitor in the calibration capacitor array of the N-terminal capacitor array that provides charge to the lower segment capacitor array, and connect it to the lower reference voltage potential of the first reference voltage potential and the second reference voltage potential; control the second terminal of the capacitor in the calibration capacitor array of the N-terminal capacitor array that does not provide charge to the lower segment capacitor array, and connect it to the first reference voltage potential.

[0039] Furthermore, the calibration circuit using the method further includes a fixed capacitor CT, the first terminal of which is connected to the first terminal of a capacitor in the low-segment capacitor array, and the second terminal of which is connected to ground potential. The characteristic feature is that, before step 1, the method further includes the following step:

[0040] Based on the capacitance values ​​of the bridging capacitor and its parasitic capacitance, the capacitance value of the fixed capacitor CT is determined such that the calibration evaluation value D is greater than or equal to 1 when the calibration capacitor array does not provide charge to the lower-segment capacitor array. The calibration evaluation value D is:

[0041]

[0042] Where Cs represents the capacitance of the bridging capacitor, Cs_par represents the capacitance of the parasitic capacitance of the bridging capacitor, and C N+1 This indicates the capacitance value of the capacitor to be calibrated in the high-segment capacitor array;

[0043]

[0044] Among them, C total_P2_conv This represents the total capacitance value of the capacitors in the low-segment capacitor array;

[0045]

[0046] Where Cpar represents the parasitic capacitance of the fixed capacitor, CT represents the capacitance of the fixed capacitor, and Ctrim represents the capacitance of the capacitor that provides charge in the calibration capacitor array.

[0047] Furthermore, in step 3, when adjusting the charge provided by the calibration capacitor array at the lower segment capacitor array in the P-end capacitor array and N-end capacitor array, the input capacitance value of the calibration capacitor is increased successively, or the input capacitance value of the calibration capacitor array is adjusted by using the dichotomy method.

[0048] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0049] (1) The present invention adjusts the total weight of the low segment array by adjusting the total capacitance value at the low segment array, so that the weight of the high segment capacitor array is equal to the total weight of the low segment potential array, avoiding weight adjustment on the lowest capacitor of the high segment capacitor array, thereby avoiding the need to make a multiple weight adjustment on the deviation of the total weight of the low segment capacitor array for all capacitors in the high segment capacitor array.

[0050] (2) The present invention calibrates the linearity of the lowest capacitor in the low-segment capacitor array and the high-segment capacitor array by adjusting the bridging capacitor, parasitic capacitor and the total capacitance of the low-segment capacitor array, thereby reducing the calibration range of all capacitors in the high-segment capacitor array and thus reducing the area of ​​the calibration circuit of the high-segment capacitor array. Attached Figure Description

[0051] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a schematic diagram of the structure of the P-terminal capacitor array according to an embodiment of the present invention;

[0053] Figure 2 This is a circuit diagram of the sampling and pre-charging steps in an embodiment of the present invention when the calibration capacitor array is not connected.

[0054] Figure 3 This is a circuit diagram showing the pre-charging step at the end of an embodiment of the present invention when the calibration capacitor array is not connected.

[0055] Figure 4 This is a circuit schematic diagram of the conversion stage in an embodiment of the present invention when the calibration capacitor array is not connected;

[0056] Figure 5This is a circuit diagram of the sampling and pre-charging steps when capacitor Cu3 is connected in an embodiment of the present invention.

[0057] Figure 6 This is a circuit diagram showing the pre-charging step at the end of the process when capacitor Cu3 is connected in an embodiment of the present invention.

[0058] Figure 7 This is a circuit diagram of the conversion stage when capacitor Cu3 is connected in an embodiment of the present invention. Detailed Implementation

[0059] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0060] It should be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, the terms "first," "second," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance, or suggesting any such actual relationship or order between these entities or operations.

[0061] This invention is achieved through the following technical solution: a calibration circuit for a bridging capacitor array, such as... Figure 2 As shown, the system includes a comparator, a P-terminal capacitor array, and an N-terminal capacitor array. In one embodiment, the P-terminal capacitor array and the N-terminal capacitor array have the same structure, and the P-terminal capacitor array is connected to the first input terminal of the comparator, while the N-terminal capacitor array is connected to the second input terminal of the comparator. It is readily understood that when the first input terminal of the comparator is a positive input terminal, the second input terminal is an inverting input terminal; or when the first input terminal of the comparator is an inverting input terminal, the first input terminal is a positive input terminal.

[0062] Please see Figure 1 Taking the structure of the P-terminal capacitor array as an example, the P-terminal capacitor array has a first terminal P1 and a second terminal P2. The first terminal P1 is connected to the first input terminal of the comparator. Between the first terminal P1 and the second terminal P2, there are a high-segment capacitor array, a bridging capacitor, a low-segment capacitor array, and a calibration capacitor array. The high-segment capacitor array includes the capacitor to be calibrated.

[0063] In this configuration, the first terminal of the bridging capacitor is connected to the first terminal of the capacitor to be calibrated, and the first terminal of the bridging capacitor is also connected to the first terminal P1 of the P-terminal capacitor array. The second terminal of the bridging capacitor is connected to the first terminal of the capacitor in the low-segment capacitor array. The second terminal of the capacitor to be calibrated is connected to a first reference voltage potential or a second reference voltage potential, and the second terminal of the capacitor in the low-segment capacitor array is connected to either a first reference voltage potential or a second reference voltage potential. The first terminal of the capacitor in the calibration capacitor array is connected to the first terminal of the low-segment capacitor array, and the second terminal of the capacitor in the calibration capacitor array is connected to either a first reference voltage potential or a second reference voltage potential, or is in a high-resistance state.

[0064] As is easily understood, in one embodiment, the first reference voltage potential and the second reference voltage potential are not equal. If the first reference voltage potential is greater than the second reference voltage potential, then the first reference voltage potential is the positive terminal REFP of the reference voltage, and the second reference voltage potential is the negative terminal REFN of the reference voltage. If the first reference voltage potential is less than the second reference voltage potential, then the first reference voltage potential is the negative terminal REFN of the reference voltage, and the second reference voltage potential is the positive terminal REFP of the reference voltage.

[0065] Please continue reading Figure 1 The P-terminal capacitor array also includes a fixed capacitor CT. The first end of the fixed capacitor CT is connected to the first end of the capacitor in the low-segment capacitor array, and the second end of the fixed capacitor CT is connected to ground potential.

[0066] Due to the inherent parasitic capacitance of both the bridging capacitor and the fixed capacitor, the bridging capacitor Cs contains a first parasitic capacitance Cs_par, which is equivalent to being connected in parallel with the bridging capacitor Cs. The fixed capacitor CT contains a second parasitic capacitance Cpar, which is equivalent to having its first terminal connected to the first terminal of a capacitor in the low-level capacitor array, and its second terminal connected to ground potential.

[0067] The first terminal P1 of the P-terminal capacitor array is connected to the common-mode voltage VCM via a switch. Similarly, the N-terminal capacitor array also has a first terminal N1 and a second terminal N2. The first terminal N1 of the N-terminal capacitor array is connected to the common-mode voltage VCM via a switch. The remaining structure is the same as that of the P-terminal capacitor array, and will not be described in detail here.

[0068] Since this method allows for individual calibration of each capacitor in the high-segment capacitor array, and calibration begins sequentially from the lowest-ranking capacitor in the array, the capacitor to be calibrated in this embodiment is the capacitor adjacent to the bridging capacitor in the high-segment capacitor array. Please refer to [link to relevant documentation]. Figure 1 or Figure 2The capacitor to be calibrated is C6, which is the lowest capacitor in the high-segment capacitor array, and only the capacitor to be calibrated C6 is shown in each figure.

[0069] In this embodiment, please refer to Figure 1 or Figure 2 The capacitors in the low-segment capacitor array include C0R, C0, C1, C2, C3, C4, and C5, while the capacitors in the high-segment capacitor array include C6. Ideally, the capacitance value of the high-segment capacitor in the bridging capacitor array composed of the low-segment and high-segment capacitor arrays is twice the capacitance value of the adjacent low-segment capacitors. For example, 2C0=C1, 2C1=C2, 2C2=C3, 2C3=C4, and 2C4=C5. Capacitor C0R is also added to the low-segment capacitor array, and C0R=C0. Furthermore, the weight of all capacitors in the low-segment capacitor array is equal to the weight of the calibrated capacitor C6 in the high-segment capacitor array. This ensures that, ideally, the weight of the low-segment capacitor array is equal to the weight of the lowest-value capacitor C6 in the high-segment capacitor array.

[0070] In practice, as other implementations, the capacitance value of the higher-order capacitor can also be 3 times, 4 times, or so on, of the capacitance value of the adjacent lower-order capacitor, and is therefore not limited to a 2-fold relationship. Furthermore, the number of capacitors in the lower-order capacitor array is not limited to the 6 capacitors listed in this embodiment.

[0071] In practice, due to parasitic capacitance and process deviations, this calibration circuit sets the total weight of the capacitors in the uncalibrated low-segment capacitor array to be higher than the weight of the capacitor C6 being calibrated by connecting fixed capacitors, etc. Therefore, it is necessary to connect a calibration capacitor array at the low-segment capacitor array to calibrate the weight relationship, so that the total weight of the capacitors in the low-segment capacitor array plus the connected calibration capacitor array can approach the weight of the capacitor being calibrated.

[0072] When the low-segment capacitor array includes N+1 capacitors, the total capacitance of the low-segment capacitor array is:

[0073]

[0074] Where C0 = C0R, C total_P2_conv This indicates the total capacitance of the low-segment capacitor array.

[0075] The calibration capacitor array Ctrim includes at least one capacitor. If it contains multiple capacitors, the capacitance value of the higher-order capacitor is twice the capacitance value of the adjacent lower-order capacitor. Similarly, in practice, the capacitance value of the higher-order capacitor in the calibration capacitor array can also be three times, four times, or so on, the capacitance value of the adjacent lower-order capacitor.

[0076] For example, if the capacitance value of the higher-order capacitors in the calibration capacitor array is twice the capacitance value of the adjacent lower-order capacitors, the calibration capacitor array Ctrim selectively connects 4Cu3 / 2Cu3 / Cu3 capacitors. The corresponding calibration bit has 3 bits. If the trim code is 110, it means that 4Cu3 and 2Cu3 capacitors are connected, while Cu3 is not connected, and Ctrim = 6Cu3. However, the actual number of capacitors connected in Ctrim needs to be determined in subsequent calibration steps.

[0077] The second terminal of the capacitor in the calibration capacitor array is equipped with two switches. The first switch is connected to the positive terminal REFP of the reference voltage, and the second switch is connected to the negative terminal REFN of the reference voltage. When both switches are open, the capacitor is in a high-resistance state.

[0078] In one embodiment, the switches connecting the capacitors in the calibration capacitor array are implemented using PMOS transistors or NMOS transistors. Furthermore, the switch connected to the positive terminal REFP of the reference voltage is implemented using a PMOS transistor, and the switch connected to the negative terminal REFN of the reference voltage is implemented using an NMOS transistor.

[0079] In the subsequent pre-charging step, the voltages at terminals P2, A1P, A2P, and A3P are less than the positive terminal REFP of the reference voltage but greater than the negative terminal REFN. This ensures that the PMOS and NMOS transistors at terminals A1P, A2P, and A3P are free from parasitic diode leakage; the same applies to the N-side. Because the high-resistivity capacitors not connected in the calibration capacitor array are also pre-charged during the sampling phase in the subsequent conversion stage, if the high-resistivity voltage is higher than the positive terminal REFP of the reference voltage, it will cause parasitic diode leakage in the PMOS transistor; if the high-resistivity voltage is lower than the negative terminal REFN of the reference voltage, it will also cause parasitic diode leakage in the NMOS transistor. Therefore, a high-resistivity voltage less than the positive terminal REFP and greater than the negative terminal REFN of the reference voltage prevents the high-resistivity voltage from remaining unchanged during calibration and normal conversion, thus ensuring that the voltages at points P1 and N1 are not affected by parasitic diode leakage, and guaranteeing that the calibration and normal conversion processes are unaffected.

[0080] Based on the above calibration circuit, this solution also proposes a calibration method for a bridge capacitor array. As one possible implementation, it is assumed that the first reference voltage potential is less than the second reference voltage potential, i.e., the first reference voltage potential is the negative terminal REFN of the reference voltage, and the second reference voltage potential is the positive terminal REFP of the reference voltage. The calibration method includes the following steps:

[0081] For steps 0-1, please refer to [link / reference]. Figure 2 Sampling steps: Connect the first terminal P1 of the P-terminal capacitor array and the first terminal N1 of the N-terminal capacitor array to the common-mode voltage VCM through switches respectively.

[0082] Please continue reading Figure 2 Pre-charging steps: Connect the first terminal of the capacitor C6 to be calibrated in the high-segment capacitor array of the P-terminal capacitor array, the first terminal of the capacitors C5 to C0R in the low-segment capacitor array, and the first terminal of the capacitors in the calibration capacitor array Ctrim to the positive terminal REFP of the reference voltage; connect the second terminal of the capacitor C6 to be calibrated in the high-segment capacitor array of the P-terminal capacitor array to the negative terminal REFN of the reference voltage; connect the second terminal of the capacitors C5 to C0R in the low-segment capacitor array of the P-terminal capacitor array, and the second terminal of the capacitors in the calibration capacitor array Ctrim to the positive terminal REFP of the reference voltage.

[0083] The first terminal of the capacitor C6 to be calibrated in the high-segment capacitor array of the N-terminal capacitor array, the first terminal of the capacitors C5 to C0R in the low-segment capacitor array, and the first terminal of the capacitor in the calibration capacitor array Ctrim are all connected to the negative terminal of the reference voltage REFN. The second terminal of the capacitor C6 to be calibrated in the high-segment capacitor array of the N-terminal capacitor array is connected to the positive terminal of the reference voltage REFP. The second terminal of the capacitors C5 to C0R in the low-segment capacitor array of the P-terminal capacitor array and the second terminal of the capacitor in the calibration capacitor array Ctrim are connected to the negative terminal of the reference voltage REFN.

[0084] The sampling step and the pre-charging step described above can be performed simultaneously, but the pre-charging step must be completed before the sampling step ends.

[0085] For steps 0-2, please refer to [link / reference]. Figure 3 Sampling continues, pre-charging ends: the first terminal of the capacitor to be calibrated C6 in the high-segment capacitor array of the P-terminal capacitor array, the first terminal of the capacitors C5 to C0R in the low-segment capacitor array, and the first terminal of the capacitor in the calibration capacitor array Ctrim are all disconnected from the positive terminal of the reference voltage REFP. The second terminal of the capacitor in the calibration capacitor array Ctrim of the P-terminal capacitor array is disconnected from the positive terminal of the reference voltage REFP.

[0086] The first terminal of the capacitor to be calibrated C6 in the high-segment capacitor array of the N-terminal capacitor array, the first terminal of the capacitors C5 to C0R in the low-segment capacitor array, and the first terminal of the capacitor in the calibration capacitor array Ctrim are all disconnected from the negative terminal of the reference voltage REFN. The second terminal of the capacitor in the calibration capacitor array Ctrim of the N-terminal capacitor array is also disconnected from the negative terminal of the reference voltage REFN.

[0087] Since this is the first calibration process for the capacitor C6 to be calibrated, all capacitors in the calibration capacitor array Ctrim are controlled to be in a high-resistance state, indicating that no capacitors in the calibration capacitor array Ctrim are connected. The purpose is to determine the weight relationship between the high-segment capacitor array and the low-segment capacitor array in the uncalibrated state.

[0088] Step 1, please refer to Figure 4 Sampling ends, conversion stage: After pre-charging, sampling ends. The first terminal P1 of the P-terminal capacitor array and the first terminal N1 of the N-terminal capacitor array are disconnected from the common-mode voltage VCM by switches. At this time, the voltage V_P1 of the first terminal P1 of the P-terminal capacitor array is equal to VCM, and the voltage V_N1 of the first terminal N1 of the N-terminal capacitor array is equal to VCM.

[0089] When the capacitor C6 in the high-segment capacitor array of the P-terminal capacitor array is switched from the negative reference voltage terminal REFN to the positive reference voltage terminal REFP, and the capacitors C5 to C0R in the low-segment capacitor array of the P-terminal capacitor array are switched from the positive reference voltage terminal REFP to the negative reference voltage terminal REFN, the capacitor C6 in the P-terminal capacitor array will generate a first voltage difference dv1 at the first terminal P1, which will raise the voltage at the first terminal P1. The capacitors C5 to C0R in the low-segment capacitor array of the P-terminal capacitor array will generate a second voltage difference dv2 at the first terminal P1, which will lower the voltage at the first terminal P1.

[0090] Simultaneously, the capacitor C6 to be calibrated in the high-segment capacitor array of the N-terminal capacitor array is switched from the positive reference voltage terminal REFP to the negative reference voltage terminal REFN, and the capacitors C5 to C0R in the low-segment capacitor array of the N-terminal capacitor array are switched from the negative reference voltage terminal REFN to the positive reference voltage terminal REFP. At this time, the capacitor C6 to be calibrated in the N-terminal capacitor array will generate a third voltage difference dv3 at the first terminal N1, which will reduce the voltage at the first terminal P1. The capacitors C5 to C0R in the low-segment capacitor array of the N-terminal capacitor array will generate a fourth voltage difference dv4 at the first terminal N1, which will increase the voltage at the first terminal P1.

[0091] Step 2: Determine whether the sum of the absolute values ​​of the first voltage difference and the third voltage difference is equal to the sum of the absolute values ​​of the second voltage difference and the fourth voltage difference. If they are not equal, proceed to step 3.

[0092] Due to the weighting error during capacitor potential transition caused by parasitic capacitance and process variations, when the bridging capacitor array Ctrim is not connected, the sum of the absolute values ​​of the first voltage difference |dv1| and the third voltage difference |dv3| is not equal to the sum of the absolute values ​​of the second voltage difference |dv2| and the fourth voltage difference |dv4|, i.e., |dv1|+|dv3|≠|dv2|+|dv4|. The specific reason is as follows:

[0093] Please see Figure 1The calibration circuit also includes a fixed capacitor CT. The first terminal of the fixed capacitor CT is connected to the first terminal of capacitors C5 to C0R in the low-segment capacitor array, and the second terminal of the fixed capacitor CT is connected to ground potential. Before performing steps 0-1, the capacitance value of the fixed capacitor CT needs to be determined, therefore the following steps are also included:

[0094] Based on the capacitance values ​​of the bridging capacitor Cs and its parasitic capacitance Cs_par, the capacitance value of the fixed capacitor CT is determined such that the calibration evaluation value D is greater than or equal to 1 when the calibration capacitor array Ctrim does not provide charge to the lower segment capacitor array. In other words, the weight of capacitors C5 to C0R in the lower segment capacitor array is greater than the weight of the capacitor C6 to be calibrated. The calibration evaluation value D is:

[0095]

[0096] Where Cs represents the capacitance of the bridging capacitor, Cs_par represents the capacitance of the parasitic capacitance of the bridging capacitor, and C N+1 This indicates the capacitance value of the capacitor to be calibrated in the high-segment capacitor array;

[0097]

[0098] Among them, C total_P2_conv This represents the total capacitance value of the capacitors in the low-segment capacitor array;

[0099]

[0100] Where Cpar represents the parasitic capacitance of the fixed capacitor, CT represents the capacitance of the fixed capacitor, and Ctrim represents the capacitance of the capacitor that provides charge in the calibration capacitor array.

[0101] Before the potential conversion between the capacitor to be calibrated and the low-segment capacitor array, the voltage at the first terminal P1 of the P-end capacitor array is VCM. After the potential conversion, the first voltage difference generated by the capacitor to be calibrated at the first terminal P1 is |dv1|, and the second voltage difference generated by the low-segment capacitor array at the first terminal P1 is |dv2|. Since the first voltage difference dv1 is positive, it raises the voltage VCM at the first terminal P1, and the second voltage difference dv2 is negative, it lowers the voltage VCM at the first terminal P1. Therefore, the voltage change at the first terminal P1 is V_P1`=VCM+|dv1|-|dv2|.

[0102] Similarly, before the potential conversion of the capacitor to be calibrated and the low-stage capacitor array, the voltage at the first end N1 of the N-terminal capacitor array is VCM. After the potential conversion, the third voltage difference generated by the capacitor to be calibrated at the first end N1 is |dv3|, and the fourth voltage difference generated by the low-stage capacitor array at the first end N1 is |dv4|. Also, since the third voltage difference dv3 is negative, it reduces the voltage VCM at the first end N1, and the second voltage difference dv4 is positive, which raises the voltage VCM at the first end N1. Therefore, the voltage change at the first end N1 is V_N1` = VCM - |dv3| + |dv4|.

[0103] In an ideal state, the sum of the voltage differences generated after the potential conversion of the capacitor to be calibrated in the high-stage capacitor array of the P-terminal capacitor array and the voltage differences generated after the potential conversion of the capacitor to be calibrated in the high-stage capacitor array of the N-terminal capacitor array should be equal to the sum of the voltage differences generated after the potential conversion of the capacitors in the low-stage capacitor array of the P-terminal capacitor array and the voltage differences generated after the potential conversion of the capacitors in the low-stage capacitor array of the N-terminal capacitor array. This ideal state is called the weights of the high-stage capacitor array and the low-stage capacitor array being equal.

[0104] In one embodiment, when determining whether the weights are equal, refer to Figure 4 , the inverting input terminal of the comparator is connected to the first end P1 of the P-terminal capacitor array, and the non-inverting input terminal of the comparator is connected to the first end N1 of the N-terminal capacitor array. After the comparator amplifies the values of V_P1` and V_N1`, the values output through the output terminals VOP and VON can be used to calculate the magnitudes of V_P1` and V_N1`, thereby determining whether the sum of the absolute values of the first voltage difference and the third voltage difference is equal to the sum of the absolute values of the second voltage difference and the fourth voltage difference.

[0105] V_P1` - V_N1` = (|dv1| - |dv2|) - (|dv4| - |dv3|) = (|dv1| + |dv3|) - (|dv2| + |dv4|)

[0106] Among them, |dv1| + |dv3| is the total weight of the capacitor to be calibrated C6 in the P-terminal capacitor array and the N-terminal capacitor array, and |dv4| + |dv2| is the total weight of the capacitors C5~C0R in the P-terminal capacitor array and the N-terminal capacitor array.

[0107] When V_P1` - V_N1` > 0, it indicates that the weight of capacitor C6 is greater than the weights of capacitors C5~C0R. At this time, the inverting input terminal P1 of the comparator > the non-inverting input terminal N1, and it will be observed that VOP < VON. When V_P1` - V_N1` < 0, it indicates that the weight of capacitor C6 is less than the weights of capacitors C5~C0R. At this time, the inverting input terminal P1 of the comparator < the non-inverting input terminal N1, and it will be observed that VOP > VON.

[0108] Step 3: Adjust the charge provided by the calibration capacitor array at the low-segment capacitor array in the P-terminal capacitor array and N-terminal capacitor array, and repeat steps 1 and 2 to change the second voltage difference and the fourth voltage difference until the sum of the absolute values ​​of the first voltage difference and the third voltage difference is equal to the sum of the absolute values ​​of the second voltage difference and the fourth voltage difference.

[0109] After concluding in step 2 that V_P1` and V_N1` are not equal, step 2 begins the second and multiple calibration processes for the capacitor C6 to be calibrated. In each calibration process, the second voltage difference and the fourth voltage difference are changed by adjusting the charge provided by the calibration capacitor array at the lower segment capacitor array in the P-terminal capacitor array and the N-terminal capacitor array, so that V_P1` and V_N1` continuously approach each other, and the calibration evaluation value D continuously decreases.

[0110] In one embodiment, the charge provided by the calibration capacitor array at the lower segment capacitor array in the P-end capacitor array and N-end capacitor array is adjusted by successively increasing the input capacitance value of the capacitor in the calibration capacitor array, or by using the dichotomy method to adjust the input capacitance value of the capacitor in the calibration capacitor array.

[0111] In this embodiment, the method of successively increasing the capacitance value of the calibration capacitors is selected, that is, first connecting the lowest-order capacitor Cu3 in the calibration capacitor array. Each time a capacitor in the calibration capacitor array is connected, the sampling step and the pre-charging step need to be repeated, specifically:

[0112] Please see Figure 5 Sampling steps: Connect the first terminal P1 of the P-terminal capacitor array and the first terminal N1 of the N-terminal capacitor array to the common-mode voltage VCM through switches respectively.

[0113] Please continue reading Figure 5 Pre-charging steps: Connect the first terminal of the capacitor C6 to be calibrated in the high-segment capacitor array of the P-terminal capacitor array, the first terminal of the capacitors C5 to C0R in the low-segment capacitor array, and the first terminal of the capacitors in the calibration capacitor array Ctrim to the positive terminal REFP of the reference voltage; connect the second terminal of the capacitor C6 to be calibrated in the high-segment capacitor array of the P-terminal capacitor array to the negative terminal REFN of the reference voltage; and connect the second terminal of the capacitors C5 to C0R in the low-segment capacitor array of the P-terminal capacitor array to the positive terminal REFP of the reference voltage.

[0114] The second terminal of capacitor Cu3, which supplies charge to the lower segment capacitor array in the calibration capacitor array Ctrim of the P-terminal capacitor array, is connected to the lower reference voltage potential of the first and second reference voltage potentials, i.e., connected to the negative terminal REFN of the reference voltage; the second terminals of capacitors 2Cu3 and 4Cu3, which do not supply charge to the lower segment capacitor array in the calibration capacitor array Ctrim of the P-terminal capacitor array, are connected to the positive terminal REFP of the reference voltage.

[0115] The first terminal of the capacitor C6 to be calibrated in the high-segment capacitor array of the N-terminal capacitor array, the first terminal of the capacitors C5 to C0R in the low-segment capacitor array, and the first terminal of the capacitor in the calibration capacitor array Ctrim are all connected to the negative terminal of the reference voltage REFN. The second terminal of the capacitor C6 to be calibrated in the high-segment capacitor array of the N-terminal capacitor array is connected to the positive terminal of the reference voltage REFP. The second terminal of the capacitors C5 to C0R in the low-segment capacitor array of the N-terminal capacitor array is connected to the negative terminal of the reference voltage REFN.

[0116] The second terminal of capacitor Cu3, which supplies charge to the lower segment capacitor array in the calibration capacitor array Ctrim of the N-terminal capacitor array, is connected to the lower reference voltage potential of the first and second reference voltage potentials, i.e., connected to the negative reference voltage terminal REFN; the second terminals of capacitors 2Cu3 and 4Cu3, which do not supply charge to the lower segment capacitor array in the calibration capacitor array Ctrim of the N-terminal capacitor array, are connected to the negative reference voltage terminal REFN.

[0117] Please see Figure 6 Sampling continues, pre-charging ends: The first terminal of the capacitor to be calibrated C6 in the high-segment capacitor array of the P-terminal capacitor array, the first terminal of the capacitors C5 to C0R in the low-segment capacitor array, and the first terminal of the capacitors in the calibration capacitor array Ctrim are all disconnected from the positive terminal REFP of the reference voltage. The second terminal of the capacitors 2Cu3 and 4Cu3 in the calibration capacitor array Ctrim of the P-terminal capacitor array that do not provide charge to the low-segment capacitor array are disconnected from the positive terminal REFP of the reference voltage. The second terminal of the capacitor Cu3 in the calibration capacitor array Ctrim that provides charge to the low-segment capacitor array is kept connected to the negative terminal REFN of the reference voltage.

[0118] Disconnect the first terminal of the capacitor C6 to be calibrated in the high-segment capacitor array of the N-terminal capacitor array, the first terminal of the capacitors C5 to C0R in the low-segment capacitor array, and the first terminal of the capacitors in the calibration capacitor array Ctrim from the negative terminal of the reference voltage REFN. Disconnect the second terminal of the capacitors 2Cu3 and 4Cu3 in the calibration capacitor array Ctrim of the N-terminal capacitor array that do not provide charge to the low-segment capacitor array from the negative terminal of the reference voltage REFN. Keep the second terminal of the capacitor Cu3 in the calibration capacitor array Ctrim that provides charge to the low-segment capacitor array connected to the negative terminal of the reference voltage REFN.

[0119] Please see Figure 7 Sampling ends, conversion stage: After pre-charging, sampling ends. The first terminal P1 of the P-terminal capacitor array and the first terminal N1 of the N-terminal capacitor array are disconnected from the common-mode voltage VCM by switches. At this time, the voltage V_P1 of the first terminal P1 of the P-terminal capacitor array is equal to VCM, and the voltage V_N1 of the first terminal N1 of the N-terminal capacitor array is equal to VCM.

[0120] The capacitor C6 in the high-segment capacitor array of the P-terminal capacitor array is switched from the negative reference voltage terminal REFN to the positive reference voltage terminal REFP. The capacitors C5 to C0R in the low-segment capacitor array of the P-terminal capacitor array are switched from the positive reference voltage terminal REFP to the negative reference voltage terminal REFN. At this time, the capacitor C6 in the P-terminal capacitor array will generate a first voltage difference dv1 at the first terminal P1. Since the capacitor Cu3 is connected, the capacitors C5 to C0R and the capacitor Cu3 in the low-segment capacitor array of the P-terminal capacitor array will generate a second voltage difference dv5 at the first terminal P1.

[0121] Simultaneously, the capacitor C6 to be calibrated in the high-segment capacitor array of the N-terminal capacitor array is switched from the positive reference voltage terminal REFP to the negative reference voltage terminal REFN, and the capacitors C5 to C0R in the low-segment capacitor array of the N-terminal capacitor array are switched from the negative reference voltage terminal REFN to the positive reference voltage terminal REFP. At this time, the capacitor C6 to be calibrated in the N-terminal capacitor array will generate a third voltage difference dv3 at the first terminal N1. Since the capacitor Cu3 is connected, the capacitors C5 to C0R and the capacitor Cu3 in the low-segment capacitor array of the N-terminal capacitor array will generate a fourth voltage difference dv6 at the first terminal N1.

[0122] Next, determine whether the sum of the absolute values ​​of the first voltage difference and the third voltage difference is equal to the sum of the absolute values ​​of the second voltage difference and the fourth voltage difference, that is, determine whether |dv1|+|dv3| is equal to |dv5|+|dv6|.

[0123] If the values ​​are equal, the calibration is successful. If they are still unequal, continue connecting the calibration capacitor array Ctrim as described above until the sum of the absolute values ​​of the first and third voltage differences equals the sum of the absolute values ​​of the second and fourth voltage differences.

[0124] In a further refinement, the second terminal of the capacitor connected to the calibrating capacitor array Ctrim can be connected to the positive terminal of the reference voltage REFP, or any fixed voltage, during the pre-charging and conversion phases, as long as it ensures that the connected capacitor receives a continuous and stable voltage.

[0125] As another possible implementation, assuming that the first reference voltage potential is greater than the second reference voltage potential, that is, the first reference voltage potential is the positive terminal REFP of the reference voltage and the second reference voltage potential is the negative terminal REFN of the reference voltage, the calibration is still performed according to the above method.

[0126] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A calibration circuit for a bridged capacitor array, comprising a comparator, a P-terminal capacitor array, and an N-terminal capacitor array, wherein the P-terminal capacitor array and the N-terminal capacitor array are respectively connected to the first input terminal and the second input terminal of the comparator, characterized in that: The P-end capacitor array includes a high-segment capacitor array, a low-segment capacitor array, a bridging capacitor, and a calibration capacitor array. The structure of the N-end capacitor array is the same as that of the P-end capacitor array. The capacitors in the high-segment capacitor array include the capacitor to be calibrated, wherein the first end of the bridging capacitor is connected to the first end of the capacitor to be calibrated, and the second end of the bridging capacitor is connected to the first end of the capacitor in the low-segment capacitor array. The second end of the capacitor to be calibrated is connected to the first reference voltage potential or the second reference voltage potential, and the second end of the capacitor in the low-segment capacitor array is connected to the first reference voltage potential or the second reference voltage potential; The first terminal of the capacitor in the calibration capacitor array is connected to the first terminal of the capacitor in the low-segment capacitor array, and the second terminal of the capacitor in the calibration capacitor array is connected to the first reference voltage potential or the second reference voltage potential, or is in a high-resistance state.

2. The calibration circuit for a bridge capacitor array according to claim 1, characterized in that: The capacitor to be calibrated is the capacitor adjacent to the bridging capacitor in the high-segment capacitor array.

3. The calibration circuit for a bridge capacitor array according to claim 1, characterized in that: The P-terminal capacitor array also includes a fixed capacitor CT. The first end of the fixed capacitor CT is connected to the first end of the capacitor in the low-segment capacitor array, and the second end of the fixed capacitor CT is connected to ground potential.

4. The calibration circuit for a bridge capacitor array according to claim 1, characterized in that: The first terminal of the capacitor in the high-segment capacitor array is connected to the common-mode voltage VCM via a switch.

5. The calibration circuit for a bridge capacitor array according to claim 1, characterized in that: The first terminal of the capacitor in the calibration capacitor array is also connected to a first reference voltage potential or a second reference voltage potential, or is in a high-resistivity state.

6. A calibration method for a bridged capacitor array, wherein the calibration circuit using the method includes a comparator, a P-terminal capacitor array, and an N-terminal capacitor array, wherein the P-terminal capacitor array and the N-terminal capacitor array are respectively connected to the first input terminal and the second input terminal of the comparator, characterized in that: Includes the following steps: Step 1: Convert the capacitor to be calibrated in the high-segment capacitor array of the P-end capacitor array from the first reference voltage potential to the second reference voltage potential, and convert the capacitor in the low-segment capacitor array of the P-end capacitor array from the second reference voltage potential to the first reference voltage potential. At this time, the capacitor to be calibrated in the P-end capacitor array generates a first voltage difference, and the capacitor in the low-segment capacitor array of the P-end capacitor array generates a second voltage difference. Simultaneously, the capacitor to be calibrated in the high-segment capacitor array of the N-terminal capacitor array is converted from the second reference voltage potential to the first reference voltage potential, and the capacitor in the low-segment capacitor array of the N-terminal capacitor array is converted from the first reference voltage potential to the second reference voltage potential. At this time, the capacitor to be calibrated in the N-terminal capacitor array generates a third voltage difference, and the capacitor in the low-segment capacitor array of the N-terminal capacitor array generates a fourth voltage difference. Step 2: Determine whether the sum of the absolute values ​​of the first voltage difference and the third voltage difference is equal to the sum of the absolute values ​​of the second voltage difference and the fourth voltage difference. If they are not equal, proceed to step 3. Step 3: Adjust the charge provided by the calibration capacitor array at the low-segment capacitor array in the P-terminal capacitor array and N-terminal capacitor array, and repeat steps 1 and 2 to change the second voltage difference and the fourth voltage difference until the sum of the absolute values ​​of the first voltage difference and the third voltage difference is equal to the sum of the absolute values ​​of the second voltage difference and the fourth voltage difference.

7. The calibration method for a bridging capacitor array according to claim 6, characterized in that: Before performing step 1, a sampling step is also included: Connect the first terminal of the P-terminal capacitor array and the first terminal of the N-terminal capacitor array to the common-mode voltage VCM, so that the voltage V_P1 of the first terminal of the P-terminal capacitor array is VCM, and the voltage V_N1 of the first terminal of the N-terminal capacitor array is VCM.

8. The calibration method for a bridging capacitor array according to claim 7, characterized in that: Step 2 specifically includes the following steps: If the first reference voltage potential is less than the second reference voltage potential, then: The first voltage difference |dv1| and the second voltage difference |dv2| generated in the P-terminal capacitor array cause the voltage change at the first terminal of the P-terminal capacitor array to be V_P1`=VCM+|dv1|-|dv2|. The third voltage difference |dv3| and the fourth voltage difference |dv4| generated in the N-terminal capacitor array cause the voltage change at the first terminal of the N-terminal capacitor array to be V_N1`=VCM-|dv3|+|dv4|. If the first reference voltage potential is greater than the second reference voltage potential, then: The first voltage difference |dv1| and the second voltage difference |dv2| generated in the P-terminal capacitor array cause the voltage change at the first terminal of the P-terminal capacitor array to be V_P1`=VCM-|dv1|+|dv2|. The third voltage difference |dv3| and the fourth voltage difference |dv4| generated in the N-terminal capacitor array cause the voltage change at the first terminal of the N-terminal capacitor array to be V_N1`=VCM+|dv3|-|dv4|. The comparator is connected to the first terminal of the P-terminal capacitor array and the first terminal of the N-terminal capacitor array to calculate the magnitudes of V_P1` and V_N1`, thereby determining whether the sum of the absolute values ​​of the first voltage difference and the third voltage difference is equal to the sum of the absolute values ​​of the second voltage difference and the fourth voltage difference.

9. The calibration method for a bridging capacitor array according to claim 6, characterized in that: Before performing step 1, a pre-charging step is also included: The first terminal of the capacitor to be calibrated in the high-segment capacitor array, the first terminal of the capacitor in the low-segment capacitor array, and the first terminal of the capacitor in the calibration capacitor array are all connected to the second reference voltage potential. The second terminal of the capacitor to be calibrated in the high-segment capacitor array is connected to the first reference voltage potential. The second terminal of the capacitor in the low-segment capacitor array and the second terminal of the capacitor in the calibration capacitor array are connected to the second reference voltage potential. The first terminal of the capacitor to be calibrated in the high-segment capacitor array of the N-terminal capacitor array, the first terminal of the capacitor in the low-segment capacitor array, and the first terminal of the capacitor in the calibration capacitor array are all connected to the first reference voltage potential. The second terminal of the capacitor to be calibrated in the high-segment capacitor array of the N-terminal capacitor array is connected to the second reference voltage potential. The second terminal of the capacitor in the low-segment capacitor array of the P-terminal capacitor array and the second terminal of the capacitor in the calibration capacitor array are connected to the first reference voltage potential.

10. The calibration method for a bridging capacitor array according to claim 6, characterized in that: Before repeating step 1 in step 3, a pre-charging step is also included: The first terminal of the capacitor to be calibrated in the high-segment capacitor array, the first terminal of the capacitor in the low-segment capacitor array, and the first terminal of the capacitor in the calibration capacitor array in the P-terminal capacitor array are all connected to the second reference voltage potential. The second terminal of the capacitor to be calibrated in the high-segment capacitor array in the P-terminal capacitor array is connected to the first reference voltage potential. The second terminal of the capacitor in the low-segment capacitor array in the P-terminal capacitor array is connected to the second reference voltage potential. Control the second terminal of the capacitor in the calibration capacitor array of the P-terminal capacitor array that provides charge to the lower segment capacitor array, and connect it to the lower reference voltage potential of the first reference voltage potential and the second reference voltage potential; control the second terminal of the capacitor in the calibration capacitor array of the P-terminal capacitor array that does not provide charge to the lower segment capacitor array, and connect it to the second reference voltage potential. The first terminal of the capacitor to be calibrated in the high-segment capacitor array, the first terminal of the capacitor in the low-segment capacitor array, and the first terminal of the capacitor in the calibration capacitor array in the N-terminal capacitor array are all connected to the first reference voltage potential. The second terminal of the capacitor to be calibrated in the high-segment capacitor array in the N-terminal capacitor array is connected to the second reference voltage potential. The second terminal of the capacitor in the low-segment capacitor array in the N-terminal capacitor array is connected to the first reference voltage potential. The second terminal of the capacitor in the calibration capacitor array of the N-terminal capacitor array that provides charge to the low-segment capacitor array is connected to the lower reference voltage potential of the first reference voltage potential and the second reference voltage potential. The second terminal of the capacitor in the calibration capacitor array of the N-terminal capacitor array that does not provide charge to the lower segment capacitor array is connected to the first reference voltage potential.

11. The calibration method for a bridging capacitor array according to claim 6, wherein the calibration circuit using the method further includes a fixed capacitor CT, the first terminal of the fixed capacitor CT being connected to the first terminal of a capacitor in the low-segment capacitor array, and the second terminal of the fixed capacitor CT being connected to ground potential, characterized in that: Before step 1, the following steps are also included: Based on the capacitance values ​​of the bridging capacitor and its parasitic capacitance, the capacitance value of the fixed capacitor CT is determined such that the calibration evaluation value D is greater than or equal to 1 when the calibration capacitor array does not provide charge to the lower-segment capacitor array. The calibration evaluation value D is: Where Cs represents the capacitance of the bridging capacitor, Cs_par represents the capacitance of the parasitic capacitance of the bridging capacitor, and C N+1 This indicates the capacitance value of the capacitor to be calibrated in the high-segment capacitor array; Among them, C total_P2_conv This represents the total capacitance value of the capacitors in the low-segment capacitor array; Where Cpar represents the parasitic capacitance of the fixed capacitor, CT represents the capacitance of the fixed capacitor, and Ctrim represents the capacitance of the capacitor that provides charge in the calibration capacitor array.

12. The calibration method for a bridging capacitor array according to claim 6, characterized in that: In step 3, when adjusting the charge provided by the calibration capacitor array at the lower segment capacitor array in the P-end capacitor array and N-end capacitor array, the input capacitance value of the calibration capacitor is increased successively, or the input capacitance value of the calibration capacitor array is adjusted by using the dichotomy method.

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