Layout Graphic Edge Segmentation Method
By adopting the layout graphic edge segmentation method based on the OPC model in the lithography process, the spatial light intensity curve and extreme points are used for automatic segmentation, and the OPC parameters are optimized through the grid point search method, the edge segmentation deviation problem caused by the optical proximity effect in the lithography process is solved, and efficient and accurate OPC correction is achieved.
Patent Information
- Application Number
- CN202211390612.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-11-08
- Publication Date
- 2025-05-30
- Estimated Expiration
- 2042-11-08
AI Technical Summary
In the existing lithography process, due to the optical proximity effect, the projection of the layout pattern on the silicon wafer is deviated, and it is necessary to debug the OPC formula for effective edge segmentation through a large amount of time, and the OPC correction accuracy is insufficient.
Using the OPC model method, the spatial light intensity curve of the layout graph is extracted, the extreme value points are calculated, and the slicing segment is formed based on the extreme value points. The OPC model parameters are selected in combination with the grid point search method to realize automated edge slicing and OPC correction.
It reduces the time for engineers to debug OPC formulas, improves OPC correction accuracy, and ensures the stability and efficiency of edge segmentation of layout graphics.
Smart Images

Figure CN115629518B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly to a method for segmenting the edge of a layout pattern. Background Art
[0002] With the continuous development of wafer foundry process technology, the feature size on logic device nodes approaches or even is less than the wavelength of the light wave used in the lithography process. According to the principles of light wave diffraction and interference: when the light wave passes through the mask, diffraction will occur, and interference will also occur at different positions of the mask. Therefore, the actual light intensity distribution projected onto the silicon wafer is the result of the superposition of these diffracted and interfered light waves, which is not exactly the same as the mask pattern. This phenomenon that the lithography pattern deviates from the mask pattern due to light wave diffraction and interference is called the Optical Proximity Effect (OPE). In the lithography process, the optical proximity effect is inevitable. The existing method is to use Optical Proximity Correction (OPC) technology to minimize the deformation and deviation of the mask pattern projected onto the silicon wafer pattern as much as possible, so that the exposed pattern meets the design requirements.
[0003] OPC has always been the core technology in the process of manufacturing nanoscale wafers. With the continuous shrinking of logic device nodes, OPC technology also occupies a dominant position in advanced lithography processes. Currently, as a kind of Resolution Enhancement Techniques (RET), OPC technology is widely used in the process of manufacturing integrated circuit chips and becomes more and more important as the feature linewidth continues to decrease. In the mainstream OPC process, the segmentation of the layout pattern is based on the light intensity rule of the pattern, specifically achieved by debugging the OPC recipe. With the continuous shrinking of the process node, the complexity and density of the layout are continuously increasing, which forces engineers to spend a lot of time debugging the OPC recipe to cover various complex two-dimensional patterns in order to eliminate the manufacturing defects caused by various improper segmentations. Summary of the Invention
[0004] The technical problem to be solved by the present invention is to provide a method for segmenting the edge of a layout pattern, which can improve the edge segmentation of the layout pattern based on the OPC model, without the need for engineers to spend a lot of time debugging the OPC recipe, so as to obtain a stable debugging time of the OPC recipe and have better OPC correction accuracy.
[0005] To solve the above technical problem, the method for segmenting the edge of a layout pattern provided by the present invention includes edge segmentation with ripple suppression in the edge segmentation, and the edge segmentation with ripple suppression includes the following steps:
[0006] Step 1: Extract the spatial light intensity curves of the edges of the patterns in the layout using a lithography model of the OPC model.
[0007] Step 2: Calculate the extreme points on the spatial light intensity curves.
[0008] Step 3: Form segmentation segments centered on each of the extreme points on the corresponding edges of the patterns in the layout.
[0009] A further improvement is that in Step 3, if multiple extreme points are adjacent, it further includes a step of merging multiple adjacent extreme points, and then setting the corresponding segmentation segments for the merged extreme points.
[0010] A further improvement is that the sum of the distances between multiple extreme points to be merged is less than the length of the segmentation segment.
[0011] A further improvement is that in Step 1, the lithography model uses an optical imaging model plus a variable threshold process model, and the threshold in the variable threshold process model is the exposure threshold of the photoresist.
[0012] A further improvement is that in Step 1, there is a corresponding mapping relationship between the spatial light intensity curve and the pattern simulation profile obtained by simulating the patterns in the layout using the OPC model.
[0013] A further improvement is that in the OPC model, the parameters of the optical imaging model of the lithography model include:
[0014] λ, NA, σ_out, σ_in, K num, K grid, and OD;
[0015] Among them, λ represents the wavelength of the light source used by the lithography machine; NA represents the numerical aperture of the illumination system of the lithography machine, without unit; σ_out and σ_in are the partial coherence factor numbers of the annular illumination light source; K num is the number of convolution kernels used by the lithography model; K grid is the numerical value of the convolution kernel grid point size; OD is the optical diameter size used by the lithography model.
[0016] A further improvement is that it further includes the step of:
[0017] Step 4: Select the parameters of the OPC model based on the segmentation segments obtained by cutting the edges with ripple suppression.
[0018] A further improvement is that in Step 4, the grid search method is used to exhaustively search the parameters of the OPC model within the selected range to select the parameters of the OPC model.
[0019] A further improvement is that step four includes the following sub-steps:
[0020] Step 41: Read the position information of the optimized edges in the layout described in the OPC program.
[0021] Step 42: Copy the graphics around the optimized edges in the layout and generate a layout slice.
[0022] Step 43: Perform edge segmentation for ripple suppression on the graphics of the layout slice, perform OPC correction, extract OPC verification results, and extract edge position errors.
[0023] Repeat the processes of edge segmentation for ripple suppression, OPC correction, OPC verification result extraction, and edge position error extraction multiple times iteratively. The subsequent iteration is based on the result of the previous iteration until the iteration count is completed. After multiple iterations, write the optimal segmentation result of the graphics of the layout slice, the corresponding parameters of the OPC model, and the segmentation parameters into a report file.
[0024] Step 44: Change the parameters of the optimized edges and repeat step 43.
[0025] Step 45: After the grid search ends, compare the results obtained from the parameters of each group of optimized edges, report the optimal segmentation result and the corresponding parameter values of the OPC model and the segmentation parameters, and write the segmentation parameters into the final segmentation recipe.
[0026] Step 46: Perform OPC correction, OPC verification, and extract edge position errors according to the final segmentation recipe.
[0027] A further improvement is that in step 42, copy the graphics within 3 - 4 optical diameters around the optimized edges in the layout to generate the layout slice.
[0028] A further improvement is that in step 45, write the segmentation parameters into the final segmentation recipe in a marked segmentation manner.
[0029] A further improvement is that in step one, the layout is imported from the original GDS layout.
[0030] Different from the existing methods that achieve graphic segmentation based on graphic light intensity rules, the present invention utilizes the characteristic of one-to-one mapping between the exposure spatial light intensity curve of the lithography model and the exposure profile of the graphics in the layout. By extracting the spatial light intensity curve, and then segmenting the graphics according to the extreme points of the spatial light intensity curve to form corresponding segmentation segments. That is, the present invention improves the graphic segmentation based on the OPC model to obtain the corresponding segmentation segments. On this basis, OPC correction can eliminate manufacturing defects caused by various improper segmentations, and does not require engineers to spend a lot of time debugging the OPC recipe, so as to obtain a stable debugging time for the OPC recipe, and also has better OPC correction accuracy.
[0031] Based on the segmentation segments obtained according to the spatial light intensity curve, the present invention can select the parameters of the OPC model through the grid search method, obtain the optimal segmentation scheme, and make the OPC correction accuracy reach the best. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] The present invention will be further described in detail below with reference to the drawings and specific embodiments:
[0033] Figure 1 is the flowchart of the layout graphic edge segmentation method of the embodiment of the present invention;
[0034] Figure 2 is the mapping relationship diagram between the spatial light intensity curve and the graphic simulation profile in the layout graphic edge segmentation method of the embodiment of the present invention;
[0035] Figure 3 is the schematic diagram of segmenting the edges of the graphics in the layout according to the extreme points of the spatial light intensity curve in the layout graphic edge segmentation method of the embodiment of the present invention;
[0036] Figure 4 is the layout in the layout graphic edge segmentation method of the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0037] As Figure 1 shown, it is the flowchart of the layout graphic edge segmentation method of the embodiment of the present invention; for the layout graphic edge segmentation method of the embodiment of the present invention, the edge segmentation includes edge segmentation for ripple suppression, and the edge segmentation for ripple suppression includes the following steps:
[0038] Step 1: Use the lithography model of the OPC model to extract the spatial light intensity curve 101 of each edge 202 of the graphic 201 of the layout 203.
[0039] In the embodiment of the present invention, the layout 203 is imported from the original GDS layout 203.
[0040] The lithography model adopts an optical imaging model plus a variable threshold process model, and the threshold in the variable threshold process model is the exposure threshold of the photoresist.
[0041] There is a corresponding mapping relationship between the spatial light intensity curve 101 and the graphic simulation contour 201a obtained by simulating the graphic 201 of the layout 203 using the OPC model. That is, in the embodiment of the present invention, the spatial light intensity curve 101 can be obtained through OPC simulation by the lithography model finally. As Figure 2 shown, it is a mapping relationship diagram between the spatial light intensity curve 101 and the graphic simulation contour 201a in the layout graphic 201 edge segmentation method of the embodiment of the present invention; it can be seen that the edge 202a of the graphic simulation contour 201a corresponds to the spatial light intensity curve 101.
[0042] In the OPC model, the parameters of the optical imaging model of the lithography model include:
[0043] λ, NA, σ_out, σ_in, K num, K grid, and OD;
[0044] Among them, λ represents the light source wavelength used by the lithography machine; NA represents the numerical aperture of the illumination system of the lithography machine, without unit; σ_out and σ_in are the partial coherence factor numbers of the annular illumination light source; K num is the number of convolution kernels used by the lithography model; K grid is the numerical value of the convolution kernel grid point size; OD is the size of the optical diameter (Optical Diameter, OD) used by the lithography model.
[0045] In the embodiment of the present invention, part of the features of step one and Figure 1 the steps S101 and S102 in Figure 1 correspond. In
[0046] step S101 is the import of the original GDS layout 203; step S102 is the image edge segmentation method for ripple suppression, and forming the spatial light intensity curve 101 in step one belongs to step S102.
[0046] Step two: Calculate the extreme points on the spatial light intensity curve 101.
[0047] As Figure 2 shown, a total of 5 extreme points are displayed on the spatial light intensity curve 101, which are represented by points a, b, c, d, and e respectively.
[0048] Step two corresponds to part of the features of step S102.
[0049] Step three: Form segmentation segments centered on each of the extreme points on the corresponding edge 202 of the graphic 201 of the layout 203.
[0050] In an embodiment of the present invention, if multiple of the extreme points are adjacent, it further includes the step of merging multiple adjacent extreme points, and then setting corresponding segmentation segments for the merged extreme points.
[0051] The distance sum between the multiple extreme points to be merged is less than the length of the segmentation segment.
[0052] As Figure 3 shown, points b, c, and d are adjacent, and the three points are merged into point c.
[0053] When performing edge segmentation, corresponding segmentation segments are obtained respectively centered at points a, c, and e. The three segmentation segments are the line segments between point a1 and point a2, the line segment between point c1 and point c2, and the line segment between point e1 and point e2.
[0054] Step three corresponds to Figure 1 step S103 in
[0055] In an embodiment of the present invention, it further includes the step:
[0056] Step four, select parameters of the OPC model based on the segmentation segments obtained from the edge segmentation for ripple suppression. Further, in some embodiments, in step four, the grid search method is used to exhaustively search for the parameters of the OPC model within the selected range to select the parameters of the OPC model. Step four includes the following sub-steps:
[0057] Step 41, read the position information of the edges to be optimized in the layout 203 in the OPC program.
[0058] As Figure 4 shown, it is the layout 203 in the layout graphic edge segmentation method of an embodiment of the present invention, and the corresponding side 202 of the triangle is the edge to be optimized read.
[0059] Step 42, copy the graphics 201 around the edges to be optimized in the layout 203 and generate a layout slice.
[0060] In some preferred embodiments, copy the graphics 201 within 3 - 4 optical diameters around the edges to be optimized in the layout 203 to generate the layout slice.
[0061] Step 43, perform edge segmentation for ripple suppression on the graphics 201 of the layout slice, perform OPC correction, perform OPC verification result extraction, and extract edge position errors.
[0062] The processes of splitting the edges with ripple suppression, OPC correction, extracting the OPC verification results, and extracting the edge position errors are repeatedly iterated multiple times. The subsequent iteration is based on the results of the previous iteration until the number of iterations is completed. After multiple iterations are completed, the optimal splitting result of the pattern 201 of the layout slice, the parameters of the corresponding OPC model, and the splitting parameters are written into a report file.
[0063] Step 44: Change the parameters of the optimized edge and repeat Step 43.
[0064] Step 45: After the lattice search is completed, compare the results obtained with the parameters of each optimized edge, report the optimal splitting result, the parameter values of the corresponding OPC model, and the splitting parameters, and write the splitting parameters into the final splitting recipe. In some preferred embodiments, the splitting parameters are written into the final splitting recipe in a marked splitting manner.
[0065] Step 46: Perform OPC correction, OPC verification, and extract the edge position error according to the final splitting recipe.
[0066] In the method of the embodiment of the present invention, Step Four corresponds to Figure 1 Step S104 in [reference], and Step S104 is to select method parameters by lattice search. After that, Step S105 is further included. Step S105 determines whether the error curve is optimal. If not, return to Step S103 to continue the loop operation; if so, perform Step S106, and Step S106 is the end.
[0067] Different from the existing method of realizing the splitting of the pattern 201 based on the light intensity rule of the pattern 201, the embodiment of the present invention utilizes the characteristic that the exposure spatial light intensity curve 101 of the lithography model and the exposure profile of the pattern 201 of the layout 203 are mapped one by one. By extracting the spatial light intensity curve 101, and then splitting the pattern 201 according to the extreme points of the spatial light intensity curve 101 to form corresponding splitting segments, that is, the embodiment of the present invention improves the splitting of the pattern 201 based on the OPC model to obtain corresponding splitting segments. On this basis, OPC correction can eliminate manufacturing defects caused by various improper splittings, and it does not require engineers to spend a lot of time debugging the OPC recipe, so that a stable OPC recipe debugging time can be obtained, and it also has better OPC correction accuracy.
[0068] The embodiment of the present invention can select the parameters of the OPC model by the lattice search method based on the splitting segments obtained according to the spatial light intensity curve 101, and can obtain the optimal splitting scheme to make the OPC correction accuracy reach the best.
[0069] The method of the embodiment of the present invention will be further described below in combination with specific parameters:
[0070] The embodiment of the present invention applies the OPC model to improve the layout graphic edge segmentation method, including: the image edge segmentation method with ripple suppression, optimizing the extreme point allocation segmentation, and lattice search to select method parameters, so as to obtain the optimal segmentation scheme.
[0071] Among them, in the image edge segmentation method with ripple suppression in step S102, since various non-linear processes in the exposure process need to be simulated, the actual process model used is a variable threshold model, so the lithography model is the optical imaging model plus the variable threshold process model.
[0072] In the optimized extreme point allocation segmentation in step S103, the basic method of the ripple suppression method is to first extract the spatial light intensity curve 101 and calculate the extreme positions (a - e) on the spatial light intensity curve 101. Then, a segmentation segment is allocated with each extreme point as the center point, and adjacent extreme points, such as Figure 2 the midpoints b, c, and d will be merged first. The segmentation result obtained by using the ripple suppression method is as Figure 3 shown. The three extreme points corresponding to points a, c, and e respectively generate a segmentation segment on the corresponding side of the original layout, as shown by the line segment between the two points pointed by the vertical arrow.
[0073] In the lattice search to select method parameters in step S104, the OPC model adopted by the embodiment of the present invention uses the simplest lattice search method to exhaustively search the parameters in a small range. The optimization process is as follows:
[0074] Step 41: Read the position information of the edge to be optimized in the optimization recipe, that is, the OPC program.
[0075] Step 42: Copy the graphics within 3 - 4 optical diameters around the edge to be optimized in the layout to generate a small layout slice.
[0076] Step 43: Apply the image edge segmentation method with ripple suppression in this small layout slice for correction, verify the result extraction and extract the edge position error. And repeat this process iteratively several times (the number of iterations can be freely selected), and the subsequent iteration is based on the result of the previous iteration until the number of iterations is completed. After the iteration ends, write the optimal result and its corresponding segmentation scheme into the report file.
[0077] Step 44: Change the optimization parameters and repeat step 43.
[0078] Step 45: After the lattice search ends, compare the results obtained by each group of parameters. Report the optimal segmentation result, its corresponding parameter values and segmentation scheme, and write the segmentation scheme into the final segmentation recipe in a marked segmentation manner.
[0079] Step 46: Perform calibration according to the final cutting distribution recipe, verify the results, and extract the edge position error.
[0080] In order to compare with the existing method, in the embodiments of the present invention, the parameters of the optical imaging model can adopt the values shown in Table 1.
[0081] Table 1
[0082]
[0083] The layout adopts Figure 4 the structure shown.
[0084] In the embodiments of the present invention, the optimized OPC results are compared with the reference recipe results, and the results are shown in Table 2.
[0085] Table 2
[0086]
[0087] After the entire layout is optimized, compared with the original, the total edge position error (EPE) of the OPC results has decreased by 5%. As a cost, the number of segmentation segments has increased by 3% accordingly. This is consistent with the general understanding that improving the accuracy of OPC requires finer segmentation. It can be seen from the experimental results in Table 2 that simply increasing the number of segmentation segments does not necessarily improve the OPC accuracy. The key lies in segmenting segments that conform to the ripple frequency rhythm, and the improved layout edge segmentation method proposed in the embodiments of the present invention has better achieved this goal.
[0088] The present invention has been described in detail through specific embodiments above, but these do not constitute a limitation to the present invention. Without departing from the principle of the present invention, those skilled in the art can also make many deformations and improvements, which should also be regarded as the protection scope of the present invention.
Claims
1. A method for dividing the edge of a layout pattern, characterized in that, the edge division includes edge segmentation for ripple suppression, and the edge segmentation for ripple suppression includes the following steps: Step 1: Extract the spatial light intensity curves of each edge of the pattern in the layout using the lithography model of the OPC model; Step 2: Calculate the extreme points on the spatial light intensity curve; Step 3: Form segmentation segments centered on each of the extreme points on the corresponding edge of the pattern in the layout.
2. The method for dividing the edge of a layout pattern according to claim 1, characterized in that: In step 3, if multiple extreme points are adjacent, it further includes the step of merging multiple adjacent extreme points, and then setting the corresponding segmentation segments for the merged extreme points.
3. The method for dividing the edge of a layout pattern according to claim 2, characterized in that: The sum of the distances between multiple extreme points to be merged is less than the length of the segmentation segment.
4. The method for dividing the edge of a layout pattern according to claim 1, characterized in that: In step 1, the lithography model uses an optical imaging model plus a variable threshold process model, and the threshold in the variable threshold process model is the exposure threshold of the photoresist.
5. The method for dividing the edge of a layout pattern according to claim 1, characterized in that: In step 1, there is a corresponding mapping relationship between the spatial light intensity curve and the pattern simulation contour obtained by simulating the pattern in the layout using the OPC model.
6. The method for dividing the edge of a layout pattern according to claim 4, characterized in that: In the OPC model, the parameters of the optical imaging model of the lithography model include: λ, NA, σ_out, σ_in, K num, K grid, and OD; where λ represents the wavelength of the light source used by the lithography machine; NA represents the numerical aperture of the illumination system of the lithography machine, without unit; σ_out and σ_in are the partial coherence factor numbers of the annular illumination light source; K num is the number of convolution kernels used by the lithography model; K grid is the numerical value of the convolution kernel grid point size; OD is the optical diameter size used by the lithography model.
7. The method for dividing the edge of a layout pattern according to claim 1, characterized in that, it further includes the step: Step 4: Select the parameters of the OPC model based on the segmentation segments obtained by the edge segmentation for ripple suppression.
8. The method for dividing the edge of a layout pattern according to claim 7, characterized in that, In step 4, the grid search method is used to exhaustively select the parameters of the OPC model within the selected range to select the parameters of the OPC model.
9. The method for dividing the edge of a layout pattern according to claim 8, characterized in that, Step 4 includes the following sub-steps: Step 41: Read the position information of the edge to be optimized in the layout in the OPC program; Step 42: Copy the pattern around the edge to be optimized in the layout and generate a layout slice; Step 43: Perform edge segmentation for ripple suppression on the pattern of the layout slice, perform OPC correction, perform OPC verification result extraction, and extract the edge position error. The processes of edge segmentation for ripple suppression, OPC correction, extraction of OPC verification results, and extraction of edge position errors are repeatedly iterated multiple times. Each subsequent iteration is based on the results of the previous iteration until the number of iterations is completed. After multiple iterations are completed, the optimal segmentation result of the layout slice's graphics, the parameters of the corresponding OPC model, and the segmentation parameters are written to a report file. Step 44: Modify the parameters of the optimized edge and repeat Step 43. Step 45: After the grid search is completed, compare the results obtained with the parameters of each optimized edge, report the optimal segmentation result, the parameter values of the corresponding OPC model, and the segmentation parameters, and write the segmentation parameters to the final segmentation recipe. Step 46: Perform OPC correction, OPC verification, and extraction of edge position errors according to the final segmentation recipe.
10. The layout graphic edge segmentation method according to claim 9, wherein: In Step 42, the graphics within 3 - 4 optical diameters around the optimized edge in the layout are copied to generate the layout slice.
11. The layout graphic edge segmentation method according to claim 9, wherein: In Step 45, the segmentation parameters are written to the final segmentation recipe in a marked segmentation manner.
12. The layout graphic edge segmentation method according to claim 9, wherein: In Step 1, the layout is imported from the original GDS layout.
Citation Information
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