Fpga prototyping platform for verifiable emmc user interface

Abstract

The FPGA prototype verification platform of the verifiable EMMC user interface of the application, by introducing the testcase module to output the user test instruction data corresponding to the same test operation of the EMMC chip connected with the user design interface to the EMMC chip, so as to determine whether the user design interface is correctly connected to the hardware link in the external EMMC chip through the FPGA prototype verification platform, and the problem positioning process is simplified.

Description

Technical Field

[0001] This invention relates to the field of FPGA-based prototyping platforms, and in particular to an FPGA prototyping platform capable of verifying EMMC user interfaces. Background Technology

[0002] With the continuous improvement of chip integration and the diversification of performance development, chip design has become increasingly complex. A tiny chip needs to integrate hundreds of billions of transistors. Such a delicate and massive project can no longer be covered and solved by manpower alone. Therefore, FPGA-based prototyping platforms have become the best choice for developers to test their designs.

[0003] For ASIC users, many final chip products employ an external eMMC chip architecture to access the boot code. Therefore, when using FPGA-based prototyping platforms, these users also need to connect to the external eMMC chip through the platform's interface. During the process of ASIC users downloading code to the FPGA-based prototyping platform for prototype verification, issues may arise regarding the user code itself, the conversion process from user code to FPGA code, and the connection between the prototyping platform and the eMMC chip. Users are primarily concerned with potential issues with the user code itself. The conversion process from user code to FPGA code requires cooperation between the user and the test platform, and the connection between the prototyping platform and the eMMC chip needs to be guaranteed by the prototyping platform itself.

[0004] Furthermore, when users access external eMMC chips using an FPGA-based prototyping platform, if problems arise, they are typically considered from three aspects. First, is there a problem with the user's code itself, which is also the part the user wants to verify using the prototyping platform? Second, is the user's ASIC code correctly ported to the FPGA-based prototyping platform? Third, is the process of connecting the user's design to the external eMMC chip via the prototyping platform's interface correct?

[0005] Previously, when problems arose with the use of the EMMC chip, it was necessary to first check whether the prototype verification platform's conversion of the user's EMMC interface was correct and whether the hardware link was normal, which wasted a lot of time. Therefore, a method was needed to decouple the user side and the prototype verification platform side when the user encountered problems connecting the external EMMC chip using the FPGA-based prototype verification platform for analysis. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an FPGA prototype verification platform that can verify the EMMC user interface, so as to solve the above-mentioned technical problems in the prior art.

[0007] To achieve the above and other related objectives, the present invention provides a platform comprising: a testcase module for outputting user test instruction data corresponding to the user design interface connected to the external EMMC chip to perform the same test operation on the EMMC chip; and a user interface conversion module, connected to the testcase module, for sending the user test instruction data to the external EMMC chip to perform the corresponding test operation on the external EMMC chip, so as to determine whether the hardware link between the user design interface and the external EMMC chip is correct through the FPGA prototyping platform by judging whether the test operation on the external EMMC chip is successfully completed.

[0008] In one embodiment of the present invention, the testcase module includes a parameterization module, configured to generate user operation instruction data that conforms to the timing of the external EMMC chip and performs the same test operation on the EMMC chip by the user design interface connected to the external EMMC chip, based on parameters input through the platform visualization interface of the FPGA prototype verification platform.

[0009] In one embodiment of the present invention, the testcase module includes a data import module, used to import the user operation instruction data through the platform visualization interface of the FPGA prototype verification platform.

[0010] In one embodiment of the present invention, the platform visualization interface of the FPGA prototype verification platform determines whether the test operation on the external EMMC chip has been completed.

[0011] In one embodiment of the present invention, the method for determining whether the test operation on the external EMMC chip is completed includes: comparing the operation result data fed back on the platform visualization interface when the corresponding test operation is performed on the external EMMC chip based on the user operation instruction with the operation result data corresponding to the test operation performed on the external EMMC chip by the user design interface; if they are consistent, it is determined that the test operation on the external EMMC chip is successfully completed; otherwise, it is not successfully completed.

[0012] In one embodiment of the present invention, the testcase module stores a test operation step file corresponding to the test operation performed on the EMMC chip, including: user test instruction data corresponding to performing one or more test operations on the EMMC chip respectively, and operation result data corresponding to performing each test operation on the EMMC chip according to the user design interface.

[0013] In one embodiment of the present invention, the user test instruction data includes: initialization operation instruction data corresponding to initialization operation and / or read / write operation instruction data corresponding to read / write operation.

[0014] In one embodiment of the present invention, the timing can also be determined by comparing the entry waveform of the user interface conversion module captured through the platform visualization interface with the entry waveform of the user design interface in the user interface conversion module.

[0015] In one embodiment of the present invention, the testcase version used by the testcase module is associated with the socket location of the EMMC chip on the FPGA prototype verification platform.

[0016] In one embodiment of the present invention, the data import module is further configured to import the user operation instruction data and the operation result data corresponding to the test operation performed on the EMMC chip by the user design interface through the built-in RAM of the platform visualization interface.

[0017] As described above, the FPGA prototype verification platform for verifying EMMC user interfaces of the present invention has the following beneficial effects: The present invention introduces a testcase module to output user test instruction data corresponding to the user design interface connected to the external EMMC chip to perform the same test operation on the EMMC chip, so as to determine whether the hardware link of the user design interface connected to the external EMMC chip through the FPGA prototype verification platform is correct by judging whether the test operation is successfully completed on the external EMMC chip, thus simplifying the problem localization process. Attached Figure Description

[0018] Figure 1 The diagram shows a structural schematic of an FPGA prototype verification platform for a verifiable EMMC user interface according to an embodiment of the present invention.

[0019] Figure 2 The diagram shown is a structural schematic of an FPGA prototype verification platform according to an embodiment of the present invention. Detailed Implementation

[0020] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0021] It should be noted that in the following description, reference is made to the accompanying drawings, which illustrate several embodiments of the invention. It should be understood that other embodiments may also be used, and changes in mechanical composition, structure, electrical system, and operation may be made without departing from the spirit and scope of the invention. The following detailed description should not be considered limiting, and the scope of the embodiments of the invention is defined only by the claims of the published patents. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. Spatially related terms, such as “upper,” “lower,” “left,” “right,” “below,” “below,” “lower part,” “above,” “upper part,” etc., may be used herein to illustrate the relationship between one element or feature shown in the figures and another element or feature.

[0022] Throughout this specification, when it is said that a part is "connected" to another part, this includes not only "direct connection" but also "indirect connection" by placing other elements in between. Furthermore, when it is said that a part "includes" a certain constituent element, unless otherwise stated otherwise, this does not exclude other constituent elements, but rather means that other constituent elements may also be included.

[0023] The terms "first," "second," and "third," etc., used herein are for the purpose of describing various parts, components, regions, layers, and / or segments, but are not limiting. These terms are used only to distinguish one part, component, region, layer, or segment from others. Therefore, the "first part," "component," "region," "layer," or "segment" described below may refer to a "second part," "component," "region," "layer," or "segment" without departing from the scope of this invention.

[0024] Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of the stated feature, operation, element, component, item, kind, and / or group, but do not preclude the presence, occurrence, or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. The terms “or” and “and / or” as used herein are interpreted as inclusive, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of: A; B; C; A and B; A and C; B and C; A, B, and C.” Exceptions to this definition arise only when combinations of elements, functions, or operations are inherently mutually exclusive in some manner.

[0025] This invention provides an FPGA prototype verification platform for verifying EMMC user interfaces. By introducing a testcase module, it outputs user test instruction data corresponding to the user design interface connected to the external EMMC chip to perform the same test operation on the EMMC chip. This allows for the determination of whether the hardware link between the user design interface and the external EMMC chip is correct through the FPGA prototype verification platform by judging whether the test operation is successfully completed on the external EMMC chip, thus simplifying the problem localization process.

[0026] The present invention will now be described in detail with reference to the accompanying drawings, so that those skilled in the art can readily implement it. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0027] like Figure 1 The diagram shown illustrates the structure of an FPGA prototype verification platform for a verifiable EMMC user interface according to an embodiment of the present invention.

[0028] The platform includes:

[0029] The testcase module 11 is used to output user test instruction data corresponding to the user design interface connected to the external EMMC chip 2 to perform one or more test operations on the EMMC chip 2. Specifically, by replacing the user code under normal circumstances with the testcase module 11, it is possible to verify whether the hardware link from the user code to the external EMMC chip is reliable under the same conditions, and to compare whether the user function can be implemented under the same operation.

[0030] User interface conversion module 12, connected to testcase module 11, is used to send the user test instruction data to the external EMMC chip 2 connected to it to perform one or more corresponding test operations on the external EMMC chip, so as to determine whether the hardware link of the user design interface is correctly connected to the external EMMC chip through the FPGA prototype verification platform by judging whether the test operation is successfully completed on the external EMMC chip 2.

[0031] In one embodiment, the testcase module 11 includes a parameterization module that implements the timing of the user interface to the external EMMC chip. This module generates user operation instruction data based on parameters input through the platform visualization interface of the FPGA prototyping platform. The user operation instruction data must conform to the timing of the external EMMC chip and correspond to the same test operation performed on the EMMC chip 2 by the user-designed interface connected to the external EMMC chip 2. For example, the user can input these parameters through the GUI interface of the prototyping platform to control the output of the testcase module.

[0032] In one embodiment, the testcase module 11 includes a data import module, used to import the user operation instruction data through the platform visualization interface of the FPGA prototype verification platform. Preferably, the data import module is further used to import the user operation instruction data and the operation result data corresponding to the test operation performed on the EMMC chip 2 according to the user design interface through the built-in RAM of the platform visualization interface.

[0033] In one embodiment, the completion of the test operation on the external EMMC chip is determined through the platform visualization interface of the FPGA prototype verification platform. The method for determining whether the test operation on the external EMMC chip is complete includes: comparing the operation result data returned on the platform visualization interface from the test operation performed on the external EMMC chip based on the user operation command with the operation result data from the user design interface for performing the test operation on the external EMMC chip; if they match, the test operation on the external EMMC chip is considered successfully completed; otherwise, it is considered unsuccessfully completed.

[0034] In one embodiment, the user test instruction data includes: initialization operation instruction data corresponding to an initialization operation and / or read / write operation instruction data corresponding to a read / write operation. It should be noted that the read / write operation instruction data includes: read operation instruction data corresponding to a read operation and write operation instruction data corresponding to a write operation; and the read / write operation can be either a read or a write operation, or a combination of both.

[0035] Each operation can correspond to one or more operation steps, and each operation step can correspond to one or more instructions.

[0036] In one embodiment, the testcase module 11 stores a test operation step file corresponding to the test operations performed on the EMMC chip 2, including: user test instruction data corresponding to performing one or more test operations on the EMMC chip 2 respectively, and operation result data corresponding to performing each test operation on the EMMC chip 2 according to the user design interface. In use, the operation result data corresponding to performing test operations on the EMMC chip according to the user design interface can be retrieved from the platform's visual interface and compared with the feedback operation result data.

[0037] In one embodiment, users can also rule out timing issues by comparing the output data of the testcase module with the user-designed output data under the same operation. Specifically, this can be achieved by comparing the input waveform of the user interface conversion module captured through the platform's visual interface with the input waveform of the user-designed interface in the user interface conversion module. The testcase module can capture the input waveform of the user interface conversion module through the prototype verification platform's GUI interface, allowing users to compare the input waveform of their own design in the user interface conversion module.

[0038] In one embodiment, the testcase version used by the testcase module is associated with the socket location of the EMMC chip on the FPGA prototyping platform. For example, a testcase version corresponding to the hardware environment is generated according to the usage flow of the prototyping platform.

[0039] To better illustrate the above-mentioned FPGA prototype verification platform for verifying the EMMC user interface, the present invention provides the following specific embodiments.

[0040] Example 1: A method for verifying the EMMC user interface using an FPGA prototyping platform. For example... Figure 2 The diagram shows the structure of an FPGA prototype verification platform.

[0041] The process includes: inserting the EMMC daughter card with the EMMC chip into an FPGA-based prototyping platform; generating a testcase version for the corresponding hardware environment according to the platform's usage procedures; importing this version into the platform via the software; starting the platform normally according to the user's instructions; and initializing the EMMC chip by issuing CMDs 0, 1, 2, 3, 7, 9, and 6 as per the operation documentation. Then, importing the local data file into the user's write memory through the GUI interface's user memory page, and writing the data from the write memory to the EMMC chip using write commands. Finally, reading the EMMC data back to the user's read memory using read commands, and comparing the read memory data with the local data through the GUI interface, confirming that the read / write functionality is available. This verifies that the prototyping platform operates correctly from the user-designed output to the external EMMC chip input.

[0042] In this embodiment, after introducing the testcase module, users only need to download the testcase project to the prototype verification platform and follow the example operations to complete the initialization and data reading / writing of the eMMC chip, thereby proving whether the hardware link is normal. Users can also eliminate timing issues by comparing the output data of the testcase under the same operation with the output data of the user design. This simplifies the problem localization process.

[0043] In summary, this invention provides an FPGA prototype verification platform for EMMC user interfaces. By constructing a packaging device, a management terminal, and a terminal client program, it manages the terminals configured in each customer clinic and the applications installed on those terminals. This invention effectively solves the management challenges of managing multiple channels of customers, multiple applications, and multiple versions running concurrently. It effectively perceives the scope of impact from application and version changes, effectively controls the entire application upgrade process, and provides a completely feasible solution for the perception, monitoring, diagnosis, and recovery of managed applications. It is particularly effective in ensuring rapid recovery from catastrophic events such as customer computer equipment damage and loss of operational configurations. It significantly reduces labor costs in application deployment, installation, and upgrade management. Furthermore, when dealing with tens of thousands of enterprise customers using the application, it can efficiently and promptly identify application operational problems and respond to customer feedback in a timely manner, greatly improving customer recognition and satisfaction. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial application value.

[0044] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An FPGA prototype verification platform for verifying an EMMC user interface, characterized in that, The platform includes: The testcase module is used to output user test instruction data corresponding to the user design interface connected to the external EMMC chip performing the same test operation on the EMMC chip. The testcase module includes: a parameterization module, used to generate user operation instruction data that conforms to the timing of the external EMMC chip and corresponds to the user design interface connected to the external EMMC chip performing the same test operation on the EMMC chip, based on parameters input through the platform visualization interface of the FPGA prototyping platform; a data import module, used to import the user operation instruction data through the platform visualization interface of the FPGA prototyping platform; the data import module is also used to import the user operation instruction data and second operation result data corresponding to the test operation performed on the EMMC chip by the user design interface corresponding to the user operation instruction data through the built-in RAM of the platform visualization interface. The user interface conversion module, connected to the testcase module, is used to send the user test instruction data to the external EMMC chip it is connected to in order to perform corresponding test operations on the external EMMC chip. The user interface is then used to determine whether the hardware link between the user design interface and the external EMMC chip is correct by judging whether the test operation is successfully completed on the external EMMC chip.

2. The FPGA prototype verification platform for verifying the EMMC user interface as described in claim 1, characterized in that, The platform's visualization interface, used to verify the FPGA prototype, determines whether the test operation on the external EMMC chip has been completed.

3. The FPGA prototype verification platform for verifying the EMMC user interface as described in claim 2, characterized in that, The methods for determining whether the test operation on the external EMMC chip has been completed include: The second operation result data displayed on the platform's visual interface, which is the result of performing the corresponding test operation on the external EMMC chip based on the user operation instruction data, is compared with the first operation result data corresponding to the same test operation performed on the external EMMC chip based on the user test instruction data by the user design interface. If they match, the test operation on the external EMMC chip is considered to have been successfully completed; otherwise, it is considered to have been unsuccessfully completed.

4. The FPGA prototype verification platform for verifying the EMMC user interface as described in claim 3, characterized in that, The testcase module stores test operation step files corresponding to the test operations performed on the EMMC chip, including: user test instruction data corresponding to performing one or more test operations on the EMMC chip respectively, and first operation result data corresponding to performing each test operation on the EMMC chip according to the user design interface.

5. The FPGA prototype verification platform for verifying the EMMC user interface as described in claim 1, characterized in that, The user test instruction data includes: initialization operation instruction data corresponding to the initialization operation and / or read / write operation instruction data corresponding to the read / write operation.

6. The FPGA prototype verification platform for verifying the EMMC user interface as described in claim 2, characterized in that, The timing can also be determined by comparing the entry waveform of the user interface conversion module captured through the platform's visual interface with the entry waveform of the user-designed interface in the user interface conversion module.

7. The FPGA prototype verification platform for verifying the EMMC user interface as described in claim 1, characterized in that, The testcase version used by the testcase module is associated with the socket location of the EMMC chip on the FPGA prototype verification platform.

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