An encryption method for in-memory computing system

Abstract

The application provides an encryption method for an in-memory computing system, and belongs to the field of neural network accelerators.The application uses a field effect transistor device with a gate storage layer and bipolar transport characteristics as a ciphertext weight storage unit capable of realizing XNOR operation;the non-volatile gate storage mechanism is used to realize storage of ciphertext weights, and the controllable bipolar transport characteristics can realize XNOR operation of inputs and ciphertext weights. The application can realize in-situ decryption multiplication on ciphertext weights by using only one device, and the array formed thereby can realize an in-memory computing system with an encryption function. Compared with a conventional MOSFET-based implementation mode, the application can significantly reduce hardware overhead, and is conducive to implementation of a large-scale encrypted neural network accelerator chip.

Description

Technical Field

[0001] This invention relates to neural network accelerators based on in-memory computing architecture, and more specifically to an encryption method for in-memory computing systems. Background Technology

[0002] With the rapid development of information technology, human society has entered an era of "data explosion," and the exponentially increasing amount of data each year has brought unprecedented pressure to data processing and computing. Due to its storage-compute separation architecture, the traditional von Neumann computing architecture causes a significant waste of power and energy during data transfer between storage and computing units. In today's information society and even intelligent society, with its massive amounts of data, this problem will become increasingly serious.

[0003] Inspired by the computational patterns of the human brain, researchers have proposed the Neural Network (NN) computing architecture. Based on neuron-synapse-neuron connections, it constructs a highly parallel, in-memory distributed computing network, improving efficiency in processing complex data while avoiding the power consumption and energy consumption problems caused by the "memory wall" in traditional von Neumann architectures. In classic Artificial Neural Networks (ANNNs), the input feature vector and weight matrix undergo vector-matrix dot product to produce the output vector, which is then processed by an activation function to obtain the output activation vector. The dominant computational operation is multiplication-accumulation. Currently, ANNs have demonstrated computational efficiency surpassing traditional general-purpose computing units in applications such as image recognition, natural language processing, and autonomous driving.

[0004] Ultimately, artificial neural network architectures must achieve overall hardware implementation to completely overcome the "memory wall" bottleneck. Computing-in-memory (CIM) architectures built using non-volatile memory (NVM) devices such as resistive random access memory (RRAM) and phase-change memory (PCM) can accelerate the dominant multiply-accumulate operations in artificial neural networks, improving computational energy efficiency. However, the neural network weight parameters stored in non-volatile devices are easily read and copied, posing potential security risks such as intellectual property (IP) leakage and adversarial attacks. Encrypting CIM systems using authorized keys from specific users is crucial for the security of edge machine learning. To add encryption to non-volatile memory arrays used for in-memory matrix multiplication and addition operations, it is often necessary to first read the encrypted weight parameters stored in the array, then decrypt them using peripheral decryption circuits to obtain the original weight parameters, and finally perform matrix multiplication and addition operations in peripheral digital circuits. This sacrifices the parallelism advantage of in-memory computing based on non-volatile devices and introduces additional hardware overhead. Summary of the Invention

[0005] To address the problems existing in the prior art, this invention proposes an encryption method for in-memory computing systems. Compared with existing in-memory computing systems with encryption functions, this invention can significantly reduce hardware overhead while achieving in-situ ciphertext weight decryption and multiply-accumulate operations.

[0006] The technical content provided by this invention is as follows:

[0007] An encryption method for in-memory computing systems is characterized by using a field-effect transistor (FET) with a gate storage layer and bipolar transport characteristics (hereinafter referred to as a gate storage FET) as the ciphertext weight storage unit to form an encrypted in-memory computing array. During the computation phase, the input of the neural network is XORed with the key to obtain an intermediate signal. When the intermediate signal is the same as the ciphertext weight stored in the gate storage FET, the gate storage FET outputs a high current I. H This enables XNOR encryption operations.

[0008] In the encrypted in-memory computing array, the gate terminals of each row of gate storage bipolar field-effect transistors are connected to the word line WL, and the source terminals of each column of gate storage bipolar field-effect transistors are connected to the bit line BL. During the computing phase, the drain terminals of each column of gate storage bipolar field-effect transistors are connected to the operating voltage. The horizontal word line WL, the vertical bit line BL, and the neural network input x... i Key, shared by each row i The intermediate output signal x is applied to the XOR logic gate. WL_i Connected to the word line WL of the array.

[0009] The input value x of the neural network i "+1" is mapped to a logic high level, and "-1" is mapped to a logic low level; during the programming phase, the original weight w i，j With user authorization key i The ciphertext weight w obtained by performing XOR encryption e_i，j It is written into the gate storage bipolar field-effect transistor array; the ciphertext weight "-1" is mapped to the gate storage bipolar field-effect transistor being programmed to a high threshold state, and "+1" is mapped to the gate storage bipolar field-effect transistor being programmed to a low threshold state.

[0010] This invention utilizes a field-effect transistor (FET) with a gate storage layer and bipolar transport characteristics (gate-storage FET) as a encrypted weight storage cell, enabling XNOR operation on a single transistor cell. The gate-storage FET is structured by adding a gate storage layer to the gate stack of a FET with bipolar channel transport characteristics, or by replacing the gate dielectric layer with a gate storage layer. The device has a gate terminal, a source terminal, and a drain terminal. During in-memory computation, the gate terminal serves as the input terminal, receiving the intermediate input signal x. WL_i The voltage signal is set to a fixed voltage at the source and drain terminals, and the channel current represents the result of multiplication of the input and weights. The gate-to-grid bipolar field-effect transistor of this invention has the following characteristics: applying a programming voltage pulse to the gate terminal allows adjustment of the threshold voltage of the gate-to-grid bipolar field-effect transistor device; when a low-amplitude non-destructive readout voltage is applied to the gate terminal, it can function as a gate-controlled channel device; the channel transport of this device exhibits bipolar characteristics, and during non-destructive readout, the transfer characteristic curve of the device shows non-monotonicity, with a gate voltage (V0) corresponding to the lowest current. OFF ), and the transfer curve about V OFF It exhibits a certain degree of symmetry; the non-volatile gate storage mechanism of the gate stack adjusts V by regulating the threshold voltage of the device. OFF Different ciphertext weight states are stored. When the stored ciphertext weight state (w) is... e_i，j ) and the input signal state at the gate (x) WL_i When matched, the channel is in a low-conductivity state, enabling linearly inseparable XNOR operation on a single transistor.

[0011] The gate storage layer of the bipolar field-effect transistor device of the present invention can adopt a floating-gate storage mechanism, a charge trapping floating-gate storage mechanism, or a ferroelectric gate storage mechanism; the gate-controlled bipolar channel transport characteristics of the bipolar field-effect transistor device of the present invention can adopt the band-to-band tunneling mechanism of the gate-controlled reverse bias PIN structure of the tunneling field-effect transistor (TFET), the gate-controlled Schottky barrier MOSFET (SB-MOSFET) mechanism with Schottky source and drain, two-dimensional material channels with bipolar transport characteristics such as graphene and carbon nanotube channels, and oxide channel materials with bipolar transport characteristics such as SnO.

[0012] The beneficial effects and corresponding principles of the encryption method for in-memory computing systems of the present invention:

[0013] 1. The encryption method for in-memory computing systems of the present invention uses the classic XOR operation encryption method at the algorithm layer to encrypt the weight parameters of the neural network. It integrates the ciphertext weight decryption process into the XNOR-based multiplication and addition operation by utilizing the associative law of the eigenvalues ​​of the XOR / XNOR operator. This simplifies the multiplication and addition operation of in-memory computing to directly performing XNOR operation on the ciphertext weight, thereby avoiding the explicit decryption process of the ciphertext weight.

[0014] 2. The encryption method for in-memory computing systems of this invention combines a field-effect transistor (FET) with a gate storage layer and bipolar transport characteristics (gate-storage FET) at the device layer. It utilizes a non-volatile gate storage mechanism to store ciphertext weights and leverages the controllable bipolar transport characteristics of a three-terminal structure to perform XNOR operations on the input and ciphertext weights. Only one device is needed to achieve in-situ decryption multiplication on the ciphertext weights, and the resulting array can realize an in-memory computing system with encryption functionality. This significantly reduces hardware costs compared to traditional CMOS-based or RRAM-based solutions. Attached Figure Description

[0015] Figure 1 This is an array schematic diagram of the encryption method for in-memory computing systems according to the present invention;

[0016] Figure 2 This is a schematic diagram of an embodiment of the field-effect transistor device with bipolar transport characteristics (gate storage bipolar field-effect transistor) with a gate storage layer according to the present invention;

[0017] In the picture:

[0018] 1—A schematic diagram of the algorithm layer of encryption methods for in-memory computing systems;

[0019] 2—Signed multiplication based on XNOR;

[0020] 3—Row-wise weighted encryption based on the XOR encryption method;

[0021] 4 — XOR logic gate;

[0022] 5—Field-effect transistor devices with bipolar transport characteristics and gate storage layer (gate storage bipolar field-effect transistor);

[0023] 6—Gate stacks with gate storage mechanisms, such as floating-gate storage stacks, charge-trapping floating-gate storage stacks, and ferroelectric gate storage layers;

[0024] 7—Field-effect transistors with bipolar transport characteristics, such as tunneling field-effect transistors (TFETs, TFETs), Schottky barrier source-drain field-effect transistors (SB-MOSFETs), graphene channel field-effect transistors, carbon nanotube channel field-effect transistors, tin oxide (SnO) channel thin film field-effect transistors, etc.

[0025] 8—A field-effect transistor device with a gate storage layer and bipolar transport characteristics (gate storage bipolar field-effect transistor);

[0026] 9—Transfer curve with bipolar effect modulated by gate storage layer (I) D -V G (Diagram). By programming the gate storage layer to different states, the gate storage bipolar field-effect transistor has different threshold voltages, which is reflected in the non-destructive readout transfer curve along the gate voltage (V). G ) Directional translation; the bipolar effect is manifested in the transfer curve being non-monotonic and exhibiting a certain degree of symmetry. Detailed Implementation

[0027] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0028] This embodiment uses Hf 0.5 Zr 0.5 O2 ferroelectric layer material is used as the gate storage layer of a field-effect transistor device with bipolar transport characteristics. The bipolar current transport mechanism is realized by a tunneling field-effect transistor with a gate-controlled reverse bias PIN structure. The gate storage bipolar field-effect transistor formed is called a ferroelectric tunneling field-effect transistor (FeTFET).

[0029] like Figure 1 As shown, this example demonstrates an array circuit implementation of an in-memory computing-oriented encryption method based on FeTFETs. It includes an array of FeFET devices, horizontal word lines (WL), vertical bit lines (BL), two-input XOR logic gates, and the input (x) of a neural network. i ) and the key bits shared by each row (Key i ) operates on the XOR logic gate,

[0030]

[0031]

[0032] Formula (1) is the expression for the relationship between the original weight and the ciphertext weight in the XOR logic-based weighted encryption method.

[0033] Formula (2) is an XNOR-based multiply-accumulate operation with implicit decryption. In the formula:

[0034] —Exclusive OR operation

[0035] ⊙——XNOR operation

[0036] w i，j —The original weight parameters of the neural network

[0037] w e_i，j —The ciphertext weight parameters obtained by encrypting the original weights

[0038] Key i —The shared authorization key bits in each row of the weight matrix

[0039] x i —The individual bits of the input vector of a neural network

[0040] n — the dimension of the neural network input vector

[0041] x WL_i —The signal applied to the word lines after the neural network input and authorization undergo an XOR operation.

[0042] y j —The sum of the multiplication and addition operations of the input vector and a column in the weight matrix

[0043] The intermediate output signal (x) WL_i The FeTFETs are connected to array WL; the gate of each row of FeTFETs is connected to WL, and the source of each column of FeTFETs is connected to BL. During calculation, the drain of each column of FeTFETs is connected to the operating voltage; the input value of the neural network (x) i The "+1" of the original weights (w) is mapped to a high logic level, and the "-1" is mapped to a low logic level; during the programming phase, the original weights (w) are mapped to a high logic level. i，j ) and user authorization key (Key) i The ciphertext weight (w) obtained by performing XOR encryption operation e_i，j ) is written into the FeTFET array; such as Figure 2 As shown, the ciphertext weight "-1" maps to the FeTFET programmed to a high threshold state, and "+1" maps to the FeTFET programmed to a low threshold state; during the encrypted neural network operation, only when the intermediate signal x on WL... WL_i With ciphertext weight w e_i，j At the same time, the corresponding high current I of the FeTFET output HIt implements XNOR operation; the currents are naturally summed on BL to obtain a partial sum; when the key bit used in the operation is not the authorized key, the calculation result is wrong, which leads to the incorrect inference result of the neural network, and realizes in-memory calculation encrypted with user authorized key.

[0044] The beneficial effects of the present invention are illustrated in this embodiment:

[0045] 1. For FeTFET-based array circuits using in-memory computing encryption methods, the classic XOR operation encryption method is applied to encrypt neural network weight parameters. The associative law of the eigenvalues ​​of the XOR / XNOR operators is utilized to integrate the ciphertext weight decryption process into the XNOR-based multiply-accumulate operation. This simplifies the in-memory multiply-accumulate operation to a direct XNOR operation on the ciphertext weights, thus avoiding the explicit decryption process. Compared to traditional implementations, this significantly reduces hardware overhead and computational complexity, eliminating the need for an explicit decryption process and removing the need for external decryption and multiply-accumulate circuits.

[0046] 2. For the ciphertext weighting cell based on FeTFET, during the programming phase, a high-amplitude programming voltage pulse is applied to the gate terminal of the FeTFET, causing the voltage divider of the ferroelectric layer to exceed its coercive voltage, resulting in ferroelectric polarization reversal and storage of the ciphertext weights. During the computation phase, the FeTFET gate input is related to x. i and Key i The relevant non-destructive readout voltage V WL_i V WL_i The local XNOR-based signed multiplication result, represented by the channel current level, is achieved with ciphertext weights. In-situ decryption of the local XNOR operation requires only a single transistor. Compared to traditional CMOS implementations, this significantly reduces hardware overhead, eliminating the need for complementary ciphertext weight storage and complementary inputs.

[0047] Finally, it should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the claims.

Claims

1. An encryption method for in-memory computing systems, characterized in that, 1) An encrypted in-memory computing array is constructed using gate-based bipolar field-effect transistors (BFETs) as ciphertext weight storage units. In the encrypted in-memory computing array, the gate terminals of each row of BFETs are connected to the word line WL, and the source terminals of each column of BFETs are connected to the bit line BL. 2) During the programming phase, the ciphertext weights obtained by performing an XOR encryption operation between the original weights and the user authorization key are written into the gate storage bipolar field-effect transistor array; 3) During the computation phase, the drain of each column of gate storage bipolar field-effect transistors is connected to the operating voltage. The horizontal word line WL, the vertical bit line BL, the input of the neural network, and the key bit shared by each row act on an XOR logic gate. The input of the neural network and the key are XORed to obtain an intermediate signal. The output intermediate signal is connected to the word line WL of the array. When the intermediate signal has the same weight as the ciphertext stored by the gate storage bipolar field-effect transistors, the gate storage bipolar field-effect transistors output a high current I. H This implements in-situ decryption multiplication operations based on XNOR.

2. The encryption method for in-memory computing systems as described in claim 1, characterized in that, The input values ​​of the neural network are mapped to logic level "+1" and logic level "-1"; the ciphertext weights are mapped to gate storage bipolar field-effect transistors programmed to a high threshold state and gate storage bipolar field-effect transistors programmed to a low threshold state.

3. The encryption method for in-memory computing systems as described in claim 1, characterized in that, The gate storage layer of the gate storage bipolar field-effect transistor is designed using a floating gate storage mechanism, a charge trap floating gate storage mechanism, or a ferroelectric gate storage mechanism.

4. The encryption method for in-memory computing systems as described in claim 1, characterized in that, The bipolar transport characteristics of the gate storage bipolar field-effect transistor are achieved by using a band-to-band tunneling mechanism through a gate-controlled reverse biased PIN structure, a Schottky tunneling mechanism of Schottky barrier source-drain, or a two-dimensional material or oxide channel material with bipolar characteristics.

Images