Multi-step clamping voltage selectable SiC-TVS device and preparation method thereof

Abstract

The application relates to a multi-step clamping voltage selectable SiC-TVS device and a preparation method thereof. The device comprises a silicon carbide substrate layer, a silicon carbide epitaxial stack layer, the silicon carbide epitaxial stack layer comprising n layers of first silicon carbide epitaxial layers and n layers of second silicon carbide epitaxial layers; a first electrode located on the topmost layer of the second silicon carbide epitaxial layer; a plurality of second electrodes located on the second upper surface of the silicon carbide substrate layer and the fourth upper surface of the first layer of the second silicon carbide epitaxial layer to the (n-1) layer of the second silicon carbide epitaxial layer; wherein the first silicon carbide epitaxial layer is lightly doped, the second silicon carbide epitaxial layer is heavily doped, the silicon carbide substrate layer and the second silicon carbide epitaxial layer are of a first conductivity type, and the first silicon carbide epitaxial layer is of a second conductivity type. The application solves the problems of system size increase and power consumption increase caused by the need to adapt multiple TVS devices for protection during the non-steady-state operation of the circuit system.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of microelectronics, and particularly relates to a SiC-TVS device with multiple steps and selectable clamping voltage and a preparation method. BACKGROUND

[0002] In the fields of aerospace, rail transportation, high-voltage power grid and advanced weapon system, which are generally applied to circuit miniaturization and integration, a transient voltage suppressor (TVS) with high power absorption and fast response is generally used as a protective device to avoid damage to electronic components and downstream electronic systems caused by transient high-energy surge impact such as lightning and electromagnetic pulse (EMP). When a transient surge impact occurs in a circuit system, the TVS connected in parallel at both ends of the circuit system will quickly conduct and absorb the surge power, clamping the voltage at both ends of the circuit system to a safe preset value, thereby realizing the function of clamping protection.

[0003] Compared with traditional Si semiconductor materials, silicon carbide (SiC) materials have the advantages of large band gap, critical breakdown field strength, large electron saturation drift speed and high thermal conductivity. The SiC-TVS device prepared from the SiC material can exhibit potential advantages such as low leakage, fast response, high temperature resistance and strong robustness caused by size and density, and is getting more and more attention in extreme and complex working environments such as high temperature and strong electromagnetic interference.

[0004] The working voltage of a general circuit system is determined, so the protective TVS device at both ends of the circuit system needs to have a precise clamping voltage design value corresponding to the working voltage, i.e., a determined clamping factor. When the working voltage of the circuit system needs to be dynamically adjusted due to external conditions (such as working temperature, frequency and other factors), multiple TVSs need to be added to the protective circuit topology for clamping. In this non-steady state, the additional design and increase of the protective topology will undoubtedly lead to an increase in the size of the circuit system and even an increase in power consumption. SUMMARY

[0005] In order to solve the above problems in the prior art, the application provides a SiC-TVS device with multiple steps and selectable clamping voltage and a preparation method. The technical problems to be solved by the application are solved by the following technical solutions.

[0006] One embodiment of the application provides a SiC-TVS device with multiple steps and selectable clamping voltage, which comprises:

[0007] a silicon carbide substrate layer having a first upper surface, a second upper surface and a first sidewall surface between the first upper surface and the second upper surface, the first upper surface being above the second upper surface;

[0008] a silicon carbide epitaxial stack including n layers of first silicon carbide epitaxial layers and n layers of second silicon carbide epitaxial layers, the n layers of first silicon carbide epitaxial layers and the n layers of second silicon carbide epitaxial layers being alternately stacked on the first upper surface of the silicon carbide substrate layer, the bottommost layer of the silicon carbide epitaxial stack being the first silicon carbide epitaxial layer, the topmost layer of the silicon carbide epitaxial stack being the second silicon carbide epitaxial layer;

[0009] and the first layer of the second silicon carbide epitaxial layer to the (n-1)th layer of the second silicon carbide epitaxial layer from bottom to top has a third upper surface, a fourth upper surface and a second sidewall surface between the third upper surface and the fourth upper surface, the third upper surface being above the fourth upper surface, the first layer of the first silicon carbide epitaxial layer being on the first upper surface of the silicon carbide substrate layer, the kth layer of the first silicon carbide epitaxial layer being on the third upper surface of the (k-1)th layer of the second silicon carbide epitaxial layer, 2≤k≤n;

[0010] a first electrode on the topmost layer of the second silicon carbide epitaxial layer;

[0011] a plurality of second electrodes on the second upper surface of the silicon carbide substrate layer and on the fourth upper surface of the first layer of the second silicon carbide epitaxial layer to the (n-1)th layer of the second silicon carbide epitaxial layer;

[0012] wherein the first silicon carbide epitaxial layers are lightly doped, the second silicon carbide epitaxial layers are heavily doped, and the silicon carbide substrate layer and the second silicon carbide epitaxial layers are of a first conductivity type, and the first silicon carbide epitaxial layers are of a second conductivity type.

[0013] In an embodiment of the present application, if the conductivity type of the silicon carbide substrate layer is N-type, the conductivity type of the first silicon carbide epitaxial layers is P-type, and the conductivity type of the second silicon carbide epitaxial layers is N-type, and if the conductivity type of the silicon carbide substrate layer is P-type, the conductivity type of the first silicon carbide epitaxial layers is N-type, and the conductivity type of the second silicon carbide epitaxial layers is P-type.

[0014] In an embodiment of the present application, the first sidewall surface between the first upper surface and the second upper surface forms an angle of 90° with the second upper surface, and the second sidewall surface between the third upper surface and the fourth upper surface of each layer of the first silicon carbide epitaxial layers forms an angle of 90° with the fourth upper surface.

[0015] In one embodiment of the present application, the thickness of the first silicon carbide epitaxial layer is 0.3 μm to 10 μm.

[0016] In one embodiment of the present application, the thickness of the second silicon carbide epitaxial layer is 0.3 μm to 2 μm.

[0017] In one embodiment of the present application, when the first electrode is a positive electrode, the second electrode is a negative electrode, and when the first electrode is a negative electrode, the second electrode is a positive electrode.

[0018] In one embodiment of the present application, the doping concentration of the first silicon carbide epitaxial layer is 1 x 1018 cm-3 to 1 x 1020 cm-3. 15 17 -3

[0019] One embodiment of the present application also provides a preparation method of the multi-step clamping voltage selectable SiC-TVS device, for preparing the multi-step clamping voltage selectable SiC-TVS device of any one of the above embodiments, and the preparation method comprises:

[0020] Step 1, selecting a silicon carbide substrate layer;

[0021] Step 2, alternately epitaxially growing n layers of first silicon carbide epitaxial layers and n layers of second silicon carbide epitaxial layers on the silicon carbide substrate layer;

[0022] Step 3, depositing a SiO2 layer on the second silicon carbide epitaxial layer of the topmost layer;

[0023] Step 4, coating a photoresist on the surface of the SiO2 layer, and performing exposure, development, post-baking and UV solidification to form a photoresist etching mask;

[0024] Step 5, etching the SiO2 layer by using ICP or RIE plasma dry etching technology to form a SiO2 etching mask;

[0025] Step 6, removing the photoresist;

[0026] Step 7, etching the first silicon carbide epitaxial layers and the second silicon carbide epitaxial layers by using ICP or RIE plasma dry etching technology, so that the second silicon carbide epitaxial layer of the (n-1)th layer forms a structure having a third upper surface, a fourth upper surface and a second side wall surface located between the third upper surface and the fourth upper surface, and the third upper surface of the second silicon carbide epitaxial layer is located above the fourth upper surface;

[0027] Step 8, removing the SiO2 etching mask and cleaning the wafer;

[0028] ​​​Step 9, repeating steps 3 to 8 to make all the second silicon carbide epitaxial layers except the topmost layer form a structure with a third upper surface, a fourth upper surface and a second side wall surface between the third upper surface and the fourth upper surface, and the silicon carbide substrate layer forms a structure with a first upper surface, a second upper surface and a first side wall surface between the first upper surface and the second upper surface;

[0029] Step 10, preparing a first electrode on the topmost second silicon carbide epitaxial layer, and preparing a second electrode on the second upper surface of the silicon carbide substrate layer and the fourth upper surface of the first layer to the (n-1) layer of the second silicon carbide epitaxial layer.

[0030] Compared with the prior art, the beneficial effects of the present application are:

[0031] The adjacent three-layer structure of the present application constitutes a three-layer vertical punch-through structure unit of N / P / N or P / N / P type, thereby constructing a device structure stacked by multiple N / P / N or P / N / P vertical punch-through structures, and leading out multiple levels of mesa electrodes on multiple levels of heavily doped layers, thereby making the clamping voltage increase with the increase of the number of added lightly doped layers, and the clamping voltage realized by the lower negative electrode gradually increases, so that the integration modulation of multiple levels of clamping voltages is realized on the TVS single chip, and the problems of increased system size and power consumption caused by the need to adapt multiple TVS devices for protection during non-steady-state operation of the circuit system are solved. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 A structure schematic diagram of a multiple-step clamping voltage selectable SiC-TVS device is provided for the present application;

[0033] Figure 2 A structure schematic diagram of a three-step clamping voltage selectable SiC-TVS device is provided for the present application;

[0034] Figure 3 A clamping characteristic curve diagram of a three-step clamping voltage selectable SiC-TVS device is provided for the present application;

[0035] Figure 4 A two-dimensional punch-through electric field distribution diagram and a longitudinal electric field distribution curve diagram along the center line when the third negative electrode is turned on of a three-step clamping voltage selectable SiC-TVS device are provided for the present application;

[0036] Figure 5 A preparation process flow chart of a three-step clamping voltage selectable SiC-TVS device is provided for the present application. DETAILED DESCRIPTION

[0037] The application will be described in further detail below with reference to specific embodiments, but the embodiments of the application are not limited thereto.

[0038] It should be noted that the "upper", "lower", "left", "right" mentioned in the embodiment are the positional relationship of the SiC-TVS device in the illustrated state, "long" is the lateral dimension of the SiC-TVS device in the illustrated state, and "deep" is the longitudinal dimension of the SiC-TVS device in the illustrated state.

[0039] Embodiment one

[0040] Please refer to Figure 1 , Figure 1 A structure diagram of a multi-step clamping voltage selectable SiC-TVS device is provided in the application. The embodiment of the application provides a multi-step clamping voltage selectable SiC-TVS device, which comprises:

[0041] A silicon carbide substrate layer 101, which has a first upper surface 104, a second upper surface 105, and a first side wall surface 106 between the first upper surface 104 and the second upper surface 105, and the first upper surface 104 is located above the second upper surface 105;

[0042] A silicon carbide epitaxial stack layer, which comprises n layers of first silicon carbide epitaxial layers 102 and n layers of second silicon carbide epitaxial layers 103, and the n layers of first silicon carbide epitaxial layers 102 and the n layers of second silicon carbide epitaxial layers 103 are alternately stacked on the first upper surface 104 of the silicon carbide substrate layer 101, the bottom layer of the silicon carbide epitaxial stack layer is the first silicon carbide epitaxial layer 102, and the top layer of the silicon carbide epitaxial stack layer is the second silicon carbide epitaxial layer 103;

[0043] And the first layer of the second silicon carbide epitaxial layer 103 to the (n-1) layer of the second silicon carbide epitaxial layer 103 from bottom to top has a third upper surface 107, a fourth upper surface 108, and a second side wall surface 109 between the third upper surface 107 and the fourth upper surface 108, and the third upper surface is located above the fourth upper surface, the first layer of the first silicon carbide epitaxial layer is located on the first upper surface of the silicon carbide substrate layer 101, the k layer of the first silicon carbide epitaxial layer is located on the third upper surface of the (k-1) layer of the second silicon carbide epitaxial layer, and 2≤k≤n;

[0044] A first electrode 110 located on the top layer of the second silicon carbide epitaxial layer 103;

[0045] A plurality of second electrodes 111 located on the second upper surface 105 of the silicon carbide substrate layer 101 and the fourth upper surface 108 of the first layer of the second silicon carbide epitaxial layer to the (n-1) layer of the second silicon carbide epitaxial layer.

[0046] The first silicon carbide epitaxial layer 102 is lightly doped, the second silicon carbide epitaxial layer 103 is heavily doped, the silicon carbide substrate layer 101 and the second silicon carbide epitaxial layer 103 are of a first conductivity type, the first silicon carbide epitaxial layer 102 is of a second conductivity type, and the first conductivity type and the second conductivity type are opposite conductivity types. Thus, a concentration abrupt PN junction can be realized, and a space charge region can be advanced under an applied bias voltage, thereby realizing punch-through.

[0047] Specifically, if the silicon carbide substrate layer 101 is of an N type, the first silicon carbide epitaxial layer 102 is of a P type, and the second silicon carbide epitaxial layer 103 is of an N type, or if the silicon carbide substrate layer 101 is of a P type, the first silicon carbide epitaxial layer 102 is of an N type, and the second silicon carbide epitaxial layer 103 is of a P type.

[0048] The embodiment forms several three-layer vertical punch-through structure units composed of the second silicon carbide epitaxial layer 103 / the first silicon carbide epitaxial layer 102 / the second silicon carbide epitaxial layer 103, so as to form the base open N / P / N or P / N / P bipolar transistor, thereby realizing the punch-through structure unit. Each punch-through structure unit forms an independent device level structure through one-time dry etching. Specifically, the silicon carbide substrate layer 101, the second silicon carbide epitaxial layer 103 and the first silicon carbide epitaxial layer 102 are set to be opposite conductive types. If the silicon carbide substrate layer 101 and the second silicon carbide epitaxial layer 103 are N-type and the first silicon carbide epitaxial layer 102 is P-type, then the adjacent three-layer structure forms an N / P / N three-layer vertical punch-through structure unit. If the silicon carbide substrate layer 101 and the second silicon carbide epitaxial layer 103 are P-type and the first silicon carbide epitaxial layer 102 is N-type, then the adjacent three-layer structure forms a P / N / P three-layer vertical punch-through structure unit. Thus, a device structure stacked by multiple N / P / N or P / N / P vertical punch-through structures is constructed, and a multi-stage mesa electrode is led out on the multi-stage heavily doped layer (i.e., the second silicon carbide epitaxial layer 103), so that the clamping voltage increases with the increase of the number of the lightly doped layer (i.e., the first silicon carbide epitaxial layer 102). The clamping voltage realized by the negative electrode from top to bottom gradually increases, thereby realizing the integrated modulation of the multi-stage clamping voltage on the TVS single chip, and solving the problems of the increase of system size and power consumption caused by the need to adapt multiple TVS devices for protection during the non-steady-state operation of the circuit system. In addition, the electrodes are prepared on the second upper surface of the silicon carbide substrate layer and the fourth upper surface 108 of the second silicon carbide epitaxial layer 103. Because of the step formed in the vertical appearance of the embodiment, the second electrode is prepared on the water platform surface of the etched second silicon carbide epitaxial layer, without considering the thickness limitation of the second silicon carbide epitaxial layer, i.e., the electrode width is widely and flexibly designed, and the process is convenient and feasible. Therefore, the process is relatively simple when preparing the electrode, and the problem of the thickness of the second silicon carbide epitaxial layer does not need to be considered.

[0049] It should be noted that in actual application, the number and structure parameters of the lightly doped layer can be reasonably selected according to the target working voltage dynamic adjustment range of the circuit system.

[0050] Furthermore, the angle between the first sidewall 106 and the second upper surface 105 between the first upper surface 104 and the second upper surface 105 is 90°, and the angle between the second sidewall 109 and the fourth upper surface 108 between the third upper surface 107 and the fourth upper surface 108 of each first silicon carbide epitaxial layer 102 is also 90°. Therefore, since the first sidewall 106 between the first upper surface 104 and the second upper surface 105 and the second sidewall 109 between the third upper surface 107 and the fourth upper surface 108 are vertical sidewalls, they will not cause local electric field concentration at the edge of the device, thereby reducing the risk of edge leakage current of the device and ensuring the withstand voltage reliability of SiC-TVS clamping.

[0051] Optionally, when the first electrode is a positive electrode, the second electrode is a negative electrode, and when the first electrode is a negative electrode, the second electrode is a positive electrode.

[0052] Optionally, the thickness S1 of the first silicon carbide epitaxial layer 102 is 0.3 μm to 10 μm.

[0053] Optionally, because load bearing is required through a base region with a lower doping concentration (i.e., the first silicon carbide epitaxial layer 102), the doping concentration of the first silicon carbide epitaxial layer 102 is 1×10⁻⁶. 15 ~1×10 17 cm -3 .

[0054] Optionally, since the space charge region formed by the highly doped second silicon carbide epitaxial layer 103 is very small and can be ignored, the thickness S2 of the second silicon carbide epitaxial layer 103 can be a small value, or can be set to a fixed value. At the same time, considering that the fourth upper surface 108 and the vertical sidewall of the first silicon carbide epitaxial layer 102 need to be formed by etching, the thickness S2 of the second silicon carbide epitaxial layer 103 is 0.3 μm to 2 μm.

[0055] Optionally, because the highly doped second silicon carbide epitaxial layer 103 forms a PN junction with the less doped first silicon carbide epitaxial layer 102, a space charge region can be formed in the less doped first silicon carbide epitaxial layer 102 under an applied bias voltage, based on the one-sided approximation principle. Therefore, the doping concentration of the second silicon carbide epitaxial layer 103 is 1×10⁻⁶. 19 cm -3 .

[0056] The application is aimed at the application of circuit system in non-steady voltage working state, and provides a multi-step clamping voltage selectable SiC-TVS device, which utilizes the material characteristic advantages of SiC to solve the problems of system size increase and power consumption increase caused by the need of adapting multiple TVS devices for protection. In the application: 1) one core is used for multiple purposes, and multiple three-layer vertical punch-through structure units are used on the TVS single chip to realize multi-step clamping voltage integrated modulation, thereby the size of the circuit system can be saved. By reasonably designing the number and structure parameters of the lightly doped layer, a wide range of clamping voltage selection can be realized, and the range of clamping voltage selection is increased. 2) The application forms a multi-step horizontal structure electrode mesa on the multi-layer second silicon carbide epitaxial layer. This structure is not only conducive to the realization of multi-step clamping voltage, but also conducive to the process preparation of each step electrode, thereby the positive and negative electrodes can be integrated, and the process steps for preparing the positive and negative electrodes are greatly saved. 3) The first sidewall surface and the second sidewall surface of the application have a vertical sidewall morphology, thereby the local electric field concentration at the edge of the device can be avoided, the edge leakage risk of the device is reduced, and the voltage reliability of the SiC-TVS is improved.

[0057] In addition, because the positive electrode and the negative electrode of the application can be exchanged, bidirectional clamping protection can be realized.

[0058] Embodiment two

[0059] Please refer to Figure 2 , Figure 3 , Figure 4 , Figure 2 A three-step clamping voltage selectable SiC-TVS device structure schematic diagram is provided in the application, Figure 3 A clamping characteristic curve of the three-step clamping voltage selectable SiC-TVS device is provided in the application, Figure 4 A two-dimensional punch-through electric field distribution diagram and a longitudinal electric field distribution curve along the center line when the third negative electrode is turned on of the three-step clamping voltage selectable SiC-TVS device are provided in the application. An embodiment of a multi-step clamping voltage selectable SiC-TVS device provided in the application, the device structure of the embodiment includes:

[0060] The silicon carbide substrate layer 101 is N-type doped, the thickness is 350 μm, the doping concentration is 5×10 18 cm -3 The etching depth D mesa etched into the silicon carbide substrate layer 101 is 1 μm.

[0061] The first silicon carbide epitaxial layer 102 is P-type doped, and the first silicon carbide epitaxial layer 102 contains P -1 , P-2 , P -3 Three layers, wherein the thickness of P-1 layer is 5 μm, the doping concentration is 1.1×10 16 cm -3 ; the thickness of P -2 layer is 2 μm, the doping concentration is 3×10 16 cm -3 ; the thickness of P -3 layer is 2 μm, the doping concentration is 3×10 16 cm -3 .

[0062] A second silicon carbide epitaxial layer 103, the doping type is N type, the second silicon carbide epitaxial layer 103 comprises N +1 , N +2 , N +3 three layers, wherein the thickness of N +1 -1 layer is 1 μm, the doping concentration is 5×10 18 cm -3 ; the thickness of N +2 layer is 2 μm, the doping concentration is 5×10 18 cm -3 , the etching depth D +2 of etching into N mesa layer is 1 μm; the thickness of N +3 layer is 2 μm, the doping concentration is 5×10 18 cm -3 , the etching depth D +3 of etching into N mesa layer is 1 μm.

[0063] In this embodiment, N+ represents a heavily doped N type region, N- represents a lightly doped N type region, P+ represents a heavily doped P type region, and P- represents a lightly doped P type region.

[0064] Based on the basic structure of the three-step clamping voltage optional SiC-TVS device of this embodiment, simulation verification is carried out by using sentaurus TCAD software. The signal source used in dynamic characteristic simulation is a 10 / 1000 μs pulse signal with a peak voltage of 1000 V.

[0065] Please refer to Figure 3 , Figure 3The clamping characteristic curve of the three-step clamping voltage optional SiC-TVS device provided by the application can be seen, the first negative electrode (Cathode 1) is turned on to realize 250V clamping voltage, the second negative electrode (Cathode 2) is turned on to realize 360V clamping voltage, and the third negative electrode (Cathode 3) is turned on to realize 460V clamping voltage, and the three-step clamping voltage optional SiC-TVS device provided by the application realizes the effect of integrating three clamping voltage grades on a single tube TVS chip.

[0066] Please refer to Figure 4 , Figure 4 The two-dimensional punch-through electric field distribution graph and the longitudinal electric field distribution curve along the middle line of the three-step clamping voltage optional SiC-TVS device provided by the application when the third negative electrode is turned on can be seen, the P -1 layer, the P -2 layer and the P -3 layer of the first silicon carbide epitaxial layer 102 are all completely punched through, and the maximum peak electric field at the three PN junctions is about 1.1MV / cm, which is much smaller than the material critical breakdown field value (about 2.8MV / cm). This is because the first side wall surface and the second side wall surface have a vertical side wall morphology, which will not cause local electric field concentration at the edge of the device, thereby avoiding local electric field concentration at the edge of the device, reducing the risk of edge leakage of the device, and ensuring the voltage reliability of the SiC-TVS clamping, so that breakdown caused by electric field concentration is avoided.

[0067] Example three

[0068] Please refer to Figure 5 , Figure 5 The preparation process flow chart of the three-step clamping voltage optional SiC-TVS device provided by the application, the application also provides a preparation method of a multi-step clamping voltage optional SiC-TVS device, the preparation method is used for preparing the multi-step clamping voltage optional SiC-TVS device described in any one of the above embodiments, and main preparation process flow steps of the preparation method include:

[0069] (a), selecting a silicon carbide substrate layer 101.

[0070] For example, the silicon carbide substrate layer 101 is an N+ silicon carbide substrate layer.

[0071] (b), alternately epitaxially growing the n-layer first silicon carbide epitaxial layer 102 and the n-layer second silicon carbide epitaxial layer 103 on the silicon carbide substrate layer 101.

[0072] The P-type first silicon carbide epitaxial layer 102 and the N+ type second silicon carbide epitaxial layer 103 are alternately epitaxially grown on the silicon carbide substrate layer 101.

[0073] (c) Depositing a SiO2 layer on the second silicon carbide epitaxial layer on the topmost layer.

[0074] Specifically, a SiO2 layer is deposited on the surface of the second silicon carbide epitaxial layer 103 by PECVD (Plasma Enhanced Chemical Vapor Deposition) with a thickness of 2-3 μm.

[0075] (d) Coating the surface of the SiO2 layer with photoresist, and performing exposure, development, post-baking, and UV curing to form a photoresist (PR) etching mask.

[0076] (e) Etching the SiO2 layer by ICP (Inductive Coupled Plasma Emission Spectrometer) or RIE (Reactive ion etching) plasma dry etching technology to form a SiO2 etching mask.

[0077] (f) Removing the photoresist.

[0078] Specifically, the photoresist can be removed by oxygen plasma ashing.

[0079] (g) Etching the first silicon carbide epitaxial layer and the second silicon carbide epitaxial layer by ICP or RIE plasma dry etching technology to form a structure having a third upper surface, a fourth upper surface, and a second sidewall surface between the third upper surface and the fourth upper surface, with the third upper surface of the second silicon carbide epitaxial layer being above the fourth upper surface.

[0080] For example, for a three-level step structure, the silicon carbide is etched by ICP or RIE plasma dry etching technology, and by adjusting the etching process parameters, a first-level step structure meeting the requirements of etching depth and verticality of 90° of the sidewall is formed. The water flat surface (i.e. the fourth upper surface) after etching is in the third layer, i.e. the second silicon carbide epitaxial layer 103, in the N+ / P- / N+ through structure unit composed of the first second silicon carbide epitaxial layer 103 / the first silicon carbide epitaxial layer 102 / the second silicon carbide epitaxial layer 103.

[0081] (h) Removing the SiO2 etching mask and cleaning the wafer.

[0082] Specifically, the SiO2 mask can be removed by hydrofluoric acid.

[0083] (i) repeating steps c to h to form a structure having a third upper surface, a fourth upper surface and a second sidewall surface between the third upper surface and the fourth upper surface for all the second silicon carbide epitaxial layers except the topmost layer, and the silicon carbide substrate layer forms a structure having a first upper surface, a second upper surface and a first sidewall surface between the first upper surface and the second upper surface.

[0084] For example, by repeating steps c to h, a three-level step structure in the silicon carbide epitaxial layer can be formed. Figure 5

[0085] (j) preparing a first electrode on the second silicon carbide epitaxial layer of the topmost layer, and preparing a second electrode on the second upper surface of the silicon carbide substrate layer and the fourth upper surface of the second silicon carbide epitaxial layer of the first layer to the second silicon carbide epitaxial layer of the (n-1)th layer.

[0086] Specifically, first, a thick glue is spin-coated on the surface of the silicon carbide wafer, and after exposure and development, an electrode via mask of the positive and negative electrodes is formed, and titanium or nickel metal is deposited on the surface by electron beam evaporation or magnetron sputtering; the wafer is placed in an acetone solution for ultrasonic treatment to realize the lift-off process, and the integration of the positive electrode and the negative electrode is completed.

[0087] The advantage of the preparation method of the multi-step clamping voltage optional SiC-TVS device of the application lies in the convenience of the electrode preparation process, that is: 1) the electrode is prepared on the water platform surface formed by etching, which is not affected by the thickness of the second silicon carbide epitaxial layer, and is easy to process and widely flexible in the design of electrode size; 2) the dry etching method is used to form a multi-level horizontal structure of the electrode mesa, which is beneficial to the process preparation of each step electrode; 3) after the formation of the step structure, all the positive electrodes and the negative electrodes can be integrated by using the lift-off process through thick glue coating, photolithography, which saves the process steps and reduces the cost; 4) by controlling the dry etching process, an etching morphology with a vertical sidewall is formed, which avoids the local electric field concentration at the edge of the device, reduces the risk of edge leakage of the device, and improves the voltage endurance reliability of the SiC-TVS.

[0088] In the description of the application, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second" can be explicitly or implicitly included one or more of the features. In the description of the application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0089] ​In the description of the specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" etc. means that the specific features, structures, materials or specific data points described in connection with the embodiment or example are contained in at least one embodiment or example of the present application. In the specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or specific data points described can be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate different embodiments or examples described in the specification.

[0090] The above is a further detailed description of the present application in combination with specific preferred embodiments, and cannot be considered as limiting the specific implementation of the present application to these descriptions. For those skilled in the art, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, which should be considered as falling within the protection scope of the present application.

Claims

1. A multi-step, clamp voltage selectable SiC-TVS device, characterized in that, The SiC-TVS device comprises: a silicon carbide substrate layer having a first upper surface, a second upper surface and a first sidewall surface between the first upper surface and the second upper surface, the first upper surface being above the second upper surface; a silicon carbide epitaxial stack layer comprising n layers of first silicon carbide epitaxial layers and n layers of second silicon carbide epitaxial layers, the n layers of first silicon carbide epitaxial layers and the n layers of second silicon carbide epitaxial layers being alternately stacked on the first upper surface of the silicon carbide substrate layer, the bottommost layer of the silicon carbide epitaxial stack layer being the first silicon carbide epitaxial layer, and the topmost layer of the silicon carbide epitaxial stack layer being the second silicon carbide epitaxial layer; and the first layer of the second silicon carbide epitaxial layer to the (n-1)th layer of the second silicon carbide epitaxial layer from bottom to top have a third upper surface, a fourth upper surface and a second sidewall surface between the third upper surface and the fourth upper surface, the third upper surface being above the fourth upper surface, the first layer of the first silicon carbide epitaxial layer being on the first upper surface of the silicon carbide substrate layer, the kth layer of the first silicon carbide epitaxial layer being on the third upper surface of the (k-1)th layer of the second silicon carbide epitaxial layer, 2≤k≤n; a first electrode on the topmost layer of the second silicon carbide epitaxial layer; a plurality of second electrodes on the second upper surface of the silicon carbide substrate layer and on the fourth upper surfaces of the first layer of the second silicon carbide epitaxial layer to the (n-1)th layer of the second silicon carbide epitaxial layer; wherein the first silicon carbide epitaxial layer is lightly doped, the second silicon carbide epitaxial layer is heavily doped, and the silicon carbide substrate layer and the second silicon carbide epitaxial layer are of a first conductivity type, and the first silicon carbide epitaxial layer is of a second conductivity type.

2. The multi-step clamp voltage selectable SiC-TVS device of claim 1, wherein, If the conductivity type of the silicon carbide substrate layer is N-type, the conductivity type of the first silicon carbide epitaxial layer is P-type, and the conductivity type of the second silicon carbide epitaxial layer is N-type, or if the conductivity type of the silicon carbide substrate layer is P-type, the conductivity type of the first silicon carbide epitaxial layer is N-type, and the conductivity type of the second silicon carbide epitaxial layer is P-type.

3. The multi-step clamp voltage selectable SiC-TVS device of claim 1, wherein, The first sidewall surface between the first upper surface and the second upper surface forms an angle of 90° with the second upper surface, and the second sidewall surface between the third upper surface and the fourth upper surface of each layer of the first silicon carbide epitaxial layer forms an angle of 90° with the fourth upper surface.

4. The multi-step clamp voltage selectable SiC-TVS device of claim 1, wherein, The thickness of the first silicon carbide epitaxial layer is 0.3-10 μm.

5. The multi-step clamp voltage selectable SiC-TVS device of claim 1, wherein, The thickness of the second silicon carbide epitaxial layer is 0.3-2 μm.

6. The multi-step, clamp voltage selectable SiC-TVS device of claim 1, wherein, When the first electrode is a positive electrode, the second electrode is a negative electrode, and when the first electrode is a negative electrode, the second electrode is a positive electrode.

7. The multi-step, clamp voltage selectable SiC-TVS device of claim 1, wherein, The first silicon carbide epitaxial layer has a doping concentration of 1 x 1014 15 ~ 1 x 1016 17 cm -3 .

8. A method for fabricating a SiC-TVS device with selectable clamping voltage across multiple steps, characterized in that, A method for preparing the multi-step clamping voltage selectable SiC-TVS device of any one of claims 1-7, the method comprising: Step 1: selecting a silicon carbide substrate layer; Step 2: alternately epitaxially growing n layers of first silicon carbide epitaxial layers and n layers of second silicon carbide epitaxial layers on the silicon carbide substrate layer; Step 3, depositing a SiO2 layer on the second silicon carbide epitaxial layer at the topmost layer; Step 4, coating the surface of the SiO2 layer with photoresist and performing exposure, development, post-baking and UV curing to form a photoresist etching mask; Step 5, etching the SiO2 layer by using ICP or RIE plasma dry etching technology to form a SiO2 etching mask; Step 6, removing the photoresist; Step 7, etching the first silicon carbide epitaxial layer and the second silicon carbide epitaxial layer by using ICP or RIE plasma dry etching technology, so that the second silicon carbide epitaxial layer at the (n-1)th layer forms a structure having a third upper surface, a fourth upper surface and a second sidewall surface located between the third upper surface and the fourth upper surface, and the third upper surface of the second silicon carbide epitaxial layer is located above the fourth upper surface; Step 8, removing the SiO2 etching mask and cleaning the wafer; Step 9, repeating steps 3 to 8, so that all the second silicon carbide epitaxial layers except the topmost layer form a structure having a third upper surface, a fourth upper surface and a second sidewall surface located between the third upper surface and the fourth upper surface, and the silicon carbide substrate layer forms a structure having a first upper surface, a second upper surface and a first sidewall surface located between the first upper surface and the second upper surface; Step 10, preparing a first electrode on the second silicon carbide epitaxial layer at the topmost layer, and preparing a second electrode on the second upper surface of the silicon carbide substrate layer and the fourth upper surfaces of the first layer of the second silicon carbide epitaxial layer to the (n-1)th layer of the second silicon carbide epitaxial layer.

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