Method of forming bulk acoustic wave resonator device

Abstract

A method of forming a bulk acoustic wave resonator device, comprising: forming a first part, comprising: providing a first substrate; forming a seed layer on the first substrate; forming a second electrode material layer on the seed layer; forming a piezoelectric layer on the second electrode material layer; forming a first electrode layer on the piezoelectric layer, the first electrode layer being on a first side; forming a cavity pre-treatment layer on the piezoelectric layer, the cavity pre-treatment layer being on the first side, and the cavity pre-treatment layer covering the first electrode layer; forming a second part, comprising: providing a second substrate; joining the second part to the first part, the second part being on the first side; removing the first substrate and the seed layer; patterning the second electrode material layer to form a second electrode layer on a second side of the piezoelectric layer; forming a cavity based on the cavity pre-treatment layer, the first electrode layer partially overlapping the second electrode layer above the cavity. The performance of the bulk acoustic wave filter is improved.

Description

Technical Field

[0001] This invention relates to the field of filters, and more particularly to a method for forming a bulk acoustic resonator. Background Technology

[0002] Existing resonator technologies mainly include surface acoustic wave (SAW) resonator technology, bulk acoustic wave (BAW) resonator technology, and low-temperature co-fired ceramic (LTCC) resonator technology. Filters with good passband performance can be formed by combining and arranging resonators.

[0003] Bulk acoustic resonator technology, thanks to its high quality factor (Q) and small structural size, is widely used in wireless communication of modern handheld devices to achieve good radio frequency signal filtering performance.

[0004] However, the performance of existing bulk acoustic resonators still needs to be improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for forming a bulk acoustic wave resonator to improve the performance of thin-film bulk acoustic wave resonators.

[0006] To solve the above-mentioned technical problems, the present invention provides a method for forming a bulk acoustic resonator, comprising: forming a first part, including: providing a first substrate; forming a seed layer on the first substrate; forming a second electrode material layer on the seed layer; forming a piezoelectric layer on the second electrode material layer, the piezoelectric layer including a first side and a second side opposite to each other, the first substrate, the seed layer and the second electrode material layer being located on the second side; forming a first electrode layer on the piezoelectric layer, the first electrode layer being located on the first side; forming a cavity pretreatment layer on the piezoelectric layer, the cavity pretreatment layer being located on the first side and covering the first electrode layer; forming a second part, including: providing a second substrate; joining the second part to the first part, the second part being located on the first side; removing the first substrate and the seed layer; patterning the second electrode material layer; forming a second electrode layer on a second side of the piezoelectric layer; forming a cavity based on the cavity pretreatment layer, the first electrode layer and the second electrode layer partially overlapping above the cavity.

[0007] Optionally, the method for forming the seed layer includes: forming an initial seed layer on the first substrate; and planarizing the initial seed layer to form the seed layer. Optionally, the material of the seed layer includes a metallic material or an inorganic non-metallic material, wherein the metallic material includes titanium, aluminum, or molybdenum; and the inorganic non-metallic material includes aluminum nitride, aluminum oxide, silicon oxide, silicon nitride, aluminum oxynitride, or silicon carbide.

[0008] Optionally, the planarization process includes plasma etching or chemical mechanical polishing.

[0009] Optionally, the seed layer is made of titanium; the process for forming the initial seed layer includes physical vapor deposition, the parameters of which include: a titanium target; a power range of 500 watts to 800 watts; an argon flow rate range of 20 sccm to 100 sccm; and a temperature range of 100 degrees Celsius to 200 degrees Celsius.

[0010] Optionally, the seed layer material includes alumina; the process for forming the initial seed layer includes atomic layer deposition (ALD), the parameters of which include: gases including trimethylaluminum, ozone, and nitrogen, the flow rate of the trimethylaluminum gas being in the range of 100 sccm to 200 sccm, the flow rate of the ozone gas being in the range of 100 sccm to 200 sccm, and the flow rate of the nitrogen gas being in the range of 100 sccm to 200 sccm; and a temperature range of 200 degrees Celsius to 300 degrees Celsius.

[0011] Optionally, the thickness of the seed layer ranges from 150 angstroms to 500 angstroms.

[0012] Optionally, the method for removing the first substrate and the seed layer includes: removing a portion of the first substrate using a first process; removing the remaining first substrate using a second process; and removing the seed layer after removing the first substrate.

[0013] Optionally, the first process includes physical mechanical polishing (PMP) or chemical mechanical polishing (CMP); the second process includes dry etching, wet etching, or plasma etching; and the process for removing the seed layer includes wet etching or plasma etching.

[0014] Optionally, the method of forming the cavity pretreatment layer includes: forming a sacrificial layer on the piezoelectric layer, located on the first side, the sacrificial layer covering at least one end of the first electrode layer.

[0015] Optionally, the method for forming the cavity includes: removing the sacrificial layer; wherein the process for removing the sacrificial layer includes a wet etching process.

[0016] Optionally, the method for forming the cavity pretreatment layer further includes: forming a first intermediate layer on the piezoelectric layer, located on the first side, the first intermediate layer covering the sacrificial layer and the first electrode layer; wherein the material of the first intermediate layer includes: silicon dioxide, polycrystalline silicon or polyimide.

[0017] Optionally, forming the second part further includes: forming a second intermediate layer located on one side of the second substrate and covering the second substrate; wherein the material of the second intermediate layer includes: silicon dioxide, polycrystalline silicon, or polyimide.

[0018] Optionally, the method of joining the second part with the first part includes: bonding the first intermediate layer and the second intermediate layer.

[0019] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0020] The technical solution of this invention involves forming a seed layer on a first substrate, wherein the seed layer has a relatively small roughness. On one hand, when a second electrode material layer is formed on the surface of the seed layer, the second electrode material layer has a high degree of crystallinity, i.e., a neat lattice arrangement and high crystal orientation consistency. When a piezoelectric layer is then formed on the surface of the second electrode material layer, the quality of the piezoelectric layer material crystal is good, with fewer grains exhibiting significant orientation. On the other hand, because the surface roughness of the seed layer is small, the subsequent film layers formed on the seed layer surface grow continuously on a flat surface, resulting in a more uniform stress distribution in each film layer. This makes it less likely that defects caused by uneven stress distribution in the film layers will occur in the bulk acoustic wave resonator after the sacrificial layer is removed to form a cavity, thereby improving the reliability of the bulk acoustic wave resonator.

[0021] Furthermore, the seed layer can act as an etching barrier layer during the removal of the first substrate, protecting the second electrode material layer and reducing the damage caused by etching to the second electrode material layer. Attached Figure Description

[0022] Figures 1 to 8 This is a schematic diagram of the formation process of the bulk acoustic resonator in an embodiment of the present invention. Detailed Implementation

[0023] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0024] Figures 1 to 8 This is a schematic diagram of the formation process of the bulk acoustic resonator in an embodiment of the present invention.

[0025] The first part is formed; please refer to the process of forming the first part. Figures 1 to 4 .

[0026] Please refer to Figure 1 Provides the first substrate 200.

[0027] In this embodiment, the material of the first substrate 200 includes silicon. The first substrate 200 provides structural support for the subsequent formation of the second electrode layer, the first electrode layer, and the sacrificial layer.

[0028] Please continue to refer to this. Figure 1 Seed layer 201 is formed on the first substrate 200.

[0029] The method for forming the seed layer 201 includes: forming an initial seed layer (not shown) on a first substrate 200; and planarizing the initial seed layer to form the seed layer 201.

[0030] Before forming the initial seed layer on the first substrate 200, the process further includes: pre-cleaning the surface of the first substrate 200. The process parameters for the pre-cleaning process include: a temperature range of 300°C to 500°C; an argon flow rate range of 10 sccm to 30 sccm; an RF coil power range of 500 watts to 1000 watts; a planar RF bias power range of 100 watts to 300 watts; and a time range of 10 seconds to 60 seconds. The planarization process for the initial seed layer includes plasma etching or chemical mechanical polishing. Planarizing the initial seed layer reduces the surface roughness of the initial seed layer. Subsequently, when forming the second electrode material layer on the surface of the seed layer 201, the crystal lattice of the second electrode material layer is neatly arranged with high crystal orientation consistency. When forming the piezoelectric layer on the surface of the second electrode material layer, the quality of the piezoelectric layer material crystal is better, with fewer obviously oriented grains, which can optimize the full width at half maximum (FWHM) of the piezoelectric layer.

[0031] In this embodiment, the seed layer 201 is made of a metallic material or an inorganic non-metallic material; the metallic material includes titanium, aluminum or molybdenum; the inorganic non-metallic material includes aluminum nitride, aluminum oxide, silicon oxide, silicon nitride, aluminum oxynitride or silicon carbide.

[0032] In this embodiment, the thickness of the seed layer 201 ranges from 150 angstroms to 500 angstroms.

[0033] In one embodiment, the seed layer is made of titanium; the process for forming the initial seed layer includes physical vapor deposition, the parameters of which include: a titanium target; a power range of 500 watts to 800 watts; an argon flow rate range of 20 sccm to 100 sccm; and a temperature range of 100 degrees Celsius to 200 degrees Celsius.

[0034] In one embodiment, the seed layer material includes alumina; the process for forming the initial seed layer includes atomic layer deposition (ALD), the parameters of which include: gases including trimethylaluminum, ozone, and nitrogen, the flow rate of the trimethylaluminum gas ranging from 100 sccm to 200 sccm, the flow rate of the ozone gas ranging from 100 sccm to 200 sccm, the flow rate of the nitrogen gas ranging from 100 sccm to 200 sccm, and the temperature ranging from 200 degrees Celsius to 300 degrees Celsius.

[0035] Please continue to refer to this. Figure 1 A second electrode material layer 202 is formed on the seed layer 201.

[0036] The material of the second electrode material layer 202 includes metals, such as molybdenum, aluminum, tungsten, gold, platinum, or ruthenium.

[0037] The seed layer 201 has a low surface roughness, resulting in a second electrode material layer 202 formed on a surface with high flatness. The crystal lattice of the second electrode material layer 202 is preferentially oriented and ordered, resulting in high crystallinity, neat lattice arrangement, and high crystal orientation consistency.

[0038] Please continue to refer to this. Figure 1 A piezoelectric layer 203 is formed on the second electrode material layer 202, the piezoelectric layer 203 including a first side and a second side opposite to each other. The first substrate 200, the seed layer 201 and the second electrode material layer 202 are located on the second side.

[0039] The piezoelectric layer 203 is made of aluminum nitride, scandium aluminum nitride, lead zirconate titanate, or zinc oxide. In this embodiment, the piezoelectric layer 203 is made of aluminum nitride.

[0040] The second electrode material layer 202 has a high degree of crystallinity, resulting in a better quality piezoelectric layer 203 with fewer obviously oriented grains and an optimized full width at half maximum (FWHM) of the piezoelectric layer 203.

[0041] In this embodiment, the thickness of the piezoelectric layer 203 ranges from 5000 angstroms to 20000 angstroms.

[0042] Please refer to Figure 2 A first electrode layer 204 is formed on the first side of the piezoelectric layer 203, and the first electrode layer 204 overlaps with a portion of the first side surface of the piezoelectric layer 203.

[0043] The method for forming the first electrode layer 204 includes: forming an initial first electrode layer (not shown) on a first side of the piezoelectric layer 203; removing a portion of the initial first electrode layer until the surface of the piezoelectric layer 203 is exposed, thereby forming the first electrode layer 204.

[0044] In this embodiment, the material of the first electrode layer 204 includes metal, such as molybdenum, aluminum, tungsten, gold, platinum, or ruthenium.

[0045] In this embodiment, the thickness of the first electrode layer 204 ranges from 1000 angstroms to 4000 angstroms.

[0046] Next, a cavity pretreatment layer is formed on the first electrode layer 204. The cavity pretreatment layer includes a sacrificial layer and a first intermediate layer covering the sacrificial layer. Please refer to [reference needed] for the formation process of the cavity pretreatment layer. Figure 3 and Figure 4 .

[0047] Please refer to Figure 3 A sacrificial layer 205 is formed on the first side of the piezoelectric layer 203, and the sacrificial layer 205 covers at least one end of the first electrode layer 204.

[0048] The method for forming the sacrificial layer 205 includes: forming an initial sacrificial layer (not shown) on the first electrode layer 204 and on the first side of the piezoelectric layer 203; removing a portion of the initial sacrificial layer to form the sacrificial layer 205.

[0049] The materials of the sacrificial layer 205 include: polycrystalline silicon, silicon oxide, organic materials or metallic materials; the metallic materials include titanium, aluminum or copper; the organic materials include amorphous carbon.

[0050] Please refer to Figure 4 A first intermediate layer 206 is formed on the first side of the piezoelectric layer 203, the first electrode layer 204, and the sacrificial layer 205.

[0051] The first intermediate layer 206 provides a bonding interface for subsequent bonding with the second substrate, and also provides structural support for the subsequent formation of the cavity.

[0052] The material of the first intermediate layer 206 includes polycrystalline silicon, silicon oxide, or polyimide.

[0053] In other embodiments, the first intermediate layer may not be formed.

[0054] Please refer to Figure 5 The second part is formed by: providing a second substrate 300; and forming a second intermediate layer 301 on the surface of the second substrate 300.

[0055] In this embodiment, the material of the second substrate 300 includes high-resistivity silicon; the material of the second intermediate layer 301 includes polycrystalline silicon, silicon oxide, or polyimide.

[0056] Please continue to refer to this. Figure 5 The second part is joined to the first part, with the second part located on the first side.

[0057] The method of joining the second part to the first part includes: bonding the first intermediate layer 206 to the second intermediate layer 301.

[0058] Please refer to Figure 6 Remove the first base layer 200 and the seed layer 201.

[0059] The method for removing the first substrate 200 and the seed layer 201 includes: removing a portion of the first substrate 200 using a first process; removing the remaining first substrate 200 using a second process; and removing the seed layer 201 after removing the first substrate 200.

[0060] In this embodiment, the first process includes physical mechanical polishing (PMP) or chemical mechanical polishing (CMP). The second process includes dry etching, wet etching, or plasma etching. This two-step removal process ensures that the removal of the first substrate 200 is accurately stopped on the seed layer 201, avoiding damage to the second electrode material layer 202.

[0061] In this embodiment, the process for removing the seed layer 201 includes wet etching or plasma etching.

[0062] During the removal of the first substrate 200, the seed layer 201 can act as an etching barrier layer to protect the second electrode material layer 202 and reduce damage to the second electrode material layer 202.

[0063] Please continue to refer to this. Figure 6 A portion of the second electrode material layer 202 is removed, and a second electrode layer 207 is formed on the second side of the piezoelectric layer 203, wherein the second electrode layer 207 overlaps with a portion of the second side surface of the piezoelectric layer 203.

[0064] In this embodiment, the projection ranges of the first electrode layer 204 and the second electrode layer 207 on the surface of the piezoelectric layer 203 partially overlap, and the overlapping projection ranges of the first electrode layer 204 and the second electrode layer 207 on the surface of the piezoelectric layer 203 are located within the projection range of the sacrificial layer 205 on the surface of the piezoelectric layer 203.

[0065] Please refer to Figure 7 A first electrical connection layer 209 and a second electrical connection layer 208 are formed. The first electrical connection layer 209 is located on the surface of the second electrode layer 207. The second electrical connection layer 208 penetrates the piezoelectric layer 203 from the first side to the second side, and the second electrical connection layer 208 is in contact with the first electrode layer 204.

[0066] The first connection layer 209 and the second electrical connection layer 208 are respectively connected to the external circuit, so that the first electrode layer 207 and the first electrode layer 204 are connected to the external circuit to form a loop.

[0067] Please refer to Figure 8 Remove the sacrificial layer 205 to form a cavity 210 between the first intermediate layer 206 and the first electrode layer 204. A portion of the top surface and a portion of the sidewall surface of the first electrode layer 204 are located within the cavity 210. The first electrode layer 204 and the second electrode layer 207 partially overlap above the cavity 210.

[0068] The process for removing the sacrificial layer 205 includes a dry etching process or a wet etching process.

[0069] Because the surface roughness of the seed layer 201 is small, the various film layers subsequently formed on the surface of the seed layer 201 grow continuously on the flat surface, and the stress distribution of each film layer is relatively uniform. As a result, after the sacrificial layer 205 is removed, the bulk acoustic wave resonator is less likely to have defects caused by uneven stress distribution of the film layers, thereby improving the reliability of the bulk acoustic wave resonator.

[0070] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a bulk acoustic resonator, characterized in that, include: The first part is formed by: providing a first substrate; forming a seed layer on the first substrate; forming a second electrode material layer on the seed layer; forming a piezoelectric layer on the second electrode material layer, the piezoelectric layer including a first side and a second side opposite to each other, the first substrate, the seed layer and the second electrode material layer being located on the second side; forming a first electrode layer on the piezoelectric layer, the first electrode layer being located on the first side; forming a cavity pretreatment layer on the piezoelectric layer, the cavity pretreatment layer being located on the first side and covering the first electrode layer; wherein the material of the seed layer includes alumina, silicon oxide, silicon nitride, aluminum oxynitride or silicon carbide; Forming the second part includes: providing a second base; The second part is joined to the first part, with the second part located on the first side; Removing the first substrate includes: removing a portion of the first substrate using a first process, and removing the remaining first substrate using a second process, wherein the second process is an etching process; wherein, during the removal of the first substrate, the seed layer serves as an etching barrier layer. After removing the first substrate, remove the seed layer; The second electrode material layer is patterned, and a second electrode layer is formed on the second side of the piezoelectric layer; A cavity is formed based on the cavity pretreatment layer, and the first electrode layer and the second electrode layer partially overlap above the cavity.

2. The method for forming a bulk acoustic resonator as described in claim 1, characterized in that, The method for forming a seed layer includes: forming an initial seed layer on a first substrate; and planarizing the initial seed layer to form the seed layer.

3. The method for forming the bulk acoustic resonator as described in claim 2, characterized in that, The seed layer is made of alumina; the process for forming the initial seed layer includes atomic layer deposition (ALD), the parameters of which include: gases including trimethylaluminum, ozone, and nitrogen, the flow rate of the trimethylaluminum gas being in the range of 100 sccm to 200 sccm, the flow rate of the ozone gas being in the range of 100 sccm to 200 sccm, and the flow rate of the nitrogen gas being in the range of 100 sccm to 200 sccm. The temperature range is 200 degrees Celsius to 300 degrees Celsius.

4. The method for forming the bulk acoustic resonator as described in claim 2, characterized in that, The planarization process includes plasma etching or chemical mechanical polishing.

5. The method for forming a bulk acoustic resonator as described in claim 1, characterized in that, The thickness of the seed layer ranges from 150 angstroms to 500 angstroms.

6. The method for forming a bulk acoustic resonator as described in claim 1, characterized in that, The first process includes physical mechanical polishing or chemical mechanical polishing; the second process includes dry etching, wet etching or plasma etching; the process for removing the seed layer includes wet etching or plasma etching.

7. The method for forming a bulk acoustic resonator as described in claim 1, characterized in that, The method of forming a cavity pretreatment layer includes: forming a sacrificial layer on a first side of the piezoelectric layer, the sacrificial layer covering at least one end of the first electrode layer.

8. The method for forming a bulk acoustic resonator as described in claim 7, characterized in that, The method for forming a cavity includes: removing the sacrificial layer; wherein the process for removing the sacrificial layer includes a wet etching process.

9. The method for forming a bulk acoustic resonator as described in claim 7, characterized in that, The method for forming the cavity pretreatment layer further includes: forming a first intermediate layer on the piezoelectric layer, located on the first side, the first intermediate layer covering the sacrificial layer and the first electrode layer; wherein the material of the first intermediate layer includes: silicon dioxide, polycrystalline silicon or polyimide.

10. The method for forming a bulk acoustic resonator as described in claim 9, characterized in that, The second step further includes forming a second intermediate layer located on one side of the second substrate and covering the second substrate; wherein the material of the second intermediate layer includes silicon dioxide, polycrystalline silicon, or polyimide.

11. The method for forming a bulk acoustic resonator as described in claim 10, characterized in that, A method for joining the second part to the first part includes: bonding the first intermediate layer to the second intermediate layer.

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